A MOS device and a method of manufacturing the same

Abstract

This application belongs to the field of semiconductor manufacturing technology and discloses a MOS device and its fabrication method. The fabrication method includes the following steps: obtaining a semiconductor silicon substrate and etching to form an active region trench; the active region trench undergoes a first thermal oxidation treatment to form a first silicon dioxide layer, and then a source polysilicon layer not exceeding the arrangement plane is formed; locally etching to remove part of the first silicon dioxide layer on the surface of each sidewall, retaining the two ends to form a corner deposition block; depositing a second silicon dioxide layer and filling the active region trench, and sequentially performing wet etching and a second thermal oxidation; finally forming the source, drain, and gate to obtain the MOS device. This application relies on differentiated oxide layer preparation and selective structure control design to precisely strengthen the key areas at the trench corners, effectively improving the local electric field distribution, weakening the electric field accumulation effect caused by structural abrupt changes, and improving the tolerance performance of the inter-gate oxide layer from the core structure level.

Description

Technical Field

[0001] This application belongs to the field of semiconductor manufacturing technology, and specifically relates to a MOS device and its fabrication method. Background Technology

[0002] MOS devices are the core components of semiconductor integrated circuits and power electronic devices. Among them, high-voltage trench MOS devices and shielded gate MOSFETs have been widely used in many key fields such as power management, motor drive, and new energy due to their significant advantages of fast switching speed and low conduction loss. Their operational reliability directly determines the operational stability of terminal equipment.

[0003] In the reverse withstand voltage operation state, the corner where the gate polysilicon layer connects to the active trench sidewall is subject to a sudden change in geometry, which can easily lead to severe electric field concentration. The electric field intensity in this area can be several times that of other areas of the device, making the inter-gate oxide layer a weak link in the overall device structure. This makes the gate oxide layer prone to gate oxide breakdown, severely shortening the device's lifespan and limiting its stable application in high-voltage scenarios. Summary of the Invention

[0004] This application aims to improve at least one technical problem in the background art.

[0005] The first aspect of this application provides a method for fabricating a MOS device, comprising the following steps: Obtain a semiconductor silicon substrate, with one side of the semiconductor silicon substrate serving as an arrangement surface, and form an active region trench on the arrangement surface by etching. A first silicon dioxide layer is formed at the bottom of the active region trench and on the surface of the four sidewalls by a first thermal oxidation process, and then a source polysilicon layer is formed in the active region trench, wherein the source polysilicon layer does not extend beyond the arrangement surface. The first silicon dioxide layer on the surface of the sidewall is locally etched. After the first silicon dioxide layer on the surface of each sidewall is etched, a retention portion is retained at least at both ends. Two adjacent retention portions are connected and form a corner deposition block in the active area trench. A second silicon dioxide layer is formed in the active region trench by plasma chemical vapor deposition. The second silicon dioxide layer fills the active region trench and is flush with the arrangement surface. Then, wet etching and second thermal oxidation processes are performed in sequence. The corner deposition block and the second silicon dioxide layer constitute an inter-gate oxide layer, and the source, drain and gate are formed based on the inter-gate oxide layer to obtain the MOS device.

[0006] Furthermore, the thickness of the first silicon dioxide layer on the surface of the active region trench sidewall is A1, and the length of the retained portion is A2, satisfying: 0.1μm≤A2-A1≤0.3μm.

[0007] Furthermore, after the second thermal oxidation treatment, the thickness ratio of the second silicon dioxide layer on the surface of the retained portion and the active region trench sidewall is (1.5-2.5):1.

[0008] Furthermore, the depth of the active region trench is 1μm-10μm, and the opening width of the active region trench is 0.2μm-1.8μm.

[0009] Furthermore, the thickness of the first silicon dioxide layer is 500 Å-2000 Å.

[0010] Furthermore, the distance between the source polycrystalline silicon layer and the arrangement surface is 0.5μm-2μm.

[0011] Furthermore, the parameters for the plasma chemical vapor deposition are: deposition pressure 5mTorr-20mTorr, radio frequency power 1000W-2000W, deposition temperature 350℃-450℃, and deposition rate 50Å / min-150Å / min.

[0012] Furthermore, the wet etching process includes the following steps: Immerse the semiconductor silicon substrate with the second silicon dioxide layer deposited into an aqueous solution of hydrofluoric acid for 5-10 minutes. The volume ratio of hydrofluoric acid to water in the aqueous solution of hydrofluoric acid is 1:(80-120).

[0013] Furthermore, the temperature of the second thermal oxidation treatment is 900℃-1100℃, and the second thermal oxidation treatment uses alternating dry oxygen atmosphere and wet oxygen atmosphere, and the time of the second thermal oxidation treatment is 30min-120min.

[0014] A second aspect of this application provides a MOS device, which is fabricated according to the above-described fabrication method.

[0015] The beneficial effects of this application are as follows: Addressing the inherent problems of concentrated electric fields and easily damaged dielectrics at trench corners in existing high-voltage trench devices, this application utilizes differentiated oxide layer preparation and selective structural control design to precisely strengthen key areas at trench corners. This effectively improves the local electric field distribution, weakens the impact of electric field accumulation caused by structural abrupt changes, and enhances the resilience of the inter-gate oxide layer at the core structural level. Combined with an optimized thermal oxidation treatment mode, it can achieve directional growth of the local oxide layer while rationally controlling the process heat load, alleviating stress accumulation during dielectric preparation, reducing film defects, and ensuring the overall density and structural integrity of the inter-gate oxide layer. This application only improves the structure of weak areas with concentrated electric fields, while maintaining the conventional structural settings in the main sidewall area. This avoids the device's electrical performance deviation caused by overall thickening design, ensuring the stability and controllability of the device's basic operating characteristics. The overall fabrication process is seamless and compatible with conventional semiconductor mass production systems. It does not rely on high-precision equipment and stringent process conditions, and has stronger process compatibility and feasibility. While simplifying the difficulty of fabrication control, it can effectively improve the operational stability and service life of devices under high-voltage conditions, and effectively make up for the shortcomings of existing technologies in terms of structural optimization and process adaptability. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of an active region trench formed on a semiconductor silicon substrate in one embodiment; Figure 2 This is a schematic diagram of a structure in which a first silicon dioxide layer and a source polysilicon layer are formed in an active region trench in one embodiment. Figure 3 This is a schematic diagram of the structure after partial etching of the first silicon dioxide layer in one embodiment; Figure 4 This is a schematic diagram of a corner deposition block structure in one embodiment; Figure 5 for Figure 4 Enlarged view of point A in the middle; Figure 6 This is a schematic diagram of a structure in which a second silicon dioxide layer is formed in a trench in the active region in one embodiment. Figure 7 This is a schematic diagram of the structure after the second thermal oxidation treatment in one embodiment.

[0017] In the attached figure: 100 - semiconductor silicon substrate; 110 - arrangement surface; 200 - active region trench; 300 - first silicon dioxide layer; 310 - retention area; 320 - corner deposition block; 400 - source polysilicon layer; 500 - second silicon dioxide layer. Detailed Implementation

[0018] The present application will be further described below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the application. Furthermore, it should be understood that after reading the contents of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope defined by the appended claims.

[0019] refer to Figure 1-7 This application provides a method for fabricating a MOS device, comprising the following steps: Obtain a semiconductor silicon substrate 100, one side of which is used as a layout surface 110, and an active region trench 200 is etched on the layout surface 110. A first silicon dioxide layer 300 is formed at the bottom of the active region trench 200 and on the surface of the four sidewalls by a first thermal oxidation treatment, and then a source polysilicon layer 400 is formed in the active region trench 200, wherein the source polysilicon layer 400 does not extend beyond the arrangement surface 110. The first silicon dioxide layer 300 on the surface of the sidewall is locally etched. After the first silicon dioxide layer 300 on the surface of each sidewall is etched, a retention portion 310 is retained at least at both ends. Two adjacent retention portions 310 are connected and form a corner deposition block 320 in the active area trench 200. A second silicon dioxide layer 500 is formed in the active region trench 200 by plasma chemical vapor deposition. The second silicon dioxide layer 500 fills the active region trench 200 and is flush with the arrangement surface 110. Then, wet etching process and second thermal oxidation process are performed in sequence. The corner deposition block 320 and the second silicon dioxide layer 500 constitute an inter-gate oxide layer, and the source, drain and gate are formed based on the inter-gate oxide layer to obtain the MOS device.

[0020] The method for fabricating a MOS device provided in this application first selects a semiconductor silicon substrate 100 as the fabrication substrate, and uses one side surface of the semiconductor silicon substrate 100 as the arrangement surface 110 of the device structure. According to the preset active region location, an active region trench 200 is formed on the arrangement surface 110 through an etching process (e.g., ...). Figure 1 As shown in the figure, this lays the foundation for the fabrication of subsequent layers of the device. Figure 2As shown, a first silicon dioxide layer 300 is then formed at the bottom of the active region trench 200 and on the surface of the four sidewalls through a first thermal oxidation process. This silicon dioxide layer is formed by the oxidation of the silicon substrate itself, forming a tight and stable native bonding interface with the silicon substrate, which serves as the basis for the subsequent thickening of the corner deposition block 320. After the preparation of the first silicon dioxide layer 300 is completed, a source polysilicon layer 400 is formed inside the active region trench 200. Finally, the top surface of the source polysilicon layer 400 is made flat and does not exceed the arrangement surface 110 (that is, the source polysilicon layer 400 only fills the inside of the active region trench 200, does not overflow the trench range, and does not protrude above the arrangement surface 110), providing stable support for the subsequent inter-gate oxide layer. Next, the first silicon dioxide layer 300 on the surface of the active region trench 200 is locally etched. During the etching process, the retention portions 310 at both ends of the first silicon dioxide layer 300 on each sidewall surface are retained. Adjacent retention portions 310 form corner deposition blocks 320 (e.g., Figure 3 and Figure 4 As shown), this delineates the area for differentiated treatment of the silicon dioxide layer at the subsequent corner position. Then, a second silicon dioxide layer 500 is deposited within the active region trench 200 using plasma-enhanced chemical vapor deposition (HDP CVD). This second silicon dioxide layer 500 fully fills the internal space of the active region trench 200, completely filling the groove formed after the partial etching removal of the first silicon dioxide layer 300, while simultaneously covering the area above the source polysilicon layer 400. The second silicon dioxide layer 500 is filled to the level of the arrangement surface 110 (e.g., ...). Figure 6 (As shown). The second silicon dioxide layer 500 is then subjected to wet etching and a second thermal oxidation process. Wet etching can uniformly trim the deposited second silicon dioxide layer 500, removing excess material and optimizing the layer thickness distribution, making the second silicon dioxide layer 500 more regular. During the second thermal oxidation process, a native thermal oxidation interface exists between the corner deposition block 320 (the remaining first silicon dioxide layer 300 etched) and the silicon substrate. Oxygen can easily penetrate this interface and react with the underlying silicon substrate, generating new silicon dioxide and thickening the original silicon dioxide layer horizontally along the sidewalls. In contrast, the sidewalls of non-corner areas are directly attached to the second silicon dioxide layer 500 formed by plasma chemical vapor deposition. This deposited oxide layer has a dense structure, preventing oxygen from penetrating its interior to reach the silicon substrate surface, thus failing to trigger an oxidation reaction and achieve thickening. Ultimately, only the silicon dioxide layer in the corner area achieves thickening (e.g., Figure 7(As shown). After fabricating the source, drain, and gate based on the inter-gate oxide layer (composed of corner deposition block 320 and second silicon dioxide layer 500), a MOS device with stable overall structure, better voltage withstand performance, and higher operational reliability is finally obtained. The inter-gate oxide layer formed by this fabrication method has the structural characteristics of a larger thickness in the corner region and a moderate thickness in the main sidewall region. It can solve the technical problem that the electric field is easily excessively concentrated in the corner region of the active trench 200 of traditional high-voltage trench MOS devices during operation, which leads to the breakdown of the inter-gate oxide layer and a decrease in device reliability.

[0021] In this specific embodiment of the application, the semiconductor silicon substrate 100 is an N-type single-crystal silicon substrate.

[0022] In some specific embodiments, the active region trench 200 is etched on the arrangement surface 110, including the following steps: A silicon nitride hard mask layer with a thickness of 1000Å-2000Å was deposited on the arrangement surface 110 using a low-pressure chemical vapor deposition (LPCVD) process. Photoresist is coated and patterned using photolithography to obtain patterned photoresist, which forms the first mask window at the preset active region position. Using patterned photoresist as a mask, the silicon nitride hard mask layer is etched using an inductively coupled plasma (ICP) dry etching process (the etching gas is a mixture of CF4 and O2 with a volume ratio of 5:1, the etching power is 600W-1000W, and the etching time is 30s-60s). The surface 110 was etched using inductively coupled plasma dry etching (the etching gas was a mixture of SF6 and O2 with a volume ratio of 4:1, and the etching pressure was 5 mTorr-10 mTorr) to form an active region trench 200. Residual patterned photoresist was removed using a plasma ashing process.

[0023] This implementation method uses a mature inductively coupled plasma etching process to ensure the verticality and morphological uniformity of the active region trench 200, avoiding the exacerbation of electric field concentration due to irregular trench morphology.

[0024] In some specific embodiments, the depth of the active region trench 200 is 1μm-10μm, and the opening width of the active region trench 200 is 0.2μm-1.8μm. In this specific embodiment of the present application, the depth of the active region trench 200 is 5μm, and the opening width of the active region trench 200 is 1μm.

[0025] In some specific embodiments, the temperature of the first thermal oxidation treatment is 900℃-1050℃, the first thermal oxidation treatment is carried out in a dry oxygen atmosphere, and the time of the first thermal oxidation treatment is 30min-90min.

[0026] In some specific embodiments, the thickness of the first silicon dioxide layer 300 is 500 Å to 2000 Å. In this specific embodiment of the present application, the thickness of the first silicon dioxide layer 300 is 1000 Å.

[0027] In some specific embodiments, forming a source polysilicon layer 400 within the active region trench 200 includes the following steps: A polycrystalline silicon layer A is deposited in the active region trench 200 using a chemical vapor deposition (CVD) process at a deposition temperature of 600℃-650℃. The polycrystalline silicon layer A fills the active region trench 200 and extends 1μm-2μm beyond the arrangement surface. Polysilicon layer A is ground using a chemical mechanical planarization (CMP) process (grinding pressure 3psi-5psi, grinding rate 1000Å / min-1500Å / min) to form polysilicon layer B, the surface of polysilicon layer B being flush with the arrangement plane 110. The polysilicon layer B was partially etched using an inductively coupled plasma dry etching process (the etching gas was a mixture of SF6 and O2 with a volume ratio of 3:1) to obtain the source polysilicon layer 400.

[0028] This implementation employs a step-by-step molding process to fabricate the source polysilicon layer 400, ensuring that the polysilicon structure fully fills the bottom of the active region trench 200, thus providing a reliable support for the subsequent formation of the inter-gate oxide layer. First, chemical vapor deposition (CVD) completes the overall filling of the polysilicon material, with excess material extending outwards to cover the arrangement surface 110, thoroughly eliminating voids within the trench and ensuring the integrity of the substrate structure. Subsequently, a chemical mechanical planarization (CMP) process is used to grind and level the surface polysilicon layer, using stable process parameters to remove surface protrusions and achieve a large-scale surface smoothness. On this basis, inductively coupled plasma dry etching (ICP-D) is used for fine leveling, uniformly smoothing any remaining micro-undulations and local unevenness after grinding. The combined effect of these two leveling processes significantly improves the surface smoothness of the source polysilicon layer 400, avoiding the adverse effects of substrate surface irregularities and preventing uneven oxide layer thickness distribution during subsequent dielectric deposition. This continuously ensures the adhesion and stability of the interlayer structure within the active region trench 200, meeting the requirements for continuous fabrication of subsequent multilayer dielectric structures.

[0029] In some specific embodiments, the distance between the source polysilicon layer 400 and the arrangement surface 110 is 0.5 μm-2 μm. In this specific embodiment of the present application, the distance between the source polysilicon layer 400 and the arrangement surface 110 is 1 μm.

[0030] In some specific embodiments, the first silicon dioxide layer 300 on the surface of the sidewall of the active region trench 200 is selectively etched using a plasma dry etching process (the corners can be masked with a photoresist mask, and the etching is removed by a plasma ashing process after etching). The etching gas is a mixture of CF4 and O2 with a volume ratio of (2-4):1, the etching power is 600W-1000W, and the etching pressure is 8mTorr-12mTorr.

[0031] like Figure 5 As shown, in some specific embodiments, the thickness of the first silicon dioxide layer 300 on the surface of the active region trench 200 sidewall is A1, and the length of the retention portion 310 is A2, satisfying: 0.1μm≤A2-A1≤0.3μm. This region is precisely the core location where the electric field is easily concentrated under high voltage conditions. By reasonably controlling the size difference between the retention portion 310 and the first silicon dioxide layer 300 on the sidewall surface, the target area requiring differentiated thickening can be precisely locked, ensuring that the subsequent thermal oxidation treatment can be targeted at the high-stress electric field area in the corner region. The oxide layer is thickened and strengthened only within this limited range, while the remaining non-critical areas of the sidewall maintain the original thin-layer structure. This can effectively alleviate the electric field concentration phenomenon at the location of the corner deposition block 320, improve the local insulation tolerance, and maintain the reasonable ratio of the overall oxide layer structure of the trench, avoiding structural redundancy and negative performance effects caused by large-scale thickening, and further adapting to the working environment requirements of MOS devices (high-voltage MOS devices). In this specific embodiment of the application, A1 is 1000 Å, A2 is 0.2 μm, and satisfies 0.1 μm ≤ A2 - A1 ≤ 0.3 μm.

[0032] In some specific embodiments, the parameters of the plasma chemical vapor deposition are: deposition pressure 5 mTorr-20 mTorr, RF power 1000 W-2000 W, deposition temperature 350 °C-450 °C, and deposition rate 50 Å / min-150 Å / min. In this specific embodiment of the present application, the deposition pressure is 10 mTorr, the RF power is 1500 W, the deposition temperature is 400 °C, and the deposition rate is 100 Å / min.

[0033] In some specific embodiments, the wet etching process includes the following steps: The semiconductor silicon substrate 100, after the second silicon dioxide layer 500 has been deposited, is immersed in an aqueous solution of hydrofluoric acid for 5-10 minutes. The volume ratio of hydrofluoric acid to water in the aqueous solution of hydrofluoric acid is 1:(80-120).

[0034] In this specific embodiment of the application, the soaking time is 10 minutes, and the volume ratio of hydrofluoric acid to water in the aqueous solution of hydrofluoric acid is 1:100.

[0035] In some specific embodiments, the temperature of the second thermal oxidation treatment is 900℃-1100℃, and the second thermal oxidation treatment uses alternating dry oxygen atmosphere and wet oxygen atmosphere (for example, 30 minutes in dry oxygen atmosphere and 15 minutes in wet oxygen atmosphere constitute one alternation cycle), and the time of the second thermal oxidation treatment is 30 minutes-120 minutes. The alternation of dry and wet oxygen atmospheres allows the dry oxygen atmosphere to improve the density of the oxide layer, ensuring its insulation performance and structural stability, while the wet oxygen atmosphere effectively alleviates the internal stress generated during oxide layer growth, reducing stress accumulation. Combined with the surface smoothing effect of the oxide layer brought about by the previous wet etching process, crack defects caused by stress concentration in the oxide layer can be completely avoided, significantly improving the reliability of the inter-gate oxide layer. Meanwhile, compared to the existing technology where overall thermal oxidation requires 2-4 hours, this specific embodiment significantly shortens the heat treatment time, reduces the thermal budget, minimizes the adverse effects of high-temperature processes on device structure, and lowers fabrication energy consumption and production costs. While ensuring the 320 thickening effect of the corner deposition block, it achieves dual optimization of process efficiency and device performance, further enhancing the practicality and economy of the entire fabrication method. In this specific embodiment of the application, the temperature of the second thermal oxidation treatment is 1000℃, and the time of the second thermal oxidation treatment is 90 minutes (30 minutes in dry oxygen atmosphere, 15 minutes in wet oxygen atmosphere, 30 minutes in dry oxygen atmosphere, 15 minutes in wet oxygen atmosphere, two alternating cycles).

[0036] In some specific embodiments, after the second thermal oxidation treatment, the thickness ratio of the second silicon dioxide layer 500 on the surface of the retained portion 310 and the sidewall of the active region trench 200 is (1.5-2.5):1. This value range can stably achieve a differentiated thickening layout of the oxide layer at the trench corner deposition block 320, and optimize the electric field distribution at the trench corner deposition block 320 by relying on reasonable thickness differences, effectively improving the phenomenon of local electric field accumulation. By thickening the oxide layer at the key position of the corner deposition block 320, the electric field intensity at this position can be significantly weakened, making the electric field distribution of the overall structure more uniform and reducing the structural damage caused by excessive local field strength under high voltage operating conditions. This ratio, while maintaining the stability of the surface structure of the trench sidewall, specifically strengthens the protective capability of the corner deposition block 320, improves the high voltage bearing capacity of the device from the structural level, and ensures the long-term operational stability of the device. In this specific embodiment of the present application, after the second thermal oxidation treatment, the thickness ratio of the second silicon dioxide layer 500 on the surface of the retaining portion 310 and the sidewall of the active region trench 200 is 2:1.

[0037] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature.

[0038] The above description is only a preferred embodiment of this application. It should be noted that those skilled in the art can make several improvements and additions without departing from the method of this application, and these improvements and additions should also be considered within the scope of protection of this application.

Claims

1. A method for fabricating a MOS device, characterized in that, Includes the following steps: Obtain a semiconductor silicon substrate, with one side of the semiconductor silicon substrate serving as an arrangement surface, and form an active region trench on the arrangement surface by etching. A first silicon dioxide layer is formed at the bottom of the active region trench and on the surface of the four sidewalls by a first thermal oxidation process, and then a source polysilicon layer is formed in the active region trench, wherein the source polysilicon layer does not extend beyond the arrangement surface. The first silicon dioxide layer on the surface of the sidewall is locally etched. After the first silicon dioxide layer on the surface of each sidewall is etched, a retention portion is retained at least at both ends. Two adjacent retention portions are connected and form a corner deposition block in the active area trench. A second silicon dioxide layer is formed in the active region trench by plasma chemical vapor deposition. The second silicon dioxide layer fills the active region trench and is flush with the arrangement surface. Then, wet etching and second thermal oxidation processes are performed in sequence. The corner deposition block and the second silicon dioxide layer constitute an inter-gate oxide layer, and the source, drain and gate are formed based on the inter-gate oxide layer to obtain the MOS device.

2. The method for fabricating a MOS device according to claim 1, characterized in that, The thickness of the first silicon dioxide layer on the surface of the active region trench sidewall is A1, and the length of the retained portion is A2, satisfying: 0.1μm≤A2-A1≤0.3μm.

3. The method for fabricating a MOS device according to claim 1, characterized in that, After the second thermal oxidation treatment, the thickness ratio of the second silicon dioxide layer on the surface of the retained part and the active area trench sidewall is (1.5-2.5):

1.

4. The method for fabricating a MOS device according to claim 1, characterized in that, The depth of the active region trench is 1μm-10μm, and the opening width of the active region trench is 0.2μm-1.8μm.

5. The method for fabricating a MOS device according to claim 1, characterized in that, The thickness of the first silicon dioxide layer is 500 Å-2000 Å.

6. The method for fabricating a MOS device according to claim 1, characterized in that, The distance between the source polycrystalline silicon layer and the arrangement surface is 0.5μm-2μm.

7. The method for fabricating a MOS device according to claim 1, characterized in that, The parameters for plasma chemical vapor deposition are: deposition pressure 5 mTorr-20 mTorr, RF power 1000 W-2000 W, deposition temperature 350 °C-450 °C, and deposition rate 50 Å / min-150 Å / min.

8. The method for fabricating a MOS device according to claim 1, characterized in that, The wet etching process includes the following steps: Immerse the semiconductor silicon substrate with the second silicon dioxide layer deposited into an aqueous solution of hydrofluoric acid for 5-10 minutes. The volume ratio of hydrofluoric acid to water in the aqueous solution of hydrofluoric acid is 1:(80-120).

9. The method for fabricating a MOS device according to claim 1, characterized in that, The temperature of the second thermal oxidation treatment is 900℃-1100℃, and the second thermal oxidation treatment uses alternating dry oxygen atmosphere and wet oxygen atmosphere. The time of the second thermal oxidation treatment is 30min-120min.

10. A MOS device, characterized in that, The MOS device is prepared by the method according to any one of claims 1-9.

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