A MOSFET fabrication process with high bvdss
Patent Information
- Application Number
- CN202611046233.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-14
- Publication Date
- 2026-09-22
AI Technical Summary
然而现有方案中，外延层优化会导致Rdson升高(厚度增加、掺杂降低，漂移区电阻增大)；其次传统超级结技术存在N/P柱掺杂不均、耗尽层扩展不完全、高频场景下损耗较大、芯片成本较高等问题，为此特提供一种具有高bvdss的MOSFET制造工艺
1、该具有高bvdss的MOSFET制造工艺，采用四段式梯度外延层结构，由衬底侧高掺杂过渡薄层、中间低掺杂核心耐压厚层、栅极侧中掺杂衔接薄层组成，并在核心耐压层边缘设置N型浅掺杂凹槽，通过厚度与掺杂的动态梯度分布拓宽耗尽区扩展空间、分散边缘电场集中，在大幅提升BVdss的同时，降低外延层整体电阻，有效缓解传统均匀外延耐压提升与导通电阻增大的固有矛盾。
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Figure CN122803316A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor processing technology, and in particular to a MOSFET manufacturing process with high bvdss. Background Technology
[0002] Drain-source breakdown voltage (bvdss) is a critical limiting parameter in semiconductor devices such as power MOSFETs. It mainly represents the maximum voltage that the drain and source of a MOSFET can withstand when the gate-source voltage is zero. Exceeding this voltage will cause the device to enter a breakdown state, which may lead to irreversible damage. Therefore, improving the bvdss of a MOSFET is crucial for MOSFET design.
[0003] However, for planar IOSFETs, the breakdown voltage is mainly borne by the low-doped, high-resistivity epitaxial layer. Its thickness and doping concentration directly determine the breakdown voltage capability. Increasing the thickness of the epitaxial layer provides a wider space for the expansion of the depletion region, while reducing the doping concentration of the epitaxial layer makes the depletion region easier to expand and reduces the peak electric field strength. Secondly, by arranging N-type and P-type pillars alternately in the vertical direction, a low-resistance channel is provided when conducting and they deplete each other when turning off, forming a near-ideal rectangular electric field distribution. This breaks through the traditional "silicon limit" and allows the use of thinner, higher-doped epitaxial layers at the same breakdown voltage, thereby significantly improving Bvdss while significantly reducing Rdson. However, in existing solutions, epitaxial layer optimization leads to an increase in Rdson (increased thickness, reduced doping, and increased drift region resistance); secondly, traditional superjunction technology has problems such as uneven N / P pillar doping, incomplete depletion layer expansion, high loss in high-frequency scenarios, and high chip cost. Therefore, a MOSFET manufacturing process with high bvdss is provided. Summary of the Invention
[0004] The purpose of this invention is to provide a MOSFET manufacturing process with high bvdss to solve the problems mentioned in the background art.
[0005] To achieve the above objectives, the present invention provides the following technical solution: a MOSFET manufacturing process with high bvdss, comprising the following steps: S1. Optimize the epitaxial layer thickness and doping concentration, including: S11, the gradient epitaxial layer thickness dynamic matching design adopts a four-segment gradient structure of "substrate + transition thin layer + core withstand voltage thick layer + gate connection thin layer", which provides a wider space for the expansion of the depletion region; S12. The gradient control of doping concentration is precisely controlled and matched with the four-segment gradient structure of the epitaxial layer thickness. A dynamic doping gradient of "high-medium-low-medium" is adopted to accurately calculate the doping concentration threshold of each layer. S13. Coordinated regulation of depletion region expansion: An adjustable P-type transition layer structure is adopted, and the doping concentration of this layer is flexibly adjusted according to the target BVdss accuracy requirements; combined with a temperature and voltage coordinated adaptive regulation mechanism, the obstruction to carrier transport is reduced, and the increase in conduction loss is avoided. S2. The superjunction structure is optimized by adopting a composite structure of vertical N / P pillars and horizontal P-type doped strips to further improve the drain-source breakdown voltage. S3. Synergistic optimization of epitaxial layer and superjunction: By using the core voltage-resistant thick layer of epitaxial layer as the bottom voltage-resistant substrate of superjunction, the structure of vertical N / P pillars + horizontal P-type doped strips is directly prepared on the gate connection layer of gradient epitaxial layer to ensure interface bonding between the two without lattice mismatch.
[0006] Preferably, in step S11, in the four-segment gradient structure, the thickness of the transition thin layer is 0.75 μm to alleviate the lattice mismatch between the substrate and the core layer; the thickness of the core withstand voltage thick layer is designed to be 10 μm to bear the main withstand voltage requirements and provide sufficient space for the lateral and vertical expansion of the depletion region; the thickness of the gate connection thin layer is 0.5 μm to match the interface characteristics of the gate oxide layer and reduce the gate-drain parasitic capacitance.
[0007] Preferably, in step S12, the doping concentration of the transition thin layer is 1e17-5e17. This ensures rapid carrier transport; the core voltage-resistant thick layer has a doping concentration of 1e15-5e15. The electric field peak is reduced and the depletion region is expanded by low doping characteristics; the doping concentration of the gate bonding thin layer is 5e16-1e17. This matches the gate operating characteristics and reduces carrier transport resistance.
[0008] Preferably, the core withstand voltage thick layer adopts a micro-gradient design with a thicker middle and thinner edges to avoid electric field concentration caused by the shrinkage of the depletion layer in the edge region, further improving the stability of BVdss and reducing the risk of breakdown and leakage.
[0009] Preferably, in step S12, when doping each layer, an "in-situ doping + segmented ion implantation control" process is adopted. The flow rate of the doping source is adjusted in real time during the epitaxial growth process to achieve a continuous gradient change in doping concentration, avoid interface abrupt changes caused by segmented doping, reduce carrier scattering, and further reduce Rdson. At the same time, secondary ion mass spectrometry detection is used to ensure that the doping concentration gradient error is controlled within +5%.
[0010] Preferably, in step S13, the adjustable P-type transition layer structure adopts a layered adjustable design, dividing the transition layer into upper and lower layers. The lower layer, closer to the core withstand voltage layer, uses low-doped P-type with a concentration of 5e15-1e16. This is used to guide the initial expansion of the depletion region and avoid abrupt changes in the electric field at the interface between the core layer and the transition layer. The upper layer near the gate connection layer adopts an adjustable hybrid structure. By adjusting the doping concentration of this layer according to the target BVdss accuracy requirements through a local ion implantation fine-tuning process after epitaxial growth, the expansion range of the depletion region can be accurately calibrated.
[0011] Preferably, in step S13, the temperature and voltage coordinated adaptive control mechanism introduces a "depletion region dynamic compensation structure" by embedding an extremely thin thermistor doped unit (thickness 0.05-0.1 μm, doped with thermistor semiconductor material) in the P-type transition layer. The doping concentration of this unit can be automatically adjusted with the change of device operating temperature. When the temperature rises (e.g., exceeding 125°C), the doping concentration of the thermistor unit increases slightly, enhancing the guiding effect on the depletion region and offsetting the effect of depletion region shrinkage at high temperatures. When the operating voltage fluctuates (e.g., below 80% of the rated voltage), the doping concentration of the thermistor unit decreases, reducing the obstruction to carrier transport and avoiding increased conduction losses.
[0012] Preferably, in step S13, a "local shallow implantation" process is used in the edge region of the core withstand voltage thick layer to form a tiny N-type doped groove (depth 0.2-0.3 μm, concentration 1e15 cm-3), which forms an "edge electric field shunt structure" with the P-type transition layer. This disperses the electric field of the edge set to the groove region, avoiding breakdown caused by excessively high local electric fields. This reduces the edge breakdown probability of the device by more than 60%, further offsetting the effect of depletion region shrinkage at high temperatures.
[0013] Preferably, in step S2, a combination of "ion implantation + in-situ doping" is used to precisely control the doping concentration and distribution uniformity of the N / P pillars, reduce doping defects, and lower the risk of device breakdown and leakage. At the same time, an insulating isolation layer (such as a SiO2 / SIN composite layer) is introduced between the N / P pillars to reduce the parasitic capacitance between the N / P pillars and reduce switching losses in high-frequency scenarios.
[0014] Preferably, in step S3, the process is performed in the following order: "gradient epitaxial growth → composite superjunction preparation → synergistic fine-tuning". First, the gradient epitaxial layer growth (four-segment structure + gradient doping) is completed, reserving the interface for superjunction preparation. Then, on the gate junction layer (medium-doped N-type) of the gradient epitaxial layer, a composite superjunction (vertical N / P0 pillars + lateral P-type doped strips) is prepared using an "ion implantation + in-situ doping" process to ensure uniform doping of the N / P pillars. Finally, through "local ion implantation fine-tuning", the doping concentration of the upper layer of the P-type transition layer is adjusted to meet the depletion region expansion requirements of the superjunction, achieving functional synergy between the two. The doping concentration of the core voltage-resistant thick layer of the gradient epitaxial layer is (1e15-5e15). The doping concentration of the N / P pillars of the composite superjunction is matched (the N pillars are slightly higher than the core layer, and the P pillars are adapted to the transition layer) to form the gate connection layer (medium doping) of the "dual withstand voltage" gradient epitaxial layer. This layer is linked with the P-type doping strip of the superjunction to guide the depletion region to expand from both the core layer (gradient epitaxy) and the N / P pillars (composite superjunction) at the same time, achieving uniform coverage.
[0015] The technical effects and advantages of this invention are as follows: 1. This MOSFET manufacturing process with high BVdss adopts a four-segment gradient epitaxial layer structure, consisting of a highly doped transition thin layer on the substrate side, a low-doped core withstand voltage thick layer in the middle, and a medium-doped connecting thin layer on the gate side. An N-type shallow doped groove is set at the edge of the core withstand voltage layer. By widening the depletion region expansion space and dispersing the concentrated edge electric field through the dynamic gradient distribution of thickness and doping, the overall resistance of the epitaxial layer is reduced while significantly improving BVdss. This effectively alleviates the inherent contradiction between the improvement of withstand voltage and the increase of on-resistance in traditional uniform epitaxial layers.
[0016] 2. This MOSFET manufacturing process with high BVdss introduces an adjustable layered P-type transition layer between the core breakdown layer and the gate junction layer. The lower layer is a fixed low-doped P-type layer that guides the initial expansion of the depletion region, while the upper layer is a process-adjustable doped layer with built-in thermistor doping units. This allows for precise calibration of the depletion region between process batches through ion implantation and adaptive compensation for depletion region morphology shifts under high-temperature conditions. This makes the device's BVdss more stable across the entire temperature and voltage range, while also avoiding premature breakdown caused by back-end electric field spikes.
[0017] 3. This MOSFET manufacturing process with high BVdss integrates a gradient epitaxial layer with a composite superjunction with optimized trench width ratio. The superjunction adopts a vertical N / P pillar alternating structure with a top horizontal P-type doped strip. A composite insulating layer is set between the pillars. The N / P pillar trench width ratio is controlled within a preset range to meet charge balance. The gradient epitaxial layer undertakes the main breakdown voltage, and the superjunction achieves auxiliary breakdown voltage and low resistance conduction. It not only breaks through the traditional silicon limit to further improve BVdss, but also significantly reduces the on-resistance Rdson and parasitic capacitance, taking into account high breakdown voltage, low loss and high frequency application performance. Attached Figure Description
[0018] Figure 1 This is a flowchart of the MOSFET manufacturing process of the present invention; Figure 2 This is a schematic diagram of a MOSFET manufactured using the MOSFET manufacturing process of this invention. Detailed Implementation
[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0020] This invention provides, for example Figures 1-2 The illustrated MOSFET manufacturing process includes the following steps: S1. Optimize the epitaxial layer thickness and doping concentration, including: S11, the gradient epitaxial layer thickness dynamic matching design adopts a four-segment gradient structure of "substrate + transition thin layer + core withstand voltage thick layer + gate connection thin layer", which provides a wider space for the expansion of the depletion region; S12. The gradient control of doping concentration is precisely controlled and matched with the four-segment gradient structure of the epitaxial layer thickness. A dynamic doping gradient of "high-medium-low-medium" is adopted to accurately calculate the doping concentration threshold of each layer. S13. Coordinated regulation of depletion region expansion: An adjustable P-type transition layer structure is adopted, and the doping concentration of this layer is flexibly adjusted according to the target BVdss accuracy requirements; combined with a temperature and voltage coordinated adaptive regulation mechanism, the obstruction to carrier transport is reduced, and the increase in conduction loss is avoided. S2. The superjunction structure is optimized by adopting a composite structure of vertical N / P pillars and horizontal P-type doped strips to further improve the drain-source breakdown voltage. S3. Synergistic optimization of epitaxial layer and superjunction: By using the core voltage-resistant thick layer of epitaxial layer as the bottom voltage-resistant substrate of superjunction, the structure of vertical N / P pillars + horizontal P-type doped strips is directly prepared on the gate connection layer of gradient epitaxial layer to ensure interface bonding between the two without lattice mismatch.
[0021] In step S11, in the four-segment gradient structure, the thickness of the transition thin layer is 0.75um to alleviate the lattice mismatch between the substrate and the core layer; the thickness of the core withstand voltage thick layer is designed to be 10um to bear the main withstand voltage requirements and provide sufficient space for the lateral and vertical expansion of the depletion region; the thickness of the gate connection thin layer is 0.5um to match the interface characteristics of the gate oxide layer and reduce the gate-drain parasitic capacitance.
[0022] In step S12, the doping concentration of the transition thin layer is 1e17-5e17. This ensures rapid carrier transport; the core voltage-resistant thick layer has a doping concentration of 1e15-5e15. The electric field peak is reduced and the depletion region is expanded by low doping characteristics; the doping concentration of the gate bonding thin layer is 5e16-1e17. This matches the gate operating characteristics and reduces carrier transport resistance.
[0023] The core withstand voltage thick layer adopts a micro-gradient design with a thicker middle and thinner edges to avoid electric field concentration caused by the shrinkage of the depletion layer in the edge area, further improving the stability of BVdss and reducing the risk of breakdown and leakage.
[0024] In step S12, when doping each layer, the "in-situ doping + segmented ion implantation" process is adopted. The flow rate of the doping source is adjusted in real time during the epitaxial growth process to achieve a continuous gradient change in doping concentration, avoid interface abrupt changes caused by segmented doping, reduce carrier scattering, and further reduce Rdson. At the same time, secondary ion mass spectrometry detection is used to ensure that the doping concentration gradient error is controlled within +5%.
[0025] In step S13, the adjustable P-type transition layer structure adopts a layered adjustable design, dividing the transition layer into upper and lower layers. The lower layer, closer to the core withstand voltage layer, uses low-doped P-type with a concentration of 5e15-1e16. This is used to guide the initial expansion of the depletion region and avoid abrupt changes in the electric field at the interface between the core layer and the transition layer. The upper layer near the gate connection layer adopts an adjustable hybrid structure. By adjusting the doping concentration of this layer according to the target BVdss accuracy requirements through a local ion implantation fine-tuning process after epitaxial growth, the expansion range of the depletion region can be accurately calibrated.
[0026] In step S13, the temperature and voltage coordinated adaptive control mechanism introduces a "depletion region dynamic compensation structure" by embedding an extremely thin thermistor doped unit (thickness 0.05-0.1um, doped with thermistor semiconductor material) in the P-type transition layer. The doping concentration of this unit can be automatically adjusted with the device operating temperature: when the temperature rises (e.g., above 125°C), the doping concentration of the thermistor unit increases slightly, enhancing the guiding effect on the depletion region and offsetting the effect of depletion region shrinkage at high temperatures; when the operating voltage fluctuates (e.g., below 80% of the rated voltage), the doping concentration of the thermistor unit decreases, reducing the obstruction to carrier transport and avoiding increased conduction losses.
[0027] In step S13, a tiny N-type doped groove (depth 0.2-0.3 μm, concentration 1e15 cm-3) is formed in the edge region of the core withstand voltage thick layer by using a "local shallow implantation" process. This groove forms an "edge electric field shunt structure" with the P-type transition layer, dispersing the electric field of the edge set to the groove region. This avoids breakdown caused by excessively high local electric fields, reducing the edge breakdown probability of the device by more than 60%, and further offsetting the effect of depletion region shrinkage at high temperatures.
[0028] In step S2, a combination of "ion implantation + in-situ doping" is used to precisely control the doping concentration and distribution uniformity of the N / P pillars, reduce doping defects, and lower the risk of device breakdown and leakage. At the same time, an insulating isolation layer (such as a Si0x / SIN composite layer) is introduced between the N / P pillars to reduce the parasitic capacitance between the N / P pillars and reduce switching losses in high-frequency scenarios.
[0029] In step S3, the process is executed in the following order: "gradient epitaxial growth → composite superjunction fabrication → synergistic fine-tuning". First, the gradient epitaxial layer growth (four-segment structure + gradient doping) is completed, reserving the interface for superjunction fabrication. Then, on the gate junction layer (medium-doped N-type) of the gradient epitaxial layer, a composite superjunction (vertical N / P0 pillars + lateral P-type doped strips) is fabricated using an "ion implantation + in-situ doping" process to ensure uniform doping of the N / P pillars. Finally, through "local ion implantation fine-tuning", the doping concentration of the upper layer of the P-type transition layer is adjusted to adapt to the depletion region expansion requirements of the superjunction, achieving functional synergy between the two. The doping concentration of the core voltage-resistant thick layer of the gradient epitaxial layer is (1e15-5e15). The doping concentration of the N / P pillars of the composite superjunction is matched (the N pillars are slightly higher than the core layer, and the P pillars are adapted to the transition layer) to form the gate connection layer (medium doping) of the "dual withstand voltage" gradient epitaxial layer. This layer is linked with the P-type doping strip of the superjunction to guide the depletion region to expand from both the core layer (gradient epitaxy) and the N / P pillars (composite superjunction) to achieve uniform coverage.
[0030] Working Principle: This scheme employs a four-segment gradient epitaxial layer structure. From the substrate upwards, the device sequentially consists of a highly doped transition thin layer, a low-doped core withstand voltage thick layer, an adjustable P-type transition layer, and a medium-doped gate connection thin layer. Simultaneously, an N-type shallow-doped groove structure is introduced at the edge region of the core withstand voltage layer. Through a dynamic gradient distribution of thickness and doping concentration along the longitudinal direction, more sufficient expansion space is provided for the depletion region, effectively suppressing abrupt changes in the interface electric field and edge electric field concentration problems, significantly improving the device's BVdss. At the same time, it takes into account the requirement of low on-resistance, fundamentally alleviating the inherent contradiction between the improvement of withstand voltage and the deterioration of on-resistance in traditional uniform epitaxial structures, and improving the overall withstand voltage reliability of the device. An adjustable layered P-type transition layer is set between the core withstand voltage layer and the gate junction thin layer. This structure is divided into a fixed low-doped lower layer and a process-adjustable doped upper layer, and a thermistor doped unit is embedded inside. The lower layer is used to stably guide the uniform expansion of the depletion region, and the upper layer can achieve precise adjustment of doping concentration through subsequent ion implantation to compensate for the process deviation of epitaxial batches. At the same time, the thermistor can adaptively adjust the morphology of the depletion region with the change of operating temperature, offsetting the withstand voltage drift caused by the shrinkage of the depletion region at high temperature, so that the device maintains high stability of BVdss in the entire temperature range and the entire voltage operating range, avoiding premature breakdown caused by local electric field spikes, and significantly improving the durability of the device under high temperature and high voltage conditions.
[0031] The gradient epitaxial substrate is synergistically integrated with an optimized composite superjunction structure. The superjunction adopts a vertically alternating N / P pillar structure with a slot width ratio controlled at 1:1 to 1.2:1 to achieve precise charge balance. A SiO2 / SiN composite insulating layer is added between the pillars to reduce parasitic capacitance, and a transverse P-type doped strip is set at the top of the N / P pillars to accelerate the lateral expansion of the depletion region. The gradient epitaxial layer bears the main breakdown voltage, while the superjunction structure provides auxiliary breakdown voltage and a low-resistance conduction channel. The synergistic effect of the two further breaks through the breakdown voltage limit of traditional silicon materials, significantly improving BVdss while significantly reducing the on-resistance Rdson and reducing switching losses. This enables the device to simultaneously possess high breakdown voltage, low loss, and excellent high-frequency adaptability.
[0032] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A MOSFET manufacturing process with high bvdss, characterized in that... Includes the following steps: S1. Optimize the epitaxial layer thickness and doping concentration, including: S11, the gradient epitaxial layer thickness dynamic matching design adopts a four-segment gradient structure of "substrate + transition thin layer + core withstand voltage thick layer + gate connection thin layer", which provides a wider space for the expansion of the depletion region; S12. The gradient control of doping concentration is precisely controlled and matched with the four-segment gradient structure of the epitaxial layer thickness. A dynamic doping gradient of "high-medium-low-medium" is adopted to accurately calculate the doping concentration threshold of each layer. S13. Coordinated regulation of depletion region expansion: An adjustable P-type transition layer structure is adopted, and the doping concentration of this layer is flexibly adjusted according to the target BVdss accuracy requirements; combined with a temperature and voltage coordinated adaptive regulation mechanism, the obstruction to carrier transport is reduced, and the increase in conduction loss is avoided. S2. The superjunction structure is optimized by adopting a composite structure of vertical N / P pillars and horizontal P-type doped strips to further improve the drain-source breakdown voltage. S3. Synergistic optimization of epitaxial layer and superjunction: By using the core voltage-resistant thick layer of epitaxial layer as the bottom voltage-resistant substrate of superjunction, the structure of vertical N / P pillars + horizontal P-type doped strips is directly prepared on the gate connection layer of gradient epitaxial layer to ensure interface bonding between the two without lattice mismatch.
2. The MOSFET manufacturing process with high bvdss according to claim 1, characterized in that, In step S11, in the four-segment gradient structure, the thickness of the transition thin layer is 0.75um to alleviate the lattice mismatch between the substrate and the core layer; the thickness of the core withstand voltage thick layer is designed to be 10um to bear the main withstand voltage requirements and provide sufficient space for the lateral and vertical expansion of the depletion region; the thickness of the gate connection thin layer is 0.5um to match the interface characteristics of the gate oxide layer and reduce the gate-drain parasitic capacitance.
3. The MOSFET manufacturing process with high bvdss according to claim 2, characterized in that, In step S12, the doping concentration of the transition thin layer is 1e17-5e17. This ensures rapid carrier transport; the core voltage-resistant thick layer has a doping concentration of 1e15-5e15. The electric field peak is reduced and the depletion region is expanded by low doping characteristics; the doping concentration of the gate bonding thin layer is 5e16-1e17. This matches the gate operating characteristics and reduces carrier transport resistance.
4. The MOSFET manufacturing process with high bvdss according to claim 1, characterized in that, The core high-voltage thick layer adopts a micro-gradient design with a thicker middle and thinner edges to avoid electric field concentration caused by the shrinkage of the depletion layer in the edge region, thereby further improving the stability of BVdss and reducing the risk of breakdown and leakage.
5. A MOSFET manufacturing process with high bvdss according to claim 4, characterized in that, In step S12, when doping each layer, the "in-situ doping + segmented ion implantation" process is adopted. The flow rate of the doping source is adjusted in real time during the epitaxial growth process to achieve a continuous gradient change in doping concentration, avoid interface abrupt changes caused by segmented doping, reduce carrier scattering, and further reduce Rdson.
6. The MOSFET manufacturing process with high bvdss according to claim 1, characterized in that, In step S13, the adjustable P-type transition layer structure adopts a layered adjustable design, dividing the transition layer into upper and lower layers. The lower layer, near the core withstand voltage layer, uses a low-doped P-type with a concentration of 5e15-1e16. This is used to guide the initial expansion of the depletion region and avoid abrupt changes in the electric field at the interface between the core layer and the transition layer. The upper layer near the gate junction layer adopts an adjustable heterostructure. By adjusting the doping concentration of this layer according to the target BVdss accuracy requirements through a local ion implantation fine-tuning process after epitaxial growth, the depletion region expansion range can be accurately calibrated.
7. A MOSFET manufacturing process with high bvdss according to claim 6, characterized in that, In step S13, the temperature and voltage coordinated adaptive control mechanism introduces a "depletion region dynamic compensation structure" by embedding an extremely thin thermistor doped unit (0.05-0.1 μm thick, doped with thermistor semiconductor material) in the P-type transition layer. The doping concentration of this unit can be automatically adjusted with the change of device operating temperature. When the temperature rises, the doping concentration of the thermistor unit increases slightly, enhancing the guiding effect on the depletion region and offsetting the effect of depletion region shrinkage at high temperature. When the operating voltage fluctuates, the doping concentration of the thermistor unit decreases, reducing the obstruction to carrier transport and avoiding an increase in conduction loss.
8. A MOSFET manufacturing process with high bvdss according to claim 7, characterized in that, In step S13, a "local shallow injection" process is used in the edge region of the core withstand voltage thick layer to form a tiny N-type doped groove, which forms an "edge electric field shunt structure" with the P-type transition layer, dispersing the electric field of the edge set to the groove region and avoiding breakdown caused by excessive local electric field.
9. A MOSFET manufacturing process with high bvdss according to claim 8, characterized in that, In step S2, a combination of "ion implantation + in-situ doping" is used to precisely control the doping concentration and distribution uniformity of the N / P pillars, reduce doping defects, and lower the risk of device breakdown and leakage. At the same time, an insulating isolation layer is introduced between the N / P pillars to reduce the parasitic capacitance between the N / P pillars.
10. A MOSFET manufacturing process with high bvdss according to claim 9, characterized in that, In step S3, firstly, the gradient epitaxial layer is grown, reserving an interface for superjunction fabrication; then, a composite superjunction is fabricated on the gate junction layer of the gradient epitaxial layer using an "ion implantation + in-situ doping" process to ensure uniform doping of the N / P pillars; finally, the doping concentration of the upper layer of the P-type transition layer is adjusted through "local ion implantation fine-tuning" to adapt to the depletion region expansion requirements of the superjunction, achieving functional synergy between the two, and the doping concentration of the core voltage-resistant thick layer of the gradient epitaxial layer (1e15-5e15) is adjusted. The doping concentration of the N / P pillars of the composite superjunction is matched to form a "dual breakdown voltage". The gate connection layer of the gradient epitaxial layer is linked with the P-type doping strip of the superjunction to guide the depletion region to expand from the core layer and the N / P pillar at the same time, so as to achieve uniform coverage.