High temperature high voltage ldmos device and method based on thin silicon film soi process
Patent Information
- Application Number
- CN202611242170.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-17
- Publication Date
- 2026-09-22
AI Technical Summary
在深井钻头探测系统(工作温度＞200℃)、航空发动机电子控制系统(工作温度＞200℃)、新能源汽车刹车系统(工作温度＞175℃)、汽车发动机ECU系统(工作温度150℃→175℃)等恶劣高温环境下，传统的半导体器件性能受到严重挑战，主要表现为阈值电压移动、漏电增加、击穿电压降低，严重时会导致电路的失效
本发明针对现有体硅工艺LDMOS器件在高温应用的不足，综合考虑LDMOS器件高温失效机理，结合薄硅膜SOI CMOS器件的特点，本发明创新性的通过使用薄硅膜SOI CMOS工艺，采用源极和体接触区域交叉设计，在源漏离子注入工艺中将离子浓度扩散到BOX层上方(源漏注入到底的工艺)，在漂移区工艺中通过两次横向注入和三次纵向注入将漂移区离子浓度扩散至BOX层上方(漂移区注入到底工艺)，将源极、漏极和体接触区的P型硅膜层全部改性为高掺杂区域，将漂移区的P型硅膜层全部改性为漂移区注入一区和漂移区注入二区，从而实现了充分的体接触、并减小器件中PN结面积并改变横向电场分布，实现器件击穿电压改善，器件高温下漏电流降低，器件耐高温性能提升的效果，可工作在-55℃~225℃宽温区环境中，工作电压可至45V，器件击穿电压超过60V，在225℃高温下器件漏电流小于1nA/μm，可应用于功率放大、电源转换和功率管理等电路中，满足电路对高温、宽温区、高压器件的设计及制造需求。
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Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a high-temperature, high-voltage LDMOS device and method based on thin silicon film SOI process. Background Technology
[0002] LDMOS high-voltage devices are widely used power semiconductor devices. Power semiconductor devices possess capabilities such as frequency conversion, rectification, voltage transformation, power amplification, and power management, playing a crucial role in improving power supply, controlling electrical energy, and promoting energy conservation and environmental protection. They are essential in the fields of Smart Power Integrated Circuits (SPIC) and High Voltage Integrated Circuits (HVIC). Modern power semiconductor technology has been widely applied in various fields, from traditional industrial electronics to information and communication, computers, consumer electronics, and automotive sectors. Currently, new energy, rail transportation, automotive engines, and smart grids are becoming powerful engines for the growth of the power semiconductor market.
[0003] With the rapid development of modern electronic technology, high-temperature and high-pressure applications place increasingly stringent demands on power semiconductor devices. In harsh high-temperature environments such as deep well drill bit detection systems (operating temperature > 200℃), aero-engine electronic control systems (operating temperature > 200℃), new energy vehicle braking systems (operating temperature > 175℃), and automotive engine ECU systems (operating temperature 150℃ → 175℃), the performance of traditional semiconductor devices is severely challenged, mainly manifested as threshold voltage shift, increased leakage current, and decreased breakdown voltage, which can lead to circuit failure in severe cases.
[0004] like Figure 1 The diagram shows the structure of a traditional LDMOS device fabricated using bulk silicon technology, including a P-type well, a P+ bulk contact injection layer, an N+ source injection layer, an N+ drain injection layer, a drift region, a GOX gate oxide layer, a POLY polysilicon gate, a field oxide layer, an STI isolation trench, and a PN junction region. Due to the large contact area between the drift region and the well region, and the large area of the PN junction region, the leakage current of the device increases sharply at high temperatures, making it unable to function properly.
[0005] Therefore, there is an urgent need to propose a high-temperature, high-voltage LDMOS device and method based on thin silicon film SOI process to solve the above-mentioned technical defects. Summary of the Invention
[0006] The purpose of this invention is to provide a high-temperature and high-voltage LDMOS device and method based on thin silicon film SOI technology, so as to reduce the PN junction area in the device and change the lateral electric field distribution, thereby improving the device breakdown voltage, reducing the leakage current at high temperature, and improving the high-temperature resistance of the device, thus meeting the requirements of high-temperature and high-voltage application scenarios for LDMOS devices.
[0007] To address the aforementioned technical problems, this invention provides a method for fabricating a high-temperature, high-voltage LDMOS device based on thin-film SOI technology. The method uses a thin-film SOI wafer as a substrate, wherein the thin-film SOI wafer comprises, from bottom to top, a P-type silicon substrate layer, a buried oxide BOX layer, and a P-type silicon film layer. The method includes: By employing two transverse injections, the drift region is divided into two adjacent drift region injection zones: Drift Region Injection Zone 1 and Drift Region Injection Zone 2, in order to adjust the transverse electric field distribution. Each transverse injection includes three longitudinal injections, with the injection energy increasing sequentially from top to bottom and the injection dose decreasing sequentially from top to bottom, in order to adjust the longitudinal electric field distribution. By employing a process of bottom-drain and bottom-drift region implantation, the implanted ion concentrations on the N-type source implantation layer, N-type drain implantation layer, and drift region are diffused to the BOX buried oxide layer, thereby reducing the area of the PN region. By arranging the P-type body contact injection layer and the N-type source injection layer in a longitudinally adjacent and staggered manner, the P-type body contact injection layer and the P-type well region can achieve sufficient and effective body contact.
[0008] Preferably, the P-type well region and the drift region are formed laterally on both sides of the P-type silicon film layer, wherein the step of forming the P-type well region includes three longitudinal implantations, from top to bottom: boron implantation, boron implantation and boron fluoride implantation, and the implantation energy decreases sequentially from top to bottom.
[0009] Preferably, the steps of forming the first drift region implantation region and the second drift region implantation region each include three vertical implantations, namely phosphorus implantation, phosphorus implantation and arsenic implantation from top to bottom, to form N-type doping; and the doping concentration of the second drift region implantation region is greater than the doping concentration of the first drift region implantation region.
[0010] Preferably, the thickness of the P-type silicon film is ≤300 nm, and it is lightly doped with P-type silicon with a doping concentration of 1.5 × 10⁻⁶. 13 cm -3 ~1.5×10 15 cm -3 .
[0011] Preferably, the P-type body contact implantation layer is heavily P-type doped, and the N-type source implantation layer and the N-type drain implantation layer are heavily N-type doped.
[0012] Preferably, the thicknesses of the drift region injection region one, the drift region injection region two, the N-type source injection layer, the P-type body contact injection layer, and the N-type drain injection layer are equal to the thickness of the P-type silicon film.
[0013] Preferably, the method specifically includes: By employing photolithography and etching techniques, STI trenches are etched and deposited on the top P-type silicon film layer of the thin silicon SOI wafer to form the STI trench isolation region. The active region is defined by photolithography and then a well is implanted to form a P-type well region; The regions of drift region implantation 1 and drift region implantation 2 are defined by photolithography, and three ion implantations with different energies are performed to form drift region implantation 1 and drift region implantation 2. The silicon nitride is deposited, and the area defined by field oxygen is defined by photolithography and the silicon nitride in that area is removed by etching. A silicon dioxide layer is grown by high-temperature oxidation to form a FOX field oxygen layer; A gate oxide layer is grown by high-temperature oxidation to form the GOX gate oxide layer; A POLY gate is formed by depositing polysilicon and etching the polysilicon and gate oxide layer. The source region, drain region, and body contact region are defined by photolithography and ion implantation is performed to form an N-type source implantation layer, an N-type drain implantation layer, and a P-type body contact implantation layer. Contact holes that interconnect with aluminum metal are formed by depositing an ILD dielectric layer and etching and depositing.
[0014] Preferably, the depth of the STI groove is equal to the thickness of the P-type silicon film.
[0015] This invention also provides a high-temperature, high-voltage LDMOS device based on thin-film SOI technology, which is fabricated using the above-described method for fabricating a high-temperature, high-voltage LDMOS device based on thin-film SOI technology, comprising: Thin silicon film SOI wafer; STI trench isolation region is formed on the outer side of the top surface of the thin silicon film SOI wafer; The P-type well region and the drift region are respectively arranged on both sides of the top surface of the thin silicon film SOI wafer and are in contact with the STI trench isolation region; wherein the drift region includes a drift region injection region one and a drift region injection region two that are laterally adjacent to each other. The P-type body contact injection layer and the N-type source injection layer are arranged longitudinally adjacently and alternately in the P-type well region; The PN junction region is formed in the region where the N-type source injection layer and the drift region injection layer are in contact with the P-type well region, respectively. An N-type drain injection layer is formed in the second region of the drift region; A field oxygen FOX layer covers the surface of the drift region; The gate oxide (GOX) layer has one end covering the surface of the P-type well region between the drift region and the N-type source injection layer, and the other end partially covering the surface of the field oxide (FOX) layer. A POLY gate is used to cover the surface of the gate oxide GOX layer; An ILD dielectric layer is formed on the top surface of the thin silicon film SOI wafer; The contact holes are located inside the ILD dielectric layer. The P-type body contact injection layer, the N-type source injection layer, and the N-type drain injection layer are led out to the outside of the ILD dielectric layer and interconnected with the aluminum metal through the contact holes.
[0016] Preferably, the P-type body contact injection layer and the N-type source injection layer are arranged longitudinally adjacent to each other from front to back, and the drift region injection zone one and the drift region injection zone two are arranged laterally adjacent to each other from left to right.
[0017] Compared with the prior art, the present invention has the following beneficial effects: This invention addresses the shortcomings of existing bulk silicon LDMOS devices in high-temperature applications. Considering the high-temperature failure mechanism of LDMOS devices and combining the characteristics of thin-film silicon SOI CMOS devices, this invention innovatively utilizes a thin-film silicon SOI CMOS process with a cross-design of the source and body contact regions. In the source / drain ion implantation process, the ion concentration is diffused above the BOX layer (source / drain implantation to the bottom). In the drift region process, the ion concentration in the drift region is diffused above the BOX layer through two lateral implantations and three vertical implantations (drift region implantation to the bottom). The entire P-type silicon film layer of the source, drain, and body contact regions is modified into a highly doped region, and the entire P-type silicon film layer of the drift region is modified into drift region implantation region one and drift region implantation region two, thereby achieving full doping. By reducing the PN junction area and altering the lateral electric field distribution through partial contact, the device achieves improved breakdown voltage, reduced leakage current at high temperatures, and enhanced high-temperature performance. It can operate in a wide temperature range of -55℃ to 225℃, with an operating voltage up to 45V. The device breakdown voltage exceeds 60V, and the leakage current at 225℃ is less than 1nA / μm. It can be applied to power amplification, power conversion, and power management circuits, meeting the design and manufacturing requirements of circuits for high-temperature, wide-temperature, and high-voltage devices. Attached Figure Description
[0018] Figure 1 This is a schematic diagram of a traditional LDMOS device structure fabricated using bulk silicon technology.
[0019] Figure 2 This is a cross-sectional view of a high-temperature, high-voltage LDMOS device structure based on thin silicon film SOI technology provided by the present invention. Figure 1 .
[0020] Figure 3 This is a cross-sectional view of a high-temperature, high-voltage LDMOS device structure based on thin silicon film SOI technology provided by the present invention. Figure 2 .
[0021] Figure 4 This is a partial top view of the high-temperature, high-voltage LDMOS device structure provided by the present invention, excluding the ILD dielectric layer and the STI trench isolation region.
[0022] Figure 5 This is a graph showing the gate voltage VG-drain current ID transfer characteristics of the high-temperature, high-pressure LDMOS device implemented based on this invention at -55℃, 25℃ and 225℃.
[0023] Figure 6 This is a graph showing the drain voltage VD-drain current ID transfer characteristic curves of the high-temperature and high-voltage LDMOS device implemented based on this invention at -55℃, 25℃ and 225℃.
[0024] In the figure: 1-P-type silicon substrate layer, 2-buried oxide BOX layer, 3-P-type silicon film layer, 4-STI trench isolation region, 5-P-type body contact injection layer, 6-N-type source injection layer, 7-P-type well region, 8-PN junction region, 9-drift region injection region 1, 10-drift region injection region 2, 11-N-type drain injection layer, 12-contact hole, 13-gate oxide GOX layer, 14-POLY gate, 15-field oxide FOX layer, 16-aluminum metal, 17-ILD dielectric layer. Detailed Implementation
[0025] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0026] like Figures 2 to 6 As shown, this embodiment of the invention specifically provides a method for fabricating a high-temperature, high-voltage LDMOS device based on thin-film SOI technology. A thin-film SOI wafer is used as the substrate, and the thin-film SOI wafer includes, from bottom to top, a P-type silicon substrate layer 1, a buried oxide BOX layer 2, and a P-type silicon film layer 3. The method includes: By employing two lateral injections, the drift region is divided into adjacent drift region injection area 1 (9) and drift region injection area 2 (10) to adjust the lateral electric field distribution and increase the device's high voltage withstand performance. Each lateral injection includes three longitudinal injections, with the injection energy increasing sequentially from top to bottom and the injection dose decreasing sequentially from top to bottom to adjust the longitudinal electric field distribution and increase the device's high voltage withstand performance. By employing a process of bottom-drain and bottom-drift region implantation, the implanted ion concentrations on the N-type source implantation layer 6, the N-type drain implantation layer 11, and the drift region are diffused to the BOX buried oxide layer, thereby reducing the area of the PN region and thus reducing the leakage current of the device at high temperatures. By arranging the P-type body contact injection layer 5 and the N-type source injection layer 6 in a longitudinally adjacent and staggered manner, the P-type body contact injection layer 5 and the P-type well region 7 can achieve sufficient and effective body contact, thereby realizing stable device performance.
[0027] In a preferred embodiment, the P-type well region 7 and the drift region are respectively formed laterally on both sides of the P-type silicon film layer 3. The step of forming the P-type well region 7 includes three longitudinal implantations, which are boron implantation, boron implantation and boron fluoride implantation from top to bottom, and the implantation energy decreases from top to bottom.
[0028] In a preferred embodiment, the steps of forming the first drift region implantation region 9 and the second drift region implantation region 10 each include three vertical implantations, namely phosphorus implantation, phosphorus implantation and arsenic implantation from top to bottom, to form N-type doping; and the doping concentration of the second drift region implantation region 10 is greater than the doping concentration of the first drift region implantation region 9, so as to form a gradual change in electric field and increase the breakdown voltage of the device.
[0029] In a preferred embodiment, the P-type body contact implantation layer 5 is heavily P-type doped, and the N-type source implantation layer 6 and the N-type drain implantation layer 11 are heavily N-type doped.
[0030] In a preferred embodiment, by employing a process technology that involves bottom injection of the source / drain region and bottom injection of the drift region, the thicknesses of the first drift region injection area 9, the second drift region injection area 10, the N-type source injection layer 6, the P-type body contact injection layer 5, and the N-type drain injection layer 11 are equal to the thickness of the P-type silicon film layer 3. This reduces the area of the PN junction in the drift region or the contact area between the source and the well region, thereby reducing the high-temperature leakage current.
[0031] As a further description of the embodiments of the present invention, the method for fabricating a high-temperature, high-voltage LDMOS device based on thin silicon film SOI technology provided in this embodiment specifically includes: Step S1: Provide SOI wafers for fabrication.
[0032] Optionally, for applications at high temperatures and for STI etching and source / drain implantation techniques in subsequent all-dielectric isolation, the thickness of the p-type silicon film 3 is ≤300nm, and it is lightly p-type doped with a doping concentration of 1.5×10⁻⁶. 13 cm -3 ~1.5×10 15 cm -3 .
[0033] Step S2 involves using photolithography and etching techniques to etch STI trenches into the top p-type silicon film layer 3 of the SOI wafer. The depth of the STI trenches is equal to the thickness of the p-type silicon film layer 3.
[0034] Specifically, photoresist is formed on the surface of the SOI wafer, the photoresist layer is exposed through a pre-designed photomask, then developed, the photoresist is patterned, and STI trench etching is performed using the photoresist as a mask.
[0035] Step S3: Deposit SiO2 to isolate the device.
[0036] Step S4: Define the active region of the device using photolithography, and perform well implantation using photoresist as a mask (conditions based on a high-temperature reference process). In this embodiment, well implantation is divided into three steps: boron implantation, boron implantation, and boron fluoride implantation, with the implantation energy decreasing sequentially.
[0037] Step S5: A drift region 9 is defined using photolithography and ion implantation is performed. In this embodiment, three implantations are conducted: phosphorus implantation, phosphorus implantation, and arsenic implantation, with energy increasing and dosage decreasing sequentially. The drift region 9 is implanted to form N-type doping.
[0038] Step S6: A photolithography process is used to define the drift region implantation zone 2 (10) and perform ion implantation. In this embodiment, three implantations are performed: phosphorus implantation, phosphorus implantation, and arsenic implantation, with energy increasing and dosage decreasing sequentially. The drift region is implanted into zone 2 (10) to form N-type doping. The doping concentration in the drift region implanted into zone 2 (10) is greater than that in the drift region implanted into zone 1 (9).
[0039] Step S7: Deposit silicon nitride, define the field oxygen region by photolithography, and etch away the silicon nitride in the region.
[0040] Step S8: High-temperature oxidation growth of silicon dioxide layer, namely field oxygen FOX layer 15.
[0041] Step S9: Deposit oxide layer and polysilicon. In this embodiment, the oxide layer thickness is 3nm. Photolithography is used to define the polysilicon gate and gate oxide layer. Photoresist is used as a mask to etch away the remaining polysilicon and oxide layer.
[0042] Step S10: Define the source, drain, and body positions using photolithography, and perform N-type doping on the source and drain regions and P-type doping on the body region using photoresist as a mask.
[0043] Step S11: Deposit ILD (Interlayer Dielectric Material) dielectric layer 17, define the via locations using photolithography, form vias by etching, and deposit and planarize by CMP (Chemical Mechanical Polishing) to form tungsten (W) plugs.
[0044] Step S12: An IMD (Intermetallic Dielectric Material) dielectric layer is formed by deposition and planarization by CMP (Chemical Mechanical Polishing). Aluminum metal 16 is deposited on the surface of the IMD dielectric layer. The positions of the metal lines are defined by photolithography. The aluminum metal is etched using photoresist as a mask to form metal interconnects for connection with tungsten (W) plugs.
[0045] This invention also provides a high-temperature, high-voltage LDMOS device based on thin-film SOI technology, comprising: Thin silicon film SOI wafer; STI groove isolation region 4 is formed on the outer side of the top surface of the thin silicon film SOI wafer; The P-type well region 7 and the drift region are respectively arranged on both sides of the top surface of the thin silicon film SOI wafer and are in contact with the STI trench isolation region 4; wherein the drift region includes a drift region injection region 1 9 and a drift region injection region 2 10 that are laterally adjacent to each other. The P-type body contact injection layer 5 and the N-type source injection layer 6 are arranged longitudinally adjacently and alternately within the P-type well region 7; The PN junction region 8 is formed in the region where the N-type source injection layer 6 and the drift region injection region 9 are in contact with the P-type well region 7, respectively. An N-type drain injection layer 11 is formed within the drift region injection region 10; A field oxygen FOX layer 15 covers the surface of the drift region; The gate oxide GOX layer 13 has one end covering the surface of the P-type well region 7 between the drift region and the N-type source injection layer 6, and the other end partially covering the surface of the field oxide FOX layer 15. A POLY gate 14 covers the surface of the gate oxide GOX layer 13; ILD dielectric layer 17 is formed on the top surface of the thin silicon film SOI wafer; Contact hole 12 and aluminum metal 16, the contact hole 12 is arranged inside the ILD dielectric layer 17, and the P-type body contact injection layer 5, the N-type source injection layer 6 and the N-type drain injection layer 11 are respectively led out to the outside of the ILD dielectric layer 17 and interconnected with the aluminum metal 16 through the contact hole 12.
[0046] In a preferred embodiment, the P-type body contact injection layer 5 and the N-type source injection layer 6 are arranged in a longitudinally adjacent and staggered manner from front to back (i.e., as shown in the figure). Figure 4 As shown in the figure, the first drift region injection zone 9 and the second drift region injection zone 10 are horizontally adjacent from left to right.
[0047] like Figure 5 and Figure 6 As shown, the device can operate in an environment of -55℃ to 225℃, with an operating voltage up to 45V. The device breakdown voltage exceeds 60V, and the leakage current is less than 1nA / μm at a high temperature of 225℃, meeting the requirements for the circuit to operate in a wide temperature range.
[0048] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for fabricating a high-temperature, high-voltage LDMOS device based on thin-film SOI technology, characterized in that, A thin silicon film SOI wafer is used as the substrate. The thin silicon film SOI wafer includes a P-type silicon substrate layer, a buried oxide BOX layer and a P-type silicon film layer arranged sequentially from bottom to top. The method includes: By employing two transverse injections, the drift region is divided into two adjacent drift region injection zones: Drift Region Injection Zone 1 and Drift Region Injection Zone 2, in order to adjust the transverse electric field distribution. Each transverse injection includes three longitudinal injections, with the injection energy increasing sequentially from top to bottom and the injection dose decreasing sequentially from top to bottom, in order to adjust the longitudinal electric field distribution. By employing a process of bottom-drain and bottom-drift region implantation, the implanted ion concentrations on the N-type source implantation layer, N-type drain implantation layer, and drift region are diffused to the BOX buried oxide layer, thereby reducing the area of the PN region. By arranging the P-type body contact injection layer and the N-type source injection layer in a longitudinally adjacent and staggered manner, the P-type body contact injection layer and the P-type well region can achieve sufficient and effective body contact.
2. The method for fabricating a high-temperature, high-voltage LDMOS device based on thin silicon film SOI technology as described in claim 1, characterized in that, The P-type well region and the drift region are respectively formed laterally on both sides of the P-type silicon film. The step of forming the P-type well region includes three longitudinal implantations, from top to bottom: boron implantation, boron implantation and boron fluoride implantation, and the implantation energy decreases sequentially from top to bottom.
3. The method for fabricating a high-temperature, high-voltage LDMOS device based on thin-film SOI technology as described in claim 1, characterized in that, The steps of forming the first drift region implantation region and the second drift region implantation region both include three vertical implantations, from top to bottom: phosphorus implantation, phosphorus implantation and arsenic implantation, to form N-type doping; Furthermore, the doping concentration of the second region injected into the drift region is greater than the doping concentration of the first region injected into the drift region.
4. The method for fabricating a high-temperature, high-voltage LDMOS device based on thin-film SOI technology as described in claim 1, characterized in that, The thickness of the P-type silicon film is ≤300nm, and it is lightly doped with P-type silicon at a doping concentration of 1.5×10⁻⁶. 13 cm -3 ~1.5×10 15 cm -3 .
5. The method for fabricating a high-temperature, high-voltage LDMOS device based on thin silicon film SOI technology as described in claim 1, characterized in that, The P-type body contact implantation layer is heavily P-type doped, and the N-type source implantation layer and the N-type drain implantation layer are heavily N-type doped.
6. The method for fabricating a high-temperature, high-voltage LDMOS device based on thin-film SOI technology as described in claim 1, characterized in that, The thicknesses of the drift region injection zone one, the drift region injection zone two, the N-type source injection layer, the P-type body contact injection layer, and the N-type drain injection layer are equal to the thickness of the P-type silicon film.
7. The method for fabricating a high-temperature, high-voltage LDMOS device based on thin-film SOI technology as described in claim 1, characterized in that, The method specifically includes: By employing photolithography and etching techniques, STI trenches are etched and deposited on the top P-type silicon film layer of the thin silicon SOI wafer to form the STI trench isolation region. The active region is defined by photolithography and then a well is implanted to form a P-type well region; The regions of drift region implantation 1 and drift region implantation 2 are defined by photolithography, and three ion implantations with different energies are performed to form drift region implantation 1 and drift region implantation 2. The silicon nitride is deposited, and the area defined by field oxygen is defined by photolithography and the silicon nitride in that area is removed by etching. A silicon dioxide layer is grown by high-temperature oxidation to form a FOX field oxygen layer; A gate oxide layer is grown by high-temperature oxidation to form the GOX gate oxide layer; A POLY gate is formed by depositing polysilicon and etching the polysilicon and gate oxide layer. The source region, drain region, and body contact region are defined by photolithography and ion implantation is performed to form an N-type source implantation layer, an N-type drain implantation layer, and a P-type body contact implantation layer. Contact holes that interconnect with aluminum metal are formed by depositing an ILD dielectric layer and etching and depositing.
8. The method for fabricating a high-temperature, high-voltage LDMOS device based on thin-film SOI technology as described in claim 7, characterized in that, The depth of the STI groove is equal to the thickness of the P-type silicon film.
9. A high-temperature, high-voltage LDMOS device based on thin-film SOI technology, fabricated using the fabrication method for a high-temperature, high-voltage LDMOS device based on thin-film SOI technology as described in any one of claims 1 to 8, characterized in that, include: Thin silicon film SOI wafer; STI trench isolation region is formed on the outer side of the top surface of the thin silicon film SOI wafer; The P-type well region and drift region are respectively arranged on both sides of the top surface of the thin silicon film SOI wafer and are in contact with the STI trench isolation region; The drift region includes a drift region injection zone one and a drift region injection zone two that are laterally adjacent to each other; The P-type body contact injection layer and the N-type source injection layer are arranged longitudinally adjacently and alternately in the P-type well region; The PN junction region is formed in the region where the N-type source injection layer and the drift region injection layer are in contact with the P-type well region, respectively. An N-type drain injection layer is formed in the second region of the drift region; A field oxygen FOX layer covers the surface of the drift region; The gate oxide (GOX) layer has one end covering the surface of the P-type well region between the drift region and the N-type source injection layer, and the other end partially covering the surface of the field oxide (FOX) layer. A POLY gate is used to cover the surface of the gate oxide GOX layer; An ILD dielectric layer is formed on the top surface of the thin silicon film SOI wafer; The contact holes are located inside the ILD dielectric layer. The P-type body contact injection layer, the N-type source injection layer, and the N-type drain injection layer are led out to the outside of the ILD dielectric layer and interconnected with the aluminum metal through the contact holes.
10. A high-temperature, high-voltage LDMOS device based on thin silicon film SOI technology as described in claim 9, characterized in that, The P-type body contact injection layer and the N-type source injection layer are arranged longitudinally adjacent to each other from front to back, and the drift region injection zone one and the drift region injection zone two are arranged laterally adjacent to each other from left to right.