Semiconductor device

Abstract

Embodiments of the present invention relate to a semiconductor device. The semiconductor device of this embodiment includes a semiconductor layer, first and second field plate (FP) electrode groups, a gate electrode, a fourth insulating region, first to third conductive films, and a fifth insulating region. The semiconductor layer includes a cell region and a termination region. The first and second FP electrode groups each contain a plurality of FP electrodes arranged in the termination region. The gate electrode is disposed between the first and second FP electrode groups. The first and second conductive films are electrically connected to the FP electrodes of the first and second FP electrode groups, respectively. The third conductive film is located between the first and second conductive films in a third-order direction. The fifth insulating region is disposed in a third-order direction between the first conductive film and the third conductive film, and between the second conductive film and the third conductive film, and has a lower dielectric constant than the fourth insulating region.

Description

[0001] [Related Application]

[0002] This application enjoys priority based on Japanese Patent Application No. 2025-047303 (filed on March 21, 2025). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0004] In semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), it is preferable to improve switching efficiency. Summary of the Invention

[0005] The semiconductor device of this embodiment includes a semiconductor layer, a first field plate electrode group, a second field plate electrode group, a gate electrode, a fourth insulating region, a first conductive film, a second conductive film, a third conductive film, and a fifth insulating region. The semiconductor layer has a first main surface and a second main surface. The semiconductor layer includes a cell region and a terminal region surrounding the cell region. The first field plate electrode group includes a plurality of field plate electrodes disposed in the terminal region of the semiconductor layer across the first insulating region, arranged in a second direction orthogonal to a first direction from the first main surface toward the second main surface and from the cell region toward the terminal region. The second field plate electrode group includes a plurality of field plate electrodes disposed in the terminal region of the semiconductor layer across a second insulating region and arranged in the second direction. The second field plate electrode group is adjacent to the first field plate electrode group in a third direction orthogonal to both the first and second directions. The gate electrode is opposite the semiconductor layer in the first direction across a third insulating region and is disposed between the first and second field plate electrode groups in the third direction. The fourth insulating region is disposed on the second main surface of the terminal region of the semiconductor layer. The first conductive film is disposed on the fourth insulating region and electrically connected to the plurality of field plate electrodes included in the first field plate electrode group via a first contact portion. The second conductive film is disposed on the fourth insulating region and electrically connected to the plurality of field plate electrodes included in the second field plate electrode group via a second contact portion. The third conductive film is disposed on the fourth insulating region, located between the first conductive film and the second conductive film in the third direction, electrically connected to the gate electrode via a third contact portion, and extending from the third contact portion in the second direction. The fifth insulating region is disposed between the first conductive film and the third conductive film, and between the second conductive film and the third conductive film in the third direction, and has a lower dielectric constant compared to the fourth insulating region.

[0006] According to this embodiment, a semiconductor device capable of improving switching efficiency can be provided. Attached Figure Description

[0007] Figure 1 This is a top view of the semiconductor device according to the first embodiment.

[0008] Figure 2 yes Figure 1 A magnified view of the area surrounding the terminal region.

[0009] Figure 3 The semiconductor device of the first embodiment is along Figure 1 A sectional view along line A1-A1.

[0010] Figure 4The semiconductor device of the first embodiment is along Figure 1 A sectional view along line B1-B1.

[0011] Figure 5 The semiconductor device of the first embodiment is along Figure 1 A sectional view of line C1-C1.

[0012] Figure 6A This is an example used to illustrate the manufacturing process of the semiconductor device of the first embodiment, equivalent to following... Figure 1 The figure is a cross-sectional view of line A1-A1.

[0013] Figure 6B This is an example used to illustrate the manufacturing process of the semiconductor device of the first embodiment, equivalent to following... Figure 1 The figure shows a cross-sectional view along line B1-B1.

[0014] Figure 6C This is an example used to illustrate the manufacturing process of the semiconductor device of the first embodiment, equivalent to along... Figure 1 A cross-sectional view of line C1-C1.

[0015] Figure 7A It continues Figure 6A An example of the manufacturing process of the semiconductor device of the first embodiment, corresponding to along Figure 1 The figure is a cross-sectional view of line A1-A1.

[0016] Figure 7B It continues Figure 6B An example of the manufacturing process of the semiconductor device of the first embodiment, corresponding to along Figure 1 The figure shows a cross-sectional view along line B1-B1.

[0017] Figure 7C It continues Figure 6C An example of the manufacturing process of the semiconductor device of the first embodiment, corresponding to along Figure 1 A cross-sectional view of line C1-C1.

[0018] Figure 8A It continues Figure 7A An example of the manufacturing process of the semiconductor device of the first embodiment, corresponding to along Figure 1 The figure is a cross-sectional view of line A1-A1.

[0019] Figure 8B It continues Figure 7B An example of the manufacturing process of the semiconductor device of the first embodiment, corresponding to along Figure 1 The figure shows a cross-sectional view along line B1-B1.

[0020] Figure 8C It continues Figure 7C An example of the manufacturing process of the semiconductor device of the first embodiment, corresponding to along Figure 1 A cross-sectional view of line C1-C1.

[0021] Figure 9A It continues Figure 8A An example of the manufacturing process of the semiconductor device of the first embodiment, corresponding to along Figure 1 The figure is a cross-sectional view of line A1-A1.

[0022] Figure 9B It continues Figure 8B An example of the manufacturing process of the semiconductor device of the first embodiment, corresponding to along Figure 1 The figure shows a cross-sectional view along line B1-B1.

[0023] Figure 9C It continues Figure 8C An example of the manufacturing process of the semiconductor device of the first embodiment, corresponding to along Figure 1 A cross-sectional view of line C1-C1.

[0024] Figure 10 This is a top view of the semiconductor device according to the second embodiment.

[0025] Figure 11 yes Figure 10 A magnified view of the area surrounding the terminal region.

[0026] Figure 12 The semiconductor device of the second embodiment is along Figure 10 A partial sectional view of line A2-A2.

[0027] Figure 13 The semiconductor device of the second embodiment is along Figure 10 A partial sectional view of line B2-B2.

[0028] Figure 14 The semiconductor device of the second embodiment is along Figure 10 A sectional view of line C2-C2.

[0029] Figure 15A This is an example used to illustrate the manufacturing process of the semiconductor device according to the second embodiment, equivalent to along... Figure 10 The figure is a cross-sectional view of line A2-A2.

[0030] Figure 15B This is an example used to illustrate the manufacturing process of the semiconductor device according to the second embodiment, equivalent to along... Figure 10The figure shows a cross-sectional view along line B2-B2.

[0031] Figure 16 This is a top view of the semiconductor device according to the third embodiment.

[0032] Figure 17 yes Figure 16 A magnified view of the area surrounding the terminal region.

[0033] Figure 18 The semiconductor device of the third embodiment is along Figure 16 A sectional view along line A3-A3.

[0034] Figure 19 The semiconductor device of the third embodiment is along Figure 16 A sectional view along line B3-B3.

[0035] Figure 20 The semiconductor device of the third embodiment is along Figure 16 A cross-sectional view of the DD line. Detailed Implementation

[0036] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. The drawings are schematic or conceptual, and the proportions of the parts, etc., may not be the same as in reality. In the specification and drawings, elements identical to those described in previously seen drawings are labeled with the same reference numerals, and detailed descriptions are appropriately omitted.

[0037] In addition, for ease of explanation, such as Figures 1-5 As shown, an orthogonal XYZ coordinate system is used. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. Additionally, the source electrode side in the Z-axis direction is referred to as "upper," and the drain electrode side as "lower." However, this designation is for convenience and is independent of the direction of gravity. The Z-axis direction is the first direction in the claims. The X-axis direction is the second direction in the claims. The Y-axis direction is the third direction in the claims.

[0038] Additionally, in the following explanation, to indicate the relative levels of impurity concentration in each conductivity type, n is sometimes used. + n, n - and p + p, p - The expression. That is, n + This indicates that the concentration of n-type impurities is relatively higher than that of n, n - This indicates that the concentration of n-type impurities is relatively lower than that of n. Additionally, p... + This indicates that the concentration of p-type impurities is relatively higher than that of p-type impurities. -This indicates that the concentration of p-type impurities is relatively lower than that of n-type impurities. These statements, when both p-type and n-type impurities are present in various regions, represent the relative levels of the actual impurity concentrations after these impurities compensate for each other. n-type, n... + type and n - p-type is an example of the first conductivity type in the claims. + Type and p - The n-type is an example of the second conductivity type in the claims. Furthermore, in the following description, the n-type and p-type can also be reversed. That is, the first conductivity type can also be p-type.

[0039] Furthermore, the impurity concentration in the semiconductor region can be determined, for example, by secondary ion mass spectrometry (SIMS). Additionally, the relative level of impurity concentration can be determined, for example, by the carrier concentration obtained using scanning capacitance microscopy (SCM).

[0040] In addition, dimensions such as the thickness of the field plate insulating film can be determined, for example, by surface and / or cross-sectional analysis using transmission electron microscopy (TEM), energy dispersive X-ray spectroscopy (EDX), or scanning electron microscopy (SEM).

[0041] Furthermore, the terms used in this specification, such as “same,” “identical,” “equal,” etc., regarding the determination of shape, geometric conditions, and physical properties, as well as their degree, and the values ​​of dimensions and physical properties, are not limited to a strict meaning, but are interpreted to include a range of degrees to which the same function can be expected.

[0042] (First Implementation)

[0043] Reference Figures 1-5 The semiconductor device 1 of the first embodiment will be described. Figure 1 This is a top view of the semiconductor device 1 according to the first embodiment. Figure 2 yes Figure 1 A magnified view of the area surrounding the terminal region TR in the image. Figure 3 Along the semiconductor device 1 of the first embodiment Figure 1 A sectional view along line A1-A1. Figure 4 Along the semiconductor device 1 of the first embodiment Figure 1 A sectional view along line B1-B1. Figure 5 Along the semiconductor device 1 of the first embodiment Figure 1 A sectional view along line C1-C1. Additionally, in Figure 1 and Figure 2 In this text, the source electrode 12, insulating region 53, and insulating region 54 are omitted. Furthermore, in... Figure 1 In the figure, the high-concentration region 25 in the unit region CR and the intermediate region MR, as well as the conductive film 43, are omitted.

[0044] Semiconductor device 1 is, for example, a vertically oriented MOSFET. Alternatively, semiconductor device 1 can also be a transistor or diode, such as an IGBT (Insulated Gate Bipolar Transistor). Furthermore, semiconductor device 1 can be either a vertically oriented device or a horizontally oriented device. The following explanation will use the case where semiconductor device 1 is a vertically oriented MOSFET as an example.

[0045] First, the planar structure of the semiconductor device 1 in this embodiment will be described. Figure 1 In the plane shown, the semiconductor device 1 includes a semiconductor layer 2, multiple field plate electrodes (FP electrodes) 13, a gate electrode 14, a drift region 21, a substrate region 23, a source region 24, a guard ring region 26, a contact portion 31, a contact portion 32, a contact portion 33, a contact portion 34, a conductive film 41, a conductive film 42, a conductive film 43, a conductive film 44, an insulating region 51, an insulating region 52, and an insulating region 61.

[0046] Various semiconductor regions, such as drift regions 21, are provided within the semiconductor layer 2. In this embodiment, the semiconductor layer 2 includes a unit region CR, an intermediate region MR, and a terminal region TR.

[0047] The termination region TR is a region extending from the side 2c of semiconductor layer 2 toward the inside of semiconductor layer 2. The termination region TR is, for example, set in a way that surrounds the cell region CR in a plane orthogonal to the Z-axis direction.

[0048] The cell region CR is a region located inside the semiconductor layer 2, in a plane orthogonal to the Z-axis direction, closer to the terminal region TR. The cell region CR includes the substrate region 23, the source region 24, etc., and is also the current region through which the current flows between the drain electrode 11 and the source electrode 12, as described later. The cell region CR is, for example, located at the center of the semiconductor device 1 in a plane orthogonal to the Z-axis direction.

[0049] The intermediate region MR is the region located between the cell region CR and the terminal region TR. The intermediate region MR is, for example, configured to surround the cell region CR. A gate electrode 14 and a substrate region 23 are provided in the intermediate region MR, but the source region 24 is not provided, as will be described later. By providing such an intermediate region MR, the breakdown voltage of the semiconductor device 1 can be improved.

[0050] In addition, Figure 1 In the example, two FP electrodes 13 are arranged along the X-axis in the intermediate region MR. However, this is not a limitation; one or more FP electrodes 13 can also be arranged along the X-axis in the intermediate region MR. Alternatively, the intermediate region MR may not be provided, and the cell region CR is connected to the terminal region TR.

[0051] Multiple FP electrodes 13 are arranged in a dotted pattern covering the unit region CR, intermediate region MR, and terminal region TR of the semiconductor layer 2. In this embodiment, each FP electrode 13 is arranged at a predetermined interval along the X-axis and Y-axis directions. An insulating region 51 is provided around each FP electrode 13. The FP electrodes 13 and the insulating regions 51 are disposed in field plate trenches (FP trenches) arranged in a dotted pattern within the semiconductor layer 2. That is, in the semiconductor device 1, multiple FP trenches are formed to be arranged at predetermined intervals, and FP electrodes 13 and insulating regions 51 are formed in each FP trench.

[0052] In the unit region CR, a high-concentration region 25 (described later) is provided around the insulating region 51, and a source region 24 is provided around the high-concentration region 25. Additionally, in the intermediate region MR, a high-concentration region 25 is provided around the insulating region 51, and a substrate region 23 is provided around the high-concentration region 25. Furthermore, in the terminal region TR, a drift region 21 or a guard ring region 26 is provided around the insulating region 51. In this embodiment, the position (X-coordinate) of the boundary between the drift region 21 and the guard ring region 26 in the X-axis direction is relative to the position of the FP electrode 13 in the terminal region TR. Figure 1 The X-coordinates of the third FP electrode 13 from the right are approximately the same. However, the position of the boundary between the drift region 21 and the guard ring region 26 is not limited to this example and is arbitrary.

[0053] The gate electrode 14 is separated by an insulating region 52 and is mainly disposed within the cell region CR and the intermediate region MR of the semiconductor layer 2. For example... Figure 1As shown, the gate electrode 14 is provided in a manner that divides the cell region CR and the intermediate region MR into partitions extending in the X-axis direction and the Y-axis direction, respectively. Each partition includes one FP electrode 13 provided in the cell region CR and the intermediate region MR. In this embodiment, the gate electrode 14 in the cell region CR is provided such that it surrounds the source region 24 with an insulating region 52 in between. In addition, the gate electrode 14 in the intermediate region MR is provided such that it surrounds the substrate region 23 with an insulating region 52 in between.

[0054] Furthermore, the gate electrode 14 extends along the X-axis to the middle of the terminal region TR from the intersection of the portion extending along the X-axis and the portion extending along the Y-axis at the boundary between the intermediate region MR and the terminal region TR. The end of the portion extending to the middle of the terminal region TR is electrically connected to the contact portion 32. The contact portion 32 is electrically connected to the conductive film 42. That is, the gate electrode 14 is electrically connected to the conductive film 42 via the contact portion 32. The conductive film 42 extends in the X-axis direction and is electrically connected to each other near the side portion 2c via the conductive film 44 extending in the Y-axis direction. The conductive film 44 is electrically connected, for example, to a gate pad (not shown).

[0055] Contact portion 31 electrically connects the FP electrode 13 disposed in the terminal region TR to the conductive film 41. Furthermore, the conductive films 41 are electrically connected to each other via conductive films 43 disposed in the cell region CR and the intermediate region MR. The conductive films 43 are electrically connected to the source electrode 12. Additionally, the conductive films 43 are electrically connected to contact portions 33 and 34. Contact portion 33 is electrically connected to the FP electrode 13, the substrate region 23, and the high-concentration region 25 in the cell region CR and the intermediate region MR. Similarly, contact portion 34 is electrically connected, for example, to the source region 24 and the high-concentration region 25 in the cell region CR, and to the substrate region 23 and the high-concentration region 25 in the intermediate region MR.

[0056] In this embodiment, the contact portion 33 and the contact portion 34 have Figure 1 The planar shape is shown. More specifically, the contact portion 34 is configured as a rectangular frame along the outer edge of the rectangular partition defined by the gate electrode 14 extending along the X-axis and Y-axis directions. Furthermore, the contact portion 33 connects the middle portions of each contact portion 34 extending along the X-axis direction to each other. That is, the contact portion 33 is configured to divide the rectangular area defined by the contact portion 34 into two regions arranged in the X-axis direction. Additionally, the middle portion of each contact portion 33 in the Y-axis direction is located above the FP electrode 13.

[0057] The insulating region 61 is provided such that conductive films 41 and 42 cover the terminal region TR. Details regarding the insulating region 61 are described later. The insulating region 61 is an example of the fifth insulating region as claimed.

[0058] Next, refer to Figure 2 The periphery of the terminal region TR of semiconductor layer 2 will be described in more detail. For example... Figure 2 As shown, the FP electrodes 13 disposed within the terminal region TR constitute, for example, a first field plate electrode group (first FP electrode group) including multiple FP electrodes 13a and a second field plate electrode group (second FP electrode group) including multiple FP electrodes 13b. Specifically, the first FP electrode group includes multiple FP electrodes 13a arranged in the X-axis direction, orthogonal to the Z-axis direction and extending from the cell region CR towards the terminal region TR. The second FP electrode group includes multiple FP electrodes 13b arranged in the X-axis direction. The second FP electrode group is adjacent to the first FP electrode group in the Y-axis direction, orthogonal to both the Z-axis and X-axis directions.

[0059] Here, FP electrode 13ae is the FP electrode disposed at the end of side portion 2c of FP electrode 13a included in the first FP electrode group. In other words, FP electrode 13ae is the FP electrode of FP electrode 13a included in the first FP electrode group that is closest to side portion 2c of semiconductor layer 2. In addition, FP electrode 13be is the FP electrode disposed at the end of side portion 2c of FP electrode 13b included in the second FP electrode group.

[0060] The plurality of FP electrodes 13a included in the first FP electrode group are electrically connected to the conductive film 41. More specifically, the conductive film 41 is disposed above the first FP electrode group along the X-axis direction. Furthermore, the conductive film 41 is electrically connected to each FP electrode 13a via a contact portion 31. The conductive film 41 electrically connected to each FP electrode 13a is an example of the first conductive film in the claims. Additionally, the contact portion 31 that electrically connects the conductive film 41 to each FP electrode 13a is an example of the first contact portion in the claims.

[0061] Similarly, the plurality of FP electrodes 13b included in the second FP electrode group are electrically connected to the conductive film 41. More specifically, the conductive film 41 is disposed above the second FP electrode group along the X-axis direction. Furthermore, the conductive film 41 is electrically connected to each FP electrode 13b via a contact portion 31. The conductive film 41 electrically connected to each FP electrode 13b is an example of the second conductive film in the claims. Additionally, the contact portion 31 that electrically connects the conductive film 41 to each FP electrode 13b is an example of the second contact portion in the claims.

[0062] The gate electrode 14 in the terminal region TR is disposed between the first FP electrode group and the second FP electrode group in the Y-axis direction. The gate electrode 14 includes an end portion 14a. The end portion 14a of the gate electrode 14 is electrically connected to the conductive film 42 via a contact portion 32. The conductive film 42 extends from the contact portion 32 toward the side portion 2c. More specifically, the conductive film 42 is disposed above the gate electrode 14, and in the Y-axis direction, it is located between the conductive film 41 (first conductive film) electrically connected to the FP electrode 13a and the conductive film 41 (second conductive film) electrically connected to the FP electrode 13b. The conductive film 42 is an example of the third conductive film in the claim. The contact portion 32 is an example of the third contact portion in the claim.

[0063] Here, conductive films 41 and 42 are alternately arranged along the Y-axis. Furthermore, multiple conductive films 41 are connected to conductive film 43, and multiple conductive films 42 are connected to conductive film 44. In other words, conductive films 41 to 44 form a comb-shaped wiring layer in the terminal region TR of the semiconductor layer 2. By forming a comb-shaped wiring layer, the FP electrode 13 can be positioned closer to the side portion 2c, thereby improving the withstand voltage of the semiconductor device 1.

[0064] In addition, conductive film 42 is electrically coupled to conductive film 41, which is opposite to it in the Y-axis direction. That is, there is a certain electrostatic capacitance (parasitic capacitance) between adjacent conductive films 41 and 42 in the Y-axis direction.

[0065] The insulating region 61 is provided in such a way that it covers the conductive film 41 and the conductive film 42. In this embodiment, the end 61a of the side 2c side (terminal region TR side) of the insulating region 61 is located closer to the unit region CR side than the end 41a of the side 2c side of the conductive film 41. That is, the corner 41c of the conductive film 41 is not covered by the insulating region 61. In this embodiment, the corner 41c of the conductive film 41 is covered by the insulating region 54, which has a higher dielectric constant than the insulating region 61, as described later. Alternatively, the end 61a may be located closer to the side 2c side than the end 41a. The end 61a is an example of the first end in the claims.

[0066] Furthermore, the end 61b of the insulating region 61 on the CR side is located further to the side 2c than the end 42a of the conductive film 42 on the CR side. That is, the corner 42c of the conductive film 42 is not covered by the insulating region 61. In this embodiment, the corner 42c of the conductive film 42 is covered by an insulating region 54 with a higher dielectric constant than the insulating region 61. Alternatively, the end 61b may also be located closer to the CR side than the end 42a. The end 61b is an example of the second end in the claims.

[0067] Furthermore, in this embodiment, the end portion 61a is located above the insulating region 51 between the FP electrode 13ae, which is disposed at the end of the plurality of FP electrodes 13a included in the first FP electrode group on the side 2c side, and the semiconductor layer 2. That is, the X coordinate of the end portion 61a is the same as the X coordinate of the insulating region 51 surrounding the FP electrode 13ae. In addition, the end portion 61a is located above the insulating region 51 between the FP electrode 13be, which is disposed at the end of the plurality of FP electrodes 13b included in the second FP electrode group on the side 2c side, and the semiconductor layer 2.

[0068] In this embodiment, the end portion 61b is located between the end portion 42a and the contact portion 32 in the X-axis direction. However, it is not limited to this; the end portion 61b may also be located in the X-axis direction on the side of the contact portion 32, closer to the side portion 2c.

[0069] Furthermore, in this embodiment, the FP electrodes 13a included in the first FP electrode group and the FP electrodes 13b included in the second FP electrode group are arranged along the Y-axis direction. However, this is not a limitation; the FP electrodes 13a included in the first FP electrode group and the FP electrodes 13b included in the second FP electrode group may also be arranged along a direction orthogonal to the Z-axis direction and oblique to the X-axis direction. In this case, the X-coordinate of the end portion 41a on the side 2c side of the conductive film 41 may differ for each conductive film 41. For example, the X-coordinate of the end portion 41a of the conductive film 41 (first conductive film) electrically connected to the FP electrode 13a may also be different from the X-coordinate of the end portion 41a on the side 2c side of the conductive film 41 (second conductive film) electrically connected to the FP electrode 13b.

[0070] Next, refer to Figures 3-5 The cross-sectional structure of the semiconductor device 1 in this embodiment will be described in detail. Figures 3-5 As shown, the semiconductor device 1 of this embodiment includes a semiconductor layer 2, a drain electrode 11, a source electrode 12, contact portions 31 to 34, conductive films 41 to 44, an insulating region 53, an insulating region 54, and an insulating region 61.

[0071] Semiconductor layer 2 is disposed between drain electrode 11 and source electrode 12. Semiconductor layer 2 has a lower surface 2a, an upper surface 2b opposite to the lower surface, and a side portion 2c connecting the lower surface 2a and the upper surface 2b. The lower surface 2a and the upper surface 2b are examples of the first main surface and the second main surface in the claims, respectively.

[0072] Semiconductor layer 2 can be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate and an epitaxial layer disposed thereon. In this embodiment, semiconductor layer 2 is silicon (Si). In this case, arsenic (As), phosphorus (P), or antimony (Sb) is used as an n-type impurity, and boron (B) is used as a p-type impurity. Alternatively, semiconductor layer 2 can also be composed of compound semiconductors such as silicon carbide (SiC) or gallium nitride (GaN).

[0073] The drain electrode 11 functions as the drain electrode of the MOSFET. The drain electrode 11 is disposed on the lower surface 2a of the semiconductor layer 2. The drain electrode 11 is, for example, in ohmic contact with the drain region 22. The drain electrode 11 comprises, for example, at least one of copper (Cu), titanium (Ti), tungsten (W), and aluminum (Al). The drain electrode 11 is an example of the first electrode in the claims.

[0074] The source electrode 12 functions as the source electrode of the MOSFET. The source electrode 12 is disposed on the upper surface 2b of the semiconductor layer 2, separated by a conductive film 43 and an insulating region 53. In this embodiment, the source electrode 12 is disposed on the upper surface 2b of the cell region CR and the intermediate region MR of the semiconductor layer 2. The source electrode 12 is in contact with and electrically connected to the conductive film 43. The source electrode 12 may contain at least one of copper (Cu), titanium (Ti), tungsten (W), and aluminum (Al). The source electrode 12 is an example of the second electrode as claimed in the claims.

[0075] like Figure 4 As shown, contact portion 31 is disposed on the upper surface 2b of the terminal region TR of semiconductor layer 2. More specifically, the upper end of contact portion 31 is connected to conductive film 41. In addition, the lower end of contact portion 31 extends through insulating region 53 in the Z-axis direction and is connected to FP electrode 13 disposed in terminal region TR. Contact portion 31 electrically connects FP electrode 13 disposed in terminal region TR to conductive film 41.

[0076] like Figure 3 As shown, contact portion 32 is disposed on the upper surface 2b of the terminal region TR of semiconductor layer 2. More specifically, the upper end of contact portion 32 is connected to conductive film 42. The lower end of contact portion 32 extends through insulating region 53 in the Z-axis direction and is connected to end portion 14a of gate electrode 14 in terminal region TR. Contact portion 32 electrically connects gate electrode 14 to conductive film 42.

[0077] like Figure 4As shown, contact portion 33 is disposed on the upper surface 2b of the unit region CR and the intermediate region MR of semiconductor layer 2. More specifically, the upper end of contact portion 33 is connected to conductive film 43. In addition, the lower end of contact portion 33 extends through insulating region 53 in the Z-axis direction and is connected to FP electrode 13 disposed in unit region CR and intermediate region MR. Contact portion 31 electrically connects FP electrode 13 disposed in unit region CR and intermediate region MR to conductive film 43.

[0078] A contact portion 34 is disposed on the upper surface 2b of the cell region CR and the intermediate region MR of the semiconductor layer 2. More specifically, the upper end of the contact portion 34 is connected to the conductive film 43. The lower end of the contact portion 34 extends through the insulating region 53 in the Z-axis direction and contacts the high-concentration region 25 disposed in the cell region CR and the intermediate region MR. The contact portion 34 electrically connects the high-concentration region 25 disposed in the cell region CR and the intermediate region MR to the conductive film 43. In addition, the lower end of the contact portion 34 is also connected to the source region 24 disposed in the cell region CR. The contact portion 34 electrically connects the source region 24 disposed in the cell region CR to the conductive film 43.

[0079] like Figure 4 and Figure 5 As shown, a conductive film 41 is disposed on the insulating region 53 in the terminal region TR and extends along the X-axis. The conductive film 41 may contain, for example, any one of tungsten (W), copper (Cu), titanium (Ti), and aluminum (Al). The FP electrode 13 disposed in the terminal region TR is electrically connected to the conductive film 41 via a contact portion 31.

[0080] like Figure 3 and Figure 5 As shown, the conductive film 42 is disposed above the insulating region 53 in the terminal region TR and extends along the X-axis direction. The conductive film 42 may contain, for example, any one of tungsten (W), copper (Cu), titanium (Ti), and aluminum (Al).

[0081] like Figure 3 and Figure 4 As shown, the conductive film 43 is disposed on the insulating region 53 in the unit region CR and the intermediate region MR. The conductive film 43 may contain, for example, any one of tungsten (W), copper (Cu), titanium (Ti) and aluminum (Al).

[0082] The conductive film 44 is disposed on the insulating region 53 in the terminal region TR. The conductive film 43 may contain, for example, any one of tungsten (W), copper (Cu), titanium (Ti), and aluminum (Al).

[0083] like Figures 3-5As shown, insulating region 53 is disposed on the upper surface 2b of the cell region CR, intermediate region MR, and terminal region TR of semiconductor layer 2. Insulating region 53 is a so-called interlayer insulating film. Insulating region 53 may contain, for example, silicon oxide or silicon nitride. Insulating region 53 is an example of the fourth insulating region in claim 1.

[0084] An insulating region 54 is disposed above the insulating region 53 in the intermediate region MR and the terminal region TR. The insulating region 54 is a so-called interlayer insulating film. Alternatively, the insulating region 54 may also be disposed above the insulating region 53 in the portion of the cell region CR where the source electrode 12 is not disposed. The insulating region 54 may, for example, contain silicon oxide or silicon nitride. The insulating region 54 is an example of the sixth insulating region of claim 1.

[0085] Insulation region 61 is disposed above insulation region 53 in terminal region TR. For example... Figure 5 As shown, the insulating region 61 is located between the conductive film 41 and the conductive film 42 in the Y-axis direction. In this embodiment, the insulating region 61 is embedded with the conductive film 41 and the conductive film 42. That is, the insulating region 61 is disposed not only between the conductive film 41 and the conductive film 42 in the Y-axis direction, but also on the conductive film 41 and the conductive film 42. Furthermore, as... Figures 3-5 As shown, in the portion where the insulating region 61 is provided, the insulating region 54 is disposed on top of the insulating region 61. That is, in the portion where the insulating region 61 is provided, the insulating region 54 is not directly in contact with the conductive film 41 and the conductive film 42. In other words, the semiconductor device 1 of this embodiment has a structure in which a portion of the insulating film, i.e., the insulating region 54, disposed between and on the conductive film 41 and the conductive film 42 is replaced with a low dielectric constant film, i.e., the insulating region 61.

[0086] Insulating region 61 is a low-dielectric-constant film with a lower dielectric constant than insulating region 53. For example, if insulating region 53 is a silicon oxide film containing silicon oxide, insulating region 61 is made of a material with a lower dielectric constant than the silicon oxide film. Examples of films made of materials with a lower dielectric constant than the silicon oxide film include carbon-added silicon oxide films, fluorine-added silicon oxide films, or photoresist films. Carbon-added silicon oxide films and fluorine-added silicon oxide films are films containing carbon-added silicon oxide (SiOC) and fluorine-added silicon oxide (SiOF), respectively. Photoresist films are, for example, insulating films containing organic polymers such as polyimide.

[0087] Furthermore, in the above description, the dielectric constant of insulating region 61 is compared with insulating region 53. However, this is not a limitation; the dielectric constant of insulating region 61 can also be compared with insulating region 51, insulating region 52, or insulating region 54, etc. For example, insulating region 61 may be provided with a film having a lower dielectric constant than insulating region 54.

[0088] The following describes one example of the internal structure of semiconductor layer 2. However, the internal structure of semiconductor layer 2 is not limited to the structure described below.

[0089] like Figures 3-5 As shown, the semiconductor layer 2 includes an FP electrode 13, a gate electrode 14, a drift region 21, a drain region 22, a substrate region 23, a source region 24, a high-concentration region 25, a guard ring region 26, an insulating region 51, and an insulating region 52.

[0090] like Figure 4 As shown, each FP electrode 13 is configured as a column in the drift region 21, separated by an insulating region 51. Each FP electrode 13 is electrically insulated from the semiconductor layer 2 by the insulating region 51. The FP electrodes 13 disposed in the unit region CR and the intermediate region MR are electrically connected to the source electrode 12 via the contact portion 33 and the conductive film 43. The FP electrodes 13 disposed in the terminal region TR are electrically connected to the source electrode 12 via the contact portion 31, the conductive film 41, and the conductive film 43. The FP electrodes 13 are, for example, made of polycrystalline silicon containing p-type or n-type impurities. By providing the FP electrodes 13, when the semiconductor device 1 is in the off state, by applying a reverse voltage between the drain electrode 11 and the source electrode 12, the depletion layer extends from the insulating region 51 where the FP electrodes 13 are disposed to the surrounding drift region 21. This depletion layer connects with the depletion layer extending from the insulating region 51 where adjacent FP electrodes 13 are disposed, thereby improving the withstand voltage of the semiconductor device 1.

[0091] An insulating region 51 is disposed within the drift region 21, and an FP electrode 13 is disposed therein. In this embodiment, the insulating region 51 is located on the inner wall of the FP trench where the FP electrode 13 is disposed, i.e., below and to the side of the FP electrode 13. The insulating region 51 may contain, for example, silicon oxide or silicon nitride. The insulating region 51 is an example of the first insulating region and the second insulating region in the claims.

[0092] like Figure 3 and Figure 4As shown, the gate electrode 14 functions as the gate electrode of the MOSFET. The gate electrode 14 is positioned opposite the substrate region 23 in the X-axis or Y-axis direction, separated by an insulating region 52. Furthermore, the gate electrode 14 is positioned opposite the semiconductor layer 2 (drift region 21 in this embodiment) in the Z-axis direction, separated by the insulating region 52. The gate electrode 14 is disposed within the insulating region 52. The gate electrode 14 is electrically insulated from the semiconductor layer 2 by the insulating region 52. The gate electrode 14 is, for example, made of polysilicon containing p-type or n-type impurities. When a voltage is applied to the gate electrode 14, a channel is formed in the substrate region 23 opposite to the gate electrode 14, and charge carriers (electrons in this embodiment) flow between the drift region 21 (drain region 22) and the source region 24. Thus, the MOSFET becomes in the on state.

[0093] An insulating region 52 is disposed within the substrate region 23 and the source region 24, electrically insulating the gate electrode 14 from the semiconductor layer 2. In this embodiment, the insulating region 52 is located on the inner wall of the gate trench where the gate electrode 14 is disposed, i.e., below and to the side of the gate electrode 14. The insulating region 52 may contain, for example, silicon oxide or silicon nitride. The insulating region 52 is an example of the third insulating region in the claims.

[0094] Thus, the semiconductor device 1 of this embodiment has a trench gate structure in which a gate electrode 14 and an insulating region 52 are disposed in a trench formed in the semiconductor layer 2. Alternatively, the semiconductor device 1 may have a planar gate structure in which a gate electrode 14 and an insulating region 52 are disposed on the upper surface 2b of the semiconductor layer 2.

[0095] The drift region 21 functions as the drift region of the MOSFET. In this embodiment, the drift region 21 is disposed within the cell region CR, the intermediate region MR, and the termination region TR of the semiconductor layer 2. The drift region 21 is disposed above the drain region 22 (above the drain electrode 11). The drift region 21 is, for example, n - The n-type semiconductor region. The n-type impurity concentration in drift region 21 is, for example, 1 × 10⁻⁶. 15 cm -3 Above and 2×10 16 cm -3 the following.

[0096] The drain region 22 functions as the drain region of the MOSFET. In this embodiment, the drain region 22 is disposed within the cell region CR, the intermediate region MR, and the termination region TR of the semiconductor layer 2. The drain region 22 is located above the drain electrode 11 and is disposed between the drift region 21 and the drain electrode 11. The drain region 22 is connected to and electrically connected to the drain electrode 11. The drain region 22 is, for example, n +The n-type semiconductor region. The n-type impurity concentration in the drain region 22 is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 the following.

[0097] Both the drift region 21 and the drain region 22 are examples of the first semiconductor region in the claims. Alternatively, the drain region 22 may be omitted. In this case, the drift region 21 is directly disposed on the drain electrode 11, and the drain electrode 11 is electrically connected to the drift region 21. Alternatively, the drift region 21 may also be omitted. In this case, for example, the drain region 22 may also be disposed at the location of the drift region 21.

[0098] like Figure 4 As shown, the substrate region 23 functions as the substrate region of the MOSFET. In this embodiment, the substrate region 23 is disposed within the cell region CR and the intermediate region MR of the semiconductor layer 2. The substrate region 23 is located above the drift region 21. The substrate region 23 is, for example, a p-type semiconductor region. The p-type impurity concentration of the substrate region 23 is, for example, 1 × 10⁻⁶. 16 cm -3 Above and 1×10 20 cm -3 Below, substrate region 23 is an example of the second semiconductor region in the claim.

[0099] The source region 24 functions as the source region of the MOSFET. In this embodiment, the source region 24 is disposed within the cell region CR of the semiconductor layer 2, but not within the intermediate region MR or the termination region TR. The source region 24 is located above the substrate region 23. In a cross-section not shown, the source region 24 is in contact with the contact portion 34 and electrically connected to the source electrode 12 via the contact portion 34 and the conductive film 43. The source region 24 is, for example, n + The source region 24 is a semiconductor region of type n. The n-type impurity concentration is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 22 cm -3 Below, source region 24 is an example of the third semiconductor region in the claim.

[0100] A high-concentration region 25 is disposed within the unit region CR and the intermediate region MR of the semiconductor layer 2. The high-concentration region 25 is located above the substrate region 23 and is connected to the lower end of the contact portion 34. The high-concentration region 25 is electrically connected to the source electrode 12 via the contact portion 34 and the conductive film 43. The high-concentration region 25 is, for example, p... +This refers to a high-concentration semiconductor region 25, where the impurity concentration is higher than that of the substrate region 23. The p-type impurity concentration in the high-concentration region 25 is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 Therefore, by setting a high-concentration region 25, the minority carriers (holes in this embodiment) remaining in the substrate region 23 can be easily discharged to the source electrode 12 via the contact portion 34 and the conductive film 43. As a result, the avalanche tolerance of the semiconductor device 1 can be improved.

[0101] Guard ring region 26 is disposed within the terminal region TR of semiconductor layer 2. Guard ring region 28 is, for example, a p-type semiconductor region. The p-type impurity concentration of guard ring region 28 is, for example, 1 × 10⁻⁶. 17 cm -3 Above and 1×10 19 cm -3 The following applies. By setting the protection ring region 28, the withstand voltage of the semiconductor device 1 can be improved.

[0102] As described above, the semiconductor device 1 of this embodiment includes a semiconductor layer 2, a first FP electrode group, a second FP electrode group, a gate electrode 14, an insulating region 53, a conductive film 41, a conductive film 42, and an insulating region 61. The semiconductor layer 2 includes a lower surface 2a and an upper surface 2b. The semiconductor layer 2 includes a terminal region TR extending inward from a side portion 2c connecting the lower surface 2a and the upper surface 2b, and a cell region CR located inward of the semiconductor layer 2 beyond the terminal region TR. The first FP electrode group includes a plurality of FP electrodes 13a disposed within the terminal region TR of the semiconductor layer 2, separated by the insulating region 51, and arranged in an X-axis direction orthogonal to the Z-axis direction from the lower surface 2a to the upper surface 2b and from the cell region CR to the terminal region TR. The second FP electrode group includes a plurality of FP electrodes 13b disposed within the terminal region TR of the semiconductor layer 2, separated by the insulating region 51, and arranged in the X-axis direction. The second FP electrode group is adjacent to the first FP electrode group in the Y-axis direction, which is orthogonal to both the Z-axis and X-axis directions. The gate electrode 14 is positioned opposite the semiconductor layer 2 in the Z-axis direction across the insulating region 52, and is disposed between the first FP electrode group and the second FP electrode group in the Y-axis direction. The insulating region 53 is disposed on the upper surface 2b of the terminal region TR of the semiconductor layer 2. A conductive film 41 is disposed on the insulating region 53 and is electrically connected to the plurality of FP electrodes 13a included in the first FP electrode group via a contact portion 31 penetrating the insulating region 53 in the Z-axis direction. The conductive film 41 is disposed on the insulating region 53 and is electrically connected to the plurality of FP electrodes 13b included in the second FP electrode group via a contact portion 31 penetrating the insulating region 53 in the Z-axis direction. A conductive film 42 is disposed on the insulating region 53, located in the Y-axis direction between conductive films 41 electrically connected to the plurality of FP electrodes 13a and conductive films 41 electrically connected to the plurality of FP electrodes 13b, and electrically connected to the gate electrode 14 via a contact portion 32 penetrating the insulating region 53 in the Z-axis direction, extending from the contact portion 32 toward the side portion 2c. An insulating region 61 is disposed in the Y-axis direction between conductive films 41 and 42 electrically connected to the plurality of FP electrodes 13a, and between conductive films 41 and 42 electrically connected to the plurality of FP electrodes 13b, and has a lower dielectric constant than the insulating region 53.

[0103] According to the semiconductor device 1 of this embodiment, by providing an insulating region 61 with a low dielectric constant between the conductive film 41 electrically connected to the FP electrode 13 and the conductive film 42 electrically connected to the gate electrode 14, the parasitic capacitance between the conductive film 41 and the conductive film 42 can be reduced. Therefore, the switching efficiency of the semiconductor device 1 can be improved.

[0104] Furthermore, according to this embodiment, the end 61a of the insulating region 61 on the side 2c of the semiconductor layer 2 is located closer to the cell region CR side than the end 41a of the conductive film 41 on the side 2c. Additionally, the end 61b of the insulating region 61 on the cell region CR side is located closer to the side 2c side than the end 42a of the conductive film 42 on the cell region CR side. That is, the corners 41c of the conductive film 41 and 42c of the conductive film 42 are covered by an insulating region 54 with a higher dielectric constant than the insulating region 61. This suppresses the decrease in the gate-source dielectric strength between the conductive film 41 and the conductive film 42. More specifically, as... Figure 2 As shown, the occurrence of time-dependent dielectric breakdown (TDDB) of the oxide film caused by electric field concentration between the corner 41c and the conductive film 42 near the corner 41c can be reduced. Similarly, the generation of TDDB caused by electric field concentration between the corner 42c and the conductive film 41 near the corner 42c can be reduced. Therefore, the reliability of the semiconductor device 1 can be improved. Furthermore, the conductive films 41 and 42 can also have a higher density than the conductive films 41 and 42c at their respective corner positions. Figure 2 The shape shown is further rounded. This allows for a further reduction in electric field concentration at corners 41c and 42c.

[0105] Furthermore, in this embodiment, each FP electrode 13 is arranged in a rectangular shape in both the unit region CR and the intermediate region MR. More specifically, each FP electrode 13 is arranged along the X-axis and Y-axis directions. However, it is not limited to this arrangement; each FP electrode 13 may also be arranged along the X-axis and a direction orthogonal to the Z-axis and oblique to the X-axis. Alternatively, each FP electrode 13 may be arranged along the Y-axis and a direction orthogonal to the Z-axis and oblique to the Y-axis. For example, in both the unit region CR and the intermediate region MR, each FP electrode 13 may be arranged in a hexagonal honeycomb shape. Additionally, when each FP electrode 13 is arranged in a honeycomb shape, the planar shape of each FP electrode 13 may also be hexagonal.

[0106] <Manufacturing Method of Semiconductor Device 1>

[0107] Next, refer to Figures 6A to 9C An example of the manufacturing method of the semiconductor device 1 of this embodiment will be described. Figure 6A , Figure 7A , Figure 8A as well as Figure 9A This is an example used to illustrate the manufacturing process of the semiconductor device 1 in the first embodiment, equivalent to following... Figure 1 The figure is a cross-sectional view of line A1-A1. Figure 6B , Figure 7B , Figure 8B and Figure 9B This is an example used to illustrate the manufacturing process of the semiconductor device 1 in the first embodiment, equivalent to following... Figure 1 The figure shows a cross-sectional view along line B1-B1. Figure 6C , Figure 7C , Figure 8C and Figure 9C This is an example used to illustrate the manufacturing process of the semiconductor device 1 in the first embodiment, equivalent to following... Figure 1 A cross-sectional view of line C1-C1.

[0108] First, prepare Figures 6A to 6C The semiconductor device component shown is a semiconductor layer 2, a drain electrode 11, contacts 31-34, conductive films 41-44, and an insulating region 53. Within the semiconductor layer 2 are disposed the aforementioned FP electrode 13, gate electrode 14, drift region 21, drain region 22, substrate region 23, source region 24, high-concentration region 25, guard ring region 26, insulating region 51, and insulating region 52.

[0109] Next, as Figures 7A to 7C As shown, for example, using a photolithography apparatus, an insulating material is coated on the upper surface 2b of the semiconductor layer 2 to form an insulating region 610. The insulating material is, for example, silicon oxide with added carbon or silicon oxide with added fluorine.

[0110] Next, as Figures 8A to 8C As shown, the portion of the insulating region 610 other than the insulating region 61 is removed. This process is performed as follows: First, a resist film is formed on the upper surface of the portion of the insulating region 610 corresponding to the insulating region 61. Then, the portion of the insulating region 610 other than the insulating region 61 is removed by wet etching or the like, using the resist film as a mask. Finally, the resist film is removed.

[0111] Next, as Figures 9A to 9C As shown, an insulating material is deposited on the upper surface 2b of the semiconductor layer 2 by chemical vapor deposition (CVD) to form an insulating region 540. The insulating material is, for example, silicon oxide or silicon nitride.

[0112] Subsequently, although not shown in the figure, the portion of the insulating region 540 other than the insulating region 54 itself is removed by wet etching or the like. This leaves the insulating region 54 intact. Then, a source electrode 12 is formed within the removed insulating region 540. Through the above processes, the semiconductor device 1 is manufactured.

[0113] Furthermore, when a resist film is provided as the insulating region 61, for example, in Figures 7A to 7CIn the process, instead of insulating material, an organic polymer-based material such as polyimide is coated onto the upper surface 2b of the semiconductor layer 2. Then, in... Figures 8A to 8C In the process, instead of wet etching, etc., it is left as an insulating area 61 by exposure and development.

[0114] Furthermore, in the aforementioned manufacturing method, in Figures 6A to 6C Prior to the process shown, a drain electrode 11 is formed on the lower surface 2a of the semiconductor layer 2. However, this is not a limitation; for example, it may also be formed on... Figures 9A to 9C Following the process shown, a drain electrode 11 is formed on the lower surface 2a of the semiconductor layer 2.

[0115] (Second Implementation)

[0116] Next, refer to Figures 10-14 The second embodiment, in which the insulating region 54 is directly disposed on the conductive film 41 and the conductive film 42, will be described with a focus on the differences from the first embodiment. Figure 10 This is a top view of the semiconductor device 1A according to the second embodiment.

[0117] Figure 11 yes Figure 10 A magnified view of the area surrounding the terminal region TR in the image. Figure 12 Along the semiconductor device 1A of the second embodiment Figure 10 A partial sectional view of line A2-A2. Figure 13 Along the semiconductor device 1A of the second embodiment Figure 10 A partial sectional view of line B2-B2. Figure 14 Along the semiconductor device 1A of the second embodiment Figure 10 A sectional view along line C2-C2. Furthermore, in Figure 10 as well as Figure 11 In this text, the source electrode 12, insulating region 53, and insulating region 54 are omitted. Furthermore, in... Figure 10 In the figure, the high-concentration region 25 in the unit region CR and the intermediate region MR, as well as the conductive film 43, are omitted.

[0118] like Figure 10 , Figure 11 and Figure 14 As shown, in this embodiment, instead of the insulating region 61 provided across the plurality of conductive films 41 and 42 in the first embodiment, a plurality of insulating regions 61A are respectively provided between adjacent conductive films 41 and 42 in the Y-axis direction. In this embodiment, the upper surface of each insulating region 61A is at the same height as the upper surface of the conductive films 41 and 42. Furthermore, as... Figure 14As shown, the insulating regions 61A are not disposed on the conductive films 41 and 42. Instead, the insulating regions 54 are directly disposed on the conductive films 41 and 42. That is, in this embodiment, the insulating regions 54 are directly in contact with the conductive films 41 and 42.

[0119] In addition, such as Figure 11 As shown, in this embodiment, each insulating region 61A fills a portion between the conductive films 41 and 42 that extend in the X-axis direction and are adjacent in the Y-axis direction. More specifically, the end portion 61Aa of the side portion 2c of each insulating region 61A is located closer to the unit region CR than the end portion 41a of the side portion 2c of the conductive film 41. That is, no insulating region 61A is provided between the corner portion 41c of the conductive film 41 and the conductive film 42 near the corner portion 41c. Furthermore, the end portion 61Ab of the unit region CR of each insulating region 61A is located closer to the side portion 2c than the end portion 42a of the unit region CR of the conductive film 42. That is, no insulating region 61A is provided between the corner portion 42c of the conductive film 42 and the conductive film 41 near the corner portion 42c.

[0120] According to the semiconductor device 1A of this embodiment, by directly providing the insulating region 54 on the conductive film 41 and the conductive film 42, the possibility of the insulating region 54 peeling off from the semiconductor device 1 can be reduced. More specifically, the insulating region 54, being a material with a high dielectric constant, has a higher adhesion to the conductive film 41 and the conductive film 42 compared to the insulating region 61, which is a material with a low dielectric constant. Therefore, for example, in the manufacturing process of the semiconductor device 1A, the possibility of the insulating region 54 peeling off from the upper surface of the conductive film 41 and the upper surface of the conductive film 42 when the protective strip provided on the upper surface 2b of the semiconductor layer 2 during the grinding of the lower surface 2a, which is the back side, is peeled off in a subsequent process can be reduced. As a result, the yield rate in the manufacturing of the semiconductor device 1A can be improved, for example.

[0121] <Manufacturing Method of Semiconductor Device 1A>

[0122] Next, refer to Figure 15A and Figure 15B An example of the manufacturing method of the semiconductor device 1A of this embodiment will be described. Figure 15A This is an example used to illustrate the manufacturing process of the semiconductor device 1A according to the second embodiment, equivalent to along... Figure 10 The figure is a cross-sectional view of line A2-A2. Figure 15B This is an example used to illustrate the manufacturing process of the semiconductor device 1A according to the second embodiment, equivalent to along... Figure 10 The figure shows a cross-sectional view along line B2-B2.

[0123] exist Figures 8A to 8C After the process shown, as Figure 15Aas well as Figure 15B As shown, a photoresist film 71 and a photoresist film 72 are formed on the upper surface 2b of the semiconductor layer 2. The photoresist film 71 covers the portion of the upper surface 2b of the semiconductor layer 2 that is closer to the cell region CR than the insulating region 61. The photoresist film 71 also covers the portion of the upper surface 2b of the semiconductor layer 2 that is closer to the side portion 2c than the insulating region 61.

[0124] Subsequently, although not shown, the portion of the insulating region 61 located above the conductive films 41 and 42 is removed by wet etching, etc., using the resist films 71 and 72 as masks. This exposes the upper surfaces of the conductive films 41 and 42. Furthermore, multiple insulating regions 61A remain between adjacent conductive films 41 and 42 in the Y-axis direction. Then, similarly to the first embodiment, the insulating region 54 and the source electrode 12 are formed. Through the above processes, the semiconductor device 1A is manufactured.

[0125] (Third Implementation)

[0126] Next, refer to Figures 16-20 The third embodiment, which has multiple FP electrodes 13B with stripe shapes, will be described focusing on the differences from the first embodiment. Figure 16 This is a top view of the semiconductor device 1B according to the third embodiment. Figure 17 yes Figure 16 A magnified view of the area surrounding the terminal region TR in the image. Figure 18 Along the semiconductor device 1B of the third embodiment Figure 16 A sectional view along line A3-A3. Figure 19 Along the semiconductor device 1B of the third embodiment Figure 16 A sectional view along line B3-B3. Figure 20 Along the semiconductor device 1B of the third embodiment Figure 16 A cross-sectional view of the DD line. Additionally, in Figure 16 and Figure 17 In this text, the source electrode 12, insulating region 53, and insulating region 54 are omitted. Furthermore, in... Figure 10 In the figure, the high-concentration region 25B in the unit region CR and the intermediate region MR is omitted.

[0127] First, the planar structure of the semiconductor device 1B in this embodiment will be described. Figure 16In the plane shown, the semiconductor device 1B of this embodiment includes an FP electrode 13B, a gate electrode 14B, a substrate region 23B, a source region 24B, a contact portion 31B, and insulating regions 51B and 52B, respectively, replacing the FP electrode 13, gate electrode 14, substrate region 23, source region 24, contact portion 31, and insulating regions 51 and 52 in the semiconductor device 1 of the first embodiment. Furthermore, the semiconductor device 1B includes a contact portion 34B, replacing the contacts 33 and 34 in the semiconductor device 1 of the first embodiment.

[0128] like Figure 16 As shown, the FP electrode 13B has a striped shape. In Figure 16 In this example, multiple FP electrodes 13B extending along the X-axis are provided. Each FP electrode 13B is positioned from the cell region CR and the intermediate region MR of the semiconductor layer 2 to the midway of the terminal region TR. In addition, each FP electrode 13B is arranged at a predetermined interval along the Y-axis.

[0129] An insulating region 51B is provided around each FP electrode 13B. The insulating region 51B extends in the X-axis direction. The FP electrode 13 and the insulating region 51B are disposed in an FP trench extending in the X-axis direction within the semiconductor layer 2. That is, in the semiconductor device 1B, a plurality of FP trenches are formed to be arranged at a predetermined interval, and an FP electrode 13B and an insulating region 51B are formed in each FP trench.

[0130] In the unit region CR, a high-concentration region 25B is provided in connection with the insulating region 51B, and a source region 24B is provided in connection with the high-concentration region 25B. Additionally, in the intermediate region MR, a high-concentration region 25B is provided in connection with the insulating region 51B, and a substrate region 23B is provided in connection with the high-concentration region 25B. Furthermore, in the terminal region TR, a drift region 21 or a guard ring region 26 is provided in connection with the insulating region 51B.

[0131] The gate electrode 14B is located midway from the cell region CR and intermediate region MR of the semiconductor layer 2 to the terminal region TR via the insulating region 52B. For example... Figure 16 As shown, multiple gate electrodes 14B and insulating regions 52B are provided in a manner extending along the X-axis direction. The end of the portion extending to the middle of the terminal region TR is connected to the contact portion 32.

[0132] Contact portion 31B is provided in a manner extending along the X-axis direction. Contact portion 31B electrically connects the FP electrode 13B to the conductive film 41 in the terminal region TR. Additionally, contact portion 31B electrically connects the FP electrode 13B to the conductive film 43 in the cell region CR and the intermediate region MR. Contact portion 34B is provided in a manner extending along the X-axis direction in the cell region CR and the intermediate region MR. Contact portion 34B is in contact with the source region 24B and the high-concentration region 25B in the cell region CR, and in contact with the substrate region 23B and the high-concentration region 25B in the intermediate region MR.

[0133] Next, refer to Figure 17 This provides a more detailed description of the area surrounding the terminal region (TR). For example... Figure 17 As shown, FP electrode 13Ba and FP electrode 13Bb are disposed within the terminal region TR of semiconductor layer 2. FP electrode 13Ba is an example of the first field plate electrode in the claims. FP electrode 13Bb is an example of the second field plate electrode in the claims.

[0134] The FP electrode 13Ba is electrically connected to the conductive film 41. More specifically, the conductive film 41 is disposed above the FP electrode 13Ba along the X-axis. Furthermore, the conductive film 41 is electrically connected to the FP electrode 13Ba via a contact portion 31B. The conductive film 41 electrically connected to the FP electrode 13Ba is an example of the first conductive film described in the claims.

[0135] Similarly, the FP electrode 13Bb is electrically connected to the conductive film 41. More specifically, the conductive film 41 is disposed above the FP electrode 13Bb along the X-axis. Furthermore, the conductive film 41 is electrically connected to the FP electrode 13Bb via the contact portion 31B. The conductive film 41 electrically connected to the FP electrode 13Bb is an example of the second conductive film described in the claims.

[0136] The gate electrode 14B is disposed between the FP electrode 13Ba and the FP electrode 13Bb in the Y-axis direction. The gate electrode 14B includes an end portion 14Ba. The end portion 14Ba of the gate electrode 14B is electrically connected to the conductive film 42 via a contact portion 32. More specifically, the conductive film 42 is disposed above the gate electrode 14B, and in the Y-axis direction, it is located between the conductive film 41 (first conductive film) electrically connected to the FP electrode 13Ba and the conductive film 41 (second conductive film) electrically connected to the FP electrode 13Bb.

[0137] Next, refer to Figures 18-20 The cross-sectional structure of the semiconductor device 1B of this embodiment will be described in detail.

[0138] like Figure 20 As shown, the gate electrode 14B is positioned opposite the substrate region 23B in the Y-axis direction, separated by an insulating region 52B.

[0139] like Figure 19 As shown, contact portion 31B is disposed on the upper surface 2b of the cell region CR, intermediate region MR, and terminal region TR of semiconductor layer 2. More specifically, the upper end of contact portion 31B is connected to conductive film 43 in cell region CR and intermediate region MR, and connected to conductive film 41 in terminal region TR. In addition, the lower end of contact portion 31B penetrates the insulating region 53 in the Z-axis direction and is connected to FP electrode 13B. Contact portion 31B electrically connects FP electrode 13B to conductive film 41 and conductive film 43.

[0140] like Figure 16 As shown, contact portion 34B is disposed on the upper surface 2b of the unit region CR and the intermediate region MR of semiconductor layer 2. Figure 20 As shown, the upper end of contact 34B is connected to conductive film 43. The lower end of contact 34B extends through insulating region 53 in the Z-axis direction, connecting to source region 24B and high-concentration region 25B. Contact 34B electrically connects source region 24B and high-concentration region 25B to conductive film 43.

[0141] In the case of the semiconductor device 1B according to this embodiment, when it is equipped with a plurality of FP electrodes 13B having a stripe shape, it is also possible to reduce the parasitic capacitance between the conductive film 41 and the conductive film 42, similar to the semiconductor device 1 of the first embodiment.

[0142] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the scope of the invention as set forth in the claims and its equivalents.

[0143] [Explanation of reference numerals in the attached figures]

[0144] 1 Semiconductor device

[0145] 11 Drain electrode

[0146] 12 source electrodes

[0147] 13 FP electrode

[0148] 14 gate electrodes

[0149] 2 Semiconductor Layer

[0150] 21 Drift Zones

[0151] 22 Drain Region

[0152] 23 basal regions

[0153] 24 source regions

[0154] 25 High Concentration Areas

[0155] 26 Protective Ring Area

[0156] 31~34 contact part

[0157] 41-44 conductive film

[0158] Insulation areas 51-54 and 61

[0159] CR unit region

[0160] MR intermediate region

[0161] TR terminal area

Claims

1. A semiconductor device comprising: The semiconductor layer has a first main surface and a second main surface, and includes a cell region and a terminal region surrounding the cell region; The first field plate electrode group includes a plurality of field plate electrodes, which are disposed in the terminal region of the semiconductor layer through a first insulating region and are arranged in a second direction orthogonal to a first direction from the first main surface toward the second main surface and from the unit region toward the terminal region. The second field plate electrode group includes a plurality of field plate electrodes disposed in the terminal region of the semiconductor layer with a second insulating region between them and arranged in the second direction, and adjacent to the first field plate electrode group in a third direction orthogonal to the first direction and the second direction. A gate electrode, facing the semiconductor layer in the first direction across a third insulating region, is disposed in the third direction between the first field plate electrode group and the second field plate electrode group; The fourth insulating region is disposed on the second main surface in the terminal region of the semiconductor layer; A first conductive film is disposed on the fourth insulating region and electrically connected to the plurality of field plate electrodes included in the first field plate electrode group via a first contact portion. A second conductive film is disposed on the fourth insulating region and is electrically connected to the plurality of field plate electrodes included in the second field plate electrode group via a second contact portion. A third conductive film is disposed on the fourth insulating region, located between the first conductive film and the second conductive film in the third direction, electrically connected to the gate electrode via a third contact portion, and extending from the third contact portion in the second direction. as well as The fifth insulating region is disposed in the third direction between the first conductive film and the third conductive film, and between the second conductive film and the third conductive film, and has a lower dielectric constant compared to the fourth insulating region.

2. The semiconductor device according to claim 1, wherein, The first end of the fifth insulating region on the terminal region side is located closer to the unit region side than the ends of the first conductive film and the second conductive film on the terminal region side. The second end of the fifth insulating region on the unit region side is located closer to the terminal region side than the end of the third conductive film on the unit region side.

3. The semiconductor device according to claim 2, wherein, The first end is located above the first insulating region between the end of the field plate electrode disposed on the terminal region side and the semiconductor layer, which is one of the plurality of field plate electrodes included in the first field plate electrode group.

4. The semiconductor device according to any one of claims 1 to 3, wherein, The fifth insulating region is also disposed on the first conductive film, the second conductive film, and the third conductive film.

5. The semiconductor device according to any one of claims 1 to 3, wherein, The semiconductor device also includes a sixth insulating region, which is directly disposed on the first conductive film, the second conductive film and the third conductive film, and has a higher dielectric constant compared with the fifth insulating region.

6. The semiconductor device according to any one of claims 1 to 3, wherein, The fourth insulating region is a silicon oxide film. The fifth insulating region is made of a material with a lower dielectric constant than silicon oxide film.

7. The semiconductor device according to claim 6, wherein, The fifth insulating region is a silicon oxide film with added carbon, a silicon oxide film with added fluorine, or a photoresist film.

8. The semiconductor device according to any one of claims 1 to 3, wherein, It also has: The first electrode is disposed on the first main surface of the semiconductor layer; The second electrode is disposed on the second main surface of the semiconductor layer; A first semiconductor region of a first conductivity type is disposed within the semiconductor layer and electrically connected to the first electrode; A second semiconductor region of a second conductivity type is disposed within the semiconductor layer and located above the first semiconductor region; as well as A third semiconductor region of a first conductivity type is disposed within the semiconductor layer and located above the second semiconductor region. The plurality of field plate electrodes included in the first field plate electrode group are disposed in the first semiconductor region, separated by the first insulating region. The plurality of field plate electrodes included in the second field plate electrode group are disposed in the first semiconductor region, separated by the second insulating region. The gate electrode is disposed opposite the second semiconductor region, separated by the third insulating region. The first conductive film and the second conductive film are electrically connected to the second electrode.

9. The semiconductor device according to any one of claims 1 to 3, wherein, The field plate electrodes of the first field plate electrode group and the field plate electrodes of the second field plate electrode group are arranged along the third direction.

10. A semiconductor device comprising: The semiconductor layer has a first main surface and a second main surface, and includes a cell region and a terminal region surrounding the cell region; A first field plate electrode is disposed in the terminal region of the semiconductor layer, separated by a first insulating region, and extends in a second direction orthogonal to a first direction from the first main surface toward the second main surface and from the cell region toward the terminal region; The second field plate electrode is disposed in the terminal region of the semiconductor layer, separated by a second insulating region, extends in the second direction, and is adjacent to the first field plate electrode in a third direction orthogonal to the first direction and the second direction; A gate electrode, facing the semiconductor layer in the first direction across a third insulating region, is disposed between the first field plate electrode and the second field plate electrode in the third direction. The fourth insulating region is disposed on the second main surface in the terminal region of the semiconductor layer; A first conductive film is disposed on the fourth insulating region and electrically connected to the first field plate electrode via a first contact portion; The second conductive film is disposed on the fourth insulating region and is electrically connected to the second field plate electrode via the second contact portion; A third conductive film is disposed on the fourth insulating region, located between the first conductive film and the second conductive film in the third direction, electrically connected to the gate electrode via a third contact portion, and extending from the third contact portion in the second direction. as well as The fifth insulating region is disposed in the third direction between the first conductive film and the third conductive film, and between the second conductive film and the third conductive film, and has a lower dielectric constant compared to the fourth insulating region.

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