Semiconductor structure and method of manufacturing the same, semiconductor device

Abstract

The application relates to a semiconductor structure and a manufacturing method thereof and a semiconductor device. The semiconductor structure comprises a substrate, a transistor, a hydrogen isolation layer and an etching stop layer. The transistor is located on one side of the substrate and comprises an active region located in the substrate and a gate structure located on one side of the active region in a first direction perpendicular to the substrate; the hydrogen isolation layer is located on a side of the transistor away from the substrate and covers the active region and the gate structure; and the etching stop layer is located on a side of the hydrogen isolation layer away from the transistor and covers the hydrogen isolation layer. The application can effectively improve a hot carrier injection (HCI) effect and is beneficial to improving device reliability.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method, and a semiconductor device. Background Technology

[0002] With the development of semiconductor technology, the process dimensions of semiconductor devices are constantly shrinking. However, because the power supply voltage is not proportionally matched to factors such as the channel length, junction depth, gate oxide thickness, and / or substrate doping concentration, the electric field within the device channel increases significantly, thereby converting charge carriers into high-energy hot carriers. Hot carriers enter the gate oxide through direct injection or tunneling, leading to the hot carrier injection (HCI) effect within the device.

[0003] In related technologies, the manufacturing process of the contact etch stop layer (CESL) introduces hydrogen (H) elements into semiconductor devices. These hydrogen (H) elements migrate into the gate oxide and channel, making the semiconductor devices prone to device failure due to the hot carrier injection effect, which adversely affects the device reliability. Summary of the Invention

[0004] Based on this, the embodiments of this application provide a semiconductor structure and its manufacturing method, as well as a semiconductor device, which can effectively improve the hot carrier injection (HCI) effect and help improve device reliability.

[0005] To achieve the above objectives, in a first aspect, some embodiments of this application provide a semiconductor structure. The semiconductor structure includes a substrate, a transistor, a hydrogen isolation layer, and an etch stop layer. The transistor is located on one side of the substrate and includes an active region located within the substrate and a gate structure located on one side of the active region in a first direction perpendicular to the substrate; the hydrogen isolation layer is located on the side of the transistor facing away from the substrate and covers the active region and the gate structure; the etch stop layer is located on the side of the hydrogen isolation layer facing away from the transistor and covers the hydrogen isolation layer.

[0006] In some embodiments, the thickness of the hydrogen isolation layer ranges from 100 Å to 200 Å.

[0007] In some embodiments, the material of the hydrogen isolation layer includes silicon oxycarbonate, silicon oxynitride, graphene, or nano-tantalum nitride.

[0008] In some embodiments, the active region includes a first heavily doped region, a second heavily doped region, and a channel region. The first heavily doped region and the second heavily doped region are located on opposite sides of the gate structure in a second direction parallel to the substrate; the channel region is located directly below the gate structure in the first direction and between the first heavily doped region and the second heavily doped region in the second direction; wherein the hydrogen isolation layer covers the first heavily doped region and the second heavily doped region.

[0009] In some embodiments, the active region further includes a lightly doped drain region; the lightly doped drain region is located below the gate structure in the first direction and between the channel region and the first heavily doped region and between the channel region and the second heavily doped region in the second direction.

[0010] In some embodiments, the gate structure includes a gate dielectric layer, a gate conductive layer, and a sidewall structure. The gate dielectric layer is located on the side of the active region facing away from the substrate in the first direction; the gate conductive layer is located on the side of the gate dielectric layer facing away from the active region in the first direction; the sidewall structure is located on both sidewalls of the gate conductive layer in a second direction parallel to the substrate, and on the side of the gate dielectric layer facing away from the active region in the first direction; wherein the sidewall structure along the first direction is flush with the sidewall of the gate dielectric layer along the first direction; the hydrogen isolation layer covers the sidewall of the gate dielectric layer along the first direction, the sidewall structure, and the gate conductive layer.

[0011] In some embodiments, the semiconductor structure further includes an active region contact layer, an active region contact hole, an active region contact structure, a gate contact layer, a gate contact hole, and a gate contact structure. An active region contact layer is located on the top surface of the active region away from the substrate in the first direction and is electrically connected to the active region; the hydrogen isolation layer also covers the active region contact layer; an active region contact hole is located on the side of the active region contact layer away from the active region in the first direction; the active region contact hole penetrates at least the etch stop layer and the hydrogen isolation layer and exposes at least a portion of the surface of the active region contact layer; an active region contact structure is embedded in the active region contact hole and is electrically connected to the active region contact layer; a gate contact layer is located on the top surface of the gate structure away from the substrate in the first direction and is electrically connected to the gate structure; the hydrogen isolation layer also covers the gate contact layer; a gate contact hole is located on the side of the gate contact layer away from the gate structure in the first direction; the gate contact hole penetrates at least the etch stop layer and the hydrogen isolation layer and exposes at least a portion of the surface of the gate structure; a gate contact structure is embedded in the gate contact hole and is electrically connected to the gate contact layer.

[0012] In some embodiments, the hydrogen content of the etching stop layer is less than or equal to 5%.

[0013] Secondly, according to some embodiments, this application also provides a method for manufacturing a semiconductor structure; the method for manufacturing a semiconductor structure can be used to prepare the semiconductor structure as described in the first aspect of this application.

[0014] In some embodiments, the method for manufacturing a semiconductor structure includes the following steps.

[0015] Provide substrate.

[0016] A transistor is formed on one side of the substrate; the transistor includes an active region located within the substrate and a gate structure located on one side of the active region in a first direction perpendicular to the substrate.

[0017] A hydrogen isolation layer is formed on the side of the transistor facing away from the substrate; the hydrogen isolation layer covers the active region and the gate structure.

[0018] An etch stop layer is formed on the side of the hydrogen isolation layer opposite to the transistor; the etch stop layer covers the hydrogen isolation layer.

[0019] In some embodiments, the process for forming the hydrogen isolation layer includes a plasma-enhanced chemical vapor deposition process.

[0020] In some embodiments, the process for forming the etch stop layer includes a low-hydrogen deposition process; wherein the deposition temperature range of the low-hydrogen deposition process is 350°C to 450°C; the reaction pressure range of the low-hydrogen deposition process is 2.0 Torr to 5.0 Torr; the high-frequency power range of the low-hydrogen deposition process is 600W to 1000W; and the low-frequency power range of the low-hydrogen deposition process is 200W to 400W.

[0021] In some embodiments, the reaction gases in the process of forming the etching stop layer include silane and ammonia; wherein the gas flow ratio of silane to ammonia ranges from 1:3 to 1:2.

[0022] In some embodiments, the silicon source precursor used in the etching stop layer formation process includes silane (SiH4), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), or tetrachlorosilane (SiCl4).

[0023] In some embodiments, forming a transistor on one side of the substrate includes the following steps.

[0024] A gate structure is formed on one side of the substrate.

[0025] A lightly doped drain region is formed in the substrate below the gate structure.

[0026] A first heavily doped region and a second heavily doped region are respectively formed in the substrate on both sides of the gate structure in a second direction parallel to the substrate.

[0027] In some embodiments, after forming the transistor on one side of the substrate, the manufacturing method further includes the following steps.

[0028] An active region contact layer electrically connected to the active region is formed on the top surface of the active region away from the substrate in the first direction.

[0029] A gate contact layer electrically connected to the gate structure is formed on the top surface of the gate structure facing away from the substrate in the first direction.

[0030] In some embodiments, after forming an etch stop layer on the side of the hydrogen isolation layer opposite to the transistor, the manufacturing method further includes the following steps.

[0031] The etch stop layer and the hydrogen isolation layer are etched along the first direction to form an active region contact hole on the side of the active region contact layer opposite to the active region in the first direction (e.g., the Z direction), and a gate contact hole is formed on the side of the gate contact layer opposite to the gate structure in the first direction (e.g., the Z direction). The active region contact hole penetrates at least the etch stop layer and the hydrogen isolation layer and exposes at least a portion of the surface of the active region contact layer, and the gate contact hole penetrates at least the etch stop layer and the hydrogen isolation layer and exposes at least a portion of the surface of the gate contact layer.

[0032] An active region contact structure electrically connected to the active region contact layer is formed in the active region contact hole, and a gate contact structure electrically connected to the gate contact layer is formed in the gate contact hole.

[0033] Thirdly, this application also provides a semiconductor device according to some embodiments; the semiconductor device includes the semiconductor structure as described in the first aspect of this application; or, a semiconductor structure prepared based on the manufacturing method of the semiconductor structure described in the second aspect of this application.

[0034] The embodiments of this application may have, or at least have, the following advantages:

[0035] In this embodiment, by setting a hydrogen isolation layer between the transistor and the etch stop layer, and making the hydrogen isolation layer cover the active region and gate structure of the transistor, the migration path of hydrogen (H) elements from the etch stop layer to the active region and gate structure of the transistor is effectively blocked. This effectively prevents hydrogen elements introduced during the etch stop layer manufacturing process from entering the active region and gate structure of the transistor. Without affecting the function of the etch stop layer, the hot carrier injection (HCI) effect caused by hydrogen migration can be fundamentally solved to avoid device failure. This is beneficial to improving the resistance to HCI degradation and the performance reliability of the semiconductor structure.

[0036] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of a semiconductor structure provided in some embodiments;

[0039] Figure 2 This is a hydrogen content curve of an etch stop layer provided in some embodiments;

[0040] Figure 3 This is a schematic diagram of another semiconductor structure provided in some embodiments;

[0041] Figure 4 This is a degradation curve of a semiconductor structure provided in some embodiments;

[0042] Figure 5 This is a schematic flowchart of a method for manufacturing a semiconductor structure provided in some embodiments;

[0043] Figure 6 This is a flowchart illustrating step S200 provided in some embodiments;

[0044] Figure 7 This is a schematic flowchart illustrating another method for manufacturing a semiconductor structure provided in some embodiments.

[0045] Explanation of reference numerals in the attached figures:

[0046] 1-Substrate, 2-Well region, T1-First transistor, T2-Second transistor, 3-Gate structure, 31-Gate dielectric layer, 32-Gate conductive layer, 33-Sidewall structure, AA-Active region, 41-First heavily doped region, 42-Second heavily doped region, 43-Channel region, 44-Lightly doped drain region, 5-Hydrogen isolation layer, 6-Etch stop layer, 7-Isolation structure, 8-Active region contact layer, 9-Active region contact structure, 10-Gate contact layer, 11-Gate contact structure. Detailed Implementation

[0047] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0049] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0050] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0051] Embodiments of the invention are described herein with reference to cross-sectional views illustrating preferred embodiments (and intermediate structures) of this application, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.

[0052] This application provides a semiconductor structure and its manufacturing method, as well as a semiconductor device, to effectively improve the hot carrier injection (HCI) effect and enhance device reliability.

[0053] In some embodiments, please refer to Figure 1 The semiconductor structure includes a substrate 1, a transistor, a hydrogen isolation layer 5, and an etch stop layer 6. The transistor is located on one side of the substrate 1 and includes an active region AA located within the substrate 1 and a gate structure 3 located on one side of the active region AA in a first direction perpendicular to the substrate (e.g., the Z direction). The hydrogen isolation layer 5 is located on the side of the transistor opposite to the substrate 1 and covers the active region AA and the gate structure 3. The etch stop layer 6 is located on the side of the hydrogen isolation layer 5 opposite to the transistor and covers the hydrogen isolation layer 5.

[0054] For example, substrate 1 can be made of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 1 can be a single-layer structure or a multi-layer structure. For example, substrate 1 can be a silicon (Si) substrate, silicon germanium (SiGe) substrate, silicon germanium carbon (SiGeC) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, indium antimonide (InSb) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 can be a layered substrate 1 comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator. Therefore, the type of substrate 1 should not limit the scope of protection of this application.

[0055] In some embodiments, please continue reading Figure 1 The semiconductor structure also includes a well region 2; the well region 2 is located inside the substrate 1 on the side close to the front side of the substrate 1; the active region AA is located inside the well region 2 on the side away from the back side of the substrate 1.

[0056] For example, well region 2 is of the first doping type.

[0057] For example, the thickness of the hydrogen isolation layer 5 ranges from 100 Å to 200 Å; the thickness of the hydrogen isolation layer 5 can be, for example, 100 Å, 110 Å, 120 Å, 130 Å, 140 Å, 150 Å, 160 Å, 170 Å, 180 Å, 190 Å or 200 Å, etc.

[0058] For example, the material of the hydrogen isolation layer 5 includes, but is not limited to, silicon oxycarbonate (SiOC), silicon oxynitride (SiON), graphene, or nano-tantalum nitride (TaN).

[0059] For example, the process for forming the hydrogen isolation layer 5 includes, but is not limited to, plasma-enhanced chemical vapor deposition (PECVD) process.

[0060] For example, in an embodiment where the material of the hydrogen isolation layer 5 is silicon oxycarbonate (SiOC), silicon oxycarbonate (SiOC) can be generated by reacting carbon dioxide (CO2) and silane (SiH4), with the chemical reaction formula being CO2 + SiH4 → SiOC + H2↑.

[0061] For example, in an embodiment where the material of the hydrogen isolation layer 5 is silicon oxynitride (SiON), silicon oxynitride (SiON) can be generated by reacting nitrous oxide (N2O) and silane (SiH4), with the chemical reaction formula being N2O + SiH4 → SiON + H2↑.

[0062] For example, the material of the etch stop layer 6 includes, but is not limited to, silicon nitride (SiN).

[0063] In this embodiment, by providing a hydrogen isolation layer 5 between the transistor and the etch stop layer 6, and by covering the active region AA and gate structure 3 of the transistor with the hydrogen isolation layer 5, the migration path of hydrogen (H) elements from the etch stop layer 6 to the active region AA and gate structure 3 of the transistor is effectively blocked. This effectively prevents hydrogen elements introduced during the manufacturing process of the etch stop layer 6 from entering the active region AA and gate structure 3 of the transistor. Without affecting the function of the etch stop layer 6, the hot carrier injection (HCI) effect caused by hydrogen migration can be fundamentally solved to avoid device failure. This is beneficial to improving the resistance to HCI degradation and the performance reliability of the semiconductor structure.

[0064] In some embodiments, please continue reading Figure 1The active region AA includes a first heavily doped region 41, a second heavily doped region 42, and a channel region 43. The first heavily doped region 41 and the second heavily doped region 42 are located on opposite sides of the gate structure 3 in a second direction (e.g., the X direction) parallel to the substrate; the channel region 43 is located directly below the gate structure 3 in the first direction (e.g., the Z direction) and between the first heavily doped region 41 and the second heavily doped region 42 in the second direction (e.g., the X direction); wherein, the hydrogen isolation layer 5 covers the first heavily doped region 41 and the second heavily doped region 42.

[0065] For example, both the first heavily doped region 41 and the second heavily doped region 42 are of the second doping type.

[0066] For example, please continue reading Figure 1 The transistor includes a first transistor T1 and a second transistor T2 spaced apart along a second direction (e.g., the X direction) parallel to the substrate.

[0067] For example, an isolation structure 7 is provided between the first transistor T1 and the second transistor T2. The isolation structure 7 is embedded in the substrate 1 between the first transistor T1 and the second transistor T2.

[0068] In this embodiment, the first doping type is P-type, and the second doping type is N-type, such as... Figure 1 The first transistor T1 shown; or, the first doping type is N-type and the second doping type is P-type, as shown in the example. Figure 1 The second transistor T2 is shown in the figure.

[0069] For example, the first heavily doped region 41 and the second heavily doped region 42 can be used as the source and drain regions of a transistor, respectively.

[0070] For example, the isolation structure 7 includes, but is not limited to, shallow trench isolation (STI).

[0071] In some embodiments, please continue reading Figure 1 The active region AA further includes a lightly doped drain region 44; the lightly doped drain region 44 is located below the gate structure 3 in the first direction (e.g., the Z direction), and is located between the channel region 43 and the first heavily doped region 41 and between the channel region 43 and the second heavily doped region 42 in the second direction (e.g., the X direction).

[0072] For example, the lightly doped drain region 44 is of the second doping type.

[0073] For example, the doping concentration of the lightly doped drain region 44 is less than that of the first heavily doped region 41 and the second heavily doped region 42.

[0074] For example, please continue reading Figure 1 There can be two lightly doped drain regions 44, which are located on the side of the first heavily doped region 41 and the second heavily doped region 42 in the second direction (e.g., the X direction) near the channel region 43, and are connected to the first heavily doped region 41 and the second heavily doped region 42, respectively.

[0075] In some embodiments, please continue reading Figure 1 The gate structure 3 includes a gate dielectric layer 31, a gate conductive layer 32, and a sidewall structure 33. The gate dielectric layer 31 is located on the side of the active region AA facing away from the substrate 1 in the first direction (e.g., the Z direction); the gate conductive layer 32 is located on the side of the gate dielectric layer 31 facing away from the active region AA in the first direction (e.g., the Z direction); the sidewall structure 33 is located on both sides of the gate conductive layer 32 in a second direction parallel to the substrate (e.g., the X direction), and on the side of the gate dielectric layer 31 facing away from the active region AA in the first direction (e.g., the Z direction); wherein, the sidewall structure 33 is flush with the sidewall of the gate dielectric layer 31 along the first direction (e.g., the Z direction) along the same direction; the hydrogen isolation layer 5 covers the sidewall of the gate dielectric layer 31 along the first direction (e.g., the Z direction), the sidewall structure 33, and the gate conductive layer 32.

[0076] For example, the material of the gate dielectric layer 31 includes, but is not limited to, insulating materials, such as silicon dioxide (SiO2).

[0077] For example, the material of the gate conductive layer 32 includes, but is not limited to, polysilicon.

[0078] For example, the material of the sidewall structure 33 includes, but is not limited to, insulating materials, such as silicon nitride (Si3N4) or silicon dioxide (SiO2).

[0079] In some examples, please refer to [link / reference]. Figure 1 The lightly doped region is located directly below the sidewall structure 33 in the first direction (e.g., the Z direction) and is connected to the gate dielectric layer 31.

[0080] In some embodiments, the hydrogen content of the etch stop layer 6 is less than or equal to 5%.

[0081] For example, the hydrogen content of the etch stop layer 6 can be 5%, 4%, 3%, 2.5%, 2%, 1.5%, 1%, or 0.5%, etc.

[0082] For example, the formation process of the etch stop layer 6 includes, but is not limited to, plasma-enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD).

[0083] In some examples, the etch stop layer 6 is a silicon nitride (SiN) layer; for example, silane (SiH4) and ammonia (NH3) can be used as reactant gases in the deposition process, and an inert gas can be used as an auxiliary gas.

[0084] It should be noted that the etch stop layer 6 in this embodiment is formed using a low-hydrogen deposition process. By controlling the deposition temperature, reactive gas flow rate, reaction pressure, and deposition power in the deposition process, the hydrogen content in the etch stop layer 6 is controlled within a target range (e.g., hydrogen content less than or equal to 5%). Specific process parameters for the low-hydrogen deposition process are shown in the following example.

[0085] For example, the deposition temperature range of the etch stop layer 6 includes 350°C to 450°C.

[0086] Specifically, the deposition temperature of the etch stop layer 6 can be 350℃, 360℃, 380℃, 400℃, 420℃, 440℃, or 450℃, etc.

[0087] For example, in the low-hydrogen deposition process of the etch stop layer 6, the flow rate ratio of silane (SiH4) to ammonia (NH3) gas ranges from 1:3 to 1:2.

[0088] Specifically, in the low-hydrogen deposition process of the etching stop layer 6, the flow rate ratio of silane (SiH4) to ammonia (NH3) can be, for example, 1:3, 3:8, 5:12, 11:24, or 1:2.

[0089] For example, in the low-hydrogen deposition process of the etch stop layer 6, the gas flow rate of silane (SiH4) ranges from 100 sccm to 150 sccm.

[0090] Specifically, the gas flow rate of silane (SiH4) in the low-hydrogen deposition process of the etching stop layer 6 can be, for example, 100 sccm, 110 sccm, 120 sccm, 130 sccm, 140 sccm or 150 sccm.

[0091] For example, the ammonia (NH3) gas flow rate ranges from 200 sccm to 300 sccm in the low-hydrogen deposition process of the etching stop layer 6.

[0092] Specifically, the flow rate of ammonia (NH3) in the low-hydrogen deposition process of the etching stop layer 6 can be, for example, 200 sccm, 220 sccm, 240 sccm, 250 sccm, 260 sccm, 280 sccm or 300 sccm.

[0093] In some examples, the inert gas used as an auxiliary gas in the low-hydrogen deposition process of the etch stop layer 6 includes, but is not limited to, nitrogen (N2).

[0094] For example, the nitrogen (N2) gas flow rate ranges from 15,000 sccm to 20,000 sccm in the low-hydrogen deposition process of the etching stop layer 6.

[0095] Specifically, the flow rate of nitrogen (N2) in the low-hydrogen deposition process of the etching stop layer 6 can be, for example, 15000 sccm, 16000 sccm, 17000 sccm, 18000 sccm, 19000 sccm or 20000 sccm.

[0096] For example, the reaction pressure range in the low-hydrogen deposition process of the etch stop layer 6 includes 2 Torr to 5 Torr.

[0097] Specifically, the reaction pressure in the low-hydrogen deposition process of the etching stop layer 6 can be, for example, 2 Torr, 2.5 Torr, 3 Torr, 3.5 Torr, 4 Torr, 4.5 Torr, or 5 Torr.

[0098] It should be noted that the deposition power of the etch stop layer 6 includes high frequency power (HF) and low frequency power (LF).

[0099] For example, the high-frequency power range of the low-hydrogen deposition process for the etch stop layer 6 includes 600W to 1000W.

[0100] Specifically, the high-frequency power of the low-hydrogen deposition process for the etch stop layer 6 can be, for example, 600W, 700W, 800W, 900W, or 1000W.

[0101] For example, the low-frequency power range of the low-hydrogen deposition process for the etch stop layer 6 includes 200W to 400W.

[0102] Specifically, the low-frequency power of the low-hydrogen deposition process for the etching stop layer 6 can be, for example, 200W, 250W, 300W, 350W, or 400W.

[0103] In some embodiments, the hydrogen content of the etch stop layer 6 can be further reduced by using a silicon source precursor with a relatively low hydrogen content in the deposition process of the etch stop layer 6.

[0104] For example, the silicon source precursors used in the deposition process of the etch stop layer 6 include, but are not limited to, silane (SiH4), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), or tetrachlorosilane (SiCl4).

[0105] For example, to verify the effect of the embodiments of this application on reducing the hydrogen content in the etch stop layer 6, hydrogen content tests were performed on a conventional etch stop layer formed using a conventional deposition process and an etch stop layer 6 formed using a low-hydrogen deposition process as described in the above examples of this application. The test results are as follows: Figure 2 As shown; where curve A is the hydrogen content curve of the conventional etch stop layer formed using a conventional deposition process, and curve B is the hydrogen content curve of the etch stop layer 6 formed using the low-hydrogen deposition process of this application. According to Figure 2 It can be seen that the hydrogen content (H%) at multiple different test points in the etching stop layer 6 in this embodiment is significantly lower than that of conventional etching stop layers, and is less than or equal to 5%.

[0106] As described above, by controlling the specific process parameters of the low-hydrogen deposition process, this embodiment of the application can promote the full dissociation of the silicon source and its efficient bonding with the nitrogen source, thereby minimizing the proportion of residual Si-H bonds and NH bonds in the thin film. In this way, the hydrogen content in the etch stop layer 6 can be effectively reduced, and the hydrogen content can be controlled within the target range (less than or equal to 5%), thereby reducing the introduction of hydrogen into the semiconductor structure from the source.

[0107] Furthermore, this embodiment combines the "source reduction" effect of the low-hydrogen etch stop layer 6 with the "flow blocking" effect of the hydrogen isolation layer 5 to form a dual protection mechanism for hydrogen elements in the semiconductor structure, which reduces the source and blocks the path. This significantly reduces the probability of hydrogen elements migrating from the etch stop layer 6 to the channel region 43 and the gate dielectric layer 31, thereby effectively solving the device failure problems such as threshold voltage drift and transconductance degradation caused by the hot carrier injection (HCI) effect. This is beneficial to improving the semiconductor structure's resistance to HCI degradation and its performance reliability.

[0108] In some embodiments, please refer to Figure 3The semiconductor structure also includes an active region contact layer 8, an active region contact hole, an active region contact structure 9, a gate contact layer 10, a gate contact hole, and a gate contact structure 11. The active region contact layer 8 is located on the top surface of the active region AA facing away from the substrate 1 in the first direction (e.g., the Z direction) and is electrically connected to the active region AA; the hydrogen isolation layer 5 also covers the active region contact layer 8; the active region contact hole is located on the side of the active region contact layer 8 facing away from the active region AA in the first direction (e.g., the Z direction); the active region contact hole at least penetrates the etch stop layer 6 and the hydrogen isolation layer 5, and exposes at least a portion of the surface of the active region contact layer 8; the active region contact structure 9 is embedded in the active region contact hole and is electrically connected to the active region contact layer 8. The gate contact layer 10 is located on the top surface of the gate structure 3 facing away from the substrate 1 in the first direction (e.g., the Z direction) and is electrically connected to the gate structure 3; the hydrogen isolation layer 5 also covers the gate contact layer 10; the gate contact hole is located on the side of the gate contact layer 10 facing away from the gate structure 3 in the first direction (e.g., the Z direction); the gate contact hole penetrates at least the etch stop layer 6 and the hydrogen isolation layer 5 and exposes at least a portion of the surface of the gate structure 3; the gate contact structure 11 is embedded in the gate contact hole and is electrically connected to the gate contact layer 10.

[0109] For example, the material of the active region contact layer 8 includes, but is not limited to, metal silicides.

[0110] For example, the material of the active region contact structure 9 includes, but is not limited to, conductive metals, such as copper (Cu) or zinc (Zu).

[0111] For example, the material of the gate contact layer 10 includes, but is not limited to, metal silicide.

[0112] For example, the material of the gate contact structure 11 includes, but is not limited to, conductive metals, such as copper (Cu) or zinc (Zu).

[0113] For example, the gate contact structure 11 covers the surface of the gate conductive layer 32 facing away from the gate insulating layer in a first direction (e.g., the Z direction).

[0114] For example, to verify the improvement effect of the semiconductor structure provided in this application embodiment on device failure caused by the hot carrier injection (HCI) effect, an N-channel metal-oxide-semiconductor field-effect transistor (NMOS transistor) with a rated voltage of 5V was used as an example, and it was tested with a drain voltage of 5.5V and a gate voltage of 2.8V. The degradation curve of the semiconductor structure was obtained as follows: Figure 4As shown. It should be noted that in related technologies, a 10% degradation of the drain saturation current (Idsat) is typically used as the criterion for device failure. Figure 4 As can be seen, as the working time increases, the degradation rate of the drain saturation current (Idsat) of the semiconductor structure in this embodiment remains below 10%, and no device failure occurs.

[0115] As described above, in this embodiment, by setting a hydrogen isolation layer 5 to block the migration channel of hydrogen elements between the etch stop layer 6 and the channel region 43 and the gate dielectric layer 31, and by using a low-hydrogen deposition process to control the hydrogen content in the etch stop layer 6 within the target range (less than or equal to 5%), it is possible to effectively improve the hot carrier injection (HCI) effect of the semiconductor structure to avoid device failure, thereby improving the semiconductor structure's resistance to HCI degradation and its performance reliability.

[0116] This application also provides a method for manufacturing a semiconductor structure according to some embodiments; this method can be used to prepare the semiconductor structure as described in the foregoing embodiments of this application. The manufacturing method of this semiconductor structure also possesses all the technical advantages of the aforementioned semiconductor structure. It should be noted that the parts that are the same as or corresponding to the above embodiments can be referred to the corresponding descriptions of the foregoing embodiments, and will not be elaborated upon below.

[0117] In some embodiments, please refer to Figure 5 The method for manufacturing a semiconductor structure includes the following steps S100~S400.

[0118] S100 provides a substrate.

[0119] S200, a transistor is formed on one side of a substrate; the transistor includes an active region located within the substrate and a gate structure located on one side of the active region in a first direction perpendicular to the substrate (e.g., the Z direction).

[0120] S300, a hydrogen isolation layer is formed on the side of the transistor away from the substrate; the hydrogen isolation layer covers the active region and the gate structure.

[0121] For example, the process for forming the hydrogen isolation layer includes, but is not limited to, plasma-enhanced chemical vapor deposition (PECVD).

[0122] For example, the material of the hydrogen isolation layer 5 includes, but is not limited to, silicon oxycarbonate (SiOC), silicon oxynitride (SiON), graphene, or nano-tantalum nitride (TaN).

[0123] For example, in an embodiment where the material of the hydrogen isolation layer 5 is silicon oxycarbonate (SiOC), silicon oxycarbonate (SiOC) can be generated by reacting carbon dioxide (CO2) and silane (SiH4), with the chemical reaction formula being CO2 + SiH4 → SiOC + H2↑.

[0124] For example, in an embodiment where the material of the hydrogen isolation layer 5 is silicon oxynitride (SiON), silicon oxynitride (SiON) can be generated by reacting nitrous oxide (N2O) and silane (SiH4), with the chemical reaction formula being N2O + SiH4 → SiON + H2↑.

[0125] For example, the process for forming the etch stop layer includes, but is not limited to, plasma-enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD).

[0126] In some embodiments, the process for forming the etch stop layer includes a low-hydrogen deposition process; wherein the deposition temperature range of the low-hydrogen deposition process is 350°C to 450°C; the reaction pressure range of the low-hydrogen deposition process is 2.0 Torr to 5.0 Torr; the high-frequency power range of the low-hydrogen deposition process is 600W to 1000W; and the low-frequency power range of the low-hydrogen deposition process is 200W to 400W.

[0127] For example, in the low-hydrogen deposition process of the etch stop layer, the gas flow rate of silane (SiH4) ranges from 100 sccm to 150 sccm.

[0128] For example, in the low-hydrogen deposition process of the etching stop layer, the gas flow rate of ammonia (NH3) ranges from 200 sccm to 300 sccm.

[0129] In some embodiments, the reactive gases in the etching stop layer formation process include silane (SiH4) and ammonia (NH3); wherein the gas flow ratio of silane (SiH4) to ammonia (NH3) ranges from 1:3 to 1:2.

[0130] In some examples, an inert gas is also used as an auxiliary gas in the process of forming the etch stop layer.

[0131] For example, inert gases include, but are not limited to, nitrogen (N2).

[0132] For example, in the low-hydrogen deposition process of the etching stop layer, the flow rate of nitrogen (N2) ranges from 15,000 sccm to 20,000 sccm.

[0133] In some embodiments, the silicon source precursor used in the etching stop layer formation process includes silane (SiH4), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), or tetrachlorosilane (SiCl4).

[0134] S400, an etch stop layer is formed on the side of the hydrogen isolation layer away from the transistor; the etch stop layer covers the hydrogen isolation layer.

[0135] In some embodiments, please refer to Figure 6 Step S200 includes the following steps S210~S230.

[0136] S210, a gate structure is formed on one side of the substrate.

[0137] S220, a lightly doped drain region is formed in the substrate below the gate structure.

[0138] S230, a first heavily doped region and a second heavily doped region are formed in the substrate on both sides of the gate structure in a second direction (e.g., the X direction) parallel to the substrate.

[0139] In some embodiments, please refer to Figure 7 After step S200, the manufacturing method further includes the following steps S510 to S520.

[0140] S510, an active region contact layer electrically connected to the active region is formed on the top surface of the active region away from the substrate in a first direction (e.g., the Z direction).

[0141] S520, a gate contact layer electrically connected to the gate structure is formed on the top surface of the gate structure away from the substrate in a first direction (e.g., the Z direction).

[0142] In some embodiments, please continue reading Figure 7 After step S400, the manufacturing method further includes the following steps S610 to S620.

[0143] S610, an etch stop layer and a hydrogen isolation layer are etched along a first direction (e.g., the Z direction) to form an active region contact hole on the side of the active region contact layer away from the active region in the first direction (e.g., the Z direction), and a gate contact hole is formed on the side of the gate structure away from the gate in the first direction (e.g., the Z direction); the active region contact hole penetrates at least the etch stop layer and the hydrogen isolation layer and exposes at least a portion of the surface of the active region contact layer, and the gate contact hole penetrates at least the etch stop layer and the hydrogen isolation layer and exposes at least a portion of the surface of the gate contact layer.

[0144] S620, an active region contact structure electrically connected to the active region contact layer is formed in the active region contact hole, and a gate contact structure electrically connected to the gate contact layer is formed in the gate contact hole.

[0145] It should be understood that, although Figures 5-7 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 5-7 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0146] This application also provides a semiconductor device according to some embodiments; the semiconductor device includes the semiconductor structure as described in the foregoing embodiments of this application; or, a semiconductor structure prepared based on the manufacturing method of the semiconductor structure described in the foregoing embodiments of this application. The semiconductor device also possesses the technical advantages of the aforementioned semiconductor structures and their manufacturing methods. It should be noted that the parts that are the same as or corresponding to the above embodiments can be referred to the corresponding descriptions of the foregoing embodiments, and will not be described in detail below.

[0147] In the description of this specification, references to terms such as "some embodiments," "some examples," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0148] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0149] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A transistor, located on one side of the substrate, includes an active region located within the substrate and a gate structure located on one side of the active region in a first direction perpendicular to the substrate; A hydrogen isolation layer is located on the side of the transistor facing away from the substrate, covering the active region and the gate structure; An etch stop layer is located on the side of the hydrogen isolation layer opposite to the transistor and covers the hydrogen isolation layer.

2. The semiconductor structure according to claim 1, characterized in that, The thickness of the hydrogen isolation layer ranges from 100 Å to 200 Å.

3. The semiconductor structure according to claim 1, characterized in that, The hydrogen isolation layer is made of materials including silicon oxycarbonate, silicon oxynitride, graphene, or nano-tantalum nitride.

4. The semiconductor structure according to claim 1, characterized in that, The active region includes: First doped region; The second doped region; the first doped region and the second doped region are located on both sides of the gate structure in a second direction parallel to the substrate; The channel region is located directly below the gate structure in the first direction and between the first heavily doped region and the second heavily doped region in the second direction; The lightly doped drain region is located below the gate structure in the first direction and between the channel region and the first heavily doped region and between the channel region and the second heavily doped region in the second direction; The hydrogen isolation layer covers the first heavily doped region and the second heavily doped region.

5. The semiconductor structure according to claim 1, characterized in that, The gate structure includes: A gate dielectric layer is located on the side of the active region facing away from the substrate in the first direction; A gate conductive layer is located on the side of the gate dielectric layer that is away from the active region in the first direction; The sidewall structure is located on both sides of the gate conductive layer in a second direction parallel to the substrate, and on the side of the gate dielectric layer away from the active region in the first direction. Wherein, the sidewall structure along the first direction is flush with the sidewall of the gate dielectric layer along the first direction; the hydrogen isolation layer covers the sidewall of the gate dielectric layer along the first direction, the sidewall structure, and the gate conductive layer.

6. The semiconductor structure according to claim 1, characterized in that, Also includes: An active region contact layer is located on the top surface of the active region facing away from the substrate in the first direction and is electrically connected to the active region; The hydrogen isolation layer also covers the active region contact layer; An active region contact hole is located on the side of the active region contact layer opposite to the active region in the first direction; the active region contact hole penetrates at least the etch stop layer and the hydrogen isolation layer, and exposes at least a portion of the surface of the active region contact layer; An active region contact structure is embedded in the active region contact hole and electrically connected to the active region contact layer; A gate contact layer is located on the top surface of the gate structure facing away from the substrate in the first direction and is electrically connected to the gate structure; the hydrogen isolation layer also covers the gate contact layer; A gate contact hole is located on the side of the gate contact layer opposite to the gate structure in the first direction; the gate contact hole penetrates at least the etch stop layer and the hydrogen isolation layer, and exposes at least a portion of the surface of the gate structure; A gate contact structure is embedded in the gate contact hole and electrically connected to the gate contact layer.

7. The semiconductor structure according to claim 1, characterized in that, The hydrogen content of the etching stop layer is less than or equal to 5%.

8. A method for manufacturing a semiconductor structure, characterized in that, include: Provide substrate; A transistor is formed on one side of the substrate; The transistor includes an active region located within the substrate and a gate structure located on one side of the active region in a first direction perpendicular to the substrate; A hydrogen isolation layer is formed on the side of the transistor opposite to the substrate; The hydrogen isolation layer covers the active region and the gate structure; An etch stop layer is formed on the side of the hydrogen isolation layer opposite to the transistor; the etch stop layer covers the hydrogen isolation layer.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, The process for forming the hydrogen isolation layer includes plasma-enhanced chemical vapor deposition.

10. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, The etching stop layer formation process includes a low-hydrogen deposition process; wherein the deposition temperature range of the low-hydrogen deposition process is 350℃~450℃; the reaction pressure range of the low-hydrogen deposition process is 2.0 Torr~5.0 Torr; the high-frequency power range of the low-hydrogen deposition process is 600W~1000W; and the low-frequency power range of the low-hydrogen deposition process is 200W~400W.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, The reaction gases in the process of forming the etching stop layer include silane and ammonia; wherein the gas flow ratio of silane to ammonia ranges from 1:3 to 1:

2.

12. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, The silicon source precursors used in the etching stop layer formation process include silane (SiH4), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), or tetrachlorosilane (SiCl4).

13. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, The method of forming a transistor on one side of the substrate includes: A gate structure is formed on one side of the substrate; A lightly doped drain region is formed in the substrate below the gate structure; A first heavily doped region and a second heavily doped region are respectively formed in the substrate on both sides of the gate structure in a second direction parallel to the substrate.

14. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, After forming the transistor on one side of the substrate, the manufacturing method further includes: An active region contact layer electrically connected to the active region is formed on the top surface of the active region facing away from the substrate in the first direction; A gate contact layer electrically connected to the gate structure is formed on the top surface of the gate structure facing away from the substrate in the first direction; After forming an etch stop layer on the side of the hydrogen isolation layer opposite to the transistor, the manufacturing method further includes: The etch stop layer and the hydrogen isolation layer are etched along the first direction to form an active region contact hole on the side of the active region contact layer opposite to the active region in the first direction, and a gate contact hole is formed on the side of the gate contact layer opposite to the gate structure in the first direction; the active region contact hole penetrates at least the etch stop layer and the hydrogen isolation layer and exposes at least a portion of the surface of the active region contact layer, and the gate contact hole penetrates at least the etch stop layer and the hydrogen isolation layer and exposes at least a portion of the surface of the gate contact layer; An active region contact structure electrically connected to the active region contact layer is formed in the active region contact hole, and a gate contact structure electrically connected to the gate contact layer is formed in the gate contact hole.

15. A semiconductor device, characterized in that, Includes the semiconductor structure as described in any one of claims 1 to 7; or, a semiconductor structure prepared based on the manufacturing method of the semiconductor structure as described in any one of claims 8 to 14.

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