Semiconductor device and method of manufacturing the same, electronic device

Abstract

The application provides a semiconductor device and a manufacturing method thereof and an electronic device. The semiconductor device introduces a high-resistance first epitaxial layer across the unit cell region and the termination region on the side of the super-junction drift region close to the substrate, and only performs first-conductivity-type ion implantation on a first region corresponding to the unit cell region in the first epitaxial layer, and does not perform first-conductivity-type ion implantation on a second region, so that the first region forms a first doped region in communication with a second doped region. In this way, when the semiconductor device bears a high reverse bias, the depletion region can extend to the first epitaxial layer due to the presence of the first epitaxial layer, the electric field concentration effect at the substrate junction is alleviated, the electric field distribution of the termination region tends to be uniform, and the termination efficiency of the device is improved. Meanwhile, due to the improved termination withstand voltage capacity, a more compact termination design can be adopted under the premise of meeting the same withstand voltage level, which is beneficial to the miniaturization and cost reduction of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor power device technology, and more specifically, to a semiconductor device and its fabrication method, and an electronic device. Background Technology

[0002] Superjunction MOSFETs are power semiconductor devices widely used in power management, motor drives, inverters, and various switching power supplies. Compared to traditional power MOSFETs, superjunction devices introduce alternating P-type and N-type pillars into the drift region. Utilizing the lateral charge compensation effect between the P / N pillars, the drift region is fully depleted under high reverse bias, thus achieving a higher breakdown voltage while maintaining low on-resistance. Currently, the drift region of superjunction MOSFETs is typically fabricated using a combination of multilayer epitaxy and ion implantation to ultimately form a high-voltage superjunction drift region.

[0003] However, in the aforementioned multilayer epitaxial superjunction process, the terminal region and the unit cell region of the device are usually treated with the same process. That is, after the epitaxial growth of each layer, N-type and P-type ion implantation is performed on the terminal region, resulting in a P / N pillar arrangement in the terminal region that is similar to the structure of the unit cell region. With this treatment, when the device is subjected to high reverse bias, the electric field distribution at the edge of the terminal region is relatively concentrated, and there is a significant electric field peak at the junction of the bottom of the P / N pillars and the substrate. The device is prone to premature breakdown at the edge of the terminal region, rather than uniform breakdown throughout the entire active region, resulting in a lower termination efficiency—the ratio of actual breakdown voltage to theoretical breakdown voltage. Summary of the Invention

[0004] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of this application is to provide a semiconductor device and a method for manufacturing the same, as well as an electronic device, wherein the semiconductor device includes: Substrate; A first epitaxial layer located on one side of the substrate, the first epitaxial layer including a first region and a second region, the orthographic projection of the second region on the substrate surrounding the orthographic projection of the first region on the substrate, the first region being a first doped region of a first conductivity type; The second epitaxial layer located on the side of the first epitaxial layer away from the substrate includes a third region and a fourth region in a direction parallel to the substrate. The third region includes a plurality of conductive pillars of a second conductivity type arranged at intervals. The conductive pillars extend in a direction perpendicular to the substrate. The fourth region is a second doped region of a first conductivity type. Part of the fourth region is located between two adjacent conductive pillars, and at least part of the fourth region is located between the conductive pillars and the first epitaxial layer. The second doped region is connected to the first doped region.

[0005] In one possible implementation, the first conductivity type is N-type and the second conductivity type is P-type.

[0006] In one possible implementation, the resistivity of the first epitaxial layer is 10 to 1000 Ω•cm.

[0007] In one possible implementation, the thickness of the first epitaxial layer is 2 to 20 μm.

[0008] In one possible implementation, the semiconductor device further includes a field plate structure, the orthographic projection of which onto the substrate lies within the orthographic projection of the second region of the first epitaxial layer onto the substrate; The field plate structure includes a dielectric layer located on the side of the second epitaxial layer away from the substrate and a conductive layer located on the side of the dielectric layer away from the substrate.

[0009] This application also provides a method for fabricating a semiconductor device, comprising: Provide substrate; A first epitaxial layer is formed on one side of the substrate. The first epitaxial layer includes a first region and a second region. The orthographic projection of the second region on the substrate surrounds the orthographic projection of the first region on the substrate. Ion implantation of a first conductivity type is performed in the first region of the first epitaxial layer; A second epitaxial layer is formed on the side of the first epitaxial layer away from the substrate, and ion implantation of a first conductivity type and ion implantation of a second conductivity type are performed in the second epitaxial layer; A high-temperature push-junction process is performed to allow the first type of conductivity ions implanted in the first region to diffuse with the first type of conductivity ions in the second epitaxial layer, forming a first doped region of the first conductivity type and a second doped region of the first conductivity type that are interconnected; and to allow the second type of conductivity ions to diffuse with each other, forming a plurality of conductive pillars of the second conductivity type arranged at intervals; wherein, the conductive pillars extend in a direction perpendicular to the substrate.

[0010] In one possible implementation, the step of performing ion implantation of a first conductivity type in the first region of the first epitaxial layer includes: A first photoresist layer is formed on the side of the first epitaxial layer away from the substrate; The first photoresist layer is etched to form a first window, which exposes the first region, and ion implantation of a first conductivity type is performed through the first window. Remove the first photoresist layer.

[0011] In one possible implementation, the step of forming a second epitaxial layer on the side of the first epitaxial layer away from the substrate, and performing first conductivity type ion implantation and second conductivity type ion implantation in the second epitaxial layer includes: A second epitaxial sublayer is formed on the side of the first epitaxial layer away from the substrate; The second epitaxial sublayer is implanted with ions of the first conductivity type; A second photoresist layer is formed on the side of the second epitaxial sublayer away from the substrate; The second photoresist layer is etched to form a second window, which exposes a third region of the second epitaxial sublayer. Ion implantation of a second conductivity type is performed through the second window. Remove the second photoresist layer; Repeat the above steps to form a second epitaxial layer composed of multiple stacked second epitaxial sublayers.

[0012] In one possible implementation, the first conductivity type ion is a phosphorus ion, and the second conductivity type ion is a boron ion.

[0013] This application also provides an electronic device, including any of the semiconductor devices described in the preceding claims, or a semiconductor device manufactured by the method described in any of the preceding claims.

[0014] Based on any of the above aspects, this application provides a semiconductor device and its fabrication method, as well as an electronic device. The semiconductor device introduces a high-resistivity first epitaxial layer spanning a unit cell region and a termination region on the side of the superjunction drift region near the substrate. Simultaneously, only a first region corresponding to the unit cell region in the first epitaxial layer undergoes ion implantation of a first conductivity type, while the second region does not undergo ion implantation of the first conductivity type, thus forming a first doped region connected to a second doped region. In this way, when the semiconductor device is subjected to a high reverse bias, due to the presence of the first epitaxial layer, the depletion region can extend into the first epitaxial layer, alleviating the electric field concentration effect at the substrate interface, making the electric field distribution in the termination region more uniform, and improving the termination efficiency of the device. At the same time, because the termination breakdown voltage is improved, a more compact termination design can be adopted while meeting the same breakdown voltage level, which is beneficial for the miniaturization and cost reduction of the semiconductor device. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is one of the schematic diagrams of the semiconductor device provided in this embodiment; Figure 2 This is the second schematic diagram of the semiconductor device provided in this embodiment; Figure 3 This is a schematic flowchart illustrating the method for fabricating the semiconductor device provided in this embodiment; Figure 4 This is a schematic diagram of the process structure for fabricating a semiconductor device provided in this embodiment; Figure 5 A schematic diagram of the flow structure of step S13 of the semiconductor device fabrication method provided in this embodiment; Figure 6 This is a schematic diagram of the process structure of step S14 of the semiconductor device fabrication method provided in this embodiment.

[0017] Icons: Semiconductor device-10; Substrate-100; First epitaxial layer-200; First region-201; Second region-202; First doped region-210; Second epitaxial layer-300; Third region-301; Fourth region-302; Conductive pillar-310; Second doped region-320; Field structure-400; Dielectric layer-410; Conductive layer-420; First photoresist layer-910; First window-911; Second photoresist layer-920; Second window-921; Second epitaxial sublayer-390. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0021] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0023] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0024] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0025] The inventors discovered that related technologies improve the electric field distribution in the termination region of a superjunction MOSFET by setting a specific electric field modulation structure thereon, thereby enhancing the device's breakdown voltage characteristics. However, this approach primarily relies on an additional structure above the termination region for electric field modulation, which limits its effectiveness in improving the electric field distribution in the drift region within the termination region. Under specific device design conditions, the termination region still requires a significant chip area to meet the breakdown voltage requirements.

[0026] In view of this, please refer to Figure 1 This application provides a semiconductor device 10, including a substrate 100, a first epitaxial layer 200 located on one side of the substrate 100, and a second epitaxial layer 300 located on the side of the first epitaxial layer 200 away from the substrate 100.

[0027] The first epitaxial layer 200 includes a first region 201 and a second region 202. The orthographic projection of the second region 202 on the substrate 100 surrounds the orthographic projection of the first region 201 on the substrate 100. The first region 201 is a first doped region 210 of a first conductivity type.

[0028] In a direction parallel to the substrate 100, the second epitaxial layer 300 includes a third region 301 and a fourth region 302. The third region 301 includes a plurality of conductive pillars 310 of a second conductivity type arranged at intervals. The conductive pillars 310 extend in a direction perpendicular to the substrate 100. The fourth region 302 is a second doped region 320 of a first conductivity type. Part of the fourth region 302 is located between two adjacent conductive pillars 310. In addition, at least part of the fourth region 302 is located between the conductive pillars 310 and the first epitaxial layer 200.

[0029] The second doped region 320 is connected to the first doped region 210.

[0030] It should be noted that the first doped region 210 of the first region 201, the second doped region 320 and the conductive pillar 310 located above the first region 201 together constitute a single cell region, and the second doped region 320 and the conductive pillar 310 above the second region 202 constitute a termination region. The semiconductor device 10 in this embodiment is a superjunction MOSFET with high termination efficiency, small termination area and unaffected on-resistance.

[0031] In this embodiment, the semiconductor device 10 introduces a high-resistivity first epitaxial layer 200 spanning the unit cell region and the terminal region on the side of the superjunction drift region near the substrate 100. At the same time, only the first region 201 corresponding to the unit cell region in the first epitaxial layer 200 is implanted with ions of the first conductivity type, while the second region 202 is not implanted with ions of the first conductivity type, so that the first region 201 forms a first doped region 210 connected to the second doped region 320.

[0032] Thus, when the semiconductor device 10 is subjected to a high reverse bias, due to the presence of the first epitaxial layer 200, the depletion region can extend to the first epitaxial layer 200, which alleviates the electric field concentration effect at the junction of the substrate 100, makes the electric field distribution in the termination region more uniform, and improves the termination efficiency of the device. At the same time, since the termination withstand voltage is improved, a more compact termination design can be adopted under the premise of meeting the same withstand voltage level, which is conducive to the miniaturization and cost reduction of the semiconductor device 10.

[0033] In one possible implementation, the first conductivity type is N-type and the second conductivity type is P-type.

[0034] Specifically, the substrate 100 in the semiconductor device 10 is an N-type silicon substrate 100, the first epitaxial layer 200 is an N-type high-resistivity epitaxial layer grown on the surface of the N-type silicon substrate 100, the first region 201 is an N-type first doped region 210, and the second region 202 retains a high-resistivity state. In the second epitaxial layer 300, alternating N-type second doped regions 320 and P-type conductive pillars 310 are formed through multiple epitaxial and ion implantation processes to achieve charge balance in the superjunction drift region.

[0035] In this way, the semiconductor device 10 can achieve full depletion through lateral charge compensation when reverse biased, while providing a low-resistance current path when forward biased, thereby simultaneously achieving the performance advantages of high withstand voltage and low on-resistance.

[0036] In one possible implementation, the resistivity of the first epitaxial layer 200 is 10 to 1000 Ω•cm. If the resistivity is too low, there is insufficient space for the depletion region to extend into the first epitaxial layer 200, which cannot alleviate the electric field concentration effect at the interface of the substrate 100; if the resistivity is too high, it will increase the process cost and may affect the crystal quality of the epitaxial layer.

[0037] In this way, sufficient vertical depletion space is provided while ensuring process feasibility, thereby improving the terminal's pressure resistance.

[0038] In one possible implementation, the thickness of the first epitaxial layer 200 is 2–20 μm. If the thickness is too thin, the space for the depletion region to extend longitudinally into the first epitaxial layer 200 is insufficient, making it difficult to adequately alleviate the electric field concentration effect at the interface of the substrate 100; if the thickness is too thick, it may increase the device size and may affect the diffusion distribution of doped ions during the subsequent high-temperature bonding process.

[0039] Thus, by limiting the thickness within the aforementioned range, the effective buffering of electric field concentration effects is ensured while also taking into account the miniaturization and process compatibility of the semiconductor device 10.

[0040] In one possible implementation, please refer to Figure 2 The semiconductor device 10 also includes a field plate structure 400, the orthographic projection of the field plate structure 400 on the substrate 100 being located within the orthographic projection of the second region 202 of the first epitaxial layer 200 on the substrate 100. The field plate structure 400 includes a dielectric layer 410 located on the side of the second epitaxial layer 300 away from the substrate 100 and a conductive layer 420 located on the side of the dielectric layer 410 away from the substrate 100.

[0041] Specifically, after the second doped region 320 and conductive pillar 310 are prepared, a silicon dioxide dielectric layer 410 can be formed on the side of the second epitaxial layer 300 above the second region 202 away from the substrate 100 by chemical vapor deposition. Then, the field plate region is defined by photolithography and etching processes. A polysilicon or metal conductive layer 420 is formed on the silicon dioxide dielectric layer 410 as a field plate. The conductive layer 420 is isolated from the surface of the second epitaxial layer 300 above the second region 202 through the dielectric layer 410. That is, the conductive layer 420 is isolated from the terminal region of the semiconductor device 10 through the dielectric layer 410.

[0042] Thus, the field plate structure 400, by regulating the surface electric field of the terminal region, works in conjunction with the homogenization effect of the bottom electric field of the first epitaxial layer 200 to further improve the overall electric field distribution of the terminal region. This makes the longitudinal electric field distribution of the second region 202 more uniform from the surface to the bottom, thereby improving the terminal withstand voltage capability of the semiconductor device 10. Based on this, the area required for the terminal region is further reduced while meeting the same withstand voltage level.

[0043] To verify the technical effect of the semiconductor device 10 in this application, the applicant also conducted electrical performance tests and TCAD simulations on the semiconductor device 10 in this embodiment and semiconductor devices in related technologies through experiments. The test items included measured breakdown voltage, termination efficiency, termination region width, on-resistance, and peak electric field strength. The theoretical breakdown voltage was taken as 650V. The test results are shown in the table below:

[0044] In Comparative Example 1, the semiconductor device uses an N-type silicon substrate as the semiconductor material wafer. No high-resistivity first epitaxial layer is grown; the first layer photolithography is performed directly on the N-type silicon substrate. Phosphorus ion implantation is performed on both the unit cell region and the terminal region, without implementing a differentiated implantation strategy. Example 1 is a semiconductor device 10 excluding the field plate structure 400 in this application. An N-type silicon substrate 100 is used as the semiconductor material wafer, and a high-resistivity first epitaxial layer 200 is grown on its surface. A differentiated phosphorus ion implantation strategy is applied to the first region 201 and the second region 202 of the first epitaxial layer 200. Example 2 is a semiconductor device 10 based on the semiconductor device 10 of Example 1, with the addition of a field plate structure 400 including a dielectric layer 410 and a conductive layer 420. Other structures and fabrication methods are the same for Comparative Example 1, Example 1, and Example 2. Based on this, the design withstand voltage of Comparative Example 1, Example 1, and Example 2 is 600V.

[0045] As can be seen from the data in the table above, compared with Comparative Example 1, the terminal efficiency of Example 1 increased from 87.7% to 95.1%, an increase of approximately 7.4 percentage points, while the peak electric field strength decreased from 2.85 MV / cm to 2.31 MV / cm. This demonstrates that the differentiated first-layer ion implantation strategy in this application significantly improves the terminal withstand voltage characteristics.

[0046] Example 2 further introduces a field plate structure 400 based on Example 1, further improving the terminal efficiency to 97.2% and reducing the peak electric field strength to 2.18 MV / cm. That is, the synergistic control of the high-resistivity first epitaxial layer 200 and the field plate structure 400 can achieve further optimization of the electric field distribution in the terminal region.

[0047] The on-resistance Rdson of the semiconductor devices in Comparative Example 1, Example 1 and Example 2 is 42mΩ·cm², which is basically consistent, fully demonstrating that the differentiated injection strategy in this application can significantly improve the terminal withstand voltage characteristics without affecting the on-resistance.

[0048] The terminal region widths of the semiconductor devices in Comparative Example 1, Example 1, and Example 2 are 180μm, 140μm, and 125μm, respectively, which fully demonstrates that under the premise of meeting the same withstand voltage level, the solution in this application can adopt a more compact terminal design, which is beneficial to the miniaturization and cost reduction of semiconductor devices. At the same time, the semiconductor device 10 synergistically controlled by the high-resistivity first epitaxial layer 200 and the field plate structure 400 has a higher degree of miniaturization.

[0049] This application also provides a method for fabricating a semiconductor device 10, used to form the semiconductor device 10 described in any of the preceding claims. Please refer to... Figure 3 This includes the following steps.

[0050] Step S11, please refer to Figure 4 Substrate 100 is provided.

[0051] For example, N-type silicon is used as the substrate 100 to ensure good electrical performance and isolation.

[0052] Step S12, please refer to Figure 4 A first epitaxial layer 200 is formed on one side of the substrate 100. The first epitaxial layer 200 includes a first region 201 and a second region 202. The orthographic projection of the second region 202 on the substrate 100 surrounds the orthographic projection of the first region 201 on the substrate 100.

[0053] Specifically, a high-quality first epitaxial layer 200 can be formed on the surface of the substrate 100 using epitaxial growth techniques such as chemical vapor deposition and molecular beam epitaxy.

[0054] For example, the first epitaxial layer 200 is an N-type epitaxial layer grown on the surface of the N-type silicon substrate 100.

[0055] It should be noted that, in order to provide sufficient longitudinal depletion space in subsequent processes to alleviate the electric field concentration effect at the junction of substrate 100, the first epitaxial layer 200 formed in this step is a high-resistivity epitaxial layer with a resistivity of 10 to 1000 Ω•cm and a thickness of 2 to 20 μm.

[0056] Step S13, please refer to Figure 4 Ion implantation of a first conductivity type is performed in the first region 201 of the first epitaxial layer 200.

[0057] In this embodiment, in order to enable the bottom of the subsequently formed unit cell region corresponding to the first region 201 to form a low-resistance current channel to ensure that the semiconductor device 10 has a low on-resistance, and at the same time, to prevent the introduction of additional doping at the bottom of the subsequently formed terminal region corresponding to the second region 202 to maintain its high-resistance buffer characteristics, thereby avoiding the destruction of the sufficient depletion condition of the terminal region under high voltage and improving the reliability of the semiconductor device 10, ion implantation of the first conductivity type is performed only in the first region 201 of the first epitaxial layer 200, and ion implantation is not performed in its second region 202.

[0058] Step S14, please refer to Figure 4 A second epitaxial layer 300 is formed on the side of the first epitaxial layer 200 away from the substrate 100, and first conductivity type ion implantation and second conductivity type ion implantation are performed in the second epitaxial layer 300.

[0059] Step S15, please refer to Figure 4 The high-temperature push-junction process is performed to allow the first type of conductive ions implanted in the first region 201 to diffuse with the first type of conductive ions in the second epitaxial layer 300, forming a first doped region 210 and a second doped region 320 of the first type of conductive ions that are interconnected; and to allow the second type of conductive ions to diffuse with each other, forming a plurality of conductive pillars 310 of the second type of conductive ions arranged at intervals; wherein the conductive pillars 310 extend in a direction perpendicular to the substrate 100.

[0060] During the high-temperature bonding process, the first conductivity type ions implanted in the second epitaxial layer 300 and the first conductivity type ions implanted in the first region 201 of the first epitaxial layer 200 diffuse to form interconnected second doped regions 320 and first doped regions 210. Simultaneously, the second conductivity type ions implanted in the second epitaxial layer 300 are aligned and stacked vertically and diffuse to form multiple spaced-apart conductive pillars 310 of the second conductivity type, which extend in a direction perpendicular to the substrate 100.

[0061] Specifically, the above structure can be placed in a diffusion furnace for high-temperature bonding treatment to achieve the diffusion of ions of the first and second conductivity types.

[0062] That is, the first doped region 210 of the first region 201, the second doped region 320 and the conductive pillar 310 located above the first region 201 together constitute a unit cell region, and the second doped region 320 and the conductive pillar 310 above the second region 202 constitute a termination region. Thus, by setting a high-resistance first epitaxial layer 200 and applying a differentiated implantation strategy to the first region 201 and the second region 202 of the first epitaxial layer 200, the depletion region of the semiconductor device 10 can extend into the first epitaxial layer 200 when subjected to a high reverse bias, thereby alleviating the electric field concentration effect at the interface of the substrate 100, making the electric field distribution in the termination region more uniform, and improving the termination efficiency of the device. Simultaneously, since the termination withstand voltage is improved, a more compact termination design can be adopted while meeting the same withstand voltage level, which is beneficial for the miniaturization and cost reduction of the semiconductor device 10. Furthermore, since no additional doping is introduced into the second region 202 of the first epitaxial layer 200, synergistic optimization of withstand voltage performance and conduction performance is achieved, and the on-resistance remains unaffected. In this embodiment, the semiconductor device 10 is a superjunction MOSFET with high termination efficiency, small termination area, and unaffected on-resistance.

[0063] In one possible implementation, please refer to Figure 5 Step S13 includes the following sub-steps.

[0064] First, a first photoresist layer 910 is formed on the side of the first epitaxial layer 200 away from the substrate 100.

[0065] Specifically, first, ensure that the surface of the first epitaxial layer 200 is clean and free of impurities, and then use a spin coater to uniformly coat the photoresist on the side of the first epitaxial layer 200 away from the substrate 100.

[0066] Next, the first photoresist layer 910 is etched to form a first window 911, which exposes a first region 201, through which ion implantation of a first conductivity type is performed.

[0067] For example, a dose of 1× can be injected into the first region 201. ~1× Phosphate ions.

[0068] Specifically, a mask with a preset first window 911 pattern is placed above the photoresist layer, and then the photoresist is exposed and developed using ultraviolet light or light of a specific wavelength. Next, using the first window 911 pattern formed on the photoresist layer as a masking layer, an ion implanter is used to implant ions of a first conductivity type into the first region 201 exposed by the first window 911.

[0069] Finally, the first photoresist layer 910 is removed.

[0070] For example, residual photoresist can be removed by stirring and ultrasonic cleaning.

[0071] Thus, the first region 201 of the first epitaxial layer 200 obtains the required first doped region 210 to ensure the low on-resistance of the unit cell region, while the terminal region corresponding to the second region 202 does not introduce additional doping to avoid disrupting the full depletion condition of the terminal region under high voltage.

[0072] In one possible implementation, please refer to Figure 6 Step S14 includes the following sub-steps.

[0073] A second epitaxial sublayer 390 is formed on the side of the first epitaxial layer 200 away from the substrate 100; ion implantation of the second epitaxial sublayer 390 is performed on the side of the second epitaxial sublayer 390 away from the substrate 100; a second photoresist layer 920 is formed on the side of the second epitaxial sublayer 390 away from the substrate 100; a portion of the second photoresist layer 920 is etched to form a second window 921, the second window 921 exposing a third region 301 of the second epitaxial sublayer 390, and ion implantation of the second conductivity type is performed through the second window 921; the second photoresist layer 920 is removed.

[0074] For example, an N-type second epitaxial sublayer 390 can be grown on the side of the first epitaxial layer 200 away from the substrate 100 and phosphorus ion implantation can be performed; then photoresist can be coated on the N-type second epitaxial sublayer 390 and photolithography can be performed, and a second window 921 can be defined by a mask. The second window 921 exposes the third region 301 corresponding to the P-type conductive pillar 310, and then boron ion implantation can be performed; after removing the photoresist, the next cycle can be started.

[0075] Repeat the above steps to form a second epitaxial layer 300 composed of multiple second epitaxial sublayers 390 stacked together.

[0076] For example, the above process sequence is repeated 5 times. After 5 cycles, the boron ion implantation sites in each of the second epitaxial sublayers 390 are aligned and stacked in the vertical direction, and finally, after high-temperature push-junction, a superjunction drift region consisting of an N-type second doped region 320 and a P-type conductive pillar 310 is formed. In a cross-section parallel to the substrate 100, the N-type pillars and P-type conductive pillars 310 in the second doped region 320 are arranged alternately.

[0077] Optionally, the above steps can be repeated 4 to 12 times.

[0078] Optionally, the thickness of the second epitaxial sublayer 390 is the same in each repeated process.

[0079] Thus, the regions including the second doped region 320 and the conductive pillar 310 are simultaneously distributed in the unit cell region and the terminal region of the semiconductor device 10, and are stacked layer by layer in the vertical direction to form a superjunction drift structure with a sufficient aspect ratio.

[0080] In one possible implementation, the first conductivity type ion is a phosphorus ion, and the second conductivity type ion is a boron ion.

[0081] In this embodiment, phosphorus ions are used to form the first doped region 210 and the second doped region 320 of the N type, and boron ions are used to form the P-type conductive pillar 310.

[0082] This application also provides an electronic device including the semiconductor device 10 described in any one of the foregoing claims, or a semiconductor device 10 manufactured using the manufacturing method of the semiconductor device 10 described in any one of the foregoing claims. Since the aforementioned semiconductor device 10 or the semiconductor device 10 manufactured using the manufacturing method of the semiconductor device 10 described in any one of the foregoing claims has good terminal efficiency and high reliability, the electronic device including this semiconductor device 10 is competitive in the market.

[0083] In summary, this application provides a semiconductor device and its fabrication method, as well as an electronic device. The semiconductor device introduces a high-resistivity first epitaxial layer spanning the unit cell region and the termination region on the side of the superjunction drift region near the substrate. Simultaneously, only the first region corresponding to the unit cell region in the first epitaxial layer undergoes ion implantation of a first conductivity type, while the second region does not undergo ion implantation of the first conductivity type, thus forming a first doped region connected to the second doped region. Therefore, when the semiconductor device is subjected to a high reverse bias, due to the presence of the first epitaxial layer, the depletion region can extend into the first epitaxial layer, alleviating the electric field concentration effect at the substrate interface, making the electric field distribution in the termination region more uniform, and improving the termination efficiency of the device. At the same time, because the termination breakdown voltage is improved, a more compact termination design can be adopted while meeting the same breakdown voltage level, which is beneficial for the miniaturization and cost reduction of the semiconductor device.

[0084] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0085] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A first epitaxial layer located on one side of the substrate, the first epitaxial layer including a first region and a second region, the orthographic projection of the second region on the substrate surrounding the orthographic projection of the first region on the substrate, the first region being a first doped region of a first conductivity type; The second epitaxial layer located on the side of the first epitaxial layer away from the substrate includes a third region and a fourth region in a direction parallel to the substrate. The third region includes a plurality of conductive pillars of a second conductivity type arranged at intervals. The conductive pillars extend in a direction perpendicular to the substrate. The fourth region is a second doped region of a first conductivity type. Part of the fourth region is located between two adjacent conductive pillars, and at least part of the fourth region is located between the conductive pillars and the first epitaxial layer. The second doped region is connected to the first doped region.

2. The semiconductor device according to claim 1, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type.

3. The semiconductor device according to claim 1, characterized in that, The resistivity of the first epitaxial layer is 10 to 1000 Ω•cm.

4. The semiconductor device according to claim 1, characterized in that, The thickness of the first epitaxial layer is 2–20 μm.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a field plate structure, wherein the orthographic projection of the field plate structure on the substrate is located within the orthographic projection of the second region of the first epitaxial layer on the substrate; The field plate structure includes a dielectric layer located on the side of the second epitaxial layer away from the substrate and a conductive layer located on the side of the dielectric layer away from the substrate.

6. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A first epitaxial layer is formed on one side of the substrate. The first epitaxial layer includes a first region and a second region. The orthographic projection of the second region on the substrate surrounds the orthographic projection of the first region on the substrate. Ion implantation of a first conductivity type is performed in the first region of the first epitaxial layer; A second epitaxial layer is formed on the side of the first epitaxial layer away from the substrate, and ion implantation of a first conductivity type and ion implantation of a second conductivity type are performed in the second epitaxial layer; A high-temperature push-bonding process is performed to allow the first type of conductivity ions implanted in the first region to diffuse with the first type of conductivity ions in the second epitaxial layer, forming a first doped region of the first conductivity type and a second doped region of the first conductivity type that are interconnected; and to allow the second type of conductivity ions to diffuse with each other, forming a plurality of conductive pillars of the second conductivity type arranged at intervals; wherein the conductive pillars extend in a direction perpendicular to the substrate.

7. The method according to claim 6, characterized in that, The step of performing ion implantation of a first conductivity type in the first region of the first epitaxial layer includes: A first photoresist layer is formed on the side of the first epitaxial layer away from the substrate; The first photoresist layer is etched to form a first window, which exposes the first region, and ion implantation of a first conductivity type is performed through the first window. Remove the first photoresist layer.

8. The method according to claim 6, characterized in that, The step of forming a second epitaxial layer on the side of the first epitaxial layer away from the substrate, and performing first conductivity type ion implantation and second conductivity type ion implantation in the second epitaxial layer includes: A second epitaxial sublayer is formed on the side of the first epitaxial layer away from the substrate; The second epitaxial sublayer is implanted with ions of the first conductivity type; A second photoresist layer is formed on the side of the second epitaxial sublayer away from the substrate; The second photoresist layer is etched to form a second window, which exposes a third region of the second epitaxial sublayer. Ion implantation of a second conductivity type is performed through the second window. Remove the second photoresist layer; Repeat the above steps to form a second epitaxial layer composed of multiple stacked second epitaxial sublayers.

9. The method according to claim 6, characterized in that, The first type of conductive ion is phosphorus ion, and the second type of conductive ion is boron ion.

10. An electronic device, characterized in that, The semiconductor device includes the semiconductor device according to any one of claims 1-5, or the semiconductor device manufactured by the method of manufacturing the semiconductor device according to any one of claims 6-9.

Images