Semiconductor device

Abstract

This invention provides a semiconductor device with high ESD resistance. The semiconductor device of this embodiment includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type disposed on the first semiconductor layer; a third semiconductor layer of a second conductivity type disposed on the first semiconductor layer and separated from the second semiconductor layer; a fourth semiconductor layer of a first conductivity type connected to the first and third semiconductor layers, having an impurity concentration higher than that of the first semiconductor layer; a first insulating film disposed on the first semiconductor layer; a second insulating film disposed on the fourth semiconductor layer and thicker than the first insulating film; an electrode disposed on the first insulating film; a first contact connected to the electrode; a second contact connected to the second semiconductor layer; a third contact connected to the third semiconductor layer; and a fourth contact penetrating the second insulating film and connected to the fourth semiconductor layer.

Description

[0001] Related applications:

[0002] This application enjoys priority based on Japanese Patent Application No. 2025-042382 (filed on March 17, 2025). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Technology

[0004] Semiconductor devices require ESD (Electrostatic Discharge) resistance. To improve ESD resistance, a method is used where a back gate region with a high impurity concentration is formed in the bulk region, and contacts are connected to this back gate region. This reduces the damage to the semiconductor device caused by holes generated by ESD being discharged through the back gate region and contacts. However, a wider back gate region and a narrower source region lead to an increase in the on-resistance of the semiconductor device. Summary of the Invention

[0005] The embodiments of the present invention provide a semiconductor device with high ESD resistance.

[0006] The semiconductor device of the embodiment includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type disposed on the first semiconductor layer; a third semiconductor layer of a second conductivity type disposed on the first semiconductor layer and separated from the second semiconductor layer; a fourth semiconductor layer of a first conductivity type connected to the first semiconductor layer and the third semiconductor layer, having an impurity concentration higher than that of the first semiconductor layer; a first insulating film disposed on the first semiconductor layer; a second insulating film disposed on the fourth semiconductor layer and thicker than the first insulating film; an electrode disposed on the first insulating film; a first contact connected to the electrode; a second contact connected to the second semiconductor layer; a third contact connected to the third semiconductor layer; and a fourth contact penetrating the second insulating film and connected to the fourth semiconductor layer. Attached Figure Description

[0007] Figure 1 This is a top view showing the semiconductor device according to the first embodiment.

[0008] Figure 2 yes Figure 1 The cross-sectional view of line A-A' shown.

[0009] Figure 3 This is a diagram illustrating the operation of the semiconductor device according to the first embodiment.

[0010] Figure 4 This is a cross-sectional view showing the semiconductor device according to the second embodiment.

[0011] Figure 5 This is a cross-sectional view showing the semiconductor device according to the third embodiment.

[0012] Figure 6 (a) to (c) are process cross-sectional views showing the manufacturing method of the semiconductor device according to the third embodiment.

[0013] Figure 7 (a) to (c) are process cross-sectional views showing the manufacturing method of the semiconductor device according to the third embodiment.

[0014] Figure 8 This is a process cross-sectional view showing the manufacturing method of the semiconductor device according to the third embodiment.

[0015] Figure 9 This is a cross-sectional view showing the semiconductor device according to the fourth embodiment.

[0016] Figure 10 (a) to (c) are process cross-sectional views showing the manufacturing method of the semiconductor device according to the fourth embodiment.

[0017] Figure 11 (a) to (c) are process cross-sectional views showing the manufacturing method of the semiconductor device according to the fourth embodiment.

[0018] Figure 12 This is a cross-sectional view showing the semiconductor device according to the fifth embodiment.

[0019] Figure 13 This is a top view showing the area near the lower end of the common contact of the semiconductor device according to the fifth embodiment.

[0020] Figure 14 yes Figure 13 The cross-sectional view of line B-B' shown.

[0021] Figure 15 This is a cross-sectional view showing the semiconductor device according to the sixth embodiment.

[0022] Figure 16 This is a cross-sectional view showing the semiconductor device according to the seventh embodiment.

[0023] Figure 17 This is a cross-sectional view showing the semiconductor device according to the eighth embodiment.

[0024] Figure 18 This is a cross-sectional view showing the semiconductor device according to the ninth embodiment.

[0025] Explanation of reference numerals in the attached figures:

[0026] 1, 2, 3, 4, 5, 6, 7, 8, 9 Semiconductor devices

[0027] 10 Semiconductor Section

[0028] 10a upper surface

[0029] 11 Basal layer

[0030] 12 layers

[0031] 13 Drift Layers

[0032] 14 Drain Layer

[0033] 15 source layers

[0034] 16LDD layers

[0035] 17. Back gate layer (fourth semiconductor layer)

[0036] 21 Drain silicide layer

[0037] 22 source silicide layers

[0038] 23 Gate electrode (electrode)

[0039] 24 gate silicide layer

[0040] 25 back gate silicide layers

[0041] 31 Gate insulating film (first insulating film)

[0042] 32LOCOS film (second insulating film)

[0043] 32a end

[0044] 32b upper slope

[0045] 32c lower slope

[0046] 32d lower surface

[0047] 32h through hole

[0048] 33STI

[0049] 34 sidewalls

[0050] 35-layer interlayer insulation film

[0051] 36STI (Third Insulation Film)

[0052] 36a end

[0053] 37LOCOS film (third insulating film)

[0054] 38 sidewalls

[0055] 39-step oxide film (third insulating film)

[0056] 41 Gate contact (first contact)

[0057] 41h contact hole

[0058] 42 Drain contact (second contact)

[0059] 42h contact hole

[0060] 43 Source contact (third contact)

[0061] 43h contact hole

[0062] 44 Back gate contact (fourth contact)

[0063] 44h contact hole

[0064] 45. Shared contact (third contact)

[0065] 51 gate wiring

[0066] 52 drain wiring

[0067] 53 Source Wiring

[0068] 54 Back Grid Wiring

[0069] 55 shared cabling

[0070] Paths 201, 202, and 203 Detailed Implementation

[0071] <First Implementation Method>

[0072] Figure 1 This is a top view showing the semiconductor device of this embodiment.

[0073] Figure 2 yes Figure 1 The cross-sectional view of line A-A' shown.

[0074] exist Figure 1 The diagrams of wiring, interlayer insulating film, and silicide layer, which will be described later, are omitted here.

[0075] Furthermore, the figures are schematic and conceptual, and have been appropriately emphasized and simplified. Also, even for the same constituent elements, the size ratios and positional relationships may not be strictly consistent between figures. The same applies to the other figures described later.

[0076] like Figure 1 and Figure 2As shown, the semiconductor device 1 in this embodiment is a DMOS (Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor).

[0077] The semiconductor device 1 includes a semiconductor portion 10, a drain silicide layer 21, a source silicide layer 22, a gate electrode 23, a gate silicide layer 24, a gate insulating film 31 (first insulating film), a LOCOS (Local Oxidation of Silicon) film 32 (second insulating film), an STI (Shallow Trench Isolation) film 33, a sidewall 34, an interlayer insulating film 35, a gate contact 41 (first contact), a drain contact 42 (second contact), a source contact 43 (third contact), a back gate contact 44 (fourth contact), a gate wiring 51, a drain wiring 52, a source wiring 53, and a back gate wiring 54. Furthermore, in this specification, the direction from the semiconductor portion 10 toward the interlayer insulating film 35 is referred to as "up," and the opposite direction is referred to as "down," but this designation is for convenience and is unrelated to the direction of gravity.

[0078] Semiconductor portion 10 is made of semiconductor material, such as single-crystal silicon (Si). Impurities are locally contained in semiconductor portion 10, and the conductivity type of each portion is either p-type (first conductivity type) or n-type (second conductivity type). Semiconductor portion 10 includes a substrate layer 11, a bulk layer 12, a drift layer 13, a drain layer 14, a source layer 15, an LDD (Lightly Doped Drain) layer 16, and a back gate layer 17 (fourth semiconductor layer).

[0079] The substrate layer 11 has a p-type conductivity. A body layer 12 is disposed on a portion of the substrate layer 11. The body layer 12 also has a p-type conductivity. The substrate layer 11 and the body layer 12 constitute the first semiconductor layer. Furthermore, "p-type" refers to an effective impurity concentration lower than "p-type," and "p+type" refers to an effective impurity concentration higher than "p-type." "Effective impurity concentration" refers to the concentration of impurities that contribute to the conduction of the semiconductor material; in the case where a region contains both acceptor and donor impurities, it refers to the concentration after removing their offsetting amounts. The same applies to n-type.

[0080] Another portion of the drift layer 13 on the substrate layer 11 is grounded to the body layer 12. The drift layer 13 has an n-type conductivity. A drain layer 14 is disposed on the drift layer 13. The drain layer 14 has an n+ type conductivity. The drift layer 13 and the drain layer 14 constitute a second semiconductor layer.

[0081] The source layer 15 is disposed separately from the drift layer 13 and the substrate layer 11 on the body layer 12. The conductivity type of the source layer 15 is n+. The LDD layer 16 is disposed on the drain layer 14 side of the source layer 15 and is connected to the source layer 15. The conductivity type of the LDD layer 16 is n-type. The source layer 15 and the LDD layer 16 constitute a third semiconductor layer.

[0082] The back gate layer 17 is disposed on the body layer 12 and below the source layer 15. The lower surface of the back gate layer 17 is in contact with the body layer 12, and a portion of the upper surface of the back gate layer 17 is in contact with a portion of the lower surface of the source layer 15. The back gate layer 17 has a p+ type conductivity. That is, the impurity concentration of the back gate layer 17 is higher than that of the body layer 12.

[0083] The gate insulating film 31 is continuously disposed on the portion between the LDD layer 16 and the drift layer 13 in the body layer 12 and on the portion between the body layer 12 and the STI 33 in the drift layer 13. The gate insulating film 31 is formed, for example, from silicon oxide.

[0084] A LOCOS film 32 is disposed on the back gate layer 17. The LOCOS film 32 is thicker than the gate insulating film 31. The LOCOS film 32 is made of silicon oxide and is formed by locally thermally oxidizing the upper surface of the semiconductor portion 10. The LOCOS film 32 extends both above and below the upper surface 10a of the semiconductor portion 10. The upper surface of the LOCOS film 32 is located above the upper surface of the gate insulating film 31, and the lower surface of the LOCOS film 32 is located below the lower surface of the gate insulating film 31.

[0085] Furthermore, the end 32a of the LOCOS film 32 is beak-shaped, with an upper slope 32b and a lower slope 32c. The lower surface 32d of the LOCOS film 32 is in contact with the back gate layer 17, the lower slope 32c is in contact with both the back gate layer 17 and the source layer 15, and the upper slope 32b is in contact with the interlayer insulating film 35, which will be described later. Alternatively, a silicon nitride film (not shown) may be disposed on the upper surface of the LOCOS film 32.

[0086] STI33 is disposed on the drift layer 13 between the drain contact 42 and the source contact 43 when viewed from above. STI33 is thicker than the gate insulating film 31. The portion of STI33 located below the upper surface 10a of the semiconductor portion 10 is thicker than the portion located above the upper surface 10a. The upper surface 10a of the semiconductor portion 10 is, for example, the upper surface of the drift layer 13. STI33 is in contact with both the drift layer 13 and the drain layer 14. STI33 is made of silicon oxide.

[0087] A drain silicide layer 21 is disposed on and connected to the drain layer 14. In this specification, "connection" refers to electrical connection. A source silicide layer 22 is disposed on and connected to the source layer 15. The upper surface of the source silicide layer 22 is approximately the same height as the lower surface of the gate insulating film 31.

[0088] Gate electrode 23 is disposed on gate insulating film 31 and a portion of STI 33. Gate silicide layer 24 is disposed on gate electrode 23 and connected to gate electrode 23. Sidewall 34 is disposed on the side of gate electrode 23, on semiconductor portion 10, and on STI 33. Sidewall 34 is made of insulating material, such as silicon oxide and silicon nitride.

[0089] An interlayer insulating film 35, for example made of silicon oxide, is disposed above the semiconductor portion 10, the LOCOS film 32, the gate electrode 23, etc. A gate contact 41 extends vertically within the interlayer insulating film 35, with its lower end connected to the gate silicide layer 24. A drain contact 42 extends vertically within the interlayer insulating film 35, with its lower end connected to the drain silicide layer 21. A source contact 43 extends vertically within the interlayer insulating film 35, with its lower end connected to the source silicide layer 22. A back gate contact 44 extends vertically within the interlayer insulating film 35, penetrating the LOCOS film 32, with its lower end connected to the back gate layer 17. The back gate contact 44 is in contact with the interlayer insulating film 35, the LOCOS film 32, and the back gate layer 17.

[0090] In addition, Figure 1 and Figure 2 For simplicity, the diagram depicts the gate contact 41, drain contact 42, source contact 43, and back gate contact 44 arranged in a row, but the actual product is not limited to this. For example, the gate contact 41 may also be configured in... Figure 1 outside the scope and Figure 2 The inside or near the front of the paper.

[0091] Gate wiring 51 is disposed within interlayer insulating film 35 and connected to the upper end of gate contact 41. Drain wiring 52 is disposed within interlayer insulating film 35 and connected to the upper end of drain contact 42. Source wiring 53 is disposed within interlayer insulating film 35 and connected to the upper end of source contact 43. Back gate wiring 54 is disposed within interlayer insulating film 35 and connected to the upper end of back gate contact 44.

[0092] Next, the operation and effects of the semiconductor device 1 in this embodiment will be explained.

[0093] Figure 3 This is a diagram illustrating the operation of the semiconductor device according to this embodiment.

[0094] like Figure 3 As shown, when a reference potential, such as a ground potential, is applied to the back gate wiring 54 and the source wiring 53, and a positive potential is applied to the drain wiring 52, if a potential lower than a threshold is applied to the gate wiring 51, a depletion layer is generated starting from the interface between the n-type drift layer 13 and the p-type substrate layer 11 and the p-type body layer 12, and the semiconductor device 1 becomes off. On the other hand, when a potential higher than the threshold is applied to the gate wiring 51, an inversion layer is formed in the portion of the body layer 12 that is in contact with the gate insulating film 31, and current flows along the path 201. As a result, the semiconductor device 1 becomes on.

[0095] When ESD is applied from the outside of the semiconductor device 1 via drain wiring 52 or source wiring 53, impact ionization sometimes occurs near the interface between drift layer 13 and body layer 12 or near the corner of STI 33. Holes generated by impact ionization flow along path 202, through the p-type body layer 12 into the p+ type back gate layer 17, and are discharged to the outside of the semiconductor device 1 via back gate contact 44 and back gate wiring 54. Electrons generated by impact ionization flow along path 203 and are discharged to the outside of the semiconductor device 1 via drift layer 13, drain layer 14, drain silicide layer 21, drain contact 42, and drain wiring 52.

[0096] Thus, in semiconductor device 1, the back gate layer 17 is disposed below the LOCOS film 32 and connected to the back gate wiring 54 via a back gate contact 44 penetrating the LOCOS film 32. This allows for the recovery of holes generated by impact ionization at a deeper location in the semiconductor portion 10, suppressing inflow into the source layer 15. As a result, ESD resistance is improved.

[0097] In contrast, assuming the back gate layer 17 is disposed on the upper part of the semiconductor portion 10, holes generated by impact ionization are recovered at a shallower position in the semiconductor portion 10, resulting in a greater amount of holes flowing into the source layer 15. Consequently, the parasitic npn transistor composed of the n-type drift layer 13, the p-type base layer 11, the p-type body layer 12, and the n+ type source layer 15 is turned on, and the current concentrates flowing through the turned portion, potentially damaging the semiconductor device.

[0098] Furthermore, in semiconductor device 1, the back gate layer 17 is disposed below the source layer 15. Therefore, by providing the back gate layer 17, the area of ​​the source layer 15 is not reduced. As a result, the on-resistance of semiconductor device 1 does not increase.

[0099] Conversely, assuming the back gate layer 17 is disposed on the upper portion of the semiconductor portion 10, and the area of ​​the back gate layer 17 is increased to improve ESD resistance, the area of ​​the source layer 15 is reduced by a corresponding amount. As a result, the on-resistance of the semiconductor device increases. Thus, if the back gate layer 17 is disposed on the upper portion of the semiconductor portion 10, the improvement in ESD resistance and the reduction in on-resistance are mutually constrained and difficult to achieve simultaneously.

[0100] Furthermore, in semiconductor device 1, the back gate contact 44 penetrates the LOCOS film 32. Therefore, even if source wiring 53 and back gate wiring 54 are required separately for circuit design reasons, the distance between the back gate contact 44 and the source contact 43 can be shortened. As a result, miniaturization of semiconductor device 1 can be achieved.

[0101] In contrast, if the back gate contact 44 and the source contact 43 are arranged with the LOCOS film 32 in between, the distance between the back gate contact 44 and the source contact 43 becomes greater than the minimum dimension of the LOCOS film 32. Due to manufacturing limitations, there are limits to the miniaturization of the LOCOS film, thus hindering the miniaturization of semiconductor devices in this case.

[0102] <Second Implementation Method>

[0103] Figure 4 This is a cross-sectional view showing the semiconductor device of this embodiment.

[0104] like Figure 4 As shown, the semiconductor device 2 of this embodiment differs from the semiconductor device 1 of the first embodiment in that an STI 36 is provided instead of a LOCOS film 32. In the STI 36, the thickness of the portion of the semiconductor portion 10 located below the upper surface 10a is greater than the thickness of the portion located above the upper surface 10a. The upper surface 10a of the semiconductor portion 10 is, for example, the upper surface of the source layer 15.

[0105] Therefore, cavities can be recovered at deeper locations. The structures, operations, and effects in this embodiment other than those described above are the same as in the first embodiment.

[0106] <Third Implementation Method>

[0107] Figure 5 This is a cross-sectional view showing the semiconductor device of this embodiment.

[0108] like Figure 5As shown, the semiconductor device 3 of this embodiment differs from the semiconductor device 1 of the first embodiment in that a LOCOS film 37 is provided instead of an STI 33. In the semiconductor device 3, a portion of the drain layer 14 side of the gate electrode 23 rests on the LOCOS film 37. Additionally, a silicon nitride film (not shown) is provided on the upper surface of the LOCOS film 32. Furthermore, a silicon nitride film may also be provided in other embodiments.

[0109] Next, the manufacturing method of the semiconductor device 3 of this embodiment will be described.

[0110] Figure 6 (a)~(c) Figure 7 (a) to (c) and Figure 8 This is a process cross-sectional view showing the manufacturing method of the semiconductor device according to this embodiment.

[0111] First, prepare Figure 6 The construct shown in (a).

[0112] Next, as Figure 6 As shown in (b), using LOCOS film 32, LOCOS film 37, and gate electrode 23 as a mask, impurities are implanted as donors. Therefore, an n-type LDD layer 16 is formed on the upper portion of the bulk layer 12 and the upper portion of the drift layer 13. Additionally, a sidewall 34 is formed on the side of the gate electrode 23.

[0113] Next, as Figure 6 As shown in (c), using the LOCOS film 32, LOCOS film 37, gate electrode 23, and sidewall 34 as a mask, impurities are implanted as donors. As a result, an n+ type source layer 15 is formed in the upper portion of the bulk layer 12, and an n+ type drain layer 14 is formed in the upper portion of the drift layer 13.

[0114] Next, as Figure 7 As shown in (a), impurities are locally implanted as acceptors. This ion implantation is performed under conditions where the impurities are implanted deeper than those during the formation of the source layer 15 and drain layer 14. For example, the accelerating voltage is increased. As a result, the impurities penetrate the LOCOS film 32 and reach the bulk layer 12, forming a p+ type back gate layer 17 below the LOCOS film 32 and the source layer 15.

[0115] Next, as Figure 7 As shown in (b), the exposed silicon portion is subjected to silicide treatment. As a result, a drain silicide layer 21 is formed on the upper portion of the drain layer 14, a source silicide layer 22 is formed on the upper portion of the source layer 15, and a gate silicide layer 24 is formed on the upper portion of the gate electrode 23.

[0116] Next, as Figure 7As shown in (c), a first layer of interlayer insulating film 35 is formed. Next, the first layer of interlayer insulating film 35 is selectively removed, for example, by photolithography and RIE (Reactive Ion Etching). This forms contact holes 41h, 42h, 43h, and 44h.

[0117] This RIE method is performed under conditions where the etching rate of silicon oxide is higher than that of silicide and silicon nitride. Thus, contact hole 41h terminates at the gate silicide layer 24, contact hole 42h terminates at the drain silicide layer 21, contact hole 43h terminates at the source silicide layer 22, and contact hole 44h terminates at the silicon nitride film on the LOCOS film 32.

[0118] Next, as Figure 8 As shown, the RIE method is performed again. This RIE method is performed under conditions where the etching rates of silicon oxide and silicon nitride are higher than those of silicon and silicide. As a result, contact hole 44h penetrates the LOCOS film 32 and terminates at the back gate layer 17. At this time, contact holes 41h, 42h, and 43h do not extend substantially.

[0119] Next, as Figure 5 As shown, conductive material is embedded in contact holes 41h, 42h, 43h, and 44h. Thus, a gate contact 41 is formed in contact hole 41h, a drain contact 42 is formed in contact hole 42h, a source contact 43 is formed in contact hole 43h, and a back gate contact 44 is formed in contact hole 44h. The back gate contact 44 is in contact with the interlayer insulating film 35, the LOCOS film 32, and the back gate layer 17.

[0120] Next, a second layer of interlayer insulating film 35 is formed, in which gate wiring 51, drain wiring 52, source wiring 53, and back gate wiring 54 are formed. Thus, the semiconductor device 3 of this embodiment is manufactured. The structure, operation, and effects other than those described above in this embodiment are the same as in the first embodiment.

[0121] <Fourth Implementation Method>

[0122] Figure 9 This is a cross-sectional view showing the semiconductor device of this embodiment.

[0123] like Figure 9 As shown, the semiconductor device 4 of this embodiment differs from the semiconductor device 3 of the third embodiment in that a portion of an interlayer insulating film 35 and a sidewall 38 exist between the LOCOS film 32 and the back gate contact 44, and a back gate silicide layer 25 is formed on a portion of the upper surface of the back gate layer 17.

[0124] In the semiconductor device 4, a through-hole 32h is provided in the LOCOS film 32, and a sidewall 38 is provided on the inner surface of the through-hole 32h. A portion of the interlayer insulating film 35 is disposed inside the through-hole 32h and surrounded by the sidewall 38, and a back gate contact 44 passes through it. Therefore, the back gate contact 44 is separated from the LOCOS film 32.

[0125] Next, the manufacturing method of the semiconductor device 4 in this embodiment will be described.

[0126] Figure 10 (a) to (c) and Figure 11 (a) to (c) are process cross-sectional views showing the manufacturing method of the semiconductor device according to this embodiment.

[0127] First, make Figure 6 The construct shown in (a).

[0128] Next, as Figure 10 As shown in (a), through-holes 32h are formed in the LOCOS film 32, for example, by photolithography and RIE. The bulk layer 12 is exposed from the bottom surface of the through-holes 32h.

[0129] Next, as Figure 10 As shown in (b), using the LOCOS film 32, LOCOS film 37, and gate electrode 23 as masks, impurities are implanted as donors. Therefore, an n-type LDD layer 16 is formed in the upper portion of the bulk layer 12 and the upper portion of the drift layer 13. Next, a sidewall 34 is formed on the side of the gate electrode 23, and a sidewall 38 is formed on the inner surface of the via 32h. At this time, the via 32h is shielded by a mask (not shown).

[0130] Next, as Figure 10 As shown in (c), using the LOCOS film 32, LOCOS film 37, gate electrode 23, and sidewall 34 as a mask, impurities are implanted as donors. This forms an n+ type source layer 15 on the upper portion of the bulk layer 12 and an n+ type drain layer 14 on the upper portion of the drift layer 13. Then, the mask covering the via 32h is removed.

[0131] Next, as Figure 11 As shown in (a), using the LOCOS film 32 and sidewall 38 as a mask, impurities are locally implanted as acceptors. This ion implantation is performed under the same conditions as the ion implantation during the formation of the source layer 15 and drain layer 14. As a result, the impurities reach the bulk layer 12 through the through-hole 32h in the LOCOS film 32, forming a p+ type back gate layer 17 in the region directly below the through-hole 32h in the bulk layer 12.

[0132] Next, as Figure 11As shown in (b), silicide treatment is performed on the exposed portion of silicon. As a result, a drain silicide layer 21 is formed on the upper portion of the drain layer 14, a source silicide layer 22 is formed on the upper portion of the source layer 15, a gate silicide layer 24 is formed on the upper portion of the gate electrode 23, and a back gate silicide layer 25 is formed on the portion of the back gate layer 17 exposed within the via 32h.

[0133] Next, as Figure 11 As shown in (c), a first layer of interlayer insulating film 35 is formed. The interlayer insulating film 35 is also disposed within the through-hole 32h of the LOCOS film 32. Next, contact holes 41h, 42h, 43h, and 44h are formed in the first layer of the interlayer insulating film 35. At this time, the contact hole 44h penetrates the portion of the interlayer insulating film 35 disposed within the through-hole 32h, reaching the back gate silicide layer 25 and terminating thereafter. The following processes are the same as in the third embodiment. Thus, the semiconductor device 4 of this embodiment is manufactured.

[0134] In this embodiment, ion implantation for forming the back gate layer 17 is performed through the through-hole 32h of the LOCOS film 32, thus reducing the acceleration voltage of the ion implantation compared to the third embodiment.

[0135] Therefore, for example, when simultaneously forming an n-channel DMOS and a p-channel DMOS, the p+ type back gate layer 17 of the n-channel DMOS can be formed using the process of forming the p+ type drain layer and source layer in the p-channel DMOS. Furthermore, the n+ type back gate layer of the p-channel DMOS can be formed using the process of forming the n+ type drain layer 14 and source layer 15 in the n-channel DMOS. As a result, the number of ion implantation steps can be reduced, lowering manufacturing costs. The structure, manufacturing method, operation, and effects other than those described above in this embodiment are the same as in the fourth embodiment.

[0136] <Fifth Implementation Method>

[0137] Figure 12 This is a cross-sectional view showing the semiconductor device of this embodiment.

[0138] Figure 13 This is a partial top view showing the area near the lower end of the common contact of the semiconductor device in this embodiment.

[0139] Figure 14 yes Figure 13 The cross-sectional view of line B-B' shown.

[0140] Figure 14 Equivalent to Figure 12 Region C. Additionally, in Figure 13 The diagrams of the interlayer insulating film 35 and the source silicide layer 22 are omitted.

[0141] like Figures 12-14 As shown, the semiconductor device 5 of this embodiment differs from the semiconductor device 1 of the first embodiment in that a common contact 45 is provided instead of the source contact 43 and the back gate contact 44, and a common wiring 55 is provided instead of the source wiring 53 and the back gate wiring 54.

[0142] The common contact 45 is engaged with and embedded in the end 32a of the LOCOS film 32, but is not completely surrounded by the LOCOS film 32 when viewed from above. The lower end of the common contact 45 is engaged with and connected to the source silicide layer 22, the source layer 15, and the back gate layer 17. The upper end of the common contact 45 is connected to the common wiring 55.

[0143] According to this embodiment, even when the source wiring and back gate wiring are shared as a common wiring 55 for circuit design reasons, by placing the back gate layer 17 below the source layer 15 and positioning the lower end of the common contact 45 near the lower surface 32d of the LOCOS film 32, holes can be recovered from a deeper location in the semiconductor portion 10. As a result, ESD resistance is improved. The structure, operation, and effects other than those described above in this embodiment are the same as in the first embodiment.

[0144] <Sixth Implementation Method>

[0145] Figure 15 This is a cross-sectional view showing the semiconductor device of this embodiment.

[0146] like Figure 15 As shown, the semiconductor device 6 of this embodiment differs from the semiconductor device 5 of the fifth embodiment in that an STI 36 is provided instead of a LOCOS film 32. In the STI 36, the thickness of the portion of the semiconductor portion 10 located below the upper surface 10a is greater than the thickness of the portion located above the upper surface 10a.

[0147] The common contact 45 engages with and bites into the end 36a of the STI 36, but is not completely surrounded by the STI 36 when viewed from above. The lower end of the common contact 45 engages with and connects to the source silicide layer 22, the source layer 15, and the back gate layer 17. This allows for the recovery of holes at deeper locations. The structure, operation, and effects in this embodiment other than those described above are the same as in the fifth embodiment.

[0148] <Seventh Implementation Method>

[0149] Figure 16 This is a cross-sectional view showing the semiconductor device of this embodiment.

[0150] like Figure 16 As shown, the semiconductor device 7 of this embodiment differs from the semiconductor device 5 of the fifth embodiment in that a LOCOS film 37 is provided instead of the STI 33. In the semiconductor device 7, a portion of the drain layer 14 side of the gate electrode 23 rests on the LOCOS film 37. The structure, operation, and effects in this embodiment other than those described above are the same as in the fifth embodiment.

[0151] <Eighth Implementation Method>

[0152] Figure 17 This is a cross-sectional view showing the semiconductor device of this embodiment.

[0153] like Figure 17 As shown, the semiconductor device 8 of this embodiment differs from the semiconductor device 5 of the fifth embodiment in that a stepped oxide film 39 is provided instead of STI 33. The portion of the stepped oxide film 39 located above the upper surface 10a of the semiconductor portion 10 is thicker than the portion located below the upper surface 10a. The upper surface 10a of the semiconductor portion 10 is, for example, the upper surface of the drift layer 13. Furthermore, in the semiconductor device 8, the portion of the gate electrode 23 on the drain layer 14 side rests on the stepped oxide film 39. The structure, operation, and effects in this embodiment other than those described above are the same as in the fifth embodiment.

[0154] <Ninth Implementation Method>

[0155] Figure 18 This is a cross-sectional view showing the semiconductor device of this embodiment.

[0156] like Figure 18 As shown, the semiconductor device 9 of this embodiment differs from the semiconductor device 5 of the fifth embodiment in that it does not have an STI 33. This forms a straight current path between the drain layer 14 and the source layer 15, thus reducing the on-resistance. However, as in the first to eighth embodiments, when an insulating component such as an STI 33, a LOCOS film 37, or a stepped oxide film 39 is provided between the drain layer 14 and the source layer 15, and the current path is formed by bypassing this insulating component, the ESD resistance is improved. The structure, operation, and effects other than those described above in this embodiment are the same as in the fifth embodiment.

[0157] In the above embodiments, an n-channel DMOS was used as an example for explanation, but the present invention can also be applied to a p-channel DMOS. That is, the substrate layer 11 can be set to n-type, the body layer 12 to n-type, the drift layer 13 to p-type, the drain layer 14 to p+ type, the source layer 15 to p+ type, the LDD layer 16 to p-type, and the back gate layer 17 to n+ type.

[0158] Based on the embodiments described above, a semiconductor device with high ESD resistance can be realized.

[0159] The foregoing has described several embodiments of the present invention, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention and its equivalents as described in the claims. Furthermore, the above-described embodiments can also be combined with each other.

[0160] The present invention includes the following methods.

[0161] (Postscript 1)

[0162] A semiconductor device comprising:

[0163] First semiconductor layer of first conductivity type;

[0164] A second semiconductor layer of a second conductivity type is disposed on the first semiconductor layer;

[0165] A third semiconductor layer of the second conductivity type is disposed on the first semiconductor layer and is separate from the second semiconductor layer;

[0166] The fourth semiconductor layer of the first conductivity type is connected to the first semiconductor layer and the third semiconductor layer, and the impurity concentration is higher than that of the first semiconductor layer;

[0167] A first insulating film is disposed on the first semiconductor layer;

[0168] The second insulating film is disposed on the fourth semiconductor layer and is thicker than the first insulating film;

[0169] Electrodes are disposed on the first insulating film;

[0170] The first contact element is connected to the electrode;

[0171] The second contact is connected to the second semiconductor layer;

[0172] A third contact element is connected to the third semiconductor layer; and

[0173] The fourth contact penetrates the second insulating film and is connected to the fourth semiconductor layer.

[0174] (Postscript 2)

[0175] According to Appendix 1, the fourth contact is in contact with the second insulating film in the semiconductor device.

[0176] (Note 3)

[0177] According to the semiconductor device described in Appendix 1, the fourth contact is separated from the second insulating film.

[0178] (Note 4)

[0179] A semiconductor device comprising:

[0180] First semiconductor layer of first conductivity type;

[0181] A second semiconductor layer of a second conductivity type is disposed on the first semiconductor layer;

[0182] A third semiconductor layer of the second conductivity type is disposed on the first semiconductor layer and is separate from the second semiconductor layer;

[0183] The fourth semiconductor layer of the first conductivity type is connected to the first semiconductor layer and the third semiconductor layer, and the impurity concentration is higher than that of the first semiconductor layer;

[0184] A first insulating film is disposed on the first semiconductor layer;

[0185] The second insulating film is disposed on the fourth semiconductor layer and is thicker than the first insulating film;

[0186] Electrodes are disposed on the first insulating film;

[0187] The first contact element is connected to the electrode;

[0188] The second contact is connected to the second semiconductor layer; and

[0189] The third contact is in contact with the second insulating film and connected to the third semiconductor layer and the fourth semiconductor layer.

[0190] (Note 5)

[0191] According to any one of Appendices 1 to 4, in the semiconductor device, the fourth semiconductor layer is disposed below the third semiconductor layer.

[0192] (Note 6)

[0193] In any one of Appendices 1 to 5, the upper surface of the second insulating film is located above the upper surface of the first insulating film.

[0194] The lower surface of the second insulating film is located below the lower surface of the first insulating film.

[0195] (Note 7)

[0196] According to any one of Appendices 1 to 5, in the semiconductor device, the thickness of the portion of the second insulating film located below the upper surface of the third semiconductor layer is greater than the thickness of the portion of the second insulating film located above the upper surface of the third semiconductor layer.

[0197] (Postscript 8)

[0198] The semiconductor device according to any one of Appendices 1 to 7 further comprises a third insulating film, which is disposed on the second semiconductor layer between the second contact and the third contact when viewed from above, and is thicker than the first insulating film.

[0199] (Note 9)

[0200] According to the semiconductor device described in Appendix 8, the portion of the third insulating film located below the upper surface of the second semiconductor layer is thicker than the portion of the third insulating film located above the upper surface of the second semiconductor layer.

[0201] (Postscript 10)

[0202] According to the semiconductor device described in Appendix 8, the upper surface of the third insulating film is located above the upper surface of the first insulating film.

[0203] The lower surface of the third insulating film is located below the lower surface of the first insulating film.

[0204] (Postscript 11)

[0205] According to the semiconductor device described in Appendix 8, the portion of the third insulating film located above the upper surface of the second semiconductor layer is thicker than the portion of the third insulating film located below the upper surface of the second semiconductor layer.

Claims

1. A semiconductor device, wherein, have: First semiconductor layer of first conductivity type; A second semiconductor layer of a second conductivity type is disposed on the first semiconductor layer; A third semiconductor layer of the second conductivity type is disposed on the first semiconductor layer and is separate from the second semiconductor layer; The fourth semiconductor layer of the first conductivity type is connected to the first semiconductor layer and the third semiconductor layer, and the impurity concentration is higher than that of the first semiconductor layer; A first insulating film is disposed on the first semiconductor layer; The second insulating film is disposed on the fourth semiconductor layer and is thicker than the first insulating film; Electrodes are disposed on the first insulating film; The first contact element is connected to the electrode; The second contact is connected to the second semiconductor layer; The third contact is connected to the third semiconductor layer; as well as The fourth contact penetrates the second insulating film and is connected to the fourth semiconductor layer.

2. The semiconductor device according to claim 1, wherein, The fourth contact is in contact with the second insulating film.

3. The semiconductor device according to claim 1, wherein, The fourth contact is separated from the second insulating film.

4. The semiconductor device according to claim 1, wherein, The fourth semiconductor layer is disposed below the third semiconductor layer.

5. The semiconductor device according to claim 1, wherein, The upper surface of the second insulating film is located above the upper surface of the first insulating film. The lower surface of the second insulating film is located below the lower surface of the first insulating film.

6. The semiconductor device according to claim 1, wherein, The portion of the second insulating film located below the upper surface of the third semiconductor layer is thicker than the portion of the second insulating film located above the upper surface of the third semiconductor layer.

7. The semiconductor device according to claim 1, wherein, It also includes a third insulating film, which is on the second semiconductor layer, disposed between the second contact and the third contact when viewed from above, and is thicker than the first insulating film.

8. The semiconductor device according to claim 7, wherein, The portion of the third insulating film located below the upper surface of the second semiconductor layer is thicker than the portion of the third insulating film located above the upper surface of the second semiconductor layer.

9. The semiconductor device according to claim 7, wherein, The upper surface of the third insulating film is located above the upper surface of the first insulating film. The lower surface of the third insulating film is located below the lower surface of the first insulating film.

10. The semiconductor device according to claim 7, wherein, The portion of the third insulating film located above the upper surface of the second semiconductor layer is thicker than the portion of the third insulating film located below the upper surface of the second semiconductor layer.

11. A semiconductor device, wherein, have: First semiconductor layer of first conductivity type; A second semiconductor layer of a second conductivity type is disposed on the first semiconductor layer; A third semiconductor layer of the second conductivity type is disposed on the first semiconductor layer and is separate from the second semiconductor layer; The fourth semiconductor layer of the first conductivity type is connected to the first semiconductor layer and the third semiconductor layer, and the impurity concentration is higher than that of the first semiconductor layer; A first insulating film is disposed on the first semiconductor layer; The second insulating film is disposed on the fourth semiconductor layer and is thicker than the first insulating film; Electrodes are disposed on the first insulating film; The first contact element is connected to the electrode; The second contact is connected to the second semiconductor layer; as well as The third contact is in contact with the second insulating film and connected to the third semiconductor layer and the fourth semiconductor layer.

12. The semiconductor device according to claim 11, wherein, The fourth semiconductor layer is disposed below the third semiconductor layer.

13. The semiconductor device according to claim 11, wherein, The upper surface of the second insulating film is located above the upper surface of the first insulating film. The lower surface of the second insulating film is located below the lower surface of the first insulating film.

14. The semiconductor device according to claim 11, wherein, The portion of the second insulating film located below the upper surface of the third semiconductor layer is thicker than the portion of the second insulating film located above the upper surface of the third semiconductor layer.

15. The semiconductor device according to claim 11, wherein, It also includes a third insulating film, which is on the second semiconductor layer, disposed between the second contact and the third contact when viewed from above, and is thicker than the first insulating film.

16. The semiconductor device according to claim 15, wherein, The portion of the third insulating film located below the upper surface of the second semiconductor layer is thicker than the portion of the third insulating film located above the upper surface of the second semiconductor layer.

17. The semiconductor device according to claim 15, wherein, The upper surface of the third insulating film is located above the upper surface of the first insulating film. The lower surface of the third insulating film is located below the lower surface of the first insulating film.

18. The semiconductor device according to claim 15, wherein, The portion of the third insulating film located above the upper surface of the second semiconductor layer is thicker than the portion of the third insulating film located below the upper surface of the second semiconductor layer.

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