Semiconductor device

Abstract

The present application provides a semiconductor device. The semiconductor device includes a substrate, a first high voltage well, a second high voltage well, an isolation portion, and a gate electrode. The substrate has a first conductivity type. The first high voltage well has a second conductivity type different from the first conductivity type and is disposed in the substrate. The second high voltage well has the first conductivity type, is disposed in the substrate, and surrounds the first high voltage well. The isolation portion is disposed in the first high voltage well. The gate electrode is disposed on the isolation portion. Wherein a side surface of the isolation portion contacts a side surface of the gate electrode.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a first isolation portion. Background Technology

[0002] Laterally diffused metal oxide semiconductor (LDMOS) field-effect transistors are frequently used in power devices, such as switching regulators. Because LDMOS has a horizontal structure, its main current flows in the horizontal direction.

[0003] However, the longer carrier movement path in current LDMOS devices results in higher on-state resistance, lower on-state current, and / or lower breakdown voltage, thus reducing the electrical properties and / or reliability of LDMOS. Therefore, although existing semiconductor devices have gradually met their intended applications, they are not yet completely satisfactory in all aspects. Consequently, some problems regarding semiconductor devices still need to be overcome. Summary of the Invention

[0004] The semiconductor device disclosed herein may include a first isolation portion, and the side surface of the first isolation portion may directly contact the side surface of the gate electrode, thereby shortening the movement path of charge carriers in the semiconductor device. Accordingly, the semiconductor device disclosed herein may reduce on-resistance, increase on-current and / or increase breakdown voltage, thereby improving electrical properties and / or reliability.

[0005] In some embodiments, this disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first high-voltage well, a second high-voltage well, an isolation portion, and a gate electrode. The substrate has a first conductivity type. The first high-voltage well has a second conductivity type different from the first conductivity type and is disposed in the substrate. The second high-voltage well has a first conductivity type, is disposed in the substrate, and surrounds the first high-voltage well. The isolation portion is disposed in the first high-voltage well. The gate electrode is disposed on the isolation portion. A side surface of the isolation portion contacts a side surface of the gate electrode.

[0006] The semiconductor device disclosed herein can be applied to various types of electronic devices. To make the components and advantages of this disclosure more apparent and understandable, various embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0007] This disclosure will be more fully understood when read in conjunction with the drawings, as detailed in the following description. It is important to note that, in accordance with industry standard practice, the components are not drawn to scale. In fact, for clarity, the dimensions of the components may be arbitrarily enlarged or reduced.

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 These are schematic cross-sectional views of various stages of a method for forming a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 6 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0010] Symbol Explanation

[0011] 1, 2: Semiconductor devices

[0012] 100: Substrate

[0013] 100TS, 110TS, 210TS, 220TS, 300TS, 310TS, 312TS, 320TS, 420TS: Top surface

[0014] 110: First High-Pressure Trap

[0015] 120: Second High-Pressure Trap

[0016] 210: Drain region

[0017] 210BS, 312BS, 420BS: Bottom surface

[0018] 220: Source Region

[0019] 300: Isolation layer

[0020] 301: Trench

[0021] 310, 312: First isolation section

[0022] 312S1, 410S1, 420S1: First side surface

[0023] 312S2, 410S2, 420S2: Second side surface

[0024] 320: Second Isolation Section

[0025] 330: First mask

[0026] 340: Opening

[0027] 350: Second mask

[0028] 400: Gate stack

[0029] 410: Gate dielectric layer

[0030] 420: Gate electrode

[0031] 430: Gate spacer

[0032] 510: First doped region

[0033] 520: Second doped region

[0034] A1, A2, A3: Included angle

[0035] D: Leakage extreme

[0036] D1: First Direction

[0037] D2: Second Direction

[0038] D3: Third direction

[0039] G: Gate terminal

[0040] MP: Movement Path

[0041] P1: Etching Process

[0042] P2: Doping process

[0043] S: Source Extreme

[0044] SUB: Substrate side

[0045] W1: Top width

[0046] W2: Bottom width Detailed Implementation

[0047] The semiconductor devices of various embodiments of this disclosure are described in detail below. It should be understood that the following description provides many different embodiments for implementing some embodiments of this disclosure. The specific elements and arrangements described below are merely for simple and clear description of some embodiments of this disclosure. Of course, these are only examples and not limitations of this disclosure. Furthermore, similar and / or corresponding element symbols may be used in different embodiments to identify similar and / or corresponding elements for clear description of this disclosure. However, the use of these similar and / or corresponding element symbols is only for simple and clear description of some embodiments of this disclosure and does not represent any association between the different embodiments and / or structures discussed.

[0048] It should be understood that relative terms, such as "lower," "bottom," "higher," or "top," may be used in various embodiments to describe the relative relationship of one element to another in the diagram. It is understood that if the arrangement in the diagram is flipped upside down, an element depicted on the "lower" side will become an element on the "higher" side. The embodiments disclosed herein should be understood in conjunction with the drawings, which are also considered part of the disclosure.

[0049] Furthermore, when it is mentioned that a first material layer is on or over a second material layer, it may include situations where the first material layer and the second material layer are in direct contact, or situations where the first material layer and the second material layer are not in direct contact, that is, situations where there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly on the second material layer, it indicates that the first material layer and the second material layer are in direct contact.

[0050] Furthermore, it should be understood that the ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, are not intended to imply any prior ordinal number for the element (or the plurality of elements), nor to indicate the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; for example, the first element in the specification may be the second element in the claims.

[0051] In some embodiments disclosed herein, terms such as "connect," "interconnect," and "bond," unless specifically defined, may refer to two structures in direct contact, or to two structures not in direct contact, with another structure disposed between them. Furthermore, these terms may include situations where both structures are movable or both structures are fixed. Additionally, the terms "electrical connection" or "electrical coupling" include any direct or indirect electrical connection means.

[0052] In this text, the terms "approximately," "about," and "substantially" typically indicate that a given value or range is within 10%, 5%, 3%, 2%, 1%, or 0.5%. The given quantity is an approximate quantity; that is, even without specific mention of "approximately," "about," or "substantially," the meaning of "approximately," "about," or "substantially" is implied. The phrases "the range is between the first value and the second value" or "the first value ~ the second value" indicate that the range includes the first value, the second value, and other values ​​in between. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies that there may be an error between the first and second values ​​within approximately 10%, 5%, 3%, 2%, 1%, or 0.5%.

[0053] Throughout this disclosure, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following description and claims, words such as "comprise" and "having" are open-ended terms and should therefore be interpreted as "including but not limited to...". Thus, when the terms "comprise" and / or "having" are used in the description of this disclosure, they specify the presence of the corresponding component, area, step, operation, and / or element, but do not exclude the presence of one or more of the corresponding component, area, step, operation, and / or element.

[0054] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art. It is understood that such terms, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0055] In this disclosure, the directions are not limited to the three axes of a Cartesian coordinate system such as the X, Y, and Z axes, and can be interpreted in a broader sense. For example, the X, Y, and Z axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following text, the X-axis direction is the first direction D1 (width direction), the Y-axis direction is the second direction D2 (length direction), and the Z-axis direction is the third direction D3 (thickness / height direction). In some embodiments, the cross-sectional schematic diagram described herein is a schematic diagram for viewing the XY plane. In some embodiments, the normal direction of the substrate described herein is the third direction D3.

[0056] Reference Figure 1 This is a cross-sectional schematic diagram of a stage in a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. Figure 1 As shown, in some embodiments, a substrate 100 may be provided, and the substrate 100 may have a first conductivity type. In some embodiments, the substrate 100 may include a wafer, such as a silicon wafer. In some embodiments, the substrate 100 may include a bulk semiconductor or a semiconductor-on-insulator (SOI) substrate. Generally, an SOI substrate may include a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like, to provide an insulating layer on a silicon or glass substrate. In some embodiments, the substrate may include a multilayer substrate or a gradient substrate. In some embodiments, substrate 100 may include elemental semiconductors, including silicon, germanium, the like, or combinations thereof; substrate 100 may include compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, the like, or combinations thereof; substrate 100 may include alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, the like, or combinations thereof, but this disclosure is not limited thereto.

[0057] like Figure 1As shown, in some embodiments, a first high-voltage well 110 may be formed in the substrate 100. In some embodiments, the first high-voltage well 110 may have a second conductivity type different from the first conductivity type. In some embodiments, a second high-voltage well 120 may be formed in the substrate 100. In some embodiments, the second high-voltage well 120 may have the first conductivity type. In some embodiments, the first high-voltage well 110 and the second high-voltage well 120 may be formed by doping processes such as ion implantation, diffusion, drive-in, similar processes, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the implanted dopant may be further activated by a rapid thermal annealing (RTA) process.

[0058] like Figure 1 As shown, in some embodiments, the second high-voltage well 120 may surround the first high-voltage well 110. In some embodiments, the second high-voltage well 120 may directly contact the first high-voltage well 110. In some embodiments, the first high-voltage well 110 and the second high-voltage well 120 may have substantially the same depth. In some embodiments, the first high-voltage well 110 and the second high-voltage well 120 may not penetrate the substrate 100. In some embodiments, a drain region 210 may be formed in the first high-voltage well 110. In some embodiments, the method of forming the drain region 210 may be the same as or different from the method of forming the first high-voltage well 110. In some embodiments, the drain region 210 may have a second conductivity type.

[0059] like Figure 1 As shown, in some embodiments, the first conductivity type and the second conductivity type can be adjusted according to electrical requirements. In some embodiments, the doping concentration, doping depth, and size of the doped region can also be adjusted according to electrical requirements. In some embodiments, the first conductivity type can be either P-type or N-type, and the second conductivity type can be either P-type or N-type. For ease of explanation, in the following description, the first conductivity type can be P-type, and the second conductivity type can be N-type, but this disclosure is not limited thereto. In other words, the substrate 100 and the second high-voltage well 120 can be P-type, and the first high-voltage well 110 and the drain region 210 can be N-type. Therefore, in the following description, a semiconductor device including an N-type LDMOS is used.

[0060] like Figure 1As shown, in some embodiments, an isolation layer 300 may be formed on the top surface of the substrate 100 to define the active region of the semiconductor device. In some embodiments, the isolation layer 300 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxide oxynitrides such as silicon oxynitride, the like, or combinations thereof, but this disclosure is not limited thereto. For example, the isolation layer 300 may include silicon oxide. In some embodiments, the isolation layer 300 may include shallow trench isolation (STI) or field oxide.

[0061] like Figure 1 As shown, in some embodiments, the isolation layer 300 may be a shallow trench isolation. In this embodiment, a trench 301 may be formed in the substrate 100. Then, material for the isolation layer 300 may be filled in the trench 301 to form the isolation layer 300. In some embodiments, the isolation layer 300 may be disposed in the first high-voltage well 110, at the junction of the first high-voltage well 110 and the second high-voltage well 120, and at the junction of the second high-voltage well 120 and the substrate 100. In some embodiments, the material for the isolation layer 300 may be filled by chemical vapor deposition (CVD), atomic layer deposition (ALD), similar processes, or combinations thereof. In this embodiment, a planarization process may be further performed so that the top surface 300TS of the isolation layer 300 is flush with the top surface 100TS of the substrate 100. In some embodiments, the isolation layer 300 may be formed first, followed by the formation of the first high-voltage well 110, the second high-voltage well 120, and the drain region 210, but this disclosure is not limited thereto.

[0062] like Figure 1 As shown, in some embodiments, the isolation layer 300 may include a first isolation portion 310 and a second isolation portion 320. In some embodiments, the first isolation portion 310 may be disposed in the first high-voltage well 110. In some embodiments, the first isolation portion 310 may at least partially or completely cover the top surface 110TS of the first high-voltage well 110 between the drain regions 210. In some embodiments, the second isolation portion 320 may be disposed at the junction between the first high-voltage well 110 and the second high-voltage well 120 and / or may be disposed in the second high-voltage well 120.

[0063] Reference Figure 2 This is a cross-sectional schematic diagram of a stage in a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. Figure 2As shown, in some embodiments, a first mask 330 may be formed on the first isolation portion 310. In some embodiments, the first mask 330 may cover a portion of the first isolation portion 310, the drain region 210, the second isolation portion 320, and the second high-voltage trap 120, and the first mask 330 may expose the remaining portion of the first isolation portion 310. In some embodiments, the first isolation portion 310 not covered by the first mask 330 may be located between the drain regions 210. Accordingly, the shape of the first isolation portion 310 may be adjusted based on the pattern of the first mask 330.

[0064] like Figure 2 As shown, in some embodiments, after forming the first mask 330, an etching process P1 is performed on the first isolation portion 310. In some embodiments, the etching process P1 may include dry etching, wet etching, or a combination thereof. In some embodiments, dry etching may include plasma etching, plasma-free gas etching, sputter etching, ion milling, reactive ion etching (RIE), similar processes, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, wet etching may include using an acidic solution, an alkaline solution, or a solvent to remove at least a portion of the structure to be removed. Furthermore, the etching process may also be purely chemical etching, purely physical etching, or a combination thereof. Accordingly, the included angle (e.g., ...) can be adjusted based on the etching process P1. Figure 5 The size of the included angle A1 shown.

[0065] Reference Figure 3 This is a cross-sectional schematic diagram of a stage in a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. Figure 3 As shown, in some embodiments, after performing etching process P1, the middle portion of the first isolation portion 310 may be removed, forming an opening 340. In some embodiments, after performing etching process P1, the first isolation portion 312 may be obtained. In some embodiments, the opening 340 may expose the top surface 110TS of the first high-pressure well 110. In some embodiments, the top surface 312TS of the first isolation portion 312 may be higher than the top surface 110TS of the first high-pressure well 110, and the top surface 320TS of the second isolation portion 320 may also be higher than the top surface 110TS of the first high-pressure well 110.

[0066] like Figure 3 As shown, in some embodiments, in the first direction D1, the opening 340 may have a top width W1 away from the substrate 100 and a bottom width W2 close to the substrate 100. In some embodiments, depending on the etching parameters of the etching process P1, the top width W1 of the opening 340 may be greater than or equal to the bottom width W2 of the opening 340. Figure 3 As shown, in some embodiments, the top width W1 of the opening 340 may be substantially equal to the bottom width W2 of the opening 340, but this disclosure is not limited thereto. In some embodiments, the first isolation portion 312 may have a first side surface 312S1 near the opening 340 and a second side surface 312S2 away from the opening 340. In some embodiments, the first side surface 312S1 may be substantially a vertical side surface. In some embodiments, the second side surface 312S2 may be substantially a sloped side surface, and the slope of the sloped side surface may correspond to the shape of the trench 301. In some embodiments, the first mask 330 may be removed after performing the etching process P1.

[0067] like Figure 3 As shown, in some embodiments, since the second isolation portion 320 is not etched by the etching process P1, the second isolation portion 320 may not be substantially damaged. In some embodiments, the second isolation portion 320 may have inclined side surfaces. In some embodiments, the second isolation portion 320 may have an inverted trapezoidal shape. In some embodiments, the opposite side surfaces of the second isolation portion 320 may have corresponding slopes. In some embodiments, the opposite side surfaces of the second isolation portion 320 may correspond to the shape of the trench 301. In some embodiments, the second isolation portion 320 may have a bilaterally symmetrical shape in the normal direction of the substrate 100.

[0068] Reference Figure 4 This is a cross-sectional schematic diagram of a stage in a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. Figure 4 As shown, in some embodiments, a second mask 350 may be formed on the first isolation portion 312 and the second isolation portion 320. In some embodiments, the second mask 350 may cover the first high-voltage well 110, the top surface 312TS and the first side surface 312S1 of the first isolation portion 312, the drain region 210, the second isolation portion 320, and the second high-voltage well 120. In some embodiments, the second mask 350 may expose a portion of the first high-voltage well 110.

[0069] like Figure 4As shown, in some embodiments, a doping process P2 is performed on the exposed first high-voltage well 110 to form a source region 220 in the first high-voltage well 110. In some embodiments, the doping process P2 may include an ion implantation process, a diffusion process, a thermal drive-in process, a similar process, or a combination thereof. In some embodiments, the source region 220 may have a first conductivity type, i.e., P-type. In some embodiments, the second mask 350 may be removed after performing the doping process P2. In some embodiments, the top surface 220TS of the source region 220 may be lower than the top surface 312TS of the first isolation portion 312. In some embodiments, the top surface 220TS of the source region 220 may be flush with the bottom surface 312BS of the first isolation portion 312. In some embodiments, the top surface 220TS of the source region 220 may be lower than the top surface 210TS of the drain region 210. In some embodiments, the top surface 220TS of the source region 220 may be between the top surface 210TS of the drain region 210 and the bottom surface 210BS of the drain region 210.

[0070] Reference Figure 5 This is a cross-sectional schematic diagram of a stage in a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. Figure 5 As shown, in some embodiments, a gate stack 400 may be formed on the first isolation portion 312. In some embodiments, the gate stack 400 may include a gate dielectric layer 410, a gate electrode 420, and a gate spacer 430. In some embodiments, the gate dielectric layer 410 may be compliantly formed on the first high-voltage well 110 and the source region 220. In other words, the gate dielectric layer 410 may be disposed between the first high-voltage well 110 and the subsequently formed gate electrode 420. In some embodiments, the gate dielectric layer 410 may include a dielectric material with a high dielectric constant. In some embodiments, the gate dielectric layer 410 may include an oxide such as silicon oxide.

[0071] like Figure 5As shown, in some embodiments, a gate electrode 420 may be compliantly formed on the first isolation portion 312 and the gate dielectric layer 410. In some embodiments, the gate electrode 420 may include polysilicon, amorphous silicon, metals such as silver (Ag), gold (Au), aluminum (Al), manganese (Mn), copper (Cu), tungsten (W), titanium (Ti), molybdenum (Mo), conductive metal nitrides, conductive metal oxides, the like, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, a first side surface 312S1 of the first isolation portion 312 may directly contact a second side surface 420S2 of the gate electrode 420. In some embodiments, a top surface 312TS of the first isolation portion 312 may be located between a top surface 420TS of the gate electrode 420 and a bottom surface 420BS of the gate electrode 420. In other words, a top portion of the gate electrode 420 may be located above the first isolation portion 312, and a bottom portion of the gate electrode 420 may be located on the side of the first isolation portion 312. In some embodiments, the gate electrode 420 may have a stepped shape. In some embodiments, the gate electrode 420 may cover and directly contact the top surface 312TS and the first side surface 312S1 of the first isolation portion 312.

[0072] like Figure 5 As shown, in some embodiments, a gate spacer 430 may be disposed on a first side surface 420S1 and a second side surface 420S2 of the gate electrode 420. In some embodiments, the gate spacer 430 may be a single-layer or multi-layer structure. In some embodiments, the gate spacer 430 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxides of oxynitride such as silicon oxynitride, the like, or combinations thereof, but this disclosure is not limited thereto.

[0073] like Figure 5 As shown, in some embodiments, a first doped region 510 may be formed in the source region 220 and the drain region 210. In some embodiments, the first doped region 510 may have a second conductivity type, i.e., N-type. In some embodiments, the N-type doping concentration of the first doped region 510 may be greater than the N-type doping concentration of the drain region 210. In some embodiments, a second doped region 520 may be formed in the second high-voltage well 120. In some embodiments, the second doped region 520 may have a first conductivity type, i.e., P-type. In some embodiments, the P-type doping concentration of the second doped region 520 may be greater than the P-type doping concentration of the second high-voltage well 120. Therefore, a semiconductor device 1 can be obtained. In some embodiments, the gate electrode 420 may be electrically connected to the gate terminal G, the first doped region 510 located in the source region 220 may be electrically connected to the source terminal S, the first doped region 510 located in the drain region 210 may be electrically connected to the drain terminal D, and the second doped region 520 located in the second high-voltage well 120 may be electrically connected to the substrate terminal SUB.

[0074] like Figure 5 As shown, in some embodiments, the angle A1 between the first side surface 312S1 of the first isolation portion 312 and the top surface 110TS of the first high-voltage well 110 may be equal to or greater than 90 degrees. For example, the angle A1 may be 90 degrees, 100 degrees, 110 degrees, 120 degrees, 130 degrees, 140 degrees, 150 degrees or greater, or any value between the aforementioned values ​​or a range of values ​​composed of any values, but this disclosure is not limited thereto. In some embodiments, the angle A1 may be substantially equal to 90 degrees, but this disclosure is not limited thereto. In some embodiments, the first isolation portion 312 may have a left-right asymmetrical shape in the normal direction of the substrate 100. In some embodiments, the slope of the first side surface 312S1 of the first isolation portion 312 may be different from the slope of the second side surface 312S2 of the first isolation portion 312. In some embodiments, the slope of the second side surface 312S2 of the first isolation portion 312 may be the same as the slope of the side surface of the second isolation portion 320 away from the source region 220.

[0075] Accordingly, based on the shape of the first isolation portion 312, the carrier movement path MP can be made substantially horizontal, thereby shortening the carrier movement path MP. Therefore, the semiconductor device 1 disclosed herein can reduce on-resistance, increase on-current, increase breakdown voltage, and / or improve reliability.

[0076] In the following text, identical or similar component symbols or descriptions are omitted.

[0077] Reference Figure 6 This is a schematic cross-sectional view of a semiconductor device 2 according to an embodiment of the present disclosure. Figure 6As shown, in some embodiments, when the parameters of the etching process P1 are adjusted so that the top width W1 of the opening 340 is greater than the bottom width W2, the angle A1 between the first side surface 312S1 of the first isolation portion 312 and the top surface 110TS of the first high-pressure sink 110 can be greater than 90 degrees. In some embodiments, the corner of the first isolation portion 312 near the source region 220 can have an angle A2, and the angle A2 can be a supplementary angle to the angle A1. In some embodiments, the angle A2 can be less than or equal to 90 degrees. For example, the angle A2 can be 90 degrees, 80 degrees, 70 degrees, 60 degrees, 50 degrees, 40 degrees, 30 degrees or less, or any value between the aforementioned values ​​or any range of values, but this disclosure is not limited thereto. In some embodiments, the corner of the first isolation portion 312 away from the source region 220 can have an angle A3, and the angle A3 can be less than or equal to 90 degrees. For example, the included angle A3 can be 90 degrees, 80 degrees, 70 degrees, 60 degrees, 50 degrees, 40 degrees, 30 degrees or less, or any value between the aforementioned values ​​or a range of values, but this disclosure is not limited thereto. In some embodiments, the first side surface 312S1 and the second side surface 312S2 of the first isolation portion 312 are parallel to each other, but this disclosure is not limited thereto. In some embodiments, the first isolation portion 312 can be a parallelogram, an inverted trapezoid, or other suitable shape.

[0078] Accordingly, in semiconductor device 2, when the included angle A1 is greater than 90 degrees, the on-resistance can be further reduced, the breakdown voltage increased, space utilization improved, and / or reliability enhanced. Specifically, due to the reduced area of ​​the first isolation portion 312, the resistance per unit area can be reduced. Additionally, breakdown voltage loss can be reduced, thereby improving reliability and durability. Furthermore, since the first isolation portion 312 can have a parallelogram-like shape, wafer utilization and integration density can be improved.

[0079] like Figure 6 As shown, in some embodiments, the gate dielectric layer 410 may have a first side surface 410S1 near the source region 220 and a second side surface 410S2 away from the source region 220. In some embodiments, since the gate dielectric layer 410 may be compliantly formed on the first isolation portion 312, the shape of the gate dielectric layer 410 may correspond to the shape of the first isolation portion 312. In some embodiments, the first side surface 410S1 of the gate dielectric layer 410 may be substantially a vertical side surface, and the second side surface 410S2 of the gate dielectric layer 410 may be a sloping side surface.

[0080] The semiconductor device disclosed herein may include a first isolation portion with a specific profile to shorten the carrier movement path in an LDMOS. For example, the side surface of the first isolation portion may directly contact the side surface of the gate electrode. For example, the first isolation portion may have an opening of equal width or a shape wider at the top and narrower at the bottom. For example, the side surface of the first isolation portion may be a vertical side surface, or the side surface of the first isolation portion may gradually move away from the source region. For example, the gate electrode may be compliantly disposed on the first isolation portion and have a shape corresponding to the first isolation portion. Furthermore, based on the shape of the first isolation portion, the vertical thickness of the semiconductor device can be reduced to improve thermal performance and impedance matching. Moreover, the semiconductor device formation method can simplify the masking and etching steps used to form shallow trench isolation, thereby reducing process complexity and cost. Additionally, the semiconductor device disclosed herein is also suitable for high-voltage applications. Accordingly, the semiconductor device disclosed herein can reduce on-resistance, increase on-current, and / or improve reliability.

[0081] It should be understood that, without departing from the spirit of this disclosure, components in multiple different embodiments can be replaced, reorganized, and combined to complete other embodiments. Components in each embodiment can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with it. The scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps in the specific embodiments described in the specification. Any process, machine, manufacturing, material composition, apparatus, method, and step that is currently or will be developed in the future can be understood from the content of this disclosure, and can be used according to this disclosure as long as it can perform substantially the same function or obtain substantially the same result in the embodiments described herein. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. No embodiment or claim of this disclosure needs to achieve all the purposes, advantages, and / or features described in this disclosure.

[0082] The above outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments disclosed herein. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments disclosed herein to achieve the same purposes and / or advantages as the embodiments herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a first conductivity type; A first high-voltage trap having a second conductivity type different from the first conductivity type is disposed in the substrate; A second high-voltage well, having the first conductivity type, is disposed in the substrate and surrounds the first high-voltage well; An isolation section is located within the first high-pressure trap; and A gate electrode is disposed on the isolation portion. One side surface of the isolation portion contacts one side surface of the gate electrode.

2. The semiconductor device as claimed in claim 1, characterized in that, One top surface of the isolation portion is flush with one top surface of the substrate.

3. The semiconductor device as claimed in claim 1, characterized in that, One of the top surfaces of the isolation section is higher than one of the top surfaces of the first high-pressure sink.

4. The semiconductor device as claimed in claim 3, characterized in that, The angle between the side surface of the isolation section and the top surface of the first high-pressure trap is equal to or greater than 90 degrees.

5. The semiconductor device as claimed in claim 1, characterized in that, Including: A source electrode region, having the first conductivity type, is disposed within the first high-voltage well. In this configuration, one top surface of the source region is lower than one top surface of the isolation portion.

6. The semiconductor device as claimed in claim 5, characterized in that, The top surface of the source region is flush with or higher than the bottom surface of the isolation portion.

7. The semiconductor device as claimed in claim 5, characterized in that, Including: A drain region, having the second conductivity type, is disposed within the first high-voltage well. In this case, one top surface of the source region is lower than one top surface of the drain region.

8. The semiconductor device as claimed in claim 1, characterized in that, The top surface of the isolation portion is located between the top surface of the gate electrode and the bottom surface of the gate electrode.

9. The semiconductor device as claimed in claim 1, characterized in that, The gate electrode has a stepped shape.

10. The semiconductor device as claimed in claim 1, characterized in that, Including: A gate dielectric layer is disposed between the gate electrode and the first high-voltage well. One side surface of the gate dielectric layer is a sloping side surface.

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