Trench gate p-type ldmos with two majority carrier conduction and its operating method

Abstract

This invention discloses a trench-gate P-type LDMOS with two types of majority carrier conduction and its operation method. The trench-gate P-type LDMOS includes a substrate, an N-type buried layer disposed on the substrate, and a P-type drift region disposed above the N-type buried layer. A source region, a gate region, and a drain region are formed within the P-type drift region. The drain region includes a heavily doped P-type drain region, a deep N-type drain region, and a heavily doped N-type drain region disposed within the deep N-type drain region. The heavily doped P-type drain region is located within the P-type drift region, and the deep N-type drain region directly electrically connects the heavily doped N-type drain region on the device surface to the bottom N-type buried layer. The gate region includes staggered N-type trench gates and P-type trench gates, which are electrically isolated by an oxide layer. This invention solves the problems of low current density, large device area, and limited conduction capability and reliability in traditional P-type LDMOS due to low hole mobility.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology, and particularly relates to a trench gate P-type LDMOS with two types of majority carrier conduction and its operation method. Background Technology

[0002] Laterally diffused metal-oxide semiconductors (LDMOS) are characterized by high voltage withstand capability and easy integration with CMOS circuits, and are widely used in power switches, drive circuits, power management, and automotive electronics. Based on the type of majority carriers in the channel, LDMOS can be divided into N-type LDMOS and P-type LDMOS. P-type LDMOS conducts through hole channels and typically turns on under a negative gate voltage.

[0003] In complementary power integrated circuits, it is generally desirable for N-type and P-type devices to have similar output current capabilities. However, hole mobility is lower than electron mobility, and under the same design conditions, the current density of P-type LDMOS is significantly lower than that of N-type LDMOS. To achieve similar output current, P-type LDMOS often requires a much larger layout area, potentially several times that of N-type LDMOS, thus increasing chip area cost.

[0004] One intuitive approach is to leverage the high mobility of electrons to improve the conduction capability of P-type devices. For example, bipolar structures, such as P-type IGBTs, allow electrons and holes to participate in conduction simultaneously. However, in these P-type bipolar devices, electrons typically participate in transport as minority carriers, which is limited by carrier lifetime and may introduce minority carrier accumulation effects, affecting the switching speed of the device.

[0005] On the other hand, when an LDMOS is in a high-voltage, high-current on-state, a base region broadening effect (Kirk effect) occurs. The Kirk effect increases the number of carriers generated by collisional ionization in the drift region of the LDMOS, causing the output characteristic curve of the LDMOS to show an unsaturated trend; the Kirk effect also leads to premature breakdown at the drain, reducing device reliability. Summary of the Invention

[0006] The purpose of this invention is to provide a trench-gate P-type LDMOS with two types of majority carrier conduction and its operation method, which can solve the problems of low current density, large device area, and limited device conduction capability and reliability in traditional P-type LDMOS due to low hole mobility.

[0007] To achieve the above objectives, the solution of the present invention is:

[0008] A trench gate P-type LDMOS having two types of majority carrier conduction includes a substrate, an N-type buried layer disposed on the substrate, and a P-type drift region disposed above the N-type buried layer, wherein a source region, a gate region, and a drain region are formed in the P-type drift region.

[0009] The drain region includes a heavily doped P-type drain region, a deep N-type drain region, and a heavily doped N-type drain region disposed within the deep N-type drain region. The heavily doped P-type drain region is located within the P-type drift region, and the deep N-type drain region directly electrically connects the heavily doped N-type drain region on the device surface to the bottom N-type buried layer.

[0010] The gate region includes staggered N-type trench gates and P-type trench gates, and the N-type trench gates and the P-type trench gates are electrically isolated by an oxide layer.

[0011] The source region includes a heavily P-type doped region and a heavily N-type doped region, which are spaced apart along the width of the device on one side of the source region. The gate region includes an N-type trench gate and a P-type trench gate, which are spaced apart along the width of the device. The P-type trench gate and the heavily P-type doped region are on the same cross-section along the width of the device, and the N-type trench gate and the heavily N-type doped region are on the same cross-section along the width of the device.

[0012] The P-type trench gate includes a P-type trench, a gate oxide layer disposed on the inner wall of the P-type trench, and P-type trench gate polysilicon filled in the P-type trench; the N-type trench gate includes an N-type trench, a gate oxide layer disposed on the inner wall of the N-type trench, and N-type trench gate polysilicon filled in the N-type trench.

[0013] The depth of the P-type trench grid is less than that of the N-type trench grid. The bottom of the P-type trench grid is located within the P-type drift zone, while the bottom of the N-type trench grid extends into the N-type buried layer.

[0014] The P-type trench gate is used to control the hole conduction path in which holes are transported as the majority carriers, and the N-type trench gate is used to control the electron conduction path in which electrons are transported as the majority carriers.

[0015] The P-type trench gate and the N-type trench gate are respectively connected to different gate signals.

[0016] An operating method for a trench-gate P-type LDMOS having two types of majority carrier conduction, applied to the trench-gate P-type LDMOS having two types of majority carrier conduction as described above; the method includes,

[0017] Input source signal into the source region;

[0018] Input a drain signal to the drain region; input a gate signal to the gate region, including inputting a P-type trench gate signal to a P-type trench gate, wherein the P-type trench gate signal has a negative voltage difference with the source signal; inputting an N-type trench gate signal to an N-type trench gate, wherein the N-type trench gate signal has a positive voltage difference with the source signal.

[0019] With the above scheme, the P-type trench gate in this invention is used to control the hole conduction path; the N-type trench gate is used to control the formation of the source-side electron inversion layer, and cooperates with the N-type buried layer and the drain N-type deep injection region to form the electron conduction path, wherein the drain N-type deep injection region directly electrically connects the drain N-type heavily doped region to the N-type buried layer. Thus, when the device is turned on, both hole current and electron current are generated simultaneously, increasing the current density of the P-type LDMOS, reducing the device area, and improving the on-state breakdown characteristics and switching performance.

[0020] The beneficial effects of this invention are as follows: On the one hand, by introducing an electronic conduction path and utilizing the fact that electron mobility is higher than hole mobility, the overall current density of the P-type LDMOS is increased, and the device area required to obtain the same output current is reduced; on the other hand, the charge compensation effect generated by the electronic and hole conduction paths near the drift region reduces the net charge accumulation in the drift region under high voltage and high current conduction conditions, which helps to alleviate the Kirk effect and improve the on-state breakdown characteristics; at the same time, since electrons and holes move as majority carriers in their respective conduction regions, the problem of reduced switching speed caused by minority carrier injection and accumulation can be avoided. Attached Figure Description

[0021] Figure 1 This is a top view of a trench gate P-type LDMOS structure in one embodiment of the present invention;

[0022] Figure 2 yes Figure 1 The diagram shows a cross-sectional structure of a P-type LDMOS in the hole-conducting region.

[0023] Figure 3 yes Figure 1 The diagram shows a cross-sectional structure of a P-type LDMOS in the electronically conductive region. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of protection of this invention.

[0025] Unless otherwise defined, the technical or scientific terms used in this invention should be understood in their ordinary sense by one of ordinary skill in the art. The terms "a," "an," "an," "the," etc., used in this invention do not indicate quantity limitation and may indicate singular or plural. The terms "comprising," "including," "having," and any variations thereof, used in this invention, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., used in this invention are only used to distinguish identical or similar structures and do not indicate a specific order, quantity limitation, or degree of importance among these structures. The terms "connection," "electrical connection," "connected," etc., can indicate a direct connection or an indirect electrical connection achieved through a conductive layer, contact hole, metal interconnect, or other equivalent structure. The directional terms "above," "below," "one side," "the other side," "adjacent," etc., are used to describe the directions shown in the accompanying drawings and are only for the purpose of facilitating understanding of the technical solutions of this invention, and do not constitute a limitation on the actual fabrication direction or usage direction of the device.

[0026] like Figures 1 to 3 As shown, this embodiment provides a trench-gate P-type LDMOS with two types of majority carrier conductivity. The trench-gate P-type LDMOS includes a substrate, an N-type buried layer disposed on the substrate, and a P-type drift region disposed above the N-type buried layer. A source region, a gate region, and a drain region are formed within the P-type drift region. An N-type source body region is provided within the source region. The source region and the drain region are disposed opposite each other along the length of the device, and the gate region is located on one side of the source region.

[0027] The N-type buried layer is located below the P-type drift region and is used to assist in depleting the P-type drift region and improving the electric field distribution when the device is off, while participating in the formation of electronic conduction paths when the device is on.

[0028] The source region includes a source P-type heavily doped region and a source N-type heavily doped region that are electrically connected to each other, and the drain region includes a drain P-type heavily doped region and a drain N-type heavily doped region that are electrically connected to each other, wherein the drain P-type heavily doped region is located within the P-type drift region.

[0029] In this embodiment, the source P-type heavily doped region and the source N-type heavily doped region are electrically connected to each other and are jointly connected to an external source signal, denoted as node S; the drain P-type heavily doped region and the drain N-type heavily doped region are electrically connected to each other and are jointly connected to an external drain signal, denoted as node D.

[0030] The gate region includes a P-type trench gate and an N-type trench gate. The N-type trench gate receives external N-type trench gate signals and is denoted as a GN node; the P-type trench gate receives external P-type trench gate signals and is denoted as a GP node. The control terminals of the P-type trench gate and the N-type trench gate are independent of each other to control the hole conduction path and the electron conduction path respectively.

[0031] Let the voltage between node D and node S be denoted as V. D-S The voltage between the GP node and the S node is denoted as V. GP-S The voltage between the GN node and the S node is denoted as V. GN-S The threshold voltage at which the P-type trench gate controls the opening of the hole inversion channel is denoted as V. Tp In this embodiment, V Tp <0; The threshold voltage for opening the N-type trench gate-controlled electronic inversion channel is denoted as V. Tn In this embodiment, V Tn >0.

[0032] The source N-type body region is connected to both the source P-type heavily doped region and the source N-type heavily doped region, and participates in both the hole conduction path and the electron conduction path.

[0033] In the hole conduction path, the source N-type body region is located between the source P-type heavily doped region and the P-type drift region, and can form a hole inversion layer on its side surface adjacent to the P-type trench gate under the control of the P-type trench gate; the P-type drift region provides a hole transport path on its side surface adjacent to the P-type trench gate under the control of the P-type trench gate; holes, as majority carriers, enter the P-type drift region from the source P-type heavily doped region through the hole inversion layer on the surface of the source N-type body region, and are transported along the P-type drift region to the drain P-type heavily doped region.

[0034] In the electronic conduction path, the P-type drift region between the N-type buried layer and the source N-type body region can form a source-side electron inversion layer on its side surface adjacent to the N-type trench gate under the control of the N-type trench gate. The source N-type body region is located between the source N-type heavily doped region and the source-side electron inversion layer, providing an N-type majority carrier path between the source N-type heavily doped region and the source-side electron inversion layer. The drain N-type deep injection region provides an N-type majority carrier path between the drain N-type heavily doped region and the N-type buried layer. Electrons, as majority carriers, are transported from the drain N-type heavily doped region through the drain N-type deep injection region, the N-type buried layer, the source-side electron inversion layer, and the source N-type body region to the source N-type heavily doped region. It should be noted that the movement directions of holes and electrons are either the same as or opposite to the current direction from the source to the drain in the device, i.e., the current direction is uniformly from the source to the drain.

[0035] like Figure 1 The diagram shown is a top view of the trench-gate P-type LDMOS in this embodiment. Figure 1 In the structure shown, the source region and the drain region are arranged opposite each other along the length of the device, and the P-type drift region is located between the source region and the drain region. The heavily doped P-type source region and the heavily doped N-type source region are located in the region where the source region is located and are spaced apart along the width of the device; the P-type trench gate and the N-type trench gate are located on one side of the source region and are spaced apart along the width of the device. The heavily doped P-type drain region and the heavily doped N-type drain region are located in the region where the drain region is located, wherein the heavily doped P-type drain region serves as the drain-side doped region for the hole conduction path, and the heavily doped N-type drain region serves as the drain-side doped region for the electron conduction path.

[0036] Thus, the device can form mutually distinct hole-conducting regions and electron-conducting regions along the width of the device, allowing holes and electrons to participate in conduction as majority carriers through different conductive paths.

[0037] like Figure 2 As shown, Figure 2 This is a schematic diagram of a cross-sectional structure taken along the locations of the source P-type heavily doped region and the drain P-type heavily doped region. Figure 2 The cross-section shown can be regarded as a trench gate P-type LDMOS structure, and mainly corresponds to the hole conduction path.

[0038] exist Figure 2 In the structure shown, the source P-type heavily doped region is located within the source N-type body region, and the drain P-type heavily doped region is located within the P-type drift region (PD). The P-type trench gate (GP) is disposed adjacent to the source P-type heavily doped region, the source N-type body region (NB), and the P-type drift region. The drain N-type deep implantation region (DN) and the drain N-type heavily doped region located therein are also shown at this cross-sectional location. However, in the hole conduction path, holes are collected by the drain P-type heavily doped region and do not flow through the drain N-type heavily doped region.

[0039] The P-type trench gate includes a P-type trench, a gate oxide layer disposed on the inner wall of the P-type trench, and P-type trench gate polysilicon filling the P-type trench. The P-type trench gate polysilicon is insulated from the adjacent semiconductor region by the gate oxide layer. The adjacent semiconductor region includes the source P-type heavily doped region, the source N-type body region, and the P-type drift region. The P-type trench gate is used to control the formation of a hole inversion layer on the side surface of the source N-type body region near the P-type trench gate by means of an electric field when a corresponding P-type trench gate signal is applied, thereby forming a controllable hole conduction channel between the source P-type heavily doped region and the P-type drift region.

[0040] Furthermore, the depth of the P-type trench gate is less than the depth of the N-type trench gate, and the bottom of the P-type trench gate is located above the N-type buried layer (BN). Therefore, the P-type trench gate is primarily used to control the hole conduction path near the source region, rather than extending directly to the N-type buried layer.

[0041] When the device is turned on, a source signal is input to the source region, a drain signal is input to the drain region, and a P-type trench gate signal with a negative voltage difference between it and the source signal is input to the P-type trench gate. For example, when V GP-S <V Tp V D-S When the voltage is less than 0, under the electric field control of the P-type trench gate, a hole inversion layer is formed on the side surface of the source N-type body region near the P-type trench gate. At this time, the drain node D is at a low potential relative to the source node S. Under the influence of the source-drain voltage, the holes in the heavily doped P-type region of the source, as majority carriers, enter the P-type drift region through the hole inversion layer and are further transported to the heavily doped P-type region of the drain, where they are collected by the drain electrode. The direction of hole movement is the same as the direction of device current, both from the source to the drain.

[0042] Figure 2 The hole movement path in the cross section shown can be represented as: the source P-type heavily doped region, the source N-type body region near the hole inversion layer of the P-type trench gate, the P-type drift region, and the drain P-type heavily doped region.

[0043] like Figure 3 As shown, Figure 3 This is a schematic diagram of a cross-sectional structure taken along the locations of the source N-type heavily doped region and the drain N-type heavily doped region. Figure 3 The cross-section shown includes the N-type trench gate and the drain N-type deep injection region (DN), and mainly corresponds to the electron conduction path.

[0044] exist Figure 3 In the structure shown, the source N-type heavily doped region is located on one side of the source region, and the drain N-type heavily doped region is disposed within the drain N-type deep implantation region and located on one side of the drain region. The N-type trench gate is disposed adjacent to the source N-type heavily doped region, the source N-type body region (NB), the P-type drift region (PD), and the N-type buried layer (BN); the drain N-type deep implantation region is disposed adjacent to the drain N-type heavily doped region, the P-type drift region, and the N-type buried layer, and the drain N-type heavily doped region is directly electrically connected to the N-type buried layer.

[0045] The N-type trench gate includes an N-type trench, a gate oxide layer disposed on the inner wall of the N-type trench, and N-type trench gate polysilicon filling the N-type trench. The bottom of the N-type trench extends into the N-type buried layer. One side of the gate oxide layer contacts the source N-type body region, the P-type drift region, and the N-type buried layer, while the other side contacts the N-type trench gate polysilicon. Thus, the gate oxide layer isolates the N-type trench gate polysilicon from the source N-type body region, the P-type drift region, and the N-type buried layer, preventing direct conduction between the N-type trench gate polysilicon and the semiconductor region. Simultaneously, it allows the N-type trench gate to form an electron inversion layer in its adjacent region under the influence of an electric field.

[0046] Unlike the N-type trench gate, the drain N-type deep injection region is an N-type doped region extending from the device surface to the N-type buried layer, which can provide an N-type majority carrier path between the drain N-type heavily doped region and the N-type buried layer without gate control.

[0047] Specifically, when V GN-S >V Tn Under the electric field control of the N-type trench gate, a source-side electron inversion layer is formed in the P-type drift region sidewall region located between the source N-type body region and the N-type buried layer and adjacent to the N-type trench gate, thereby forming an electron transport path between the source N-type body region, the source-side electron inversion layer and the N-type buried layer; on the drain region side, the drain N-type heavily doped region is directly connected to the N-type buried layer through the drain N-type deep implantation region, forming an electron transport path without the need to form an inversion layer.

[0048] Since the heavily doped N-type region of the drain is electrically connected to the heavily doped P-type region of the drain and shares the same drain potential, and the heavily doped N-type region of the source is electrically connected to the heavily doped P-type region of the source and shares the same source potential, electrons in the heavily doped N-type region of the drain, acting as majority carriers, are attracted by the high potential of the source and flow through the deeply injected N-type region of the drain, the buried N-type layer, the source-side electron inversion layer, and the N-type body region of the source to the heavily doped N-type region of the source, and are finally collected by the source electrode. The direction of electron movement is opposite to the direction of the device current; that is, electrons move from the drain to the source, while the current still flows from the source to the drain.

[0049] therefore, Figure 3 The electron movement path in the cross section shown can be represented as: the drain N-type heavily doped region, the drain N-type deep implantation region, the N-type buried layer, the source-side electron inversion layer, the source N-type body region, and the source N-type heavily doped region.

[0050] In the aforementioned electronic conduction path, the heavily doped N-type drain region, the deep N-type drain injection region, the N-type buried layer, the source-side electron inversion layer, the source N-type body region, and the heavily doped source N-type region are all regions or channels suitable for electrons to move as majority carriers. Therefore, electrons are not injected as minority carriers into the P-type drift region, but rather transported as majority carriers in the N-type conduction path controlled by the N-type trench gate. This reduces the switching speed reduction problem caused by minority carrier injection and accumulation.

[0051] Will Figure 2 and Figure 3 It can be concluded that when the device is turned on, along Figure 2 The cross section shown generates hole current, along... Figure 3 The cross-section shown generates an electronic current, and both the hole current and the electronic current flow from the source to the drain. Because the heavily doped P-type and N-type source regions, and the P-type and N-type trench gates are spaced apart along the device width, both hole majority carrier conducting regions and electron majority carrier conducting regions can coexist inside the device. Compared to traditional P-type LDMOS devices that only conduct electricity through holes, this embodiment can utilize the higher electron mobility to increase the overall current density.

[0052] Simultaneously, the electron conduction path is located near the P-type drift region and can generate charge compensation with the hole conduction path, making the P-type drift region closer to a charge equilibrium state under high voltage and high current conduction conditions. This helps alleviate the problems of charge accumulation and electric field concentration in the P-type drift region under high voltage and high current conduction conditions, thereby improving output characteristics and contributing to increased on-state withstand voltage capability.

[0053] In the off state, the P-type trench gate signal and the N-type trench gate signal are adjusted to potentials that prevent the corresponding conductive paths from being activated, thus shutting off the hole and electron conductive paths. The N-type buried layer and the P-type drift region form a PN junction structure. When the drain is subjected to high voltage, the N-type buried layer can help deplete the P-type drift region, making the electric field distribution within the P-type drift region more uniform, thereby improving the device's withstand voltage and reliability.

[0054] Based on the same inventive concept, this invention also provides a method for operating a trench-gate P-type LDMOS with two types of majority carrier conduction, wherein the method is applied to the trench-gate P-type LDMOS described in the above embodiments. Since this method corresponds to the structure and working principle of the trench-gate P-type LDMOS described above, the relevant specific limitations can be found in the description of the foregoing embodiments, and will not be repeated here.

[0055] In one embodiment, the operating method includes: first, inputting a source signal to the source region; then, inputting a drain signal to the drain region; inputting a P-type trench gate signal to the P-type trench gate, wherein the P-type trench gate signal and the source signal have a negative voltage difference to enable hole conduction path; and inputting an N-type trench gate signal to the N-type trench gate, wherein the N-type trench gate signal and the source signal have a positive voltage difference to enable electron conduction path.

[0056] This embodiment provides a trench-gate P-type LDMOS with two types of majority carrier conduction. By setting the source P-type heavily doped region, the source N-type heavily doped region, the drain P-type heavily doped region, the drain N-type heavily doped region, the source N-type body region, the drain N-type deep injection region, the P-type trench gate, the N-type trench gate, and the N-type buried layer, the device can simultaneously generate hole current and electron current when turned on. This improves the overall current density of the P-type LDMOS, reduces the device area required to obtain the same output current, and helps improve the on-state breakdown characteristics, thereby enhancing the switching performance and reliability of the device.

[0057] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above, which are merely illustrative and not restrictive. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A trench-gate P-type LDMOS having two types of majority carrier conduction, comprising a substrate, an N-type buried layer disposed on the substrate, and a P-type drift region disposed above the N-type buried layer, wherein a source region, a gate region, and a drain region are formed within the P-type drift region; characterized in that: The drain region includes a heavily doped P-type drain region, a deep N-type drain region, and a heavily doped N-type drain region disposed within the deep N-type drain region. The heavily doped P-type drain region is located within the P-type drift region, and the deep N-type drain region directly electrically connects the heavily doped N-type drain region on the device surface to the bottom N-type buried layer. The gate region includes staggered N-type trench gates and P-type trench gates, and the N-type trench gates and the P-type trench gates are electrically isolated by an oxide layer.

2. The trench-gate P-type LDMOS with two types of majority carrier conduction as described in claim 1, characterized in that: The source region includes a heavily P-type doped region and a heavily N-type doped region, which are spaced apart along the width of the device on one side of the source region. The gate region includes an N-type trench gate and a P-type trench gate, which are spaced apart along the width of the device. The P-type trench gate and the heavily P-type doped region are on the same cross-section along the width of the device, and the N-type trench gate and the heavily N-type doped region are on the same cross-section along the width of the device.

3. The trench-gate P-type LDMOS with two types of majority carrier conduction as described in claim 1, characterized in that: The P-type trench gate includes a P-type trench, a gate oxide layer disposed on the inner wall of the P-type trench, and P-type trench gate polysilicon filled in the P-type trench; the N-type trench gate includes an N-type trench, a gate oxide layer disposed on the inner wall of the N-type trench, and N-type trench gate polysilicon filled in the N-type trench.

4. The trench-gate P-type LDMOS with two types of majority carrier conduction as described in claim 3, characterized in that: The depth of the P-type trench grid is less than that of the N-type trench grid. The bottom of the P-type trench grid is located within the P-type drift zone, while the bottom of the N-type trench grid extends into the N-type buried layer.

5. The trench-gate P-type LDMOS with two types of majority carrier conduction as described in claim 1, characterized in that: The P-type trench gate is used to control the hole conduction path in which holes are transported as the majority carriers, and the N-type trench gate is used to control the electron conduction path in which electrons are transported as the majority carriers.

6. The trench-gate P-type LDMOS with two types of majority carrier conduction as described in claim 1, characterized in that: The P-type trench gate and the N-type trench gate are respectively connected to different gate signals.

7. A method for operating a trench-gate P-type LDMOS having two types of majority carrier conduction, applied to a trench-gate P-type LDMOS having two types of majority carrier conduction as described in any one of claims 1 to 6; characterized in that: The method includes, Input source signal into the source region; Input a drain signal to the drain region; input a gate signal to the gate region, including inputting a P-type trench gate signal to a P-type trench gate, wherein the P-type trench gate signal has a negative voltage difference with the source signal; inputting an N-type trench gate signal to an N-type trench gate, wherein the N-type trench gate signal has a positive voltage difference with the source signal.

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