LDMOS structure and method of manufacturing the same

Abstract

The application provides an LDMOS structure and a preparation method thereof. In the LDMOS structure, the thick field oxide layer is located on the sidewall of the first recess, and the included angle between the sidewall and the bottom of the first recess is an obtuse angle. Therefore, the thick field oxide layer is arranged obliquely relative to the substrate surface, so that the length of the LDMOS structure along the substrate surface direction is reduced under the condition that the breakdown voltage of the LDMOS structure is the same (i.e. the length of the thick field oxide layer in the channel direction is the same), thereby reducing the size of the LDMOS structure. In addition, the oblique arrangement of the thick field oxide layer relative to the substrate surface can improve the bird beak morphology of the edge of the LDMOS structure, so that the electric field between the thick field oxide layer and the source region is optimized, thereby further improving the breakdown voltage of the LDMOS structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and more particularly to an LDMOS structure and its fabrication method. Background Technology

[0002] LDMOS (Laterally Diffused Metal-Oxide Semiconductor) devices are high-voltage power devices. To improve the breakdown voltage of the device, a thick, horizontally positioned field oxide layer is typically placed above the drift region near the source end. This layer extends the width of the drift region, and the field plate on top of it effectively suppresses surface breakdown, thereby increasing the device's breakdown voltage.

[0003] However, while a thick field oxide layer extends the width of the drift region, the size of the LDMOS device structure also increases. Furthermore, horizontally placed thick field oxide layers are prone to surface breakdown due to their bird's beak-like edge morphology. Summary of the Invention

[0004] This invention provides an LDMOS structure and its fabrication method, which improves the breakdown voltage of the LDMOS structure while reducing its size.

[0005] According to a first aspect of the present invention, an LDMOS structure is provided, comprising: Substrate; An epitaxial layer is located on the surface of a substrate. The epitaxial layer has a first groove, and the angle between the sidewall of the first groove and the bottom surface of the first groove is an obtuse angle. The doped ions in the substrate and the epitaxial layer are first ions. A buried layer is located at the bottom of the epitaxial layer and extends into the substrate. The first groove is located above the buried layer. The doped ions in the buried layer are second ions, and the first ions and the second ions are of opposite types. The body region is located between the bottom surface of the first groove and the buried layer, the doped ion in the body region is the first ion, and the bottom surface of the body region is in contact with the top surface of the buried layer; The source region is located within the body region, and the doped ion in the source region is a second ion; A drift region is located in the epitaxial layer above the buried layer, and the drift region extends from the sidewall of the first groove in a direction away from the first groove. The doped ion in the drift region is a second ion, and there is a gap between the drift region and the buried layer. The drain region is located within the drift region of the extended region. The doped ion in the drain region is a second ion, and the concentration of the second ion in the drain region is greater than the concentration of the second ion in the drift region. A thick field oxide layer is located on the sidewall surface of the first groove; A gate structure is located on a portion of the thick field oxide layer and on the surface of the epitaxial layer and the bulk region between the source region and the drift region.

[0006] Optionally, it further includes: a body contact region located within the body region, the source region surrounding the body contact region from the periphery, and the source region in contact with the body contact region, wherein the doped ion in the body contact region is the first ion, and the concentration of the first ion in the body contact region is greater than the concentration of the first ion in the body region.

[0007] Optionally, the gate structure includes a gate oxide layer and a polysilicon layer located on the gate oxide layer.

[0008] Optionally, the concentration range of the first ion in the body region is 2 × 10⁻⁶. 13 cm -3 ~6×10 13 cm -3 The concentration range of the first ion in the body contact area is 2 × 10⁻⁶. 13 cm -3 ~6×10 13 cm -3 The concentration range of the second ion in the source region is 2 × 10⁻⁶. 13 cm -3 ~6×10 13 cm -3 .

[0009] Optionally, the concentration range of the second ion in the drift region is 2 × 10⁻⁶. 12 cm -3 ~4×10 12 cm -3 The concentration range of the second ion in the leak region is 2 × 10⁻⁶. 12 cm -3 ~4×10 12 cm -3 .

[0010] Optionally, the material of the thick field oxide layer is silicon oxide, and the thickness of the thick field oxide layer ranges from 800 angstroms to 1200 angstroms.

[0011] Optional, also includes: The first ion trap region is located in the epitaxial layer on the other side of the drift region relative to the body region. The bottom surface of the first ion trap region is in contact with the buried layer. The doped ion in the first ion trap region is the first ion. The first ion-doped region is located at the top of the first ion trap region. The doped ions in the first ion-doped region are first ions, and the concentration of the first ion in the first ion-doped region is greater than the concentration of the first ion in the first ion trap region. A first shallow trench isolation structure is located between the drift region and the first ion trap region; The second ion trap region is located in the epitaxial layer on the other side of the first ion trap region relative to the drift region. The bottom surface of the second ion trap region is in contact with the buried layer. The doped ions in the second ion trap region are second ions. The second ion-doped region is located at the top of the second ion trap region. The doped ions in the second ion-doped region are second ions, and the concentration of the second ions in the second ion-doped region is greater than the concentration of the second ions in the second ion trap region. The second shallow trench isolation structure is located between the first ion trap region and the second ion trap region; A connection doped region is located in the epitaxial layer on the other side of the second ion trap region relative to the first ion trap region. The doped ion in the connection doped region is the first ion, and the concentration of the first ion in the connection doped region is the same as the concentration of the first ion in the first ion doped region. The third shallow trench isolation structure is located between the second ion trap region and the connection doped region.

[0012] According to a second aspect of the present invention, a method for fabricating an LDMOS structure is provided, comprising: An initial structure is provided, the initial structure including a substrate, an epitaxial layer located on the surface of the substrate, and a buried layer located at the bottom of the epitaxial layer and extending into the substrate, wherein the dopants in the substrate and the epitaxial layer are first ions, and the dopants in the buried layer are second ions, wherein the first ions and the second ions are of opposite types; A first groove is formed in the epitaxial layer above the buried layer, and the angle between the sidewall of the first groove and the bottom surface of the first groove is an obtuse angle. A thick field oxide layer is formed on the sidewall surface of the first groove; A drift region is formed in the epitaxial layer above the buried layer. The drift region extends from the sidewall of the first groove toward a direction away from the first groove. The doped ions in the drift region are second ions. There is a gap between the drift region and the buried layer. A drift region is formed below the sidewall of the first groove and in the epitaxial layer outside the first groove, wherein the doped ions in the drift region are second ions; A volume region is formed between the bottom surface of the first groove and the buried layer, and the doped ion in the volume region is the first ion; A drain region is formed in the drift region, and a source region is formed in the body region. The dopants in both the drain region and the source region are second ions, and the concentration of the second ions in the drain region is greater than the concentration of the second ions in the drift region. A gate structure is formed on a portion of the thick field oxide layer and on the surface of the epitaxial layer and the body region between the source region and the drift region.

[0013] Optionally, forming the thick field oxide layer includes: A silicon oxide layer is formed on the epitaxial layer and on the inner wall surface of the first groove; A silicon nitride layer is formed on the silicon oxide layer; Remove the silicon oxide layer and silicon nitride layer from the sidewall surface of the first groove; After removing the silicon oxide and silicon nitride layers from the sidewalls of the first groove, the thick field oxide layer is grown on the exposed sidewalls of the first groove.

[0014] Optionally, before forming the source region and the drain region, the method further includes: forming a body contact region within the body region, wherein the source region surrounds the body contact region from the periphery and the source region is in contact with the body contact region, wherein the doped ion in the body contact region is the first ion, and the concentration of the first ion in the body contact region is greater than the concentration of the first ion in the body region.

[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: In the LDMOS structure provided by the technical solution of this invention, since the thick field oxide layers are all located on the sidewalls of the first groove, and the angle between the sidewalls and the bottom surface of the first groove is an obtuse angle, the thick field oxide layers are inclined relative to the substrate surface. This reduces the length of the LDMOS structure along the substrate surface while maintaining the same breakdown voltage (i.e., the same length of the thick field oxide layer in the channel direction), thereby reducing the size of the LDMOS structure. Furthermore, the inclined arrangement of the thick field oxide layers relative to the substrate surface improves the beak-like morphology at the edges of the LDMOS structure, optimizing the electric field between the thick field oxide layer and the source region, thereby further improving the breakdown voltage of the LDMOS structure. Attached Figure Description

[0016] Figures 1-10 This is a cross-sectional structural diagram corresponding to each step of the LDMOS structure fabrication method provided in the embodiments of the present invention.

[0017] Figure label: 1. Substrate; 2. Epitaxial layer; 3. Buried layer; 4. Body region; 5. Drift region; 6. Drain region; 7. Source region; 8. Thick field oxide layer; 9. Gate structure; 10. Body contact region; 11. First ion trap region; 12. Second ion trap region; 21. First ion-doped region; 22. Second ion-doped region; 23. Connector-doped region; 31. First shallow trench isolation structure; 32. Second shallow trench isolation structure; 33. Third shallow trench isolation structure; 310. First isolation trench; 320. Second isolation trench; 330. Third isolation trench; 80. First trench; 81. Silicon oxide layer; 82. Silicon nitride layer; 83. Second mask layer. Detailed Implementation

[0018] As described in the background section, a horizontally placed thick field oxide layer can make LDMOS devices too large and prone to surface breakdown due to the bird's beak-like morphology of their edges.

[0019] In view of this, the present invention creatively proposes an LDMOS structure, comprising: Substrate; An epitaxial layer is located on the surface of a substrate. The epitaxial layer has a first groove, and the angle between the sidewall of the first groove and the bottom surface of the first groove is an obtuse angle. The doped ions in the substrate and the epitaxial layer are first ions. A buried layer is located at the bottom of the epitaxial layer and extends into the substrate. The first groove is located above the buried layer. The doped ions in the buried layer are second ions, and the first ion and the second ion are of opposite types. The body region is located between the bottom surface of the first groove and the buried layer, and the doped ion in the body region is the first ion; The source region is located within the body region, and the doped ion in the source region is a second ion; A drift region is located within the epitaxial layer above the buried layer, and the drift region extends from the sidewall of the first groove in a direction away from the first groove, wherein the doped ion in the drift region is a second ion; The drain region is located within the drift region of the extended region. The doped ion in the drain region is a second ion, and the concentration of the second ion in the drain region is greater than the concentration of the second ion in the drift region. A thick field oxide layer is located on the sidewall surface of the first groove; A gate structure is located on a portion of the thick field oxide layer and on the surface of the epitaxial layer and the bulk region between the source region and the drift region.

[0020] The tilted arrangement of the thick field oxide layer reduces the length of the LDMOS structure along the substrate surface while maintaining the same breakdown voltage (i.e., the same length of the thick field oxide layer in the channel direction), thus reducing the size of the LDMOS structure. Furthermore, the tilted arrangement of the thick field oxide layer relative to the substrate surface improves the bird's beak morphology at the edges of the LDMOS structure, optimizing the electric field between the thick field oxide layer and the source region, thereby further increasing the breakdown voltage of the LDMOS structure.

[0021] The embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The terms "first," "second," "third," etc., in the specification, claims, and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] This invention provides a method for fabricating an LDMOS structure.

[0023] Please refer to Figure 1 An initial structure is provided, which may include a substrate 1, an epitaxial layer 2 located on the surface of the substrate 1, and a buried layer 3 located at the bottom of the epitaxial layer 2 and extending into the substrate 1. The doped ions in the substrate 1 and the epitaxial layer 2 are first ions, and the doped ions in the buried layer 3 are second ions. The types of the first ions and the second ions are opposite.

[0024] In this embodiment, substrate 1 may be, for example, a silicon substrate. Of course, in other embodiments, substrate 1 may also be a germanium substrate or a germanium-silicon substrate, etc.

[0025] In this embodiment, the first ion can be a P-type ion, such as boron or aluminum, and the second ion can be an N-type ion, such as phosphorus or arsenic.

[0026] Please continue to refer to this. Figure 1A first groove 80 is formed in the epitaxial layer 2 above the buried layer 3, and the angle between the side wall of the first groove 80 and the bottom surface of the first groove 80 is an obtuse angle.

[0027] Furthermore, while forming the first groove 80, a first isolation groove 310, a second isolation groove 320 and a third isolation groove 330 are formed on the epitaxial layer 2, which are spaced apart along a first direction and surround the first groove 80, wherein the first direction is the direction from the first groove 80 to the outside of the first groove 80.

[0028] A first shallow trench isolation structure, a second shallow trench isolation structure, and a third shallow trench isolation structure are formed in the first isolation groove 310, the second isolation groove 320, and the third isolation groove 330, respectively.

[0029] Please refer to Figures 2-3 The methods for forming the first shallow trench isolation structure, the second shallow trench isolation structure, and the third shallow trench isolation structure are described in detail below.

[0030] Please refer to Figure 2 An insulating material layer is deposited in the first groove 80, the first isolation groove 310, the second isolation groove 320 and the third isolation groove 330 to form a first shallow trench isolation structure 31 in the first isolation groove 310, a second shallow trench isolation structure 32 in the second isolation groove 320 and a third shallow trench isolation structure 33 in the third isolation groove 330.

[0031] In this embodiment, a patterned first mask layer (not shown) is formed on the surface of the epitaxial layer 2 and the surface of the insulating material layer. The first mask layer has a patterned opening opposite to the first groove 80 to expose the insulating material layer within the first groove 80.

[0032] Please refer to Figure 3 Using the first mask layer as a mask, the insulating material layer in the first groove 80 is removed.

[0033] In this embodiment, the method for removing the insulating material layer in the first groove 80 may be, for example, wet etching.

[0034] After removing the insulating material layer inside the first groove 80, the first mask layer is removed.

[0035] Please refer to Figures 4-5 A thick field oxide layer 8 is formed on the side wall surface of the first groove 80.

[0036] Please refer to Figures 4-5 The following section provides a detailed explanation of the method for forming the thick field oxide layer 8.

[0037] Please refer to Figure 4A silicon oxide layer 81 is formed on the epitaxial layer 2 and on the inner wall surface of the first groove 80.

[0038] Next, a silicon nitride layer 82 is formed on the silicon oxide layer 81.

[0039] Please refer to Figure 4 Remove the silicon oxide layer 81 and silicon nitride layer 82 from the sidewall surface of the first groove 80.

[0040] The method further includes, before removing the silicon oxide layer 81 and silicon nitride layer 82 on the sidewall of the first groove 80, forming a patterned second mask layer 83 on the silicon nitride layer 82, which exposes the silicon nitride layer 82 above the sidewall of the first groove 80.

[0041] In this embodiment, removing the silicon oxide layer 81 and silicon nitride layer 82 on the sidewall of the first groove 80 can be done by wet etching or dry etching.

[0042] Please refer to Figure 5 After removing the silicon oxide layer 81 and silicon nitride layer 82 on the sidewall of the first groove 80, a thick field oxide layer 8 is grown on the exposed sidewall of the first groove 80.

[0043] In this embodiment, the method for growing the thick field oxide layer 8 can be thermal oxidation.

[0044] Next, after forming the thick field oxide layer 8, the second mask layer 83, the silicon nitride layer 82 and the silicon oxide layer 81 on the epitaxial layer 2 are removed in sequence.

[0045] Please refer to Figure 6 A drift region 5 is formed in the epitaxial layer 2 above the buried layer 3. The drift region 5 extends from the sidewall of the first groove 80 in a direction away from the first groove 80. The doped ions in the drift region 5 are second ions.

[0046] For details, please refer to Figure 6 The drift zone 5 is located on both sides opposite to the first groove 80.

[0047] In this embodiment, the bottom surface of the drift region 5 is closer to the buried layer 3 than the bottom surface of the first groove 80, and there is a gap between the drift region 5 and the buried layer 3.

[0048] Furthermore, while forming the drift region 5, a second ion trap region 12 is formed between the second shallow trench isolation structure and the third shallow trench isolation structure. The bottom surface of the second ion trap region 12 is in contact with the top surface of the buried layer 3.

[0049] In this embodiment, the method for forming the drift region 5 may be, for example, thermal annealing after ion implantation.

[0050] Please refer to Figure 7 A body region 4 is formed between the bottom surface of the first groove 80 and the buried layer 3, and the doped ions in the body region 4 are the first ions. The bottom surface of the body region 4 is in contact with the top surface of the buried layer 3.

[0051] Furthermore, while forming the body region 4, a first ion trap region 11 is formed between the first shallow trench isolation structure 31 and the second shallow trench isolation structure 32. The bottom surface of the first ion trap region 11 is in contact with the top surface of the buried layer 3.

[0052] In this embodiment, the method for forming the body region 4 may be, for example, thermal annealing after ion implantation.

[0053] In this embodiment, please refer to Figure 8 Before forming the source region 7 and the drain region 6, the process may further include: forming a body contact region 10 within the body region 4; simultaneously forming a first ion-doped region 21 within the first ion trap region 11; and forming a connection-doped region 23 in the epitaxial layer 2 on the other side of the second ion trap region 12 opposite to the first ion trap region 11. Therefore, the doped ions in the body contact region 10, the first ion-doped region 21, and the connection-doped region 23 are all first ions.

[0054] Please refer to Figure 9 A drain region 6 is formed in the drift region 5 of the extended region, and a source region 7 is formed in the body region 4. The doped ions in the drain region 6 and the source region 7 are both second ions, and the concentration of the second ion in the drain region 6 is greater than the concentration of the second ion in the drift region 5.

[0055] In this embodiment, the source region 7 is formed in the body contact region 10, surrounds the body contact region 10 from the periphery, and is in contact with the body contact region 10.

[0056] In this embodiment, while forming the source region 7 and the drain region 6, a second ion doped region 22 is formed in the second ion trap region 12. The second ion concentration in the second ion doped region 22 is the same as the second ion concentration in the source region 7 and the second ion concentration in the drain region 6.

[0057] Please refer to Figure 10 A gate structure 9 is formed on a portion of the thick field oxide layer 8 and on the surface of the epitaxial layer 2 and the body region 4 between the source region 7 and the drift region 5.

[0058] In one embodiment, the gate structure 9 may include a gate oxide layer and a polysilicon gate located on the gate oxide layer.

[0059] This invention also provides an LDMOS structure, which may include: a substrate 1, an epitaxial layer 2, a buried layer 3, a body region 4, a source region 7, a drift region 5, a drain region 6, a thick field oxide layer 8, and a gate structure 9.

[0060] In this embodiment, the doped ion in substrate 1 is the first ion.

[0061] In this embodiment, the epitaxial layer 2 is located on the surface of the substrate 1. The epitaxial layer 2 has a first groove 80. The angle between the sidewall of the first groove 80 and the bottom surface of the first groove 80 is an obtuse angle. The doped ions in the epitaxial layer 2 are first ions.

[0062] In this embodiment, the buried layer 3 is located at the bottom of the epitaxial layer 2 and extends into the substrate 1. The first groove 80 is located above the buried layer 3. The doped ions in the buried layer 3 are second ions, and the first ion is of the opposite type to the second ion.

[0063] In this embodiment, the body region 4 is located between the bottom surface of the first groove 80 and the buried layer 3, and the doped ion in the body region 4 is the first ion.

[0064] In this embodiment, the source region 7 is located within the body region 4, and the doped ion in the source region 7 is a second ion.

[0065] In this embodiment, the drift region 5 is located in the epitaxial layer 2 above the buried layer 3, and the drift region 5 extends from the sidewall of the first groove 80 in a direction away from the first groove 80. The doped ions in the drift region 5 are second ions.

[0066] In this embodiment, the drain region 6 is located within the drift region 5 of the extended region, the doped ion of the drain region 6 is a second ion, and the concentration of the second ion in the drain region 6 is greater than the concentration of the second ion in the drift region 5.

[0067] In this embodiment, the thick field oxide layer 8 is located on the side wall surface of the first groove 80.

[0068] In this embodiment, the material of the thick field oxide layer 8 is silicon oxide, and the thickness of the thick field oxide layer 8 ranges from 800 angstroms to 1200 angstroms. Specifically, the specific thickness of the thick field oxide layer 8 needs to be determined by those skilled in the art based on the preset voltage of the device. If the thick field oxide layer 8 is too thin, the device is prone to surface breakdown, thereby reducing the device's withstand voltage capability.

[0069] In this embodiment, the gate structure 9 is located on a portion of the thick field oxide layer 8 and on the surface of the epitaxial layer 2 and the body region 4 between the source region 7 and the drift region 5.

[0070] In this embodiment, the gate structure 9 includes a gate oxide layer and a polysilicon layer located on the gate oxide layer.

[0071] In this embodiment, the LDMOS structure further includes a body contact region 10, which is located within the body region 4. The source region 7 surrounds the body contact region 10 from the periphery and is in contact with the body contact region 10. The doped ion in the body contact region 10 is the first ion, and the concentration of the first ion in the body contact region 10 is greater than the concentration of the first ion in the body region 4.

[0072] In this embodiment, the concentration range of the first ion in the body region 4 is 2 × 10⁻⁶. 13 cm -3 ~6×10 13 cm -3 The concentration range of the first ion in the body contact region 10 is 2 × 10⁻⁶. 13 cm-3~6×10 13 cm -3 The concentration range of the second ion in the source region 7 is 2 × 10⁻⁶. 13 cm -3 ~6×10 13 cm -3 .

[0073] In this embodiment, the concentration range of the second ion in the drift region 5 is 2 × 10⁻⁶. 12 cm -3 ~4×10 12 cm -3 The concentration range of the second ion in the leak region 6 is 2 × 10⁻⁶. 12 cm -3 ~4×10 12 cm -3 .

[0074] In this embodiment, the LDMOS structure further includes a first ion trap region 11, a first ion doped region 21, a first shallow trench isolation structure, a second ion trap region 12, a second ion doped region 22, a second shallow trench isolation structure, a third shallow trench isolation structure, and a connection doped region 23.

[0075] Specifically, the first ion trap region 11 is located in the epitaxial layer 2 on the other side of the drift region 5 relative to the body region 4, and the bottom surface of the first ion trap region 11 is in contact with the buried layer 3. The doped ions in the first ion trap region 11 are first ions. The first ion doped region 21 is located on top of the first ion trap region 11, and the doped ions in the first ion doped region 21 are first ions, and the concentration of the first ions in the first ion doped region 21 is greater than the concentration of the first ions in the first ion trap region 11. The first shallow trench isolation structure is located between the drift region 5 and the first ion trap region 11. The second ion trap region 12 is located in the epitaxial layer 2 on the other side of the first ion trap region 11 relative to the drift region 5, and the bottom surface of the second ion trap region 12 is in contact with the buried layer 3. The doped ion in the second ion trap region 12 is the second ion; the second ion doped region 22 is located at the top of the second ion trap region 12, the doped ion in the second ion doped region 22 is the second ion, and the concentration of the second ion in the second ion doped region 22 is greater than the concentration of the second ion in the second ion trap region 12; the second shallow trench isolation structure is located between the first ion trap region 11 and the second ion trap region 12; the connection doped region 23 is located in the epitaxial layer 2 on the other side of the second ion trap region 12 relative to the first ion trap region 11, the doped ion in the connection doped region 23 is the first ion, and the concentration of the first ion in the connection doped region 23 is the same as the concentration of the first ion in the first ion doped region 21; the third shallow trench isolation structure is located between the second ion trap region 12 and the connection doped region 23.

[0076] In summary, in the LDMOS structure provided by this embodiment of the invention, since the thick field oxide layers 8 are all located on the sidewalls of the first groove 80, and the angle between the sidewalls and the bottom surface of the first groove 80 is an obtuse angle, the thick field oxide layers 8 are inclined relative to the surface of the substrate 1. This reduces the length of the LDMOS structure along the surface of the substrate 1 while maintaining the same breakdown voltage (i.e., the same length of the thick field oxide layer 8 in the channel direction), thereby reducing the size of the LDMOS structure. Furthermore, the inclined arrangement of the thick field oxide layers 8 relative to the surface of the substrate 1 improves the beak-like morphology at the edge of the LDMOS structure, optimizing the electric field between the thick field oxide layers 8 and the source region 7, thereby further improving the breakdown voltage of the LDMOS structure.

[0077] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An LDMOS structure, characterized in that, include: Substrate; An epitaxial layer is located on the surface of a substrate. The epitaxial layer has a first groove, and the angle between the sidewall of the first groove and the bottom surface of the first groove is an obtuse angle. The doped ions in the substrate and the epitaxial layer are first ions. A buried layer is located at the bottom of the epitaxial layer and extends into the substrate. The first groove is located above the buried layer. The doped ions in the buried layer are second ions, and the first ions and the second ions are of opposite types. The body region is located between the bottom surface of the first groove and the buried layer, the doped ion in the body region is the first ion, and the bottom surface of the body region is in contact with the top surface of the buried layer; The source region is located within the body region, and the doped ion in the source region is a second ion; A drift region is located in the epitaxial layer above the buried layer, and the drift region extends from the sidewall of the first groove in a direction away from the first groove. The doped ion in the drift region is a second ion, and there is a gap between the drift region and the buried layer. The drain region is located within the drift region of the extended region. The doped ion in the drain region is a second ion, and the concentration of the second ion in the drain region is greater than the concentration of the second ion in the drift region. A thick field oxide layer is located on the sidewall surface of the first groove; A gate structure is located on a portion of the thick field oxide layer and on the surface of the epitaxial layer and the bulk region between the source region and the drift region.

2. The LDMOS structure according to claim 1, characterized in that, Also includes: A body contact region is located within the body region. The source region surrounds the body contact region from the periphery, and the source region is in contact with the body contact region. The doped ion in the body contact region is the first ion, and the concentration of the first ion in the body contact region is greater than the concentration of the first ion in the body region.

3. The LDMOS structure according to claim 2, characterized in that, The gate structure includes a gate oxide layer and a polysilicon layer located on the gate oxide layer.

4. The LDMOS structure according to claim 2, characterized in that, The concentration range of the first ion in the body region is 2 × 10⁻⁶. 13 cm -3 ~6×10 13 cm -3 The concentration range of the first ion in the body contact area is 2 × 10⁻⁶. 13 cm -3 ~6×10 13 cm -3 The concentration range of the second ion in the source region is 2 × 10⁻⁶. 13 cm -3 ~6×10 13 cm -3 .

5. The LDMOS structure according to claim 1, characterized in that, The concentration range of the second ion in the drift region is 2 × 10⁻⁶. 12 cm -3 ~4×10 12 cm -3 The concentration range of the second ion in the leak region is 2 × 10⁻⁶. 12 cm -3 ~4×10 12 cm -3 .

6. The LDMOS structure according to claim 1, characterized in that, The material of the thick field oxide layer is silicon oxide, and the thickness of the thick field oxide layer ranges from 800 angstroms to 1200 angstroms.

7. The LDMOS structure according to any one of claims 1 to 6, characterized in that, Also includes: The first ion trap region is located in the epitaxial layer on the other side of the drift region relative to the body region. The bottom surface of the first ion trap region is in contact with the buried layer. The doped ion in the first ion trap region is the first ion. The first ion-doped region is located at the top of the first ion trap region. The doped ions in the first ion-doped region are first ions, and the concentration of the first ion in the first ion-doped region is greater than the concentration of the first ion in the first ion trap region. A first shallow trench isolation structure is located between the drift region and the first ion trap region; The second ion trap region is located in the epitaxial layer on the other side of the first ion trap region relative to the drift region. The bottom surface of the second ion trap region is in contact with the buried layer. The doped ions in the second ion trap region are second ions. The second ion-doped region is located at the top of the second ion trap region. The doped ions in the second ion-doped region are second ions, and the concentration of the second ions in the second ion-doped region is greater than the concentration of the second ions in the second ion trap region. The second shallow trench isolation structure is located between the first ion trap region and the second ion trap region; A connection doped region is located in the epitaxial layer on the other side of the second ion trap region relative to the first ion trap region. The doped ion in the connection doped region is the first ion, and the concentration of the first ion in the connection doped region is the same as the concentration of the first ion in the first ion doped region. The third shallow trench isolation structure is located between the second ion trap region and the connection doped region.

8. A method for fabricating an LDMOS structure, characterized in that, include: An initial structure is provided, the initial structure including a substrate, an epitaxial layer located on the surface of the substrate, and a buried layer located at the bottom of the epitaxial layer and extending into the substrate, wherein the dopants in the substrate and the epitaxial layer are first ions, and the dopants in the buried layer are second ions, wherein the first ions and the second ions are of opposite types; A first groove is formed in the epitaxial layer above the buried layer, and the angle between the sidewall of the first groove and the bottom surface of the first groove is an obtuse angle. A thick field oxide layer is formed on the sidewall surface of the first groove; A drift region is formed in the epitaxial layer above the buried layer. The drift region extends from the sidewall of the first groove toward a direction away from the first groove. The doped ions in the drift region are second ions. There is a gap between the drift region and the buried layer. A volume region is formed between the bottom surface of the first groove and the buried layer, and the doped ion in the volume region is the first ion; A drain region is formed in the drift region of the extended region, and a source region is formed in the body region. The dopants in the drain region and the source region are both second ions, and the concentration of the second ions in the drain region is greater than the concentration of the second ions in the drift region. A gate structure is formed on a portion of the thick field oxide layer and on the surface of the epitaxial layer and the body region between the source region and the drift region.

9. The method for fabricating an LDMOS structure according to claim 8, characterized in that, Forming the thick field oxide layer includes: A silicon oxide layer is formed on the epitaxial layer and on the inner wall surface of the first groove; A silicon nitride layer is formed on the silicon oxide layer; Remove the silicon oxide layer and silicon nitride layer from the sidewall surface of the first groove; After removing the silicon oxide and silicon nitride layers from the sidewalls of the first groove, the thick field oxide layer is grown on the exposed sidewalls of the first groove.

10. The method for fabricating an LDMOS structure according to claim 8, characterized in that, Before forming the source region and the drain region, the method further includes: forming a body contact region within the body region, wherein the source region surrounds the body contact region from the periphery and the source region is in contact with the body contact region, wherein the doped ion in the body contact region is the first ion, and the concentration of the first ion in the body contact region is greater than the concentration of the first ion in the body region.

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