LDMOS and LDMOS devices based on 90 nm bcd process

Abstract

The application discloses a kind of LDMOS and LDMOS device based on 90 nanometer BCD process, including trench gate, substrate and the trap zone and drift zone being arranged in substrate, source region is arranged on trap zone, and drain region is arranged on drift zone.Trench gate includes the polysilicon region of substrate being in-depth between trap zone and drift zone and the gate oxide region for isolating polysilicon region. Among them, the drift zone between drain region and trench gate is provided with electric field reduction structure zone, and the electric field reduction structure zone is the same doping zone as substrate doping type, which is formed from the surface of drift zone to the substrate direction by ion implantation.Due to the electric field reduction structure zone being arranged between trench gate and drain region, the trench gate of LDMOS is three-dimensional regulation to drift zone potential and depletion layer shape in off state, and the equipotential line is transferred to the body from device surface, disperses surface local electric field peak value and optimizes drift zone electric field distribution, so as to inhibit surface early breakdown and improve withstand voltage margin.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and specifically to an LDMOS and LDMOS device based on a 90-nanometer BCD process. Background Technology

[0002] DMOS stands for Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor, primarily consisting of two types: VDMOS and LDMOS (Laterally Diffused MOSFET). LDMOS, with its advantages of high voltage withstand capability, high transconductance, and high gain, is widely used as a high-voltage power device in radio frequency power integrated circuits. An LDMOS device is composed of hundreds or thousands of individual LDMOS cells. In the 90nm BCD (Bipolar-CMOS-DMOS) process platform, the LDMOS device is the core component for achieving "high-voltage / high-current power switching capability," working in conjunction with on-chip low-voltage CMOS control and logic, as well as BJTs, ESD protection devices, and isolation devices to complete power conversion and intelligent control on the same chip. A crucial parameter for LDMOS devices is their breakdown voltage. Power semiconductor devices are preferably those capable of operating at voltages close to the theoretical breakdown voltage of semiconductors. In transistors integrating high voltage, the punch-through voltage between the drain / source and the semiconductor substrate, as well as the breakdown voltage between the drain / source and the well or substrate, must be greater than the operating voltage. As IC integration density increases and device feature sizes decrease, the gate oxide layer becomes increasingly thinner, significantly reducing its gate breakdown voltage. The breakdown voltage of LDMOS is a crucial parameter and a key aspect of its reliability. Although LDMOS possesses a low-doped drift region, giving it a higher breakdown voltage compared to other MOS devices, the increasing demand for high-voltage, high-power applications necessitates measures to further enhance its breakdown voltage to meet the requirements of high-frequency, high-voltage operation. Summary of the Invention

[0003] The main technical problem this invention addresses is how to improve the breakdown voltage of LDMOS.

[0004] According to a first aspect, one embodiment provides an LDMOS based on a 90nm BCD process, including a trench gate, a substrate, and a trap region and a drift region disposed in the substrate; the source region of the LDMOS is disposed in the trap region, and the drain region of the LDMOS is disposed in the drift region.

[0005] The trench gate includes a gate oxide region and a polysilicon region. The polysilicon region extends into the substrate between the trap region and the drift region and is isolated from the trap region and the drift region through the polysilicon region to form the trench gate of the LDMOS.

[0006] The gate connection terminal of the LDMOS is disposed on the polysilicon region, the drain of the LDMOS is disposed on the drain region, and the source of the LDMOS is disposed on the source region.

[0007] The polysilicon region extends into the substrate to a greater depth than the source region and the drain region extend into the substrate.

[0008] An electric field reduction structure region is provided in the drift region between the drain region and the trench gate; the electric field reduction structure region is a doped region of the same type as the substrate, formed from the surface of the drift region toward the substrate by ion implantation.

[0009] In one embodiment, the electric field reduction structure region is attached to the gate oxide region; the electric field reduction structure region extends into the substrate to a depth less than the polysilicon region extends into the substrate; the electric field reduction structure region extends into the substrate to a depth less than the drift region extends into the substrate.

[0010] In one embodiment, the trap region and the drift region extend from the upper surface of the LDMOS toward the substrate, the source region is disposed on the upper surface of the trap region, the drain region is disposed on the upper surface of the drift region, and the extension depth of the trap region and the drift region toward the substrate is less than the extension depth of the polysilicon region toward the substrate; wherein, the trench gate is disposed on the connection boundary of the trap region and the drift region.

[0011] In one embodiment, the upper surface of the trap region is further provided with a P-body region, which is isolated from the source region on the upper surface of the trap region by a shallow groove.

[0012] In one embodiment, the thickness of the gate oxide isolation region increases sequentially with the depth of the polysilicon region into the substrate.

[0013] In one embodiment, the polycrystalline silicon region is an inverted trapezoidal groove, exhibiting a structural shape that is wider at the top and narrower at the bottom.

[0014] In one embodiment, the polysilicon region is a stepped trench with decreasing width from top to bottom.

[0015] In one embodiment, the polysilicon region is made of polysilicon; the gate oxide region is made of silicon dioxide.

[0016] In one embodiment, the substrate of the LDMOS is a P-type substrate.

[0017] According to a second aspect, one embodiment provides an LDMOS device comprising a plurality of MOS units, wherein at least one MOS unit is an LDMOS as described in the first aspect.

[0018] According to the LDMOS of the above embodiment, since a longitudinal trench is introduced between the trap region and the drift region, and an electric field reduction structure region is set between the trench gate and the drain region, the trench gate of the LDMOS can perform three-dimensional control of the drift region potential and the depletion layer shape in the off state, transfer the equipotential line from the device surface to the bulk, disperse the local electric field peak on the surface and optimize the electric field distribution in the drift region, thereby suppressing premature surface breakdown and improving the breakdown voltage margin. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a cross-sectional structure of an LDMOS.

[0020] Figure 2 This is a schematic diagram of the electric field line distribution of a planar LDMOS.

[0021] Figure 3 This is a schematic cross-sectional view of an LDMOS based on a 90nm BCD process in one embodiment.

[0022] Figure 4 This is a schematic cross-sectional view of an LDMOS structure in one embodiment;

[0023] Figure 5 This is a schematic cross-sectional view of an LDMOS with a trapezoidal gate trench in one embodiment;

[0024] Figure 6 This is a schematic cross-sectional view of an LDMOS with a stepped gate trench in one embodiment.

[0025] Figure 7 This is a schematic diagram of LDMOS doping in one embodiment;

[0026] Figure 8 A schematic diagram comparing the breakdown voltage curves of trench gate LDMOS and planar gate LDMOS in one embodiment;

[0027] Figure 9 A schematic diagram comparing the breakdown voltage curves of a trench gate LDMOS and an LDMOS with an added electric field to reduce the structural region in one embodiment. Detailed Implementation

[0028] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0029] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0030] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0031] Please refer to Figure 1This is a schematic diagram of a cross-sectional structure of an LDMOS. Planar LDMOS typically uses a gate-N-type drift region (N-drift) for lateral voltage withstand to achieve high-voltage turn-off support. The P-body region of the LDMOS is usually short-circuited to the source. Its core functions are to form a conductive channel, form a main withstand voltage PN junction with the N-drift, and suppress parasitic BJT effects and prevent latch-up by shorting to the source. Shallow Trench Isolation (STI) serves to provide electrical isolation (isolate adjacent devices to prevent leakage) and surface electric field modulation (located on the surface of the drift region between the gate and drain, its edges help disperse the electric field and optimize the breakdown voltage). The source, as the current input terminal of the LDMOS (for N-LDMOS), has a key structural feature where the internal N+ region (providing charge carriers) and the P+ contact region (connecting the body) are shorted in the metal layer, forming a "source-body short." Polysilicon serves as the gate electrode in LDMOS (located above the gate oxide, where a voltage is applied to control the opening and closing of the channel below) and extends as a field plate (often extending to cover part of the drift region, becoming a "gate field plate" to smooth the surface electric field). Silicon nitride (Si3N4), as a dielectric material, is used in the process for etching hard masks / stop layers (due to its higher etching selectivity compared to silicon dioxide), passivation protection layers, and stress layers (to improve CMOS performance). In LDMOS, it is usually part of the process, not the active region of the device. The drain is the current output / high voltage withstand terminal of the LDMOS, located at the end of the N-drift region, led out through a metal contact, and withstands a high voltage when the LDMOS is turned off. The P-well region and the body region are usually the same area. From a manufacturing perspective, "P-well" emphasizes that it is a P-type doped region formed by ion implantation, used to form the body region of the MOSFET and the necessary PN junction. The N-type drift region is the core area for achieving high-voltage capability in LDMOS. Its functions are voltage withstand (lightly doped, it can be fully depleted to withstand high voltage during turn-off) and conductivity (providing a path for current from the channel to the drain during turn-on). Its length and doping distribution are key considerations in the trade-off design of breakdown voltage (BV) and specific on-resistance (Ron, sp). The P-type substrate (P-sub) is the mechanical base and common electrical ground of the chip. Its functions are to support all devices, provide electrical isolation (forming a PN junction with the N-type region above), and be connected to the lowest potential (e.g., grounding, providing a path for parasitic currents).

[0032] LDMOS has two operating states: off and on. Specifically, it includes:

[0033] Off-state (withstand voltage): When the gate voltage (Vg) is 0 and a high voltage (Vd) is applied to the drain, the voltage drops mainly in two regions: the reverse-biased PN junction formed by the P-well / N-drift and the fully depleted N-drift region itself. The P-sub, through its connection with the PN junction at the bottom of the N-drift region, prevents the voltage from penetrating the entire substrate. The surface electric field is most likely to concentrate at the edges of the Poly gate and the STI, thus requiring techniques such as field plates (Poly extension) and RESURF doping for optimization.

[0034] On-state (conductivity): When the gate voltage (Vg) exceeds the threshold voltage, an N-type inversion layer channel forms on the surface of the Body region beneath the Poly gate. Electrons originate from the N+ region at the Source end, pass through the channel into the N-drift region, and finally reach the N+ region at the Drain end. The resistance of the N-drift region is the main factor determining the overall on-resistance of the device; therefore, it is necessary to minimize its resistance as much as possible while ensuring the withstand voltage.

[0035] Please refer to Figure 2 The diagram shows the electric field distribution of a planar LDMOS. Due to various geometric and dielectric abrupt changes on the device surface (such as gate edge, field oxygen / isolation boundary, curvature change of P-well / N-drift junction at the surface), the potential lines are more likely to accumulate on the surface in the off state (purple area), resulting in the surface electric field peak being significantly higher than the bulk electric field, making the device prone to breakdown at the surface.

[0036] Please refer to Figure 3 This is a schematic cross-sectional view of an LDMOS based on a 90nm BCD process in one embodiment. In order to improve the breakdown voltage of the LDMOS surface, a trench gate 10 that extends deep into the substrate can be set between the P-type well region and the N-type drift region (isolated by the gate oxide region 11). This allows the trench gate of the LDMOS to perform three-dimensional control of the drift region potential and the depletion layer shape in the off state, transferring the equipotential lines from the device surface to the bulk, dispersing the local electric field peaks on the surface and optimizing the electric field distribution in the drift region, thereby improving the breakdown voltage of the LDMOS.

[0037] In this embodiment, in order to further improve the breakdown voltage margin of LDMOS based on 90nm BCD process, a voltage reduction structure region with the same substrate doping type is added in the N-type drift region between the trench gate and drain region to deepen the voltage equipotential line extending into the device, thereby improving the breakdown voltage margin of LDMOS.

[0038] Please refer to Figure 4This is a schematic cross-sectional view of an LDMOS in one embodiment. The gate of the LDMOS includes a gate oxide region 11 and a polysilicon region 12. The polysilicon region 12 extends into the substrate between the P-type well region 20 and the N-type drift region 30, and is isolated from the P-type well region 20 and the N-type drift region 30 to form a trench gate. The polysilicon region 12 extends into the substrate of the LDMOS to a greater depth than the source region 21 and the drain region 31 extend into the substrate of the LDMOS. The gate connection terminal of the LDMOS is disposed on the polysilicon region 12. The drain of the LDMOS is disposed on the drain region of the N-type drift region 30, and the source of the LDMOS is disposed on the source-drain region of the P-type well region 20. An electric field reduction structure region 41 is disposed in the N-type drift region 30 between the drain region 31 and the gate. This electric field reduction structure region 41 is a doped region of the same type as the substrate doping, formed from the surface of the N-type drift region 30 towards the substrate by ion implantation. The electric field reduction structure region 41 serves as a resurf structure, aiming to utilize the vertical electric field generated by the depletion of the pn junction to modulate the lateral electric field accumulated on the surface. The optimal resurf structure should satisfy the resurf charge balance formula, and the overall charge should satisfy Q. N =Q P The relationship between the charge and drift region of the P-top layer satisfies:

[0039] Q top =0.5×Q drift ;

[0040] Among them, Q top It is the charge of the P-top layer, Q drift It is the charge in the N-type drift region.

[0041] In one embodiment, the electric field reduction structure region 41 is bonded to the gate oxide region 11. In another embodiment, the electric field reduction structure region 41 extends into the LDMOS substrate to a depth less than the polysilicon region 12 extends into the LDMOS substrate. In yet another embodiment, the electric field reduction structure region 41 extends into the LDMOS substrate to a depth less than the N-type drift region 30 extends into the LDMOS substrate.

[0042] In one embodiment, the P-type well region 20 and the N-type drift region 30 extend from the upper surface of the LDMOS towards the substrate of the LDMOS. The source region 21 of the LDMOS is disposed on the upper surface of the P-type well region 20, and the drain region 31 of the LDMOS is disposed on the upper surface of the N-type drift region 30. The extension depth of the P-type well region 20 and the N-type drift region 30 towards the LDMOS substrate is less than the extension depth of the polysilicon region 12 towards the LDMOS substrate. In one embodiment, the gate of the LDMOS is disposed on the connection boundary between the P-type well region and the N-type drift region. In one embodiment, the extension depth of the P-type well region 20 towards the substrate of the LDMOS is less than the extension depth of the N-type drift region 30 towards the substrate of the LDMOS.

[0043] In one embodiment, a P-body region 22 is further provided on the upper surface of the P-type well region 20, and is isolated from the source region 21 on the upper surface of the P-type well region 20 by a shallow trench isolation 23.

[0044] In one embodiment of this application, an LDMOS device is also disclosed, comprising a plurality of MOS units, wherein at least one MOS unit is an LDMOS as described above.

[0045] Please refer to Figure 5 The image shows a cross-sectional view of an LDMOS with a trapezoidal gate in one embodiment. In one embodiment, the LDMOS has an inverted trapezoidal gate, exhibiting a structure that is wider at the top and narrower at the bottom.

[0046] Please refer to Figure 6 This is a schematic cross-sectional view of a stepped gate trench LDMOS in one embodiment. In one embodiment, the trench gate of the LDMOS is a stepped trench with decreasing width from top to bottom. In another embodiment, the thickness of the isolation polysilicon region of the gate oxide region 11 increases with the depth of penetration into the substrate.

[0047] Please refer to Figure 7 The diagram below illustrates the doping of an LDMOS in one embodiment. In one embodiment, the polysilicon region 12 is made of polysilicon, and the gate oxide region 11 is made of silicon dioxide. In another embodiment, the substrate of the LDMOS is a P-type substrate.

[0048] In this embodiment of the LDMOS, the gate extends vertically into the substrate, allowing for three-dimensional control of the drift region potential and depletion layer shape during the off-state. This transfers equipotential lines from the device surface to the bulk, dispersing local electric field peaks on the surface and optimizing the electric field distribution in the drift region, thereby suppressing premature surface breakdown and improving the breakdown voltage margin. In one embodiment, a thinner gate oxide region 11 in the upper half of the trench facilitates channel formation and reduces the device's on-resistance. A thicker gate oxide region in the lower half of the trench facilitates the redistribution of electric field lines at the gate corners, increasing the breakdown voltage in that area. Furthermore, a thicker gate oxide region 11 helps reduce the device's Miller capacitance and improves the cutoff frequency at high frequencies.

[0049] Please refer to Figure 8 and Figure 9 These are schematic diagrams comparing the breakdown voltage curves of trench-gate LDMOS and planar-gate LDMOS in one embodiment, and comparing the breakdown voltage curves of trench-gate LDMOS and LDMOS with an added electric field reduction structure region, respectively. The horizontal axis represents the voltage value, and the vertical axis represents the current value. The yellow curve represents... Figure 1 The breakdown voltage curve of the planar gate LDMOS is shown. Figure 8 The purple curve in the image is as follows: Figure 3 The breakdown voltage curve of the trench gate LDMOS is shown. Figure 9 The purple curve in the image is as follows: Figure 4 The diagram shows the breakdown voltage curve of the LDMOS in the structural region when an electric field is added to reduce the voltage.

[0050] The LDMOS disclosed in the embodiments of this application (such as...) Figure 3 and Figure 4 (as shown) and as Figure 1 Compared to conventional planar gate LDMOS, the three-dimensional electric field shaping introduced by the trench gate significantly reduces the peak electric field at the device surface, suppresses electric field concentration at the gate and junction edges, and shifts the breakdown point from the device surface to the device bulk, thereby improving the breakdown voltage and breakdown consistency. Simultaneously, under the same breakdown target, it reduces the dependence on "lengthening / excessive dedoping" of the drift region, reduces the drift region resistance growth, improves the BV–Ron,sp tradeoff, and reduces conduction losses.

[0051] The LDMOS structure disclosed in this application embodiment can be used as a high-voltage switch integrated in BCD technology, and its core design lies in:

[0052] 1. Vertical isolation is achieved using P-sub / N-drift junctions;

[0053] 2. Laterally, the voltage is absorbed by the P-well / N-drift junction and the N-drift region itself;

[0054] 3. The surface uses a poly gate, STI, and special doping design (such as RESURF) to manage the electric field and prevent premature breakdown.

[0055] 4. During integration, all structures share process steps with low-voltage CMOS and BJT devices, achieving "intelligent power" integration on a single chip.

[0056] The LDMOS based on 90nm BCD process disclosed in this application includes a trench gate, a substrate, and a trap region and a drift region disposed in the substrate. A source region is disposed on the trap region, and a drain region is disposed on the drift region. The trench gate includes a polysilicon region extending into the substrate between the trap region and the drift region, and a gate oxide region for isolating the polysilicon region. An electric field reduction structure region is disposed within the drift region between the drain region and the trench gate. This electric field reduction structure region is a doped region of the same type as the substrate doped, formed from the surface of the drift region towards the substrate using ion implantation. Because an electric field reduction structure region is disposed between the trench gate and the drain region, the trench gate of the LDMOS can three-dimensionally control the potential of the drift region and the shape of the depletion layer in the off state, transferring equipotential lines from the device surface to the bulk, dispersing local electric field peaks on the surface, and optimizing the electric field distribution in the drift region, thereby suppressing premature surface breakdown and improving the breakdown voltage margin.

[0057] The above examples illustrate this application only to aid understanding and are not intended to limit its scope. Those skilled in the art to which this application pertains can make various simple deductions, modifications, or substitutions based on the ideas presented.

Claims

1. An LDMOS based on 90nm BCD process, characterized in that, It includes a trench gate, a substrate, and a trap region and a drift region disposed in the substrate; the source region of the LDMOS is disposed in the trap region, and the drain region of the LDMOS is disposed in the drift region; The trench gate includes a gate oxide region and a polysilicon region. The polysilicon region extends into the substrate between the trap region and the drift region and is isolated from the trap region and the drift region through the polysilicon region to form the trench gate of the LDMOS. The gate connection terminal of the LDMOS is disposed on the polysilicon region, the drain of the LDMOS is disposed on the drain region, and the source of the LDMOS is disposed on the source region. The polysilicon region extends into the substrate to a greater depth than the source region and the drain region extend into the substrate. An electric field reduction structure region is provided in the drift region between the drain region and the trench gate. The electric field reduction structure region is a doped region with the same doping type as the substrate, formed from the surface of the drift region toward the substrate by ion implantation. The electric field reduction structure region is attached to the gate oxide region; the electric field reduction structure region extends into the substrate to a depth less than the polysilicon region extends into the substrate; the electric field reduction structure region extends into the substrate to a depth less than the drift region extends into the substrate.

2. The LDMOS as described in claim 1, characterized in that, The trap region and the drift region extend from the upper surface of the LDMOS toward the substrate. The source region is disposed on the upper surface of the trap region, and the drain region is disposed on the upper surface of the drift region. The extension depth of the trap region and the drift region toward the substrate is less than the extension depth of the polysilicon region toward the substrate. The trench gate is disposed on the connection boundary between the trap region and the drift region.

3. The LDMOS as described in claim 2, characterized in that, The upper surface of the trap region is also provided with a P-body region, which is isolated from the source region on the upper surface of the trap region by a shallow groove.

4. The LDMOS as described in claim 2, characterized in that, The thickness of the gate oxide isolation region increases sequentially with the depth of the polysilicon region into the substrate.

5. The LDMOS as described in claim 1, characterized in that, The polycrystalline silicon region is an inverted trapezoidal groove, exhibiting a structure that is wider at the top and narrower at the bottom.

6. The LDMOS as described in claim 1, characterized in that, The polycrystalline silicon region is a stepped trench with decreasing width from top to bottom.

7. The LDMOS as described in claim 1, characterized in that, The polycrystalline silicon region is made of polycrystalline silicon; the gate oxide region is made of silicon dioxide.

8. The LDMOS as described in claim 1, characterized in that, The substrate of LDMOS is a P-type substrate.

9. An LDMOS device, characterized in that, It includes multiple MOS units, wherein at least one MOS unit is an LDMOS as described in any one of claims 1 to 8.

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