A lateral diffused metal oxide semiconductor device and a method of fabricating the same

Abstract

The application provides a lateral diffusion metal oxide semiconductor device and a preparation method thereof. The lateral diffusion metal oxide semiconductor device comprises a substrate, a first drift region and a channel region arranged in the substrate, a source region and a body region arranged in the channel region, a drain region and a second drift region arranged in the first drift region, the first drift region and the second drift region having the same doping type but different doping concentrations, the second drift region being provided with a surface electric field reduction sub-region, the surface electric field reduction sub-region having a doping type opposite to that of the second drift region, a field plate arranged on and covering the second drift region, and a gate electrode arranged between the source region and the drain region and covering part of the field plate.

Description

Technical Field

[0001] This application relates to the field of semiconductor fabrication technology, and in particular to a laterally diffused metal-oxide semiconductor device and its fabrication method. Background Technology

[0002] BCD technology refers to fabricating bipolar transistors (BJTs), complementary metal-oxide-semiconductor (CMOS) semiconductors, and double-diffused metal-oxide-semiconductor (DMOS) semiconductors on the same chip. It combines the high transconductance and strong load drive capability of BJTs with the high integration density and low power consumption of CMOS, leveraging the strengths of each device. Because laterally diffused metal-oxide-semiconductor (LDMOS) is more compatible with CMOS processes, it is often used in high-voltage power integrated circuits. Furthermore, since the drain, source, and gate of LDMOS are all on the chip surface, it is easily integrated with low-voltage signals through internal interconnections. Therefore, LDMOS is often compatible with CMOS to meet requirements such as high voltage resistance and power control.

[0003] In existing technologies, the field plates for laterally diffused metal-oxide-semiconductor (MOS) semiconductors can be fabricated using shallow trench isolation (STI), local oxidation of silicon (LOCOS), or high-temperature oxide (HTO) field plates. Regardless of the field plate chosen, the device's breakdown voltage (BV) and specific on-resistance must be considered. Increasing the breakdown voltage leads to an increase in specific on-resistance, affecting device performance. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide at least one laterally diffused metal oxide semiconductor device and its fabrication method, which solves the technical problem in the prior art where the breakdown voltage and specific on-resistance both increase and affect the device performance, thereby achieving the technical effect of improving the breakdown voltage and reducing the specific on-resistance.

[0005] This application mainly includes the following aspects: In a first aspect, embodiments of this application provide a laterally diffused metal-oxide-semiconductor device, comprising: a substrate; a first drift region and a channel region disposed in the substrate, wherein a source region and a body region are disposed in the channel region, a drain region and a second drift region are disposed in the first drift region, the first drift region and the second drift region having the same doping type but different doping concentrations, the second drift region having a surface electric field reduction sub-region having the opposite doping type to the second drift region; a field plate disposed above the second drift region and covering the second drift region; and a gate disposed between the source region and the drain region and covering a portion of the field plate.

[0006] Optionally, the laterally diffused metal-oxide-semiconductor device further includes a dielectric layer located between the field plate and the second drift region.

[0007] Optionally, the gate covers a portion of the field plate near the channel region, the source region is located between the body region and the first drift region, and the drain region is located in the first drift region in the direction away from the channel region in the second drift region.

[0008] Secondly, embodiments of this application also provide a method for fabricating a semiconductor device. This method is used to fabricate a laterally diffused metal-oxide-semiconductor device. The method includes: fabricating a channel region and a first drift region on a substrate; fabricating a second drift region and a reduced surface electric field sub-region within the first drift region using a field mask according to a preset fabrication process, wherein the field mask refers to the mask used to fabricate the field mask; fabricating a field mask covering the second drift region on top of the second drift region using the field mask; depositing and forming a gate on the surface of the semiconductor device between the source region and the drain region, wherein the gate covers a portion of the field mask; fabricating the source region and the body region within the channel region using an ion implantation process; and fabricating the drain region within the first drift region using an ion implantation process.

[0009] Optionally, the preset fabrication process includes a deposition process to fabricate the second drift region and the reduced surface electric field sub-region within the first drift region in the following manner: etching an initial groove in the first drift region using the field plate photomask, wherein the depth of the initial groove in the direction perpendicular to the substrate is not greater than the depth of the first drift region; depositing a first epitaxial layer material with the same doping type but different doping concentration as the first drift region within the initial groove to fabricate the second drift region, and depositing a second epitaxial layer material with the opposite doping type to the second drift region to fabricate the reduced surface electric field sub-region.

[0010] Optionally, the preset fabrication process includes an ion implantation process to fabricate the second drift region and the reduced surface electric field sub-region within the first drift region in the following manner: a barrier layer is fabricated on the device surface using the field plate photomask, such that the barrier layer exposes only a preset area of ​​the surface of the first drift region, the preset area referring to the mapping area where the surface of the first drift region is projected by the second drift region; ion implantation is performed on the first drift region to fabricate a second drift region with the same doping type but a different doping concentration as the first drift region; ion implantation is performed on the second drift region to fabricate the reduced surface electric field sub-region with the opposite doping type to the second drift region.

[0011] Optionally, the method further includes: preparing a dielectric layer on the second drift region such that the dielectric layer is located between the field plate and the second drift region.

[0012] Optionally, the field plate includes a high-temperature oxide field plate, a silicon localized oxide field plate, or a shallow trench isolation field plate.

[0013] Optionally, after the channel region and the first drift region are formed on the substrate, or after the field plate covering the second drift region is formed on the second drift region according to the field plate photomask, the method further includes: forming an oxide layer on the device surface as a gate oxide layer.

[0014] Thirdly, embodiments of this application also provide a semiconductor device, the semiconductor device including the laterally diffused metal-oxide semiconductor device as described in the first aspect or any possible implementation of the first aspect.

[0015] This application provides a laterally diffused metal-oxide-semiconductor device and its fabrication method. The laterally diffused metal-oxide-semiconductor device includes: a substrate; a first drift region and a channel region disposed in the substrate, wherein a source region and a body region are disposed in the channel region, a drain region and a second drift region are disposed in the first drift region, the first drift region and the second drift region have the same doping type but different doping concentrations, the second drift region has a surface electric field reduction sub-region, the surface electric field reduction sub-region has the opposite doping type to the second drift region; a field plate disposed on the second drift region and covering the second drift region; and a gate disposed between the source region and the drain region and covering part of the field plate. This application solves the technical problem in the prior art where both breakdown voltage and specific on-resistance increase, affecting device performance. It designs a drain region and a second drift region within a first drift region of a laterally diffused metal-oxide-semiconductor device, and restricts the second drift region to have the same doping type but different concentration as the first drift region. A sub-region for reducing the surface electric field is set within the second drift region, with a different doping type than the first drift region. This reduces the drift region resistance by setting a non-uniform drift region concentration, and adjusts the electric field to increase the breakdown voltage by setting a sub-region for reducing the surface electric field with the opposite doping type to the drift region.

[0016] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This application provides a schematic diagram of the structure of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present application. Figure 1 .

[0019] Figure 2 This application provides a schematic diagram of the structure of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present application. Figure 2 .

[0020] Figure 3 This application provides a schematic diagram of the structure of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present application. Figure 3 .

[0021] Figure 4A flowchart of the semiconductor device fabrication method provided in the embodiments of this application is shown.

[0022] Figure 5 This application illustrates a flowchart of the fabrication process for laterally diffused metal-oxide-semiconductor devices provided in its embodiments. Figure 1 .

[0023] Figure 6 This application illustrates a flowchart of the fabrication process for laterally diffused metal-oxide-semiconductor devices provided in its embodiments. Figure 2 .

[0024] Figure 7 This illustration shows a schematic diagram of the electric field distribution of a laterally diffused metal-oxide-semiconductor device prepared according to the preparation method of this application, as provided in an embodiment of this application.

[0025] Figure 8 This illustration shows a schematic diagram of the electric field distribution of a laterally diffused metal-oxide-semiconductor device prepared according to the prior art, as provided in the embodiments of this application.

[0026] Figure 9 This illustration shows a schematic diagram of the doping distribution of a laterally diffused metal-oxide-semiconductor device prepared according to the preparation method of this application, as provided in an embodiment of this application.

[0027] Figure 10 This illustration shows a schematic diagram of the doping distribution of a laterally diffused metal-oxide-semiconductor device prepared according to the prior art, as provided in the embodiments of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0029] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0030] In existing technologies, fabricating shallow trench isolation field plates on laterally diffused metal-oxide semiconductors requires etching trenches of a certain width and depth onto the silicon surface of the device, filling them with oxide, and then fabricating the shallow trench isolation field plate. By altering the current path on the device surface, the electric field on the device surface is reduced, thereby achieving higher breakdown voltage. However, current concentration can occur at the corners of the trench structure, and reliability issues such as hot carrier injection (HCL) may arise. To avoid problems caused by the corners of the trench structure, a silicon local oxidation process can be used to fabricate a silicon local oxide field plate to modulate the electric field on the device surface.

[0031] However, no matter which type of field plate is used, the trade-off between breakdown voltage and specific on-resistance in laterally diffused metal-oxide-semiconductors cannot be resolved. Alternatively, increasing the breakdown voltage by increasing the thickness of the drift region will also increase the specific on-resistance; conversely, decreasing the specific on-resistance by reducing the thickness of the drift region will decrease the breakdown voltage.

[0032] Based on this, embodiments of this application provide a laterally diffused metal-oxide-semiconductor device and its fabrication method. By designing a drain region and a second drift region within a first drift region of the laterally diffused metal-oxide-semiconductor device, and restricting the second drift region to have the same doping type but different concentration as the first drift region, a sub-region for reducing the surface electric field is set within the second drift region. This sub-region has a different doping type than the first drift region, thereby reducing the drift region resistance by setting a non-uniform drift region concentration. Furthermore, by setting a sub-region for reducing the surface electric field with the opposite doping type to the drift region, the electric field is adjusted to improve the breakdown voltage. This solves the technical problem in the prior art where both breakdown voltage and specific on-resistance increase, affecting device performance, and achieves the technical effect of improving breakdown voltage and reducing specific on-resistance. Specifically: Please see Figure 1 , Figure 1 A schematic diagram of the structure of a laterally diffused metal-oxide-semiconductor device provided in this application embodiment. Figure 1 .like Figure 1As shown, the laterally diffused metal-oxide-semiconductor device provided in this application includes: a substrate 100; a first drift region 101 and a channel region 102 disposed in the substrate, wherein a source region 1021 and a body region 1022 are disposed in the channel region, a drain region 1011 and a second drift region 1012 are disposed in the first drift region 101, the first drift region and the second drift region have the same doping type but different doping concentrations, the second drift region has a surface electric field reduction sub-region 103, the surface electric field reduction sub-region has the opposite doping type to the second drift region; a field plate 104 disposed above and covering the second drift region; and a gate 105 disposed between the source region and the drain region and covering part of the field plate.

[0033] The gate covers the portion of the field plate near the channel region, the source region is located between the body region and the first drift region, and the drain region is located in the first drift region in the direction away from the channel region in the second drift region.

[0034] In this process, the channel region and the first drift region formed on the substrate have different doping types. The channel region forms a source region and a body region with different doping types. The channel region and the body region have the same doping type. The source region is used to form the source of the semiconductor device. The first drift region forms a drain region and a second drift region. The first drift region, the drain region and the second drift region have the same doping type. The first drift region and the second drift region have different doping concentrations. The drain region is used to form the drain of the semiconductor device.

[0035] In other words, if the laterally diffused metal-oxide-semiconductor device is a P-type laterally diffused metal-oxide-semiconductor device, then the doping type of the body region and the channel region is N-type doping, and the doping type of the source region, the first drift region, the drain region, and the second drift region is P-type doping; if the laterally diffused metal-oxide-semiconductor device is an N-type laterally diffused metal-oxide-semiconductor device, then the doping type of the body region and the channel region is P-type doping, and the doping type of the source region, the first drift region, the drain region, and the second drift region is N-type doping.

[0036] Specifically, by setting a second drift region with a different doping concentration within the first drift region, the doping concentration of the second drift region can be set to be greater than that of the first drift region. This increases the average doping concentration of the first drift region, which can reduce the resistance of the drift region and thus lower the specific on-resistance. A reduced surface field (RESURF) sub-region with the opposite doping type to the first drift region is set above the second drift region. This reduces the electric field distribution of the first drift region, thereby increasing the breakdown voltage.

[0037] like Figure 1As shown, the laterally diffused metal-oxide-semiconductor device further includes a dielectric layer 106, which is located between the field plate and the second drift region.

[0038] In other words, the dielectric layer is located on the surface of the second drift region within the first drift region, and a field plate is fabricated on top of the dielectric layer. The dielectric layer is typically made of oxide, and the field plate is typically made of silicon dioxide. Thus, by placing the dielectric layer between the surfaces of the field plate and the second drift region, the thickness of the insulating material is increased, thereby regulating the electric field on the surface of the drift region and further increasing the breakdown voltage of the drift region surface.

[0039] like Figure 1 As shown, the laterally diffused metal oxide semiconductor device is further provided with an oxide layer 107. The oxide layer is disposed on the surface of the laterally diffused metal oxide semiconductor device at a position other than the field plate, and plays a role in protecting the surface of the device. The oxide layer can also be understood as a gate oxide layer, which plays a role in electrical insulation and isolation by blocking the DC path between the gate and the semiconductor substrate, thereby ensuring the withstand voltage of the device.

[0040] Please see Figure 2 and Figure 3 , Figure 2 A schematic diagram of the structure of a laterally diffused metal-oxide-semiconductor device provided in this application embodiment. Figure 2 , Figure 3 A schematic diagram of another laterally diffused metal-oxide-semiconductor device provided in this application embodiment. Figure 3 , Figure 2 and Figure 3 Laterally diffused metal-oxide semiconductor device fabrication methods and Figure 1 Different. For example... Figure 2 and Figure 3 As shown, the laterally diffused metal-oxide-semiconductor device provided in this application includes: a substrate 200; a first drift region 201 and a channel region 202 disposed in the substrate, wherein a source region 2021 and a body region 2022 are disposed in the channel region, a drain region 2011 and a second drift region 2012 are disposed in the first drift region 201, the first drift region and the second drift region have the same doping type but different doping concentrations, the second drift region has a surface electric field reduction sub-region 203, the surface electric field reduction sub-region has the opposite doping type to the second drift region; a field plate 204 disposed above and covering the second drift region; and a gate 205 disposed between the source region and the drain region and covering part of the field plate.

[0041] like Figure 2As shown, the second drift region can contain multiple sub-regions that reduce the surface electric field, and these sub-regions are not connected within the second drift region. Furthermore, the surface of the second drift region may not have a dielectric layer, and the electric field distribution in the drift region can be adjusted by increasing the number of sub-regions that reduce the surface electric field, thereby improving the breakdown voltage. The doping concentrations of the multiple sub-regions that reduce the surface electric field in the second drift region can be different. Since breakdown in lateral devices generally occurs at the surface, the doping concentration of the sub-regions that reduce the surface electric field closer to the device surface can be set to be higher than that of the sub-regions that reduce the surface electric field farther from the device surface.

[0042] like Figure 3 As shown, multiple sub-regions for reducing the surface electric field are formed within the second drift region, and a dielectric layer 206 is formed on the surface of the second drift region. This dielectric layer is positioned between the surface of the second drift region and the field plate, serving to adjust the surface electric field of the drift region and further increase the breakdown voltage of the drift region surface. The dielectric layer can also be generated by ion implantation, or it can be generated by etching and deposition after ion implantation to form the second drift region and the sub-regions for reducing the surface electric field. The specific implementation of the dielectric layer is not limited.

[0043] like Figure 2 and Figure 3 As shown, the laterally diffused metal oxide semiconductor device is further provided with an oxide layer 207. The oxide layer is disposed on the surface of the laterally diffused metal oxide semiconductor device at a position other than the field plate, and plays a role in protecting the surface of the device. Alternatively, it can be understood as a gate oxide layer, which plays a role in electrical insulation and isolation by blocking the DC path between the gate and the semiconductor substrate to ensure the withstand voltage of the device.

[0044] Since the field plate needs to cover the second drift region, a photomask used to fabricate the field plate can be used to fabricate the second drift region. The field plate for the laterally diffused metal-oxide-semiconductor device can be a high-temperature oxide field plate, a silicon local oxide field plate, or a shallow trench isolation field plate. Therefore, the photomask corresponding to the high-temperature oxide field plate, silicon local oxide field plate, or shallow trench isolation field plate can be selected to fabricate the second drift region. Because the photomask corresponding to the shallow trench isolation field plate may be shared with other processes, and the shallow trench isolation field plate may have corner issues, it is preferable to use the photomask corresponding to the high-temperature oxide field plate or the silicon local oxide field plate.

[0045] For example, Figure 1 The field plate for laterally diffused metal-oxide-semiconductor devices can be a high-temperature oxide field plate, a silicon localized oxide field plate, or a shallow trench isolation field plate. Furthermore, Figure 1The laterally diffused metal-oxide-semiconductor device shown is fabricated by etching an initial groove in the first drift region according to a photomask corresponding to a high-temperature oxide field plate or a silicon local oxide field plate. Then, a second drift region and a reduced surface electric field sub-region are deposited sequentially. Since the second drift region and the reduced surface electric field sub-region are fabricated in the groove of the first drift region by deposition, it is possible to control that the second drift region and the reduced surface electric field sub-region do not completely fill the initial groove etched in the first drift region. When fabricating the second drift region and the reduced surface electric field sub-region, it is controlled not to fill the initial groove completely. Thus, the surface of the reduced surface electric field sub-region has a surface groove compared with the horizontal plane where the device surface is located. At this time, oxide can be deposited again to fill the surface groove to fabricate a dielectric layer, or the dielectric layer can be omitted and the surface groove can be directly filled when fabricating the field plate. Alternatively, the initial trench can be etched using the photomask corresponding to the shallow trench isolation field plate. Since the shallow trench isolation process used to fabricate the shallow trench isolation field plate requires etching first, the etching will form surface trenches on the surface of the reduced surface electric field sub-region. Oxide can then be deposited in these surface trenches to form a dielectric layer, or the field plate can be directly fabricated to fill the surface trenches. Therefore, if the shallow trench isolation field plate is fabricated on a laterally diffused metal-oxide-semiconductor device, the deposition process after etching the initial trench, whether the second drift region and the reduced surface electric field sub-region fill the initial trench or not, does not affect the fabrication of the dielectric layer.

[0046] Figure 2 For lateral diffusion metal-oxide semiconductor devices, the field plate can be a high-temperature oxide field plate or a silicon localized oxide field plate. Figure 2 The laterally diffused metal-oxide-semiconductor device shown employs ion implantation to fabricate the second drift region and the reduced surface electric field sub-region. This means that etching followed by deposition is unnecessary for fabricating these regions. Consequently, surface grooves do not form on the surface of the second drift region due to deposition, and there is no need to fill these grooves, thus eliminating the need for a dielectric layer. Furthermore, since no etching step is involved in the subsequent fabrication of the high-temperature oxide field plate or the silicon localized oxide field plate, grooves will not appear on the surface of the reduced surface electric field sub-region during field plate fabrication, eliminating the need for a dielectric layer.

[0047] like Figure 3The laterally diffused metal-oxide-semiconductor (LMDS) device shown can have a dielectric layer fabricated on the surface of the reduced surface electric field sub-region. In this case, the second drift region and the reduced surface electric field sub-region are still formed by ion implantation. When a shallow trench isolation field plate is selected, since the fabrication of the trench isolation field plate requires etching first, surface grooves are etched on the surface of the second drift region during the fabrication of the trench isolation field plate. The dielectric layer is then fabricated by depositing oxide onto these surface grooves, and the trench isolation field plate is fabricated after the dielectric layer is formed. Alternatively, a high-temperature oxide field plate or a silicon localized oxide field plate can be selected as the field plate. After the second drift region and the reduced surface electric field sub-region are formed by ion implantation, the device surface can be etched according to the high-temperature oxide field plate or silicon localized oxide field plate method to etch surface grooves on the surface of the second drift region, and the dielectric layer is fabricated by deposition.

[0048] In other words, when using deposition processes to fabricate the second drift region and the reduced surface electric field sub-region, the field plate for the laterally diffused metal-oxide-semiconductor (MMS) device can be any one of a high-temperature oxide field plate, a silicon local oxide field plate, or a shallow trench isolation field plate. Furthermore, regardless of the field plate chosen, a dielectric layer can be fabricated or not; the only consideration is whether a dielectric layer is needed to adjust the surface electric field. However, when using ion implantation processes to fabricate the second drift region and the reduced surface electric field sub-region, if a high-temperature oxide field plate or a silicon local oxide field plate is chosen for the laterally diffused MMOS device, a dielectric layer is generally not fabricated since there are no surface grooves. If a shallow trench isolation field plate is chosen, since fabricating the shallow trench isolation field plate requires etching, a dielectric layer can be fabricated to fill the surface grooves formed by etching, or the trench isolation field plate can be deposited directly without a dielectric layer; the only consideration is whether a dielectric layer is needed to adjust the surface electric field.

[0049] For example, regardless of the method chosen to fabricate the second drift region and the reduced surface electric field sub-region, and regardless of the type of field plate selected, there are no restrictions on the location and number of the reduced surface electric field sub-regions within the second drift region. Placing the reduced surface electric field sub-region on the surface of the second drift region can better increase the breakdown voltage of the device surface, while placing it inside the second drift region can better increase the breakdown voltage inside the device. In other words, it is only necessary to limit the presence of at least one reduced surface electric field sub-region within the second drift region; there are no restrictions on the specific location of the reduced surface electric field sub-region within the second drift region, nor on the number of reduced surface electric field sub-regions.

[0050] Based on the same application concept, this application also provides a semiconductor device fabrication method corresponding to the laterally diffused metal oxide semiconductor device provided in the above embodiments. Since the principle of the semiconductor device fabrication method in this application is similar to that of the laterally diffused metal oxide semiconductor device in the above embodiments of this application, the implementation of the semiconductor device fabrication method can refer to the implementation of the laterally diffused metal oxide semiconductor device, and the repeated parts will not be described again.

[0051] Please see Figure 4 , Figure 4 This is a flowchart illustrating a semiconductor device fabrication method provided in an embodiment of this application. The semiconductor device fabrication method is used to fabricate laterally diffused metal-oxide-semiconductor devices, such as... Figure 4 As shown, the semiconductor device fabrication method includes: S101: The channel region and the first drift region are formed on the substrate.

[0052] For example, the substrate can be a P-type doped substrate, and the channel region and the first drift region are prepared on the P-type doped substrate by ion implantation. The doping types of the channel region and the first drift region are different. The preparation method of the channel region and the first drift region can be any method used to prepare the channel region and the first drift region of the laterally diffused metal oxide semiconductor device. This application does not impose any restrictions.

[0053] S102: The second drift region and the reduced surface electric field sub-region are prepared in the first drift region by using a field plate photomask according to a preset preparation process.

[0054] Here, the field plate photomask refers to the photomask used to fabricate the field plate. That is, in subsequent steps, the field plate photomask is needed to fabricate the field plate covering the second drift region. After the channel region and the first drift region are fabricated, the field plate photomask is first used to fabricate the second drift region and the reduced surface electric field sub-region within the first drift region according to a preset fabrication process. Therefore, the field plate photomask is not only used to fabricate the field plate, but also participates in the fabrication of the second drift region and the reduced surface electric field sub-region.

[0055] The field plate includes a high-temperature oxide field plate, a silicon local oxide field plate, or a shallow trench isolation field plate. That is, the field plate of the laterally diffused metal oxide semiconductor device can be a high-temperature oxide field plate, a silicon local oxide field plate, or a shallow trench isolation field plate. If a high-temperature oxide field plate is selected, the field plate photomask corresponding to the high-temperature oxide field plate is used to prepare the second drift region and the reduced surface electric field sub-region. If a silicon local oxide field plate is selected, the field plate photomask corresponding to the silicon local oxide field plate is selected to prepare the second drift region and the reduced surface electric field sub-region. If a shallow trench isolation field plate is selected, the field plate photomask corresponding to the shallow trench isolation field plate is selected to prepare the second drift region and the reduced surface electric field sub-region.

[0056] The preset fabrication process includes either deposition or ion implantation. Specifically, if deposition is chosen to fabricate the second drift region and the reduced surface electric field sub-region, a field mask is used to etch initial grooves within the first drift region, thereby fabricating the second drift region and the reduced surface electric field sub-region within the initial grooves via deposition. If ion implantation is chosen to fabricate the second drift region and the reduced surface electric field sub-region, a field mask is used to generate a barrier layer on the device surface that exposes only the surface of the second drift region. This layer is then used to perform ion implantation on the portion of the first drift region corresponding to the second drift region to fabricate the second drift region, and ion implantation is also performed on the portion of the second drift region corresponding to the reduced surface electric field sub-region to fabricate the reduced surface electric field sub-region.

[0057] The preset fabrication process includes a deposition process, which prepares the second drift region and the reduced surface electric field sub-region within the first drift region in the following manner: an initial groove is etched in the first drift region using the field plate photomask, the depth of the initial groove in the direction perpendicular to the substrate being no greater than the depth of the first drift region; a first epitaxial layer material with the same doping type but different doping concentration as the first drift region is deposited in the initial groove to prepare the second drift region, and a second epitaxial layer material with the opposite doping type to the second drift region is deposited to prepare the reduced surface electric field sub-region.

[0058] In other words, since the field plate photomask is used to prepare the field plate covering the surface of the second drift region, the mapping area of ​​the initial groove etched by the field plate photomask on the surface of the first drift region is adapted to the mapping area of ​​the field plate, and this application does not limit the etching process. Furthermore, after etching the initial groove, a first epitaxial layer material can be deposited first to prepare the second drift region, and then a second epitaxial layer material can be deposited to prepare a sub-region with reduced surface electric field, so that the sub-region with reduced surface electric field is located above the second drift region, thereby increasing the breakdown voltage of the device surface; or, after etching the initial groove, a first epitaxial layer material can be deposited first to prepare a portion of the second drift region, then a second epitaxial layer material can be deposited to prepare a sub-region with reduced surface electric field, and finally a first epitaxial layer material can be deposited to prepare another portion of the second drift region, so that the sub-region with reduced surface electric field is located inside the second drift region, thereby increasing the breakdown voltage inside the device; or, after etching the initial groove, the first epitaxial layer material and the second epitaxial layer material can be alternately deposited in the initial groove, thereby setting multiple sub-regions with reduced surface electric field in the prepared second drift region, thereby increasing the breakdown voltage of the device.

[0059] The method further includes depositing a dielectric layer on the second drift region, such that the dielectric layer is located between the field plate and the second drift region.

[0060] In other words, after depositing the second drift region and the reduced surface electric field sub-region through a deposition process, an oxide material is deposited on the surface of the entire second drift region to prepare a dielectric layer, so that the dielectric layer is placed between the second drift region and the field plate subsequently prepared, thereby increasing the breakdown voltage of the device.

[0061] Specifically, the preset fabrication process includes an ion implantation process, which prepares the second drift region and the reduced surface electric field sub-region within the first drift region in the following manner: a barrier layer is prepared on the device surface using the field plate photomask, so that the barrier layer only exposes a preset area of ​​the surface of the first drift region, the preset area referring to the mapping area of ​​the second drift region projecting onto the surface of the first drift region; ion implantation is performed on the first drift region to prepare a second drift region with the same doping type but different doping concentration as the first drift region; ion implantation is performed on the second drift region to prepare the reduced surface electric field sub-region with the opposite doping type to the second drift region.

[0062] In other words, when selecting ion implantation to prepare the second drift region and the reduced surface electric field sub-region, a barrier layer is prepared on the device surface using a field mask. The barrier layer can be directly made of photoresist, i.e., photoresist is coated on the device surface and then exposed using a field mask, retaining only the photoresist in areas other than the second drift region. This exposes the mapping area on the surface of the first drift region that projects onto the second drift region. Ion implantation is then performed on the mapping area to create a second drift region with the same doping type but different doping concentration within the first drift region. The barrier layer is set to prevent the ion implantation process from implanting doped ions into areas other than the second drift region. After the second drift region is prepared, ion implantation is performed again in the second drift region to create a reduced surface electric field sub-region with the opposite doping type within the second drift region, thereby adjusting the electric field to increase the breakdown voltage.

[0063] For example, after the channel region and the first drift region are formed on the substrate, or after the field plate covering the second drift region is formed on the second drift region according to the field plate photomask, the method further includes: forming an oxide layer on the device surface as a gate oxide layer.

[0064] In other words, when using a deposition process to prepare the second drift region and the reduced surface electric field sub-region, after preparing the channel region and the first drift region on the substrate and before using a field plate photomask to prepare the second drift region and the reduced surface electric field sub-region, an oxide layer can be deposited on the device surface. During the etching of the initial groove, the oxide layer at the mapping position of the second drift region on the surface of the first drift region can be etched away, leaving the oxide layer except for the mapping position of the second drift region; or, after preparing the field plate using a field plate photomask, an oxide layer can be deposited on the device surface, and the oxide layer is located on the other surfaces of the device except for the field plate and below the gate. When using ion implantation to fabricate the second drift region and the reduced surface electric field sub-region, an oxide layer can be deposited on the device surface first, followed by a barrier layer deposited on top of the oxide layer, excluding the mapping location of the second drift region. After the barrier layer is deposited, the oxide layer above the mapping location of the second drift region is cleaned off, leaving the oxide layer outside the mapping location of the second drift region. Alternatively, a field plate can be fabricated using a field plate photomask, and then an oxide layer can be deposited on the device surface, with the oxide layer located above the other surfaces of the device (excluding the field plate) and below the gate. Thus, the oxide layer protects the device surface, or can be understood as a gate oxide layer, providing electrical insulation by blocking the DC path between the gate and the semiconductor substrate to ensure the device's withstand voltage.

[0065] S103: The field plate covering the second drift region is prepared by applying the field plate photomask to the second drift region.

[0066] In other words, after fabricating the second drift region and the reduced surface electric field sub-region, a field plate covering the second drift region is fabricated on top of the second drift region using a field plate photomask and its corresponding processes. Furthermore, the high-temperature oxide field plate, the silicon local oxide field plate, and the shallow trench isolation field plate are fabricated using different processes, and only need to be fabricated according to existing methods; therefore, this application will not elaborate further.

[0067] S104: The gate is deposited on the surface of the semiconductor device between the source region and the drain region, and the gate covers a portion of the field plate.

[0068] In other words, the gate can be fabricated using the existing gate fabrication method used to fabricate laterally diffused metal-oxide-semiconductor devices. The gate needs to cover part of the field plate, specifically the portion of the field plate closest to the source region.

[0069] S105: The source region and the body region are prepared in the channel region by ion implantation, and the drain region is prepared in the first drift region by ion implantation.

[0070] In other words, the type of dopant ions used when implanting ions into the source, body, and drain regions is selected based on whether the laterally diffused metal-oxide-semiconductor device is a P-type or an N-type laterally diffused metal-oxide-semiconductor device.

[0071] Please see Figure 5 , Figure 5 This application provides a schematic flowchart for fabricating laterally diffused metal-oxide-semiconductor devices. Figure 1 . Figure 5 The preparation process shown is used to prepare Figure 1 The laterally diffused metal-oxide-semiconductor device shown is, for example Figure 5 As shown, a channel region 102 and a first drift region 101 are fabricated on a substrate 100. An oxide layer 107 is deposited on the device surface. An initial groove is etched in the first drift region using a field plate photomask. A second drift region 1012 with different doping concentrations but the same doping type is deposited in the initial groove using a deposition process. A sub-region 103 with opposite doping type is deposited on the surface of the second drift region. A surface groove is formed on the surface of the sub-region with reduced surface electric field. A dielectric layer 106 is deposited on the surface groove. A field plate 104 covering the second drift region is fabricated on the dielectric layer using a field plate photomask. A gate 105 covering part of the field plate is deposited on the surface of the semiconductor device. Finally, a source region 1021 and a body region 1022 are fabricated in the channel region and a drain region 1011 is fabricated in the first drift region using an ion implantation process.

[0072] Furthermore, an initial trench is etched using a field mask, and epitaxial layer materials with different doping concentrations are deposited within the initial trench to prepare a second drift region. An epitaxial layer material with opposite doping types is then deposited to prepare a sub-region for reducing the surface electric field, optimizing the doping distribution of the drift region. Finally, a dielectric layer and a field mask are deposited. Thus, a hierarchical structure is formed on the device surface, consisting of a gate oxide layer, the second drift region and the sub-region for reducing the surface electric field deposited within the trench, the dielectric layer, and the field mask. This allows for adjustment of the surface electric field, thereby reducing the device's on-resistance and increasing its breakdown voltage. Moreover, using a field mask to etch the initial trench eliminates the need for additional trenches to prepare the second drift region and the sub-region for reducing the surface electric field, avoiding additional costs.

[0073] Please see Figure 6 , Figure 6 This application provides a schematic flowchart for fabricating laterally diffused metal-oxide-semiconductor devices. Figure 2 . Figure 6 The preparation process shown is used to prepare Figure 2 The laterally diffused metal-oxide-semiconductor device shown is, for example Figure 6As shown, a channel region 202 and a first drift region 201 are fabricated on a substrate 200. An oxide layer 207 is deposited on the device surface. A barrier layer 208 is generated on the device surface using a field plate photomask, exposing only the surface of the second drift region. The oxide layer on the surface of the second drift region without a barrier layer is cleaned off. Then, an ion implantation process is used to implant ions into the portion corresponding to the second drift region in the first drift region to prepare a second drift region 2012 with the same doping type but different doping concentration. Ion implantation is also performed on the portion corresponding to the reduced surface electric field sub-region in the second drift region to prepare a reduced surface electric field sub-region 203 with the opposite doping type. After ion implantation, the barrier layer is removed. A field plate 204 covering the second drift region is fabricated on the second drift region using a field plate photomask. A gate 205 covering part of the field plate is deposited on the surface of the semiconductor device. Finally, a source region 2021 and a body region 2022 are gradually fabricated in the channel region and a drain region 2011 is fabricated in the first drift region using an ion implantation process.

[0074] Furthermore, a barrier layer is formed on the device surface using a field plate photomask, exposing the mapping region of the second drift region in the first drift region. The second drift region and multiple sub-regions for reducing the surface electric field are then fabricated in the first drift region using an ion implantation process. The doping distribution of the drift region is optimized by setting second drift regions with different doping concentrations, and the surface electric field is optimized by setting sub-regions for reducing the surface electric field with opposite doping types. This reduces the specific on-resistance of the device and increases the breakdown voltage of the device.

[0075] For example, when designing semiconductor process simulation and device simulation tool (Technology Computer Aided Design, TCAD) data with the same device size, a comparison was made between the prior art N-type laterally diffused metal-oxide semiconductor device and the N-type laterally diffused metal-oxide semiconductor device prepared according to the method of this application to obtain Table 1. Table 1 is a device parameter table of prior art N-type laterally diffused metal-oxide semiconductor device A and N-type laterally diffused metal-oxide semiconductor device B prepared according to the method of this application.

[0076] Table 1:

[0077] Clearly, as shown in Table 1, fabricating laterally diffused metal-oxide-semiconductor devices according to the method described in this application can improve the breakdown voltage and increase the figure of merit. An increased figure of merit means that, if the device is fabricated using existing techniques, while achieving the same improvement in breakdown voltage as the laterally diffused metal-oxide-semiconductor device described in this application, the fabrication method described in this application can reduce the increase in specific on-resistance. In other words, the figure of merit is used to measure the breakdown voltage and conduction loss of the device to evaluate its performance; a larger figure of merit indicates better device performance.

[0078] For example, please refer to Figure 7 and Figure 8 , Figure 7 This is a schematic diagram of the electric field distribution of a laterally diffused metal-oxide-semiconductor device prepared according to the preparation method of this application, provided as an embodiment of this application. Figure 8 This is a schematic diagram of the electric field distribution of a laterally diffused metal-oxide-semiconductor device fabricated according to the prior art, as provided in an embodiment of this application. Figure 7 and Figure 8 In this context, "source" represents the source electrode, "drain" represents the drain electrode, and "gate" represents the gate electrode. Figure 7 and Figure 8 The x and y axes represent different locations on the cross-section of a laterally diffused metal-oxide-semiconductor device. The legend in the lower left corner of the figure represents the electric field magnitude corresponding to each color, in volts per centimeter (V / cm). The order from top to bottom reflects the order of electric field from largest to smallest. Figure 7 and Figure 8 As shown, the laterally diffused metal oxide semiconductor device prepared according to the method of this application can better optimize the electric field distribution compared with existing laterally diffused metal oxide semiconductor devices.

[0079] For example, please refer to Figure 9 and Figure 10 , Figure 9 This is a schematic diagram illustrating the doping distribution of a laterally diffused metal-oxide-semiconductor device prepared according to the preparation method described in this application, provided as an embodiment of the present application. Figure 10 This is a schematic diagram of the doping distribution of a laterally diffused metal-oxide-semiconductor device prepared according to the prior art, as provided in the embodiments of this application. Figure 9 and Figure 10 The x and y axes represent the locations on the cross-section of a laterally diffused metal-oxide-semiconductor device. The legend in the lower left corner of the figure represents the net doping concentration corresponding to each color, expressed in units of atomic concentration of the doping type per cubic centimeter ( / cm³). 3The order from top to bottom represents the atomic concentration of N-type doping (n-type) from largest to smallest, and the atomic concentration of P-type doping (p-type) from smallest to largest. The numbers in the legend represent powers of 10. 20 (n-type) refers to the atomic concentration of N-type doping being 10 to the power of 20 per cubic centimeter. Green represents the highest atomic concentration of N-type doping, pink represents the highest atomic concentration of P-type doping, and a doping concentration of 0 represents a junction indicating that the doping concentration of both N-type and P-type doping is 0. For example... Figure 9 and Figure 10 As shown, the laterally diffused metal-oxide-semiconductor device prepared according to the method of this application can better optimize the dopant ion concentration in the drift region compared with existing laterally diffused metal-oxide-semiconductor devices, thereby improving the breakdown voltage of the device and avoiding a surge in specific on-resistance.

[0080] Based on the same concept, embodiments of this application also provide a semiconductor device, which includes a laterally diffused metal-oxide semiconductor device as described in any of the above embodiments.

[0081] For example, the semiconductor device can be a BCD device, or any semiconductor device that requires the fabrication of a laterally diffused metal-oxide-semiconductor device.

[0082] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and devices described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division; in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0083] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0084] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0085] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0086] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A lateral diffused metal oxide semiconductor device, characterized by, The laterally diffused metal-oxide-semiconductor device includes: Substrate; A first drift region and a channel region are formed in the substrate, wherein a source region and a body region are formed in the channel region, and a drain region and a second drift region are formed in the first drift region. The first drift region and the second drift region have the same doping type, and the doping concentration of the second drift region is greater than that of the first drift region. A surface electric field reduction sub-region is formed in the second drift region, and the doping type of the surface electric field reduction sub-region is opposite to that of the second drift region. A field plate is disposed above and covers the second drift area; A gate is disposed between the source region and the drain region and covers a portion of the field plate.

2. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The laterally diffused metal-oxide-semiconductor device further includes a dielectric layer located between the field plate and the second drift region.

3. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The gate covers the portion of the field plate near the channel region, the source region is located between the body region and the first drift region, and the drain region is located in the first drift region in the direction away from the channel region in the second drift region.

4. A method for fabricating a semiconductor device, characterized in that, The semiconductor device fabrication method is used to fabricate a laterally diffused metal-oxide semiconductor device, wherein the semiconductor device fabrication method includes: A channel region and a first drift region are fabricated on a substrate; A second drift region and a reduced surface electric field sub-region are fabricated within the first drift region using a field plate photomask according to a preset fabrication process. The field plate photomask refers to the photomask used to fabricate the field plate. The first drift region and the second drift region have the same doping type, the doping concentration of the second drift region is greater than the doping concentration of the first drift region, and the second drift region is provided with a reduced surface electric field sub-region, the doping type of which is opposite to that of the second drift region. The field plate covering the second drift region is prepared by applying the field plate photomask to the second drift region; A gate is deposited on the surface of the semiconductor device between the source and drain regions, and the gate covers a portion of the field plate; The source region and the body region are prepared in the channel region by ion implantation, and the drain region is prepared in the first drift region by ion implantation.

5. The method according to claim 4, characterized in that, The preset preparation process includes a deposition process, which prepares the second drift region and the reduced surface electric field sub-region within the first drift region in the following manner: An initial groove is etched in the first drift region using the field plate photomask, and the depth of the initial groove in the direction perpendicular to the substrate is not greater than the depth of the first drift region; The second drift region is prepared by depositing a first epitaxial layer material with the same doping type but different doping concentration as the first drift region in the initial groove, and the second epitaxial layer material with the opposite doping type to the second drift region is prepared by depositing a second epitaxial layer material to prepare the reduced surface electric field sub-region.

6. The method according to claim 4, characterized in that, The preset fabrication process includes an ion implantation process, which fabricates the second drift region and the reduced surface electric field sub-region within the first drift region in the following manner: A blocking layer is prepared on the surface of the device by means of the field plate photomask, so that the blocking layer only exposes a predetermined area of ​​the surface of the first drift region. The predetermined area refers to the mapping area in which the second drift region projects onto the surface of the first drift region. Ion implantation is performed on the first drift region to prepare a second drift region with the same doping type but different doping concentration as the first drift region; Ion implantation is performed on the second drift region to prepare the reduced surface electric field sub-region with a doping type opposite to that of the second drift region.

7. The method according to claim 5 or 6, characterized in that, The method further includes: A dielectric layer is formed on the second drift region such that the dielectric layer is located between the field plate and the second drift region.

8. The method according to any one of claims 4 to 6, characterized in that, The field plate includes a high-temperature oxide field plate, a silicon localized oxide field plate, or a shallow trench isolation field plate.

9. The method according to any one of claims 4 to 6, characterized in that, After the channel region and the first drift region are formed on the substrate, or after the field plate covering the second drift region is formed on the second drift region according to the field plate photomask, wherein the method further includes: forming an oxide layer on the device surface as a gate oxide layer.

10. A semiconductor device, characterized in that, The semiconductor device includes the laterally diffused metal-oxide semiconductor device as described in any one of claims 1 to 3.

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