Semiconductor device and method of manufacture, power module, power conversion circuit and vehicle

Abstract

The application discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and relates to the technical field of semiconductor devices. The semiconductor device comprises a voltage stabilizing structure and a device functional structure. The voltage stabilizing structure comprises a first region, a second region and a third region, and the first region, the second region and the third region form a Zener diode structure, effectively preventing device breakdown and improving device performance stability. The device functional structure comprises a well region and a source region arranged on a first surface. A gate electrode at least covers the well region. The gate electrode is arranged on a side of the gate electrode away from the first surface. At least part of the gate electrode is in contact with the first region and forms an ohmic contact at an interface. The source electrode comprises a first sub-source electrode. At least part of the first sub-source electrode is in contact with the second region and forms an ohmic contact at an interface. At least part of the first sub-source electrode is in contact with the source region and forms an ohmic contact at an interface.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its preparation method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] Electrostatic discharge (ESD) is ubiquitous. During the production, packaging, testing, transportation, and use of power devices, ESD can easily cause functional failures in devices and circuits, and even directly lead to product failure. Therefore, to ensure the long-term reliable operation of SiC MOSFETs, it is necessary to suppress gate oxide voltage spikes caused by application scenarios. Currently, the main way to improve the ESD robustness of SiC MOSFETs is to design an NPN diode in the poly layer of the MOSFET to provide a discharge path.

[0003] Current technology involves integrating an NPN diode into a gate poly. This structure is highly sensitive to the thermal processes during the fabrication of SiC MOS. Furthermore, integrating the poly diode significantly increases the leakage current between the gate and source terminals of the integrated device, thereby increasing the power consumption of the drive. Summary of the Invention

[0004] This invention provides a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle, which reduces gate-source leakage current, effectively prevents device breakdown, and improves device performance stability.

[0005] In a first aspect, embodiments of the present invention provide a semiconductor device, comprising: A semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body includes a voltage regulator structure and a device functional structure; wherein the voltage regulator structure includes a first region, a second region, and a third region, the first region and the second region are disposed on the first surface and spaced apart along a first direction, the first direction being parallel to the first surface; the third region is disposed on the side of the first region and the second region away from the first surface, and is in contact with the first region and the second region; the device functional structure includes a well region and a source region disposed on the first surface; the first region, the second region, and the source region are of a first conductivity type, and the well region and the third region are of a second conductivity type; A gate is disposed on one side of the first surface, wherein the gate at least covers the well region; A gate electrode is disposed on the side of the gate away from the first surface, wherein at least a portion of the gate electrode contacts the first region and forms an ohmic contact at the interface; A source electrode is disposed on the side of the gate electrode away from the first surface; the source electrode includes a first sub-source electrode, wherein at least a portion of the first sub-source electrode contacts the second region and forms an ohmic contact at the interface; at least a portion of the first sub-source electrode contacts the source region and forms an ohmic contact at the interface; The drain electrode is disposed on the second surface.

[0006] Optionally, the semiconductor body includes at least two voltage regulator structures spaced apart along the first direction; Wherein, at least a portion of the gate electrode contacts the first region of the first voltage regulator structure located at one end of the first direction and forms an ohmic contact; at least a portion of the first sub-source electrode contacts the second region of the last voltage regulator structure located at the other end of the first direction and forms an ohmic contact; the first voltage regulator structure and the last voltage regulator structure are respectively the outermost structures of the plurality of voltage regulator structures in the first direction; The source electrode further includes a plurality of second sub-source electrodes, which are electrically connected to the first region of one of the two adjacent voltage regulator structures and the second region of the other, and form an ohmic contact at their respective contact interfaces; wherein the second sub-source electrodes are electrically isolated from the first sub-source electrodes.

[0007] Optionally, the semiconductor body further includes a temperature sensing structure, which is located on one side of the voltage regulator structure in the first direction. The temperature sensing structure includes a fifth region disposed on the first surface and located on the side of the second region away from the first region; a third region is located on the side of the fifth region away from the first surface and is in contact with at least the fifth region; the fifth region is of the first conductivity type. The source electrode further includes a third sub-source electrode, which is in contact with the fifth region and forms a Schottky contact at the contact interface; wherein the third sub-source electrode is electrically isolated from the first sub-source electrode.

[0008] Optionally, the gate electrode and the source electrode are disposed in the same layer; In the first direction, the gate electrode and the third sub-source electrode are arranged at intervals; The first sub-source electrode surrounds the third sub-source electrode and partially surrounds the gate electrode, and there is a first gap between the first sub-source electrode and the third sub-source electrode, and a second gap between the first sub-source electrode and the gate electrode.

[0009] Secondly, embodiments of the present invention provide a power module, characterized in that it includes a substrate and a semiconductor device as described in any embodiment of the present invention, wherein the substrate is used to support the semiconductor device.

[0010] Thirdly, embodiments of the present invention provide a power conversion circuit, characterized in that the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and a semiconductor device as described in any embodiment of the present invention, wherein the semiconductor device is electrically connected to the circuit board.

[0011] Fourthly, embodiments of the present invention provide a vehicle, characterized in that it includes a load and a power conversion circuit according to any embodiment of the present invention, wherein the power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0012] Fifthly, embodiments of the present invention provide a method for fabricating a semiconductor device, comprising: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body includes a voltage regulator structure and a device functional structure; wherein, the voltage regulator structure includes a first region, a second region and a third region, the first region and the second region being disposed on the first surface and spaced apart along a first direction, the first direction being parallel to the first surface; the third region being disposed on the side of the first region and the second region away from the first surface, and in contact with the first region and the second region; the device functional structure includes a well region and a source region disposed on the first surface; the first region, the second region and the source region are of a first conductivity type, and the well region and the third region are of a second conductivity type; A gate is formed on one side of the first surface, wherein the gate at least covers the well region; A gate electrode is formed on the side of the gate away from the first surface, wherein at least a portion of the gate electrode contacts the first region and forms an ohmic contact at the interface; A source is formed on the side of the gate away from the first surface; the source includes a first sub-source, wherein at least a portion of the first sub-source contacts the second region and forms an ohmic contact at the interface; at least a portion of the first sub-source contacts the source region and forms an ohmic contact at the interface; A drain electrode is formed on the second surface.

[0013] Optionally, the semiconductor body includes at least two voltage regulator structures spaced apart along the first direction; Methods for fabricating semiconductor devices include: Provide substrate; An epitaxial layer is formed on one side of the substrate; The well region and one or more of the third regions are formed in the epitaxial layer; when multiple third regions are formed, the third regions are spaced apart along the first direction. The first region and the second region are formed respectively within the third region; the source region is formed within the trap region; A gate is formed on one side of the first surface, wherein the gate at least covers the well region; A gate electrode is formed on the side of the gate away from the first surface, wherein at least a portion of the gate electrode contacts the first region of the first voltage regulator structure located at one end of the first direction and forms an ohmic contact; A source electrode is formed on the side of the gate electrode away from the first surface. The source electrode includes a first sub-source electrode. At least a portion of the gate electrode contacts the first region of a first voltage regulator structure located at one end of the first direction, forming an ohmic contact. At least a portion of the first sub-source electrode contacts the second region of a last voltage regulator structure located at the other end of the first direction, forming an ohmic contact. The first and last voltage regulator structures are respectively the outermost structures of the plurality of voltage regulator structures in the first direction. The source electrode also includes a plurality of second sub-source electrodes. The second sub-source electrodes electrically connect the first region of one of two adjacent voltage regulator structures to the second region of the other, forming an ohmic contact at their respective contact interfaces. The second sub-source electrodes are electrically isolated from the first sub-source electrodes. A drain electrode is formed on the second surface.

[0014] Optionally, the semiconductor body further includes a temperature sensing structure; After the epitaxial layer forms the well region and the third region, the method further includes: In the first direction, the temperature sensing structure is formed on one side of any of the voltage regulator structures, wherein the temperature sensing structure includes a fifth region, the fifth region is disposed on the first surface and located on the side of the second region away from the first region; the third region is located on the side of the fifth region away from the first surface and is in contact with at least the fifth region; the fifth region is of the first conductivity type; A source electrode is formed on the side of the gate away from the first surface, including: A third sub-source is formed on the side of the gate away from the first surface, the third sub-source is in contact with the fifth region, and a Schottky contact is formed at the contact interface; wherein the third sub-source is electrically isolated from the first sub-source.

[0015] The semiconductor device provided in this invention includes a voltage regulator structure and a device functional structure. The voltage regulator structure is integrated into the semiconductor body and includes a first region, a second region, and a third region. The first region, the second region, and the third region constitute a Zener diode structure. During normal operation, the voltage regulator structure exhibits high impedance, thereby reducing gate-source leakage current and improving device performance stability. When the gate electrode or source electrode encounters electrostatic discharge, a bidirectional low-resistance discharge path can be formed from the gate electrode to the source electrode or from the source electrode to the gate electrode, quickly discharging the electrostatic charge and clamping the gate-source voltage within a safe voltage range, effectively preventing device breakdown. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention; Figure 5 for Figure 3 A top view schematic diagram of the electrode structure of a semiconductor device is provided; Figure 6 for Figure 4 A top view schematic diagram of the electrode structure of another semiconductor device is provided; Figure 7 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention; Figure 8 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention; Figures 9-12 This is a schematic diagram of an intermediate process of a semiconductor device provided in an embodiment of the present invention; Figure 13 This is a schematic flowchart of another method for fabricating a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. See also... Figure 1 ,include: The semiconductor body 110 includes a first surface and a second surface disposed opposite to each other. The semiconductor body 110 includes a voltage regulator structure 111 and a device functional structure 112. The voltage regulator structure 111 includes a first region 1111, a second region 1112, and a third region 1113. The first region 1111 and the second region 1112 are disposed on the first surface and spaced apart along a first direction X, which is parallel to the first surface. The third region 1113 is disposed on the side of the first region 1111 and the second region 1112 away from the first surface and is in contact with both the first region 1111 and the second region 1112. The device functional structure 112 includes a well region 1121 and a source region 1122 disposed on the first surface. The first region 1111, the second region 1112, and the source region 1122 are of a first conductivity type, while the well region 1121 and the third region 1113 are of a second conductivity type. A gate 113 is disposed on one side of the first surface, wherein the gate 113 at least covers the well region 1121; A gate electrode 120 is disposed on the side of the gate 113 away from the first surface, wherein at least a portion of the gate electrode 120 contacts the first region 1111 and forms an ohmic contact at the interface; The source 130 is disposed on the side of the gate 113 away from the first surface; the source 130 includes a first sub-source 131, wherein at least a portion of the first sub-source 131 contacts the second region 1112 and forms an ohmic contact at the interface; at least a portion of the first sub-source 131 contacts the source region 1122 and forms an ohmic contact at the interface; Drain 140 is disposed on the second surface.

[0019] Specifically, in the embodiments of this application, the semiconductor devices include, but are not limited to, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), JFETs (Junction Field-Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), and HEMTs (High Electron Mobility Transistors). The semiconductor body 110 may include wide-bandgap or ultra-wide-bandgap semiconductor materials such as silicon carbide semiconductor body 110 and gallium nitride semiconductor body 110. Exemplarily, the MOSFET includes N-type MOSFETs or P-type MOSFETs. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type. For regions with an N-type conductivity type, N-type doping can be used; the dopant ions for N-type doping can be phosphorus (P) ions or nitrogen (N) ions. For regions with a P-type conductivity type, P-type doping can be used; the dopant ions for P-type doping can be aluminum (Al) ions or boron (B) ions. This application embodiment uses an example where the first conductivity type is N-type and the second conductivity type is P-type. For example, the semiconductor body 110 may include a substrate 114 and an epitaxial layer 115. The material of the substrate 114 and the material of the epitaxial layer 115 may be the same or different. For example, the materials of the substrate 114 and the epitaxial layer 115 may include silicon or silicon carbide. The epitaxial layer 115 is located on one side of the substrate 114, and the epitaxial layer 115 may be formed on the surface of the substrate 114 by epitaxial growth. The semiconductor body 110 integrates a voltage regulator structure 111 and a device functional structure 112. The voltage regulator structure 111 is used to provide a low-impedance discharge path in electrostatic discharge to prevent the semiconductor device from being broken down. The voltage regulator structure 111 includes a first region 1111 and a second region 1112. The first region 1111 and the second region 1112 may be formed on a first surface by an implantation process. The first surface is the surface of the epitaxial layer 115 away from the substrate 114. The first region 1111 and the second region 1112 are both of a first conductivity type and have a high doping concentration.

[0020] The third region 1113 is of the second conductivity type and is located on the side of the first region 1111 and the second region 1112 away from the first surface, and is in contact with the first region 1111 and the second region 1112. In the first direction X, the first region 1111 and the third region 1113 form a PN junction structure, and the second region 1112 and the third region 1113 form a PN junction structure. The two PN junctions together form a back-to-back Zener diode structure, thereby achieving bidirectional electrostatic discharge capability. The first region 1111, the second region 1112, and the third region 1113 can all be formed by N-type implantation and P-type implantation processes, without the need for additional photolithography or high-temperature processes, avoiding doping diffusion or junction depth drift caused by additional thermal treatment, and improving the process window and product yield.

[0021] The device functional structure 112 is used to form a semiconductor device. The device functional structure 112 includes a source region 1122, which is of a first conductivity type and is disposed on a first surface. A well region 1121, of a second conductivity type, is disposed below the source region 1122 and is in contact with at least the source region 1122. The well region 1121 and the source region 1122 are used to form a conductive channel.

[0022] The gate 113 comprises a conductive material such as polysilicon and is disposed on the first surface. A gate dielectric layer, such as SiO2 or a high-k dielectric, may be disposed between the gate 113 and the first surface. A portion of the gate 113 is located on the side of the source region 1122 away from the first surface. The orthographic projection of the gate 113 on the second surface overlaps with the source region 1122 and its covered well region 1121, thereby effectively controlling the conductive channel formed in the semiconductor body 110.

[0023] The gate electrode 120 and source electrode 130 can be formed by methods such as sputtering. The metal material used for the gate electrode 120 and source electrode 130 can be one or more of titanium (Ti), nickel (Ni), or silver (Ag). An interlayer dielectric (ILD) can be disposed in the bus region of the gate electrode 120. An ILD is disposed between the gate electrode 120 and the gate 113, covering the surface of the gate 113. The ILD has a first via, which exposes a portion of the gate 113. The gate electrode 120 is electrically connected to the gate 113 through the first via, thereby enabling external control of the voltage of the gate electrode 120. The ILD also has a second via, through which the gate electrode 120 contacts the first region 1111 of the voltage regulator structure 111, forming an ohmic contact at the contact interface to ensure that the potential of the gate electrode 120 is effectively transferred to the first region 1111 of the voltage regulator structure 111.

[0024] The source electrode 130 is disposed on the side of the gate electrode 113 away from the first surface. The source electrode 130 includes a first sub-source electrode 131. The interlayer dielectric layer also has a third via 220 and a fourth via 230. The third via 220 can expose a portion of the second region 1112, and the fourth via 230 can expose a portion of the source region 1122. The first sub-source electrode 131 contacts the second region 1112 through the third via 220, and the first sub-source electrode 131 contacts the source region 1122 through the fourth via 230, forming ohmic contacts at both interfaces. Thus, the source electrode 130 is connected to both the source region and the second region 1112 of the voltage regulator structure 111.

[0025] When a normal driving voltage is applied between the gate electrode 120 and the source electrode 130, and the driving voltage is lower than the Zener breakdown voltage, the conductive channel is turned on or off, thereby controlling the main power path. At this time, the voltage regulator structure 111 is in a reverse bias or zero bias state, exhibiting extremely high impedance and extremely low gate-source leakage current. Furthermore, due to the small temperature coefficient of the Zener structure, the leakage current is only slightly affected by temperature, ensuring the long-term stability of the device.

[0026] When the gate electrode 120 or the source electrode 130 experiences an electrostatic discharge (ESD) that causes the gate-source voltage to exceed a preset Zener breakdown threshold, the Zener diode formed by the first region 1111, the third region 1113, and the second region 1112 undergoes Zener breakdown. Since the gate electrode 120 forms an ohmic contact with the first region 1111, and the source electrode 130 forms an ohmic contact with the second region 1112, a bidirectional low-resistance discharge path is formed from the gate electrode 120 to the source electrode 130 or vice versa. This rapidly discharges the ESD charge, clamping the gate-source voltage within a safe voltage range and effectively preventing device breakdown. Furthermore, by adjusting the doping concentration and depth of the third region 1113, the Zener breakdown voltage can be controlled and adjusted, thus flexibly adapting to the ESD protection requirements of different application scenarios.

[0027] The semiconductor device provided in this embodiment of the invention includes a voltage regulator structure 111 and a device functional structure 112. The voltage regulator structure 111 is integrated into the semiconductor body 110. The voltage regulator structure 111 includes a first region 1111, a second region 1112, and a third region 1113. The first region 1111, the second region 1112, and the third region 1113 constitute a Zener diode structure. During normal driving, the voltage regulator structure 111 presents a high impedance, thereby reducing gate-source leakage current and improving device performance stability. When the gate electrode 120 or the source electrode 130 encounters electrostatic discharge, a bidirectional low-resistance discharge path can be formed from the gate electrode 120 to the source electrode 130 or from the source electrode 130 to the gate electrode 120, which can quickly discharge electrostatic charge and clamp the gate-source voltage within a safe voltage range, effectively preventing device breakdown.

[0028] Figure 2 For a schematic diagram of another semiconductor device provided in an embodiment of the present invention, see [link to schematic diagram]. Figure 2 The embodiments of the present invention and Figure 1The difference lies in that at least two voltage regulator structures 111 are integrated within the semiconductor body 110, and the voltage regulator structures 111 are arranged at intervals along the first direction X. At least a portion of the gate electrode 120 contacts the first region 1111 of the first voltage regulator structure 111 located at one end of the first direction X through the second via 210, forming an ohmic contact at the interface. At least a portion of the first sub-source electrode 131 contacts the second region 1112 of the last voltage regulator structure 111 located at the other end of the first direction X through the third via 220, forming an ohmic contact. The first and last voltage regulator structures 111 are respectively the two outermost voltage regulator structures 111 in the first direction X. In this embodiment of the invention, two voltage regulator structures 111 are taken as an example, wherein, Figure 2 The left side of the image shows the first voltage regulator structure 111, and the right side shows the last voltage regulator structure 111. The source 130 also includes multiple second sub-sources 132. Each second sub-source 132 is electrically connected to two adjacent voltage regulator structures 111. One end of each sub-source is connected to the second region 1112 of the preceding voltage regulator structure 111, and the other end is connected to the first region 1111 of the following voltage regulator structure 111. Ohmic contacts are formed at both interfaces, thus connecting the adjacent voltage regulator structures 111 in series. All second sub-sources 132 are electrically isolated from the first sub-source 131, for example, through independent metal traces or insulating media, to prevent the main source 130 signal from interfering with the electrostatic discharge network. When the gate-source voltage is lower than the breakdown voltage of any Zener diode, all voltage regulator structures 111 are in a high-resistance state, with approximately no leakage current, and the switching performance of the MOSFET is not affected. When the gate-source voltage exceeds a preset Zener breakdown threshold due to electrostatic discharge, multiple voltage regulator structures 111 undergo Zener breakdown sequentially or simultaneously. Since each voltage regulator structure 111 is connected in series through the second sub-source 132, the total breakdown voltage is the sum of the breakdown voltages of each voltage regulator structure 111. By introducing multiple series-connected voltage regulator structures 111, the trigger voltage for electrostatic discharge can be set over a wide range, precisely matching different application scenarios. Furthermore, the multiple voltage regulator structures 111 can be arranged along the first direction X, embedded in the gap region between the source 130 and the gate electrode 120, making full use of the device's planar space and avoiding additional occupation of effective area.

[0029] Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention. Figure 4 For a schematic diagram of another semiconductor device provided in an embodiment of the present invention, see [link to schematic diagram]. Figure 3 and Figure 4 The semiconductor body 110 also includes a temperature sensing structure 116, which is located on one side of the voltage regulator structure 111 in the first direction X. The temperature sensing structure 116 includes a fifth region 1161, which is disposed on the first surface and located on the side of the second region 1112 away from the first region 1111; a third region 1113 is located on the side of the fifth region 1161 away from the first surface and is in contact with the fifth region 1161; the fifth region 1161 is of a first conductivity type. The source 130 also includes a third sub-source 133, which is in contact with the fifth region 1161 and forms a Schottky contact at the contact interface; wherein the third sub-source 133 is electrically isolated from the first sub-source 131.

[0030] Specifically, the embodiments of the present invention and Figure 1 The difference lies in that, while retaining the original voltage regulator structure 111 and device functional structure 112, a temperature sensing structure 116 is further integrated to achieve real-time and accurate monitoring of the chip's operating temperature. Specifically, the temperature sensing structure 116 is disposed along the first direction X on one side of the voltage regulator structure 111. The temperature sensing structure 116 can be located on the adjacent side of the second region 1112 away from the first region 1111, or it can be located on the adjacent side of the first region 1111 away from the second region 1112. Considering the interference between the gate electrode 120 traces in the gate electrode 120 bus area and the electrode traces of the temperature sensing structure 116, in this embodiment of the invention, for example, the temperature sensing structure 116 is located on the adjacent side of the second region 1112 away from the first region 1111.

[0031] The temperature sensing structure 116 includes a fifth region 1161, which is of a first conductivity type and is formed with a low doping concentration to optimize its cathode characteristics as a Schottky Barrier Diode (SBD). A third region 1113 not only covers the first region 1111 and the second region 1112, but also extends below and at least contacts the fifth region 1161, thereby providing the necessary electric field shielding for the SBD.

[0032] In this embodiment of the invention, the source 130 further includes a third sub-source 133, and the interlayer dielectric layer is further provided with a fifth via 240. The fifth via 240 exposes at least a portion of the fifth region 1161. The third sub-source 133 contacts the fifth region 1161 through the fifth via 240, forming a Schottky contact at the interface, thereby constituting an SBD device. The forward conduction voltage of the SBD has a good linear temperature coefficient. When a constant small current is applied to the SBD, the voltage across its terminals decreases linearly with increasing temperature. By detecting this voltage change through an external circuit, the local temperature of the device can be accurately deduced. The fifth region 1161 constitutes the cathode of the SBD, and the third sub-source 133 constitutes the anode of the SBD. The SBD device and the NPN Zener diode in the voltage regulator structure 111 are physically adjacent and share the same third region 1113 and the second region 1112 of the voltage regulator structure 111, thereby eliminating the need for a separate process step of fabricating a highly doped cathode for the SBD. Furthermore, by reusing the second region 1112 of the voltage regulator structure 111 as part of the SBD cathode, the chip area occupied can also be effectively reduced.

[0033] Figure 5 for Figure 3 A top view schematic diagram of the electrode structure of a semiconductor device is provided, combined with... Figure 3 See Figure 5 The gate electrode 120 and the source electrode 130 are disposed in the same layer; In the first direction X, the gate electrode 120 and the third sub-source electrode 133 are arranged at intervals; The first sub-source 131 surrounds the third sub-source 133 and partially surrounds the gate electrode 120, and there is a first gap between the first sub-source 131 and the third sub-source 133, and a second gap between the first sub-source 131 and the gate electrode 120.

[0034] Specifically, the gate electrode 120 and the source electrode 130 are formed using a co-layer metallization process. The gate electrode 120 and the source electrode 130 are located on the same metal layer, and their patterns can be defined using processes such as sputtering, photolithography, and etching. In the first direction X, the gate electrode 120 and the third sub-source electrode 133 can be arranged at intervals, maintaining sufficient spacing between them to avoid electrical short circuits or parasitic coupling. The first sub-source electrode 131 surrounds the circumferential region of the third sub-source electrode 133 and partially surrounds the outer edge of the gate electrode 120. A first gap is provided between the first sub-source electrode 131 and the third sub-source electrode 133, and a second gap is provided between the first sub-source electrode 131 and the gate electrode 120. An interlayer dielectric layer can be filled between the first gap and the second gap to ensure electrical isolation between the electrodes.

[0035] The region between the gate electrode 120 and the third sub-source 133 can be the integrated region of the bleeder structure. In the adjacent region of the voltage regulator structure 111, a lightly doped fifth region 1161 is designed as the cathode of the SBD. The second region 1112 in the voltage regulator structure 111 directly serves as the cathode lead-out terminal of the SBD. The metal of the third sub-source 133 serves as the anode of the SBD, forming a Schottky contact with the fifth region 1161. This avoids the need for a separate cathode metal wire bonding area for the temperature sensor, as required in traditional solutions. By utilizing the existing source region, i.e., the second region 1112, the space required for designing a separate cathode contact area and metal wire bonding area for the SBD is eliminated, effectively reducing the overall chip size and manufacturing costs. The gate electrode 120, the first sub-source 131, and the third sub-source 133 are arranged in the same layer, resulting in a compact structure. Simultaneously, the SBD is adjacent to the power unit, enabling precise sensing of hotspot temperatures and improving thermal management response speed.

[0036] Figure 6 for Figure 4 A top-view schematic diagram of the electrode structure of another semiconductor device is provided, combined with Figure 4 See Figure 6 The gate electrode 120 and the source electrode 130 are disposed in the same layer; In the first direction X, the gate electrode 120, the second sub-source electrode 132, and the third sub-source electrode 133 are arranged at intervals; the first sub-source electrode 131 surrounds the third sub-source electrode 133 and partially surrounds the gate electrode 120. The region between the gate electrode 120 and the third sub-source electrode 133 can be the integrated region of the bleeder structure 111 and the temperature sensing structure 116. The metal of the third sub-source electrode 133 serves as the anode of the SBD, utilizing the existing source region, i.e., the second region 1112, eliminating the need to design a separate cathode contact region and metal bonding region for the SBD, effectively reducing the overall chip size and manufacturing costs.

[0037] This invention provides a power module based on the above embodiments, including a substrate and a semiconductor device according to any embodiment of the invention, wherein the substrate is used to support the semiconductor device. The power module provided by this invention has the same beneficial effects as the semiconductor device according to any embodiment of the invention.

[0038] This invention provides a power conversion circuit based on the above embodiments. The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this invention, with the semiconductor device electrically connected to the circuit board. The power conversion circuit provided by this invention has the same beneficial effects as the semiconductor device in any embodiment of this invention.

[0039] Based on the above embodiments, this invention provides a vehicle including a load and a power conversion circuit as described in any embodiment of this invention. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0040] Figure 7 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. (See attached diagram.) Figure 7 ,include: S110. A semiconductor body 110 is provided, comprising a first surface and a second surface disposed opposite to each other; the semiconductor body 110 includes a voltage regulator structure 111 and a device functional structure 112, with a first direction X parallel to the first surface; wherein, the voltage regulator structure 111 includes a first region 1111, a second region 1112 and a third region 1113, the first region 1111 and the second region 1112 are disposed on the first surface and are spaced apart along the first direction X; the third region 1113 is disposed on the side of the first region 1111 and the second region 1112 away from the first surface and is in contact with the first region 1111 and the second region 1112; the device functional structure 112 includes a well region 1121 and a source region 1122 disposed on the first surface; the first region 1111, the second region 1112 and the source region 1122 are of a first conductivity type, and the well region 1121 and the third region 1113 are of a second conductivity type; In this embodiment, the semiconductor device includes, but is not limited to, MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), JFET (Junction Field-Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), and HEMT (High Electron Mobility Transistor). The semiconductor body 110 may include wide-bandgap or ultra-wide-bandgap semiconductor materials such as silicon carbide semiconductor body 110 or gallium nitride semiconductor body 110. Exemplarily, the MOSFET includes an N-type MOSFET or a P-type MOSFET. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type. Regions with N-type conductivity can be formed by N-type doping, and the doping ions for N-type doping can be phosphorus (P) ions or nitrogen (N) ions. Regions with P-type conductivity can be formed by P-type doping, and the doping ions for P-type doping can be aluminum (Al) ions or boron (B) ions. This embodiment uses an example where the first conductivity type is N-type and the second conductivity type is P-type.

[0041] Specifically, the semiconductor body 110 may include a substrate 114 and an epitaxial layer 115. The material of the substrate 114 and the material of the epitaxial layer 115 may be the same or different. The epitaxial layer 115 is located on one side of the substrate 114, and the epitaxial layer 115 can be formed on the surface of the substrate 114 by epitaxial growth. The semiconductor body 110 integrates a voltage regulator structure 111 and a device functional structure 112. The voltage regulator structure 111 is used to provide a low-impedance discharge path in electrostatic discharge to prevent the semiconductor device from being broken down. The voltage regulator structure 111 includes a first region 1111 and a second region 1112. The first region 1111 and the second region 1112 can be formed on a first surface by an implantation process. The first surface is the surface of the epitaxial layer 115 away from the substrate 114. Both the first region 1111 and the second region 1112 are of a first conductivity type and have a high doping concentration.

[0042] The third region 1113 is of the second conductivity type and is located on the side of the first region 1111 and the second region 1112 away from the first surface, and is in contact with the first region 1111 and the second region 1112. In the first direction X, the first region 1111 and the third region 1113 form a PN junction structure, and the second region 1112 and the third region 1113 form a PN junction structure. The two PN junctions together form a back-to-back Zener diode structure, thereby achieving bidirectional electrostatic discharge capability. The first region 1111, the second region 1112, and the third region 1113 can all be formed by N-type implantation and P-type implantation processes, without the need for additional photolithography or high-temperature processes, avoiding doping diffusion or junction depth drift caused by additional thermal treatment, and improving the process window and product yield.

[0043] Device functional structure 112 is used to form a semiconductor power device, such as a MOSFET, wherein the device functional structure 112 includes a source region 1122, which is of a first conductivity type and is disposed on a first surface. A well region 1121, which is of a second conductivity type, is disposed below the source region 1122 and is in contact with at least the source region 1122. The source region 1122 and the well region 1121 are used to form a conductive channel of the MOSFET.

[0044] S120, A gate 113 is formed on one side of the first surface; Specifically, a gate dielectric layer, such as SiO2, SiON, or a high-k dielectric, is deposited on the first surface. Then, polysilicon is deposited on the gate dielectric layer and patterned using photolithography and etching processes to form the gate 113. The gate 113 at least covers the well region 1121, ensuring that the gate electrode 120 can effectively control the carrier concentration in the channel region, thereby enabling the MOSFET to be turned on and off normally.

[0045] S130: A gate electrode 120 is formed on the side of the gate 113 away from the first surface, wherein at least a portion of the gate electrode 120 contacts the first region 1111 and forms an ohmic contact at the interface; a source electrode 130 is formed on the side of the gate 113 away from the first surface; the source electrode 130 includes a first sub-source electrode 131, wherein at least a portion of the first sub-source electrode 131 contacts the second region 1112 and forms an ohmic contact at the interface; at least a portion of the first sub-source electrode 131 contacts the source region 1122 and forms an ohmic contact at the interface; Specifically, a metal layer is deposited on the side of the gate 113 away from the first surface, and a gate electrode 120 and a source electrode 130 are formed by photolithography and etching. The metal material used for the gate electrode 120 and the source electrode 130 can be one or more of titanium (Ti), nickel (Ni), or silver (Ag). The gate electrode 120 can be located in the gate electrode 120 bus region. An interlayer dielectric (ILD) is disposed between the gate electrode 120 and the gate 113, covering the surface of the gate 113. The ILD has a first via, which exposes a portion of the gate 113. The gate electrode 120 is electrically connected to the gate 113 through the first via, thereby enabling external regulation of the voltage of the gate electrode 120. The ILD also has a second via, through which the gate electrode 120 contacts the first region 1111 of the voltage regulator structure 111, forming an ohmic contact at the contact interface to ensure that the potential of the gate electrode 120 is effectively transferred to the first region 1111 of the voltage regulator structure 111.

[0046] The source electrode 130 is disposed on the side of the gate electrode 113 away from the first surface. The source electrode 130 includes a first sub-source electrode 131. The interlayer dielectric layer also has a third via 220 and a fourth via 230. The third via 220 can expose a portion of the second region 1112, and the fourth via 230 can expose a portion of the source region 1122. The first sub-source electrode 131 contacts the second region 1112 through the third via 220, and the first sub-source electrode 131 contacts the source region 1122 through the fourth via 230, forming ohmic contacts at both interfaces. Thus, the source electrode 130 is connected to both the source region and the second region 1112 of the voltage regulator structure 111.

[0047] When a normal driving voltage is applied between the gate electrode 120 and the source electrode 130, and the driving voltage is lower than the Zener breakdown voltage, the conductive channel is turned on or off, thereby controlling the main power path. At this time, the voltage regulator structure 111 is in a reverse bias or zero bias state, exhibiting extremely high impedance and extremely low gate-source leakage current. Furthermore, due to the small temperature coefficient of the Zener structure, the leakage current is only slightly affected by temperature, ensuring the long-term stability of the device.

[0048] When the gate electrode 120 or the source electrode 130 experiences an electrostatic discharge (ESD) that causes the gate-source voltage to exceed a preset Zener breakdown threshold, the Zener diode formed by the first region 1111, the third region 1113, and the second region 1112 undergoes Zener breakdown. Since the gate electrode 120 forms an ohmic contact with the first region 1111, and the source electrode 130 forms an ohmic contact with the second region 1112, a bidirectional low-resistance discharge path is formed from the gate electrode 120 to the source electrode 130 or vice versa. This rapidly conducts the ESD charge to the substrate 114 or ground, clamping the gate-source voltage within a safe voltage range and effectively preventing device breakdown. Furthermore, by adjusting the doping concentration and depth of the third region 1113, the Zener breakdown voltage can be controlled and adjusted, thus flexibly adapting to the ESD protection level requirements of different application scenarios.

[0049] S140, Drain 140 is formed on the second surface.

[0050] Specifically, a drain 140 is formed on the second surface of the semiconductor body 110 by thinning and back-side metallization, such as Ni / Ag sputtering or evaporation.

[0051] Figure 8 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. Figures 9-12 This is a schematic diagram of an intermediate process of a semiconductor device provided in an embodiment of the present invention, combined with... Figure 3 , Figures 9-12 See Figure 8 ,include: S210, providing substrate 114; S220, An epitaxial layer 115 is formed on one side of the substrate 114; S230, a well region 1121 and a third region 1113 are formed in the epitaxial layer 115; Specifically, a first hard mask 310 is formed on the surface of the epitaxial layer 115. The first hard mask 310 has a first opening 311, which exposes the injection regions of the well region 1121 and the third region 1113, respectively. The well region 1121 and the third region 1113 are formed by an injection process. Its structure is as follows: Figure 9 As shown.

[0052] S240, a first region 1111 and a second region 1112 are formed in the third region 1113 respectively; a source region 1122 is formed in the sink region 1121.

[0053] Specifically, a second hard mask 320 is formed on the surface of the epitaxial layer 115. The second hard mask 320 has a second opening 321, which exposes the injection regions of the first region 1111, the second region 1112, and the source region 1122, respectively. The first region 1111, the second region 1112, and the source region 1122 are formed through an implantation process. Its structure is as follows: Figure 10 As shown.

[0054] S250. In the first direction X, a temperature sensing structure 116 is formed on one side of the voltage regulator structure 111. The temperature sensing structure 116 includes a fifth region 1161, which is disposed on the first surface and located on the side of the second region 1112 away from the first region 1111. A third region 1113 is located on the side of the fifth region 1161 away from the first surface and is in contact with at least the fifth region 1161. The fifth region 1161 is of a first conductivity type. Specifically, while retaining the original voltage regulator structure 111 and device functional structure 112, a temperature sensing structure 116 is further integrated to achieve real-time and accurate monitoring of the chip's operating temperature. The temperature sensing structure 116 is disposed along the first direction X on one side of the voltage regulator structure 111. The temperature sensing structure 116 can be located on the adjacent side of the second region 1112 away from the first region 1111, or on the adjacent side of the first region 1111 away from the second region 1112. Considering the interference between the gate electrode 120 traces in the gate electrode 120 bus area and the electrode traces of the temperature sensing structure 116, in this embodiment of the invention, exemplarily, the temperature sensing structure 116 is located on the adjacent side of the second region 1112 away from the first region 1111.

[0055] A third hard mask 330 is formed on the surface of the epitaxial layer 115. The third hard mask 330 has a third opening 331, which exposes the implantation region of the fifth region 1161. The fifth region 1161 is formed through an implantation process. The fifth region 1161 is of the first conductivity type and is formed with a low doping concentration to optimize its cathode characteristics as a Schottky Barrier Diode (SBD). The third region 1113 not only covers the first region 1111 and the second region 1112, but also extends below the fifth region 1161 and at least contacts the fifth region 1161, thereby providing the necessary electric field shielding for the SBD. Its structure is as follows: Figure 11 As shown.

[0056] S260, A gate 113 is formed on one side of the first surface; S270, a gate electrode 120 is formed on the side of the gate 113 away from the first surface, wherein at least a portion of the gate electrode 120 contacts the first region 1111 and forms an ohmic contact at the interface; a source electrode 130 is formed on the side of the gate 113 away from the first surface; the source electrode 130 includes a first sub-source electrode 131, wherein at least a portion of the first sub-source electrode 131 contacts the second region 1112 and forms an ohmic contact at the interface; at least a portion of the first sub-source electrode 131 contacts the source region 1122 and forms an ohmic contact at the interface; the source electrode 130 also includes a third sub-source electrode 133, the third sub-source electrode 133 contacts the fifth region 1161 and forms a Schottky contact at the interface; Specifically, a metal layer is deposited on the side of the gate 113 away from the first surface, and a gate electrode 120 and a source electrode 130 are formed by photolithography and etching. The metal material used for the gate electrode 120 and the source electrode 130 can be one or more of titanium (Ti), nickel (Ni), or silver (Ag). The gate electrode 120 can be located in the gate electrode 120 bus region. An interlayer dielectric (ILD) is disposed between the gate electrode 120 and the gate 113. The interlayer dielectric covers the surface of the gate 113 and has a first via. The first via exposes part of the gate 113. The gate electrode 120 is electrically connected to the gate 113 through the first via, thereby realizing external control of the voltage of the gate electrode 120. The interlayer dielectric layer is also provided with a second via 210. The gate electrode 120 contacts the first region 1111 of the voltage regulator structure 111 through the second via 210 and forms an ohmic contact at the contact interface to ensure that the potential of the gate electrode 120 is effectively transferred to the first region 1111 of the voltage regulator structure 111.

[0057] The source electrode 130 is disposed on the side of the gate electrode 113 away from the first surface. The source electrode 130 includes a first sub-source electrode 131. The interlayer dielectric layer also has a third via 220 and a fourth via 230. The third via 220 can expose a portion of the second region 1112, and the fourth via 230 can expose a portion of the source region 1122. The first sub-source electrode 131 contacts the second region 1112 through the third via 220, and the first sub-source electrode 131 contacts the source region 1122 through the fourth via 230, forming ohmic contacts at both interfaces. Thus, the source electrode 130 is connected to both the source region and the second region 1112 of the voltage regulator structure 111.

[0058] In this embodiment of the invention, the interlayer dielectric layer is further provided with a fifth via 240, which exposes at least a portion of the fifth region 1161. The third sub-source 133 contacts the fifth region 1161 through the fifth via 240, forming a Schottky contact at the interface, thereby constituting an SBD device. The forward conduction voltage of the SBD has a good linear temperature coefficient. When a constant small current is applied to the SBD, its voltage decreases linearly with increasing temperature. By detecting this voltage change through an external circuit, the local temperature of the device can be accurately deduced. The fifth region 1161 constitutes the cathode of the SBD, and the third sub-source 133 constitutes the anode of the SBD. The SBD device and the NPN Zener diode in the voltage regulator structure 111 are physically adjacent and share the same third region 1113 and the second region 1112 of the voltage regulator structure 111, thus eliminating the need for a separate process step of fabricating a highly doped cathode for the SBD. Furthermore, by reusing the second region 1112 of the voltage regulator structure 111 as part of the SBD cathode, the chip area occupied can also be effectively reduced. Its structure is as follows Figure 12 As shown.

[0059] S280, Drain 140 is formed on the second surface.

[0060] Figure 13 This is a schematic flowchart of another method for fabricating a semiconductor device according to an embodiment of the present invention, combined with... Figure 2 or Figure 4 See Figure 13 ,include: S310, providing substrate 114; S320, An epitaxial layer 115 is formed on one side of the substrate 114; S330, a well region 1121 and a plurality of third regions 1113 are formed in the epitaxial layer 115; the third regions 1113 are arranged at intervals along the first direction X. S340, A first region 1111 and a second region 1112 are formed in the third region 1113; a source region 1122 is formed in the sink region 1121; S350, A gate 113 is formed on one side of the first surface, wherein the gate 113 at least covers the well region 1121; S360, A gate electrode 120 is formed on the side of the gate 113 away from the first surface, wherein at least a portion of the gate electrode 120 contacts and forms an ohmic contact with a first region 1111 of the first voltage regulator structure 111 located at one end of the first direction X. A source 130 is formed on the side of the gate 113 away from the first surface. The source 130 includes a first sub-source 131. At least a portion of the gate electrode 120 contacts a first region 1111 of a first voltage regulator structure 111 located at one end of the first direction X and forms an ohmic contact. At least a portion of the first sub-source 131 contacts a second region 1112 of a last voltage regulator structure 111 located at the other end of the first direction X and forms an ohmic contact. The first voltage regulator structure 111 and the last voltage regulator structure 111 are the outermost structures of the plurality of voltage regulator structures 111 in the first direction X, respectively. The source 130 also includes a plurality of second sub-sources 132. The second sub-sources 132 are electrically connected to the first region 1111 of one of two adjacent voltage regulator structures 111 and the second region 1112 of the other, and form an ohmic contact at their respective contact interfaces. The second sub-sources 132 are electrically isolated from the first sub-sources 131. Specifically, at least a portion of the gate electrode 120 contacts the first region 1111 of the first voltage regulator structure 111 located at one end of the first direction X through the second via 210, forming an ohmic contact at the interface. At least a portion of the first sub-source electrode 131 contacts the second region 1112 of the last voltage regulator structure 111 located at the other end of the first direction X through the third via 220, forming an ohmic contact. The first and last voltage regulator structures 111 are the two outermost voltage regulator structures 111 in the first direction X, respectively. The source electrode 130 also includes a plurality of second sub-source electrodes 132, each second sub-source electrode 132 electrically connecting two adjacent voltage regulator structures 111, with one end connected to the second region 1112 of the preceding voltage regulator structure 111 and the other end connected to the first region 1111 of the following voltage regulator structure 111, forming an ohmic contact at both contact interfaces, thereby connecting the adjacent voltage regulator structures 111 in series. All second sub-sources 132 are electrically isolated from the first sub-source 131, for example, through independent metal traces or insulating media, to prevent the main source 130 signal from interfering with the electrostatic discharge network. When the gate-source voltage is lower than the breakdown voltage of any Zener diode, all voltage regulator structures 111 are in a high-resistance state with approximately no leakage current, thus not affecting the switching performance of the MOSFET. When the gate-source voltage exceeds a preset Zener breakdown threshold due to electrostatic discharge, multiple voltage regulator structures 111 undergo Zener breakdown sequentially or simultaneously. Since each voltage regulator structure 111 is connected in series through the second sub-source 132, the total breakdown voltage is the sum of the breakdown voltages of each voltage regulator structure 111. By introducing multiple series-connected voltage regulator structures 111, the trigger voltage for electrostatic discharge can be set over a wide range, precisely matching different application scenarios. Furthermore, multiple voltage regulator structures 111 can be arranged along the first direction X, embedded in the gap region between the source 130 and the gate electrode 120, making full use of the device's planar space and avoiding additional occupation of effective area.

[0061] S370, Drain 140 is formed on the second surface.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body includes a voltage regulator structure and a device functional structure; wherein the voltage regulator structure includes a first region, a second region, and a third region, the first region and the second region are disposed on the first surface and spaced apart along a first direction, the first direction being parallel to the first surface; the third region is disposed on the side of the first region and the second region away from the first surface, and is in contact with the first region and the second region; the device functional structure includes a well region and a source region disposed on the first surface; the first region, the second region, and the source region are of a first conductivity type, and the well region and the third region are of a second conductivity type; A gate is disposed on one side of the first surface, wherein the gate at least covers the well region; A gate electrode is disposed on the side of the gate away from the first surface, wherein at least a portion of the gate electrode contacts the first region and forms an ohmic contact at the interface; A source electrode is disposed on the side of the gate electrode away from the first surface; the source electrode includes a first sub-source electrode, wherein at least a portion of the first sub-source electrode contacts the second region and forms an ohmic contact at the interface; at least a portion of the first sub-source electrode contacts the source region and forms an ohmic contact at the interface; The drain electrode is disposed on the second surface.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor body includes at least two voltage regulator structures arranged at intervals along the first direction; Wherein, at least a portion of the gate electrode contacts the first region of the first voltage regulator structure located at one end of the first direction and forms an ohmic contact; at least a portion of the first sub-source electrode contacts the second region of the last voltage regulator structure located at the other end of the first direction and forms an ohmic contact; the first voltage regulator structure and the last voltage regulator structure are respectively the outermost structures of the plurality of voltage regulator structures in the first direction; The source electrode further includes a plurality of second sub-source electrodes, which are electrically connected to the first region of one of the two adjacent voltage regulator structures and the second region of the other, and form an ohmic contact at their respective contact interfaces; wherein the second sub-source electrodes are electrically isolated from the first sub-source electrodes.

3. The semiconductor device according to any one of claims 1-2, characterized in that, The semiconductor body further includes a temperature sensing structure, which is located on one side of the voltage regulator structure in the first direction. The temperature sensing structure includes a fifth region disposed on the first surface and located on the side of the second region away from the first region; a third region is located on the side of the fifth region away from the first surface and is in contact with at least the fifth region; the fifth region is of the first conductivity type. The source electrode further includes a third sub-source electrode, which is in contact with the fifth region and forms a Schottky contact at the contact interface; wherein the third sub-source electrode is electrically isolated from the first sub-source electrode.

4. The semiconductor device according to claim 3, characterized in that, The gate electrode and the source electrode are disposed in the same layer; In the first direction, the gate electrode and the third sub-source electrode are arranged at intervals; The first sub-source electrode surrounds the third sub-source electrode and partially surrounds the gate electrode, and there is a first gap between the first sub-source electrode and the third sub-source electrode, and a second gap between the first sub-source electrode and the gate electrode.

5. A power module, characterized in that, It includes a substrate and at least one semiconductor device as described in any one of claims 1-4, wherein the substrate is used to support the semiconductor device.

6. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-4, wherein the semiconductor device is electrically connected to the circuit board.

7. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 6, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

8. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body includes a voltage regulator structure and a device functional structure; wherein, the voltage regulator structure includes a first region, a second region and a third region, the first region and the second region being disposed on the first surface and spaced apart along a first direction, the first direction being parallel to the first surface; the third region being disposed on the side of the first region and the second region away from the first surface, and in contact with the first region and the second region; the device functional structure includes a well region and a source region disposed on the first surface; the first region, the second region and the source region are of a first conductivity type, and the well region and the third region are of a second conductivity type; A gate is formed on one side of the first surface, wherein the gate at least covers the well region; A gate electrode is formed on the side of the gate away from the first surface, wherein at least a portion of the gate electrode contacts the first region and forms an ohmic contact at the interface; A source is formed on the side of the gate away from the first surface; the source includes a first sub-source, wherein at least a portion of the first sub-source contacts the second region and forms an ohmic contact at the interface; at least a portion of the first sub-source contacts the source region and forms an ohmic contact at the interface; A drain electrode is formed on the second surface.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The semiconductor body includes at least two voltage regulator structures arranged at intervals along the first direction; Methods for fabricating semiconductor devices include: Provide substrate; An epitaxial layer is formed on one side of the substrate; The well region and one or more of the third regions are formed in the epitaxial layer; when multiple third regions are formed, the third regions are spaced apart along the first direction. The first region and the second region are formed respectively within the third region; the source region is formed within the trap region; A gate is formed on one side of the first surface, wherein the gate at least covers the well region; A gate electrode is formed on the side of the gate away from the first surface, wherein at least a portion of the gate electrode contacts the first region of the first voltage regulator structure located at one end of the first direction and forms an ohmic contact; A source electrode is formed on the side of the gate electrode away from the first surface. The source electrode includes a first sub-source electrode. At least a portion of the gate electrode contacts the first region of a first voltage regulator structure located at one end of the first direction, forming an ohmic contact. At least a portion of the first sub-source electrode contacts the second region of a last voltage regulator structure located at the other end of the first direction, forming an ohmic contact. The first and last voltage regulator structures are respectively the outermost structures of the plurality of voltage regulator structures in the first direction. The source electrode also includes a plurality of second sub-source electrodes. The second sub-source electrodes electrically connect the first region of one of two adjacent voltage regulator structures to the second region of the other, forming an ohmic contact at their respective contact interfaces. The second sub-source electrodes are electrically isolated from the first sub-source electrodes. A drain electrode is formed on the second surface.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The semiconductor body also includes a temperature sensing structure; After the epitaxial layer forms the well region and the third region, the method further includes: In the first direction, the temperature sensing structure is formed on one side of any of the voltage regulator structures, wherein the temperature sensing structure includes a fifth region, the fifth region is disposed on the first surface and located on the side of the second region away from the first region; the third region is located on the side of the fifth region away from the first surface and is in contact with at least the fifth region; the fifth region is of the first conductivity type; A source electrode is formed on the side of the gate away from the first surface, including: A third sub-source is formed on the side of the gate away from the first surface, the third sub-source is in contact with the fifth region, and a Schottky contact is formed at the contact interface; wherein the third sub-source is electrically isolated from the first sub-source.

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