Semiconductor device and power module

Abstract

This application provides a semiconductor device and a power module, including: a semiconductor substrate and an epitaxial layer, the epitaxial layer including a gate trench and a first shielding region, and a drift region, a body region and a source region arranged in sequence. This application forms a first shielding region with the same conductivity type as the body region in a local area on the drift region, and configures the first shielding region to continuously cover the bottom of at least two adjacent and spaced-apart gate trenches in its extending direction. This effectively shields the electric field at the bottom and corners of the gate trenches, thereby mitigating the electric field peak at the bottom of the gate trenches during device operation and the electric field stress concentration at the bottom of the gate trenches during short circuits, thus achieving synergistic optimization of the device's conduction characteristics and short-circuit withstand capability.

Description

Technical Field

[0001] This application relates to the field of semiconductor device manufacturing technology, and more specifically, to a semiconductor device and a power module. Background Technology

[0002] Silicon carbide (SiC) power devices have become core components in high-efficiency power conversion systems due to their advantages such as high breakdown field strength, high switching speed, and low conduction loss. Conduction loss is a key performance indicator of power devices; reducing specific on-resistance (Rsp) can effectively reduce conduction loss and improve system efficiency.

[0003] However, in pursuing low specific on-resistance, existing SiC power devices often suffer from a decrease in short-circuit withstand time (SCWT). This means there is a trade-off between optimizing conduction losses and improving short-circuit reliability. This performance trade-off limits the further development of SiC power devices in applications requiring both low losses and high reliability.

[0004] Therefore, how to provide a SiC device structure and manufacturing method that can balance low conduction loss and good short-circuit withstand capability, so as to break the above-mentioned performance trade-off, has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] To address the aforementioned problems, the first aspect of this application aims to provide a semiconductor device, comprising: a semiconductor substrate and an epitaxial layer disposed on the semiconductor substrate; wherein the epitaxial layer comprises: A drift region having a first conductivity type and located on the side of the epitaxial layer closer to the semiconductor substrate; The body region has a second conductivity type and is located above the drift region; The source region has a first conductivity type and is located above the body region, adjacent to a portion of the surface of the epitaxial layer on the side opposite to the semiconductor substrate. A first shielding region having a second conductivity type is located above the drift region and is adjacent to a portion of the surface of the body region on the side closest to the drift region. A gate trench is located on the drift region and extends through the body region and the source region along a first direction; and the first shielding region continuously covers the bottom of at least two adjacent and spaced-apart gate trenches in a second direction; wherein, the first direction is the direction of the epitaxial layer thickness, the second direction is the direction in which the first shielding region extends, and the second direction is perpendicular to the first direction.

[0006] This application forms a first shielding region of a second conductivity type within the epitaxial layer, and the first shielding region continuously covers the bottom of at least two adjacent and spaced-apart gate trenches in the second direction. This allows the first shielding region to effectively shield the electric field at the bottom and corners of the gate trenches when the semiconductor device is under short-circuit conditions. This helps to reduce the peak electric field at the bottom of the gate dielectric layer, suppress the drain-induced barrier reduction effect, and avoid abnormal increases in channel carrier concentration and a sharp increase in short-circuit current. At the same time, it also helps to alleviate the electric field stress concentration in the gate dielectric layer during short-circuit operations, reducing the risk of gate dielectric breakdown and device thermal failure, thereby extending the short-circuit withstand time of the device.

[0007] To address the aforementioned problems, a second aspect of this application provides a power module, comprising: Substrate, and The semiconductor device as described in the first aspect is located on the substrate.

[0008] The power module described above has the semiconductor device described in the first aspect, and therefore has all the beneficial effects of the semiconductor device described in the first aspect, which will not be repeated here. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a semiconductor device according to an embodiment of this application.

[0010] Figure 2 This is a schematic diagram illustrating another semiconductor device according to an embodiment of this application.

[0011] Figure 3 This is a schematic diagram illustrating another semiconductor device according to an embodiment of this application.

[0012] Figure 4 This is a schematic diagram illustrating another semiconductor device according to an embodiment of this application.

[0013] Figure 5 This is a schematic diagram illustrating another semiconductor device according to an embodiment of this application.

[0014] Figure 6 This is a schematic diagram illustrating another semiconductor device according to an embodiment of this application.

[0015] Figure 7 This is a schematic diagram illustrating another semiconductor device according to an embodiment of this application.

[0016] Figure 8 This is a schematic diagram illustrating another semiconductor device according to an embodiment of this application.

[0017] Figure 9This is a schematic diagram illustrating another semiconductor device according to an embodiment of this application.

[0018] Figure 10 This is a schematic diagram of the structure of a power module according to an embodiment of this application.

[0019] Explanation of key component symbols: 100 Semiconductor device; 110 Semiconductor substrate; 120 Epitaxial layer; 121 Drift region; 122 Body region; 123 Source region; 124 First shielding region; 125 Second shielding region; 126 Ohmic contact region; 130 Gate trench; 140 Gate electrode; 150 Gate dielectric layer; 160 Interlayer dielectric layer; 170 Source metal layer; 180 Drain metal layer.

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings of the embodiments of this application will be described below in conjunction with specific implementation methods. Obviously, the drawings and embodiments described below only involve some embodiments of this application and are not intended to limit this disclosure. Detailed Implementation

[0021] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of this application, and should not be construed as limiting this application.

[0022] In the description of the embodiments of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the implementation methods of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0023] In the description of the embodiments of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features.

[0024] In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0025] In the description of the embodiments of this application, unless otherwise stated, the terms "installation", "connection" and "linking" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections, electrical connections, or connections that can communicate with each other; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two components or interactive relationships between two components.

[0026] In the description of the embodiments of this application, the term "layer" refers to a thin film or thick film structure that is arranged layer by layer along the thickness direction of the device, has a continuous overall distribution, and has a unified molding process and overall function. Its molding process is mostly a one-time continuous process. The continuity mentioned here refers to the complete form after deposition or growth but before patterning. Even if subsequent etching processes form openings, trenches, or discrete patterns (such as metal interconnects), these residual parts still belong to the same layer. The term "region" refers to a local semiconductor region within the same layer. These regions have different doping types, doping concentrations, or electrical functions. Their structures rely on the same semiconductor layer, but they have differentiated designs in local performance, thereby achieving functional partitioning and performance synergy of different regions within the same layer. Furthermore, the doping boundary of a "region" is usually determined by an ion implantation mask or diffusion window. Even if there is a gradual junction at the boundary of different regions, they are still considered as different partitions.

[0027] In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0028] Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0029] To address the technical problems described in the background art, embodiments of this application provide a semiconductor device and a power module, including a semiconductor substrate 110 and an epitaxial layer 120. A drift region, a body region, a source region, and a gate trench are formed within the epitaxial layer 120. A first shielding region is formed at the bottom of a portion of the gate trench, and this first shielding region continuously covers the bottom of at least two adjacent trenches, thereby blocking the corresponding local conductive paths of the semiconductor device. Thus, under short-circuit conditions, the continuous current path of the semiconductor device can be divided by the first shielding region, which helps to reduce or avoid current concentration in local areas forming hot spots, thereby extending the Short-Circuit Withstand Time (SCWT).

[0030] To make the above-mentioned objectives, features and beneficial effects of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0031] According to a first aspect of this application, a semiconductor device is provided.

[0032] Please see Figure 1 , Figure 1 This is a schematic cross-sectional view of a semiconductor device 100 according to an embodiment of this application.

[0033] The semiconductor device 100 in this application embodiment includes: a semiconductor substrate 110, an epitaxial layer 120, a gate electrode 140, a gate dielectric layer 150, an interlayer dielectric layer 160, a source metal layer 170, and a drain metal layer 180.

[0034] The epitaxial layer 120 is located on the semiconductor substrate 110 and includes a gate trench 130 and a first shielding region 124, as well as a drift region 121, a body region 122 and a source region 123 arranged sequentially in a first direction.

[0035] Drift region 121 has a first conductivity type and is located on the side of epitaxial layer 120 near semiconductor substrate 110; body region 122 has a second conductivity type and is located above drift region 121; source region 123 has a first conductivity type and is located above body region 122, adjacent to a portion of the surface of epitaxial layer 120 away from semiconductor substrate 110; first shielding region 124 has a second conductivity type and is located above drift region 121, adjacent to a portion of the surface of body region 122 near drift region 121.

[0036] Furthermore, the gate trench 130 extends from the surface of the epitaxial layer 120 away from the semiconductor substrate 110 toward the drift region 121, penetrating the source region 123 and the body region 122; the first shielding region 124 is located above the drift region 121 and is adjacent to a portion of the surface of the body region 122 near the drift region 121, and in the second direction, the first shielding region 124 at least continuously covers the bottom of two adjacent and spaced gate trenches 130.

[0037] For ease of description, the stacking direction of the semiconductor substrate 110 and the epitaxial layer 120 is defined as the first direction, i.e., the Z direction in the figure, or the thickness direction of the epitaxial layer 120. The direction in which the first shielding region 124 extends parallel to the surface of the epitaxial layer 120 is defined as the second direction, i.e., the X1 direction in the figure. The first direction and the second direction are perpendicular to each other.

[0038] The first conductivity type refers to the impurity ion doping type that is opposite to the second conductivity type, including N-type impurity ion doping or P-type impurity ion doping, which can be flexibly set according to the type of semiconductor device 100. For example, when the first conductivity type is N-type doping, the second conductivity type is P-type doping, or vice versa. P-type impurity ions include impurity ions such as aluminum ions, boron ions, or indium ions, while N-type impurity ions include impurity ions such as nitrogen ions, phosphorus ions, or arsenic ions.

[0039] For example, the semiconductor substrate 110 is a silicon carbide (SiC) substrate, and is an N-type heavily doped substrate. The epitaxial layer 120 is a SiC epitaxial layer located on the substrate, including but not limited to one of a 4H-SiC epitaxial layer or a 6H-SiC epitaxial layer, and the epitaxial layer 120 is an N-type lightly doped epitaxial layer. The drift region 121 is an N-type doped region formed in the epitaxial layer 120, the body region 122 is a P-type doped region formed in the epitaxial layer 120, the source region 123 is an N-type doped region formed in the body region 122, and is an N-type heavily doped region with a doping concentration higher than that of the drift region 121, and the first shielding region 124 is a P-type doped region formed in the epitaxial layer 120, and is a P-type heavily doped region with a doping concentration higher than that of the body region 122.

[0040] Furthermore, when the epitaxial layer 120 is a SiC epitaxial layer, the epitaxial layer 120 can be directly epitaxially formed on the semiconductor substrate 110.

[0041] Correspondingly, the semiconductor substrate 110 can also be made of a different material than the epitaxial layer 120. For example, the semiconductor substrate 110 is a single-crystal silicon substrate. In this case, in order to further improve the epitaxial formation quality of the epitaxial layer 120 on the semiconductor substrate 110 and reduce the defect density of the epitaxial layer 120, a buffer layer (not shown) can be formed on the substrate first, and then the epitaxial layer 120 can be epitaxially formed on the buffer layer.

[0042] The buffer layer can be a gradient-doped SiC buffer layer, wherein the gradient doping is configured such that the doping concentration is gradually adjusted from the side near the substrate to the side near the epitaxial layer 120 to match the doping concentration of the epitaxial layer 120. Alternatively, the buffer layer can also be a lattice-matched transition buffer layer, including AlN, GaN, or a composite layer of SiC and AlN with a lattice constant between Si and SiC.

[0043] It should be noted that the material composition of the heterogeneous substrate and buffer layer is only used as an example for illustration, and the specific type of substrate and buffer layer combination is not specifically limited here.

[0044] It should also be noted that the SiC material used in the semiconductor substrate 110 described above is merely an example and should not be construed as limiting the scope of protection of this application. That is to say, the semiconductor substrate 110 in this application may also be made of semiconductor materials suitable for power semiconductor devices 100, such as single-crystal silicon, silicon-on-insulator (SOI), germanium (Ge), silicon-germanium (GeSi), or gallium arsenide (GaAs).

[0045] In addition, a gate dielectric layer 150 is formed on the inner wall surface of the gate trench 130 and conformally covers the bottom wall and sidewall of the gate trench 130 to achieve electrical isolation between the gate electrode 140 and the epitaxial layer 120.

[0046] The gate electrode 140 is filled inside the gate trench 130 and is electrically isolated from the sidewalls and bottom wall of the gate trench 130 by the gate dielectric layer 150, and is used to control the opening and closing of the channel of the semiconductor device 100 under the action of gate voltage.

[0047] Interlayer dielectric layer 160 covers the surface (or front side) of epitaxial layer 120 opposite to semiconductor substrate 110 and the top surface of gate electrode 140 to achieve electrical isolation between gate electrode 140 and the upper source metal layer 170.

[0048] The source metal layer 170 is formed on the surface of the interlayer dielectric layer 160 away from the epitaxial layer 120, and forms an ohmic contact with the source region 123 or the ohmic contact region 126 formed in the source region 123 through a contact hole structure provided in the interlayer dielectric layer 160, thereby realizing the source side electrical lead-out of the semiconductor device 100.

[0049] The drain metal layer 180 is formed on the surface (or back side) of the semiconductor substrate 110 away from the epitaxial layer 120, forming an ohmic contact with the semiconductor substrate 110, thereby realizing the drain side electrical lead-out of the semiconductor device 100.

[0050] This application achieves synergistic optimization of device conduction characteristics and short-circuit withstand capability by forming a first shielding region 124 extending in a second direction in a local area on the drift region 121, and configuring the first shielding region 124 to continuously cover the bottom of at least two adjacent and spaced gate trenches 130 in the extending direction.

[0051] Specifically, when the semiconductor device 100 is normally turned on, the body region 122 corresponding to the trench sidewall of the part of the gate trench 130 covered by the first shielding region 124 is shielded by the electric field of the first shielding region 124 below, and cannot form an inversion layer channel under the action of the gate positive bias voltage. Therefore, no channel current (or conduction current) is generated in this region. However, the body region 122 of the trench sidewall of the remaining gate trench 130 region not covered by the first shielding region 124 can normally form an inversion channel under the action of the gate voltage. Charge carriers flow into the drift region 121 through the channel and generate conduction current.

[0052] When the semiconductor device 100 is in a short-circuit condition, the high electric field generated by the high voltage on the drain side will extend to the bottom region of the gate trench 130 through the drift region 121. The first shielding region 124 can effectively shield the electric field at the bottom and corner of the gate trench 130, thereby helping to reduce the peak electric field at the bottom of the gate dielectric layer 150, suppress the drain-induced barrier reduction effect, and alleviate or avoid abnormal increase in channel carrier concentration and sharp increase in short-circuit current. At the same time, the first shielding region 124 also helps to alleviate the electric field stress concentration of the gate dielectric layer 150 during the short circuit, reduce the risk of gate dielectric layer 150 breakdown and thermal failure of semiconductor device 100, thereby helping to extend the short circuit withstand time (SCWT) of the device.

[0053] Furthermore, the number of first shielding regions 124 between the drift region 121 and the body region 122 may be multiple, and the multiple first shielding regions 124 are arranged at intervals on a plane perpendicular to the first direction.

[0054] Because multiple first shielding regions 124 are spaced apart on a plane perpendicular to the first direction, and form an alternating structure of shielded and unshielded regions (conductive channel regions) in the lateral dimension of the epitaxial layer 120. Within the region corresponding to the first shielding region 124, the bottom of the gate trench 130 is protected by the electric field of the first shielding region 124, which can reduce the electric field stress of the gate dielectric layer 150 under short-circuit conditions and suppress the drain-induced barrier reduction effect, thereby improving the short-circuit withstand capability of the semiconductor device 100. In the region between adjacent first shielding regions 124, or in other regions outside the first shielding region 124, the body region 122 adjacent to a portion of the sidewall of the gate trench 130 can normally form an inversion channel under gate voltage, thereby ensuring the normal conduction of the semiconductor device 100.

[0055] Therefore, the area ratio of the shielding area formed by the first shielding area 124 in the entire epitaxial layer 120 can be flexibly adjusted by regulating the lateral width of the first shielding area 124 extending along the first direction, the spacing between adjacent first shielding areas 124, and the arrangement density of the first shielding areas 124.

[0056] For example, on a plane perpendicular to the first direction, the vertical projection corresponding to the first shielding region 124 has a first projected area, and the vertical projection corresponding to the region jointly formed by the gate trench 130, the body region 122, and the source region 123 has a second projected area. Furthermore, the ratio of the first projected area to the second projected area can be set to a range of 5% to 50%. For example, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, thereby precisely controlling the trade-off between the specific on-resistance (Rsp) and short-circuit withstand time of the semiconductor device 100, enabling the semiconductor device 100 to adapt to the performance requirements of different voltage levels and application scenarios.

[0057] The region formed by the gate trench 130, body region 122, and source region 123 within the epitaxial layer 120 is also the active region of the semiconductor device 100, or the region corresponding to the cell structure. The vertical projection of the first shielding region 124 is located within the vertical projection plane of the source region 123.

[0058] Meanwhile, this structural design can also achieve targeted optimization of device performance without changing the overall size of the 100-cell semiconductor device and the arrangement density of the gate trenches 130, thus combining design flexibility and process compatibility.

[0059] In some embodiments, please refer to Figures 2-4 The gate trench 130 consists of a plurality of parallel and spaced strip trenches arranged on a plane perpendicular to the first direction, and the extending direction of the strip trenches intersects with the second direction.

[0060] Here, the direction in which the strip groove extends along a plane perpendicular to the first direction can be defined as the third direction, i.e. Figure 2 The Y direction, and the direction in which multiple trenches are arranged at intervals are defined as the fourth direction, i.e. Figure 2 The X2 direction is perpendicular to the third direction and the first direction, respectively.

[0061] Since the extension direction of the strip groove (the third direction) intersects with the second direction (the direction in which the first shielding area 124 extends), the second direction can be a direction that maintains a certain angle α with the fourth direction. Specifically, the angle α should be less than 90°; for example, the angle α should not exceed 60°; or, the angle α should not exceed 45°; or, the angle α should not exceed 15°; or, the angle α should approach 0°, so that the second direction and the fourth direction are essentially in the same direction.

[0062] Please see Figure 1 and Figure 2, Figure 2 This is a top view schematic diagram of a semiconductor device 100 according to an embodiment of this application. Figure 1 According to Figure 2 The intercept line AA' is captured.

[0063] For example, please refer to Figure 2 The second direction and the fourth direction are basically in the same direction. Multiple first shielding areas 124 are arranged in an array in the second direction and the third direction, parallel to each other and spaced apart. In the second direction, at least two strip grooves are located in the interval area between two adjacent first shielding areas 124.

[0064] Because a gap region is provided between two adjacent first shielding regions 124 in the fourth direction, and at least two strip gate trenches 130 are arranged in the gap region, the gate trenches 130 in the gap region are not affected by the electric field shielding of the first shielding region 124. The body region 122 adjacent to its sidewall can normally form an inversion channel and provide a conduction current path under the gate voltage. The gate trenches 130 covered by the first shielding region 124 can give full play to the electric field shielding effect and reduce the electric field stress of the gate dielectric layer 150 under short-circuit conditions. This is beneficial to simplify the number of first shielding regions 124 and the process complexity while ensuring the overall conduction capability of the device, and to achieve flexible adjustment of specific on-resistance and short-circuit withstand capability.

[0065] Please see Figure 1 and Figure 3 , Figure 3 This is a top view schematic diagram of a semiconductor device 100 according to an embodiment of this application. Figure 1 According to Figure 3 The cut-off line BB' in the middle is cut off and obtained.

[0066] For example, please refer to Figure 3 The second direction and the fourth direction are basically in the same direction. Multiple first shielding areas 124 are arranged in an array in the second direction and the third direction, parallel to each other and spaced apart. In the second direction, at least two strip grooves are located in the interval area between two adjacent first shielding areas 124, and at least one first shielding area 124 is located in the interval area. The first shielding areas 124 located in the interval area are staggered with the first shielding areas 124 outside the interval area.

[0067] Please see Figure 1 and Figure 4 , Figure 4 This is a top view schematic diagram of a semiconductor device 100 according to an embodiment of this application. Figure 1 According to Figure 4 The intercept line CC' in the code is used to capture and obtain the data.

[0068] For example, please refer to Figure 4 The second direction and the fourth direction maintain an angle α. The plurality of first shielding areas 124 are arranged in an array in the fourth direction and the third direction, parallel to each other and spaced apart. In the fourth direction, at least two strip grooves are located in the interval region between two adjacent first shielding areas 124, and at least one first shielding area 124 is located in the interval region. The first shielding areas 124 located in the interval region are staggered with the first shielding areas 124 outside the interval region.

[0069] The first shielding area 124 located in the interval area and the first shielding area 124 outside the interval area are staggered, so that the first shielding areas 124 can be staggered on the plane perpendicular to the first direction. This is beneficial to allow the shielded area and the unshielded area to alternate on the plane perpendicular to the first direction. This can ensure the uniform distribution of the conduction current in the cell surface of the semiconductor device 100, avoid the problem of heat concentration caused by excessive local current density, and make the electric field shielding effect uniformly cover the entire cell area. This effectively suppresses the electric field concentration and current surge under short-circuit conditions, further improves the uniformity of the short-circuit withstand capability and the overall reliability of the semiconductor device 100, and achieves a better balance than the conduction resistance and short-circuit withstand time.

[0070] Please see Figure 1 and Figure 5 , Figure 5 This is a top view schematic diagram of a semiconductor device 100 according to an embodiment of this application. Figure 1 According to Figure 5 The cut-off line DD' in the middle is used to capture and obtain the cut-off line.

[0071] In other embodiments, please refer to Figure 5 The gate trench 130 consists of a plurality of annular trenches that are adjacent to each other and arranged in an array on a plane perpendicular to the first direction, and the vertical projection of at least one annular trench is located within the vertical projection plane of the first shielding area 124.

[0072] Here, an annular trench refers to a gate trench 130 extending in a closed ring along a plane perpendicular to the first direction, including but not limited to continuous closed annular trenches, and the shape of the central region enclosed by the annular trench includes but is not limited to a quadrilateral, hexagon, or octagon with a centrally symmetrical structure. In this context, the second direction refers to any direction along a plane perpendicular to the first direction, which is also the direction in which the plane extends. The first shielding region 124 at least continuously covers the bottom of two adjacent and spaced-apart gate trenches 130 in the second direction, or it can refer to at least two adjacent or opposite trench boundaries of the same annular trench.

[0073] For example, the central region enclosed by the annular trenches is a regular hexagon with a central symmetry structure. Multiple regular hexagonal annular trenches are arranged closely adjacent to each other within the plane of the epitaxial layer 120, forming a honeycomb-like cell array structure 127. This cell array structure 127 allows the gate trenches 130 to achieve a higher arrangement density and space utilization rate in the plane compared to strip gate trenches 130, which is beneficial for increasing the effective channel width per unit area, thereby reducing the specific on-resistance of the semiconductor device 100. Simultaneously, the central symmetry configuration of the regular hexagons also makes the electric field distribution at the corners of the gate trenches 130 more uniform, avoiding reliability problems of the gate dielectric layer 150 caused by electric field concentration.

[0074] Since the vertical projection of at least one annular trench is located within the vertical projection plane of the first shielding area 124, that is, the first shielding area 124 forms a full-coverage electric field shield for the bottom of part of the annular trench, the shielded annular trench area can effectively reduce the electric field peak at the bottom of the gate dielectric layer 150 under short-circuit conditions, suppress the drain-induced barrier reduction effect, and improve the short-circuit withstand capability of the device; while the remaining annular trenches not covered by the first shielding area 124 can normally form inversion channels, ensuring the conduction current capability of the semiconductor device 100.

[0075] In the cell array structure 127 composed of multiple annular grooves, the number of unshielded annular grooves not covered by the first shielding area 124 and the number of shielded annular grooves covered by the first shielding area 124 are kept in a preset ratio, so that the two together constitute a complete array unit.

[0076] For example, please continue reading Figure 5 By configuring the ratio of the number of annular trenches not covered by the first shielding region 124 to the number of annular trenches covered by the first shielding region 124 in each cell array structure 127 to be 8:1, the short-circuit withstand capability can be significantly improved while sacrificing only a small amount of conductive channel area and keeping the specific on-resistance degradation under control, thus achieving an optimized balance between specific on-resistance and short-circuit withstand time. Simultaneously, this array unit can also be periodically expanded as a repeating unit within the plane of the epitaxial layer 120, combining design regularity and process feasibility, facilitating targeted control of device performance and mass production.

[0077] It should be noted that the 8:1 configuration in the above example is merely illustrative and should not be construed as a limitation of this application. In other embodiments, the ratio of the number of annular trenches not covered by the first shielding region 124 to the number of annular trenches covered by the first shielding region 124 in each cell array structure 127 can be flexibly adjusted according to the shape of the annular trenches, the target voltage level of the semiconductor device 100, the application scenario, and performance trade-offs. For example, please refer to [further details omitted]. Figure 6The ratio of the number of annular grooves not covered by the first shielding region 124 to the number of annular grooves covered by the first shielding region 124 in each cell array structure 127 can be configured to 7:1. Alternatively, please refer to [link to relevant documentation]. Figure 7 Alternatively, the ratio of the number of annular grooves not covered by the first shielding area 124 to the number of annular grooves covered by the first shielding area 124 in each cell array structure 127 can be configured as 4:1. Or, in other embodiments, the ratio of the number of annular grooves not covered by the first shielding area 124 to the number of annular grooves covered by the first shielding area 124 in each cell array structure 127 can be configured as any reasonable ratio such as 3:1, 6:1, 11:1, 15:1, etc., and non-integer ratios can be used according to specific performance requirements; these will not be elaborated further here.

[0078] In some embodiments, please continue reading Figure 8 , Figure 8 According to Figure 2 The intercept line AA' is used to extract the data, or it can be obtained based on... Figure 3 The cutoff line BB' in the middle is used to extract the data, or it can be obtained based on... Figure 4 The cutoff line CC' in the code is used to extract the data, or it can be obtained based on... Figure 5 The intercept line DD' is intercepted and obtained. The epitaxial layer 120 also includes a second shielding region 125 having a second conductivity type. The second shielding region 125 is located above the drift region 121 and is adjacent to a portion of the surface of the body region 122 near the drift region 121. Furthermore, on a plane perpendicular to the first direction, the second shielding region 125 is arranged around the periphery of the gate trench 130 and maintains a preset distance from the trench.

[0079] Since the second shielding region 125 has the same second conductivity type as the first shielding region 124 and the body region 122, and is arranged around the periphery of the gate trench 130 and maintains a distance from the gate trench 130, the second shielding region 125 can form a ring-shaped P-type shielding structure around the gate trench 130, thereby providing lateral shielding for the electric field at the sidewalls and corners of the gate trench 130.

[0080] Therefore, when the semiconductor device 100 is off, the second shielding region 125 can effectively suppress the high electric field in the drift region 121 from extending toward the sidewall of the gate trench 130, thereby reducing the electric field peak at the sidewall of the gate dielectric layer 150 and the corner of the bottom of the trench, avoiding the breakdown of the gate dielectric layer 150 due to electric field concentration, and improving the breakdown voltage and gate dielectric reliability of the semiconductor device 100. Furthermore, under short-circuit conditions, the second shielding region 125 can work in conjunction with the first shielding region 124 to form an all-round electric field shield for the gate trench 130 from the bottom and the side periphery, further suppressing the drain-induced barrier reduction effect, limiting the sharp increase of short-circuit current, and effectively extending the short-circuit withstand time of the device.

[0081] Meanwhile, since there is a preset distance between the second shielding region 125 and the gate trench 130, the body region 122 within this distance range can still form an inversion channel normally under the gate voltage, and will not completely block the conduction current path due to the introduction of the second shielding region 125. Thus, while improving the device's blocking capability and short-circuit withstand performance, the degradation of the specific on-resistance is controlled within a reasonable range, achieving synergistic optimization of multiple key performance parameters of the device.

[0082] The first shielding region 124 has a first contact surface that contacts the drift region 121, and there is a first gap between the first contact surface and the surface of the epitaxial layer 120 adjacent to the source region 123. The first gap is also the junction depth of the first shielding region 124. The second shielding region 125 has a second contact surface that contacts the drift region 121, and there is a second gap between the second contact surface and the surface of the epitaxial layer 120 adjacent to the source region 123. The second gap is also the junction depth of the second shielding region 125. Furthermore, the first gap is not greater than the second gap.

[0083] Since the junction depth of both the first shielding region 124 and the second shielding region 125 is greater than 2 μm, the required ion implantation energy may exceed 2 MeV if conventional vertical incidence ion implantation is used to achieve this junction depth. High-energy ion implantation will cause severe implantation damage to the lattice structure of the surface region of the epitaxial layer 120 and introduce a large number of defects, thereby degrading the electrical performance and reliability of the semiconductor device 100. On the other hand, in order to achieve selective ion implantation and block the penetration of high-energy ions, the required thickness of the implantation mask layer also needs to be increased accordingly. For example, the mask layer thickness may exceed 3.5 μm. However, an excessively thick mask layer makes it difficult to achieve fine pattern resolution in photolithography and etching processes, which further limits the space for reducing cell size and restricts the improvement of cell density.

[0084] Therefore, this application sets the ion implantation direction of the first shielding region 124 and the second shielding region 125 to be along the [11-20] crystal orientation of the silicon carbide substrate. Utilizing the channel effect formed by the atomic arrangement of the silicon carbide single crystal along a specific crystal orientation, the implanted ions can penetrate deep into the epitaxial layer 120 along the crystal orientation channel, thereby significantly reducing the ion implantation energy required to achieve the same junction depth. The implantation energy can be reduced from the conventional 2MeV level to approximately 400keV. This reduction in implantation energy effectively reduces lattice damage caused by ion implantation, ensuring the crystal quality of the epitaxial layer 120. Simultaneously, it can significantly reduce the thickness requirement of the implantation mask layer, for example, reducing the mask layer thickness to approximately 2μm. A thinner mask layer can support finer lithographic pattern resolution, allowing the cell spacing to be reduced from 3μm to approximately 2μm. This is beneficial for increasing the cell density of the semiconductor device 100, providing a process implementation basis for further reducing specific on-resistance and improving the overall device performance.

[0085] Furthermore, by setting the junction depth of the second shielding region 125 to be no less than the junction depth of the first shielding region 124, the second shielding region 125 can extend in the first direction toward one side of the drift region 121 to a position equivalent to or even deeper than the first shielding region 124, thereby forming a shielding connection in the depth direction with the first shielding region 124. That is, the first shielding region 124 provides longitudinal electric field shielding from the bottom of the gate trench 130, and the second shielding region 125 provides lateral electric field shielding from the periphery of the gate trench 130. Together, they constitute an all-round electric field shielding structure for the bottom and sidewalls of the gate trench 130.

[0086] Furthermore, when the junction depths of the first shielding region 124 and the second shielding region 125 are similar, they can be formed simultaneously using the same mask layer and through the same ion implantation process, thereby effectively simplifying the fabrication process of the semiconductor device 100, reducing the number of photomasks used and the number of ion implantation processes, reducing process complexity and manufacturing costs, and improving production efficiency.

[0087] Furthermore, using the same mask layer and the same implantation process to prepare two shielding regions can ensure good matching between them in terms of doping concentration distribution and junction depth consistency, avoid process deviations introduced by multiple implantations, improve the uniformity of device performance and batch stability, and further ensure the electrical performance and yield of semiconductor device 100.

[0088] For example, the concentration range of P-type doping within the body region 122 is 1e17cm. -3 ~1e18 cm -3 The concentration range of P-type doping within the first shielding region 124 is 1e18cm. -3 ~1e19 cm -3 .

[0089] It should be noted that, since the first shielding area 124 extends along the second direction, the positional relationship between its two ends in the extension direction and the adjacent second shielding area 125 can be flexibly configured according to actual design requirements. For example, the two ends in the extension direction of the first shielding area 124 can be adjacent to the sidewall of the adjacent second shielding area 125, or they can extend into the internal area of ​​the adjacent second shielding area 125; or, refer to... Figure 9 The two ends of the first shielding region 124 extending in the direction of extension can also maintain a certain gap distance with the adjacent second shielding region 125. This application does not impose any special restrictions on the specific positional connection relationship between the first shielding region 124 and the second shielding region 125. Those skilled in the art can make reasonable selections based on the electric field shielding requirements of the semiconductor device 100, process conditions, and performance trade-off objectives.

[0090] It should also be noted that the aforementioned semiconductor device 100 can be a diode device, a transistor device, or a combination thereof. The diode device can include, but is not limited to, power diodes, merged PiN Schottky (MPS) diodes, Schottky diodes, metal-oxide-semiconductor gate-controlled diodes, etc. The transistor device includes, but is not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), insulated-gate bipolar transistors (IGBTs), FinField-Effect Transistors (FinFETs), high-electron-mobility transistors (HEMTs), thyristors, etc.

[0091] Alternatively, the semiconductor device 100 may be made of any semiconductor material suitable for manufacturing semiconductor chips, including but not limited to elemental semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), and binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide (InGaAsP).

[0092] According to a third aspect of this application, a power module is also provided.

[0093] Please see Figure 10 The power module 200 of this application embodiment includes a substrate 210 and a semiconductor device 100 disposed on the substrate 210. The semiconductor device 100 includes, but is not limited to, the semiconductor device 100 described in any of the embodiments of the first aspect above.

[0094] Here, substrate 210 refers to the basic support component in power module 200 used to support and fix semiconductor device 100 and realize electrical connection and heat conduction. It can form a physical bonding, welding or packaged integration connection with semiconductor device 100, providing mechanical support, circuit conduction path or heat dissipation channel for semiconductor device 100.

[0095] The specific type of substrate 210 can be flexibly selected according to the application scenario and power requirements of the power module 200, including but not limited to direct bonding copper substrate (DBC), active metal brazed ceramic substrate (AMB), low temperature co-fired ceramic substrate (LTCC), ceramic substrate, metal core printed circuit board (MCPCB), printed circuit board (PCB), insulated metal substrate (IMS), aluminum nitride ceramic substrate (AlN substrate), composite material substrate (such as AlSiC substrate, glass ceramic substrate), etc. This application does not limit the specific type of substrate 210 selected in the power module 200.

[0096] Furthermore, the electronic power equipment equipped with power semiconductor devices in the power modules of this application embodiment can be applied to various fields such as new energy power generation, power transmission, rail transportation, industrial control, new energy vehicles, consumer electronics, and aerospace. Specifically, it can include photovoltaic inverters, wind power converters, grid converter valves, locomotive traction converters, industrial frequency converters, vehicle power controllers, charging piles, power adapters, energy storage systems, etc., and this application embodiment does not limit this. Those skilled in the art can adapt the specifications of the semiconductor device 100 and the circuit topology of the power module 200 according to the power, voltage, integration, and other requirements of the actual application scenario. Moreover, the power module 200 equipped with the semiconductor device 100 described in this application can achieve higher energy conversion efficiency, more stable operation, and longer service life because the device has both excellent high-voltage reliability and switching performance.

[0097] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the spirit and scope of the technical solutions of this application.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate and an epitaxial layer situated on the semiconductor substrate; wherein the epitaxial layer comprises: A drift region having a first conductivity type and located on the side of the epitaxial layer closer to the semiconductor substrate; The body region has a second conductivity type and is located above the drift region; The source region has a first conductivity type and is located above the body region, adjacent to a portion of the surface of the epitaxial layer on the side opposite to the semiconductor substrate. A first shielding region having a second conductivity type is located above the drift region and is adjacent to a portion of the surface of the body region on the side closest to the drift region. A gate trench is located on the drift region and extends through the body region and the source region along a first direction; and the first shielding region continuously covers the bottom of at least two adjacent and spaced-apart gate trenches in a second direction; wherein, the first direction is the direction of the epitaxial layer thickness, the second direction is the direction in which the first shielding region extends, and the second direction is perpendicular to the first direction.

2. The semiconductor device according to claim 1, characterized in that, The epitaxial layer further includes: The second shielding region has a second conductivity type and is located above the drift region, adjacent to a portion of the surface of the body region on the side near the drift region. Furthermore, on a plane perpendicular to the first direction, the second shielding region surrounds the periphery of the gate trench and maintains a distance from the gate trench.

3. The semiconductor device according to claim 2, characterized in that, The first shielding area is adjacent to the sidewall of the adjacent second shielding area at its two opposite ends in the first direction, or is located within the adjacent second shielding area.

4. The semiconductor device according to claim 2, characterized in that, The first shielding region has a first contact surface that contacts the drift region, and the second shielding region has a second contact surface that contacts the drift region. In the first direction, there is a first distance between the first contact surface and the surface of the epitaxial layer adjacent to the source region, and there is a second distance between the second contact surface and the surface of the epitaxial layer adjacent to the source region. Furthermore, the first distance is not greater than the second distance.

5. The semiconductor device according to claim 2, characterized in that, The doping concentrations of impurity ions of the second conductivity type in the first shielding region and the second shielding region are matched with each other, and are both greater than the doping concentration of impurity ions of the second conductivity type in the body region.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The number of the first shielding areas between the drift region and the body region includes a plurality of such areas, and the plurality of first shielding areas are spaced apart from each other on a plane perpendicular to the first direction.

7. The semiconductor device according to claim 6, characterized in that, On a plane perpendicular to the first direction, the gate trench is a plurality of parallel and spaced strip trenches, and the extending direction of the strip trenches intersects the second direction.

8. The semiconductor device according to claim 7, characterized in that, In the second direction, a plurality of the first shielding zones are spaced apart from each other, and at least two of the strip grooves are located in the gap between two adjacent first shielding zones.

9. The semiconductor device according to claim 7, characterized in that, At least one of the first shielding areas is located in the interval region, and the first shielding area located in the interval region is staggered with two adjacent first shielding areas in the second direction.

10. The semiconductor device according to claim 6, characterized in that, On a plane perpendicular to the first direction, the gate trench is a plurality of adjacent annular trenches arranged in an array, and the vertical projection of at least one of the annular trenches is located within the vertical projection plane of the first shielding area.

11. The semiconductor device according to claim 10, characterized in that, On a plane perpendicular to the first direction, the annular trench encloses a region that is one of a quadrilateral, hexagon, or octagon with a centrally symmetrical structure.

12. The semiconductor device according to claim 10, characterized in that, In the second direction, a plurality of the first shielding zones are spaced apart from each other, and at least two of the annular grooves are located in the gap between two adjacent first shielding zones.

13. The semiconductor device according to any one of claims 6 to 12, characterized in that, On a plane perpendicular to the first direction, the vertical projection of the first shielding region has a first projected area, and the vertical projection of the region composed of the gate trench, the body region, and the source region has a second projected area. The ratio of the first projected area to the second projected area is in the range of 5% to 50%.

14. A power module, characterized in that, include: Substrate: and The semiconductor device according to any one of claims 1 to 13, wherein the semiconductor device is located on the substrate.

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