Semiconductor device, detection chip, and detection apparatus
Patent Information
- Application Number
- CN202510344298.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-21
- Publication Date
- 2026-09-22
Smart Images
Figure CN122803344A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electrochemical detection technology, and more specifically, to semiconductor devices, detection chips, and detection apparatus. Background Technology
[0002] Thin-film transistors (TFTs) are widely used in electrochemical detection due to their high sensitivity. However, the performance of single-gate TFTs is easily affected by the fabrication process, leading to large performance differences between sensors, threshold voltage drift, and insufficient measurement stability. To address this, a measurement scheme based on a dual-gate structure has been proposed. In this dual-gate structure, one gate is used to adjust the threshold voltage, while the other gate is connected to an extended gate for signal detection.
[0003] Currently, dual-gate structures are mainly divided into two types: top-gate and bottom-gate, and top-gate liquid-gate. For the top-gate and bottom-gate structure, although the individual top and bottom gates have mature processes, their combination increases process complexity, reduces fabrication stability, and imposes limitations on the active layer material. Furthermore, the introduction of the bottom gate introduces a step effect, affecting device performance. For the top-gate liquid-gate structure, using a silver / silver chloride electrode as a reference electrode improves measurement accuracy, but limitations such as the need for liquid replenishment, large size, and frequent insertion into the reaction tank make it unsuitable for large-scale, integrated production.
[0004] Therefore, there is an urgent need to propose a detection chip that is simple in structure, easy to improve in manufacturing process, and easy to mass-produce and integrate. Summary of the Invention
[0005] This application provides a semiconductor device, a detection chip, and a detection apparatus. The semiconductor device has a simple structure and is relatively easy to improve in terms of manufacturing process. When applied to a detection chip, it is also easy to achieve large-scale mass production and integration of the detection chip.
[0006] In a first aspect, a semiconductor device is provided, comprising: a source electrode located inside the semiconductor device; a drain electrode located inside the semiconductor device; a first gate electrode located between the source electrode and the drain electrode, wherein a first lead-out terminal of the first gate electrode extending from inside the semiconductor device is connected to an external power supply; a first extended electrode connected to the first lead-out terminal; a second gate electrode connected to the first gate electrode inside the semiconductor device; and a second extended electrode electrode connected to a second lead-out terminal of the second gate electrode extending from inside the semiconductor device, wherein the first extended electrode electrode and the second extended electrode electrode are adjacent to each other but not in contact.
[0007] In conjunction with the first aspect, in some implementations of the first aspect, the first extended electrode is a finger-shaped electrode, including a first body and at least one first sub-electrode, the at least one first sub-electrode being connected to the first body; the second extended electrode is a finger-shaped electrode, including a second body and at least one second sub-electrode, the at least one second sub-electrode being connected to the second body; the first body and the second body are arranged in parallel, and the first sub-electrode and the second sub-electrode are arranged alternately to form an interdigitated structure.
[0008] In conjunction with the first aspect, in some implementations of the first aspect, the distance between the first gate and the source or drain is less than or equal to the electron diffusion distance, where the electron diffusion distance is the distance by which the first gate or the second gate affects electron transport within the semiconductor device; the distance between the second gate and the source or drain is less than or equal to the electron diffusion distance; when there are multiple first sub-electrodes, the distance between two adjacent first sub-electrodes in the first extended electrode is greater than or equal to the electron diffusion distance and less than or equal to twice the electron diffusion distance; when there are multiple second sub-electrodes, the distance between two adjacent second sub-electrodes in the second extended electrode is greater than or equal to the electron diffusion distance and less than or equal to twice the electron diffusion distance.
[0009] In conjunction with the first aspect, in some implementations of the first aspect, the projection of the interdigitated structure vertically into the interior of the semiconductor device is located between the source and the drain.
[0010] In conjunction with the first aspect, in some implementations of the first aspect, the first gate is integrally formed with the first extended electrode; the second gate is integrally formed with the second extended electrode.
[0011] In conjunction with the first aspect, in some implementations of the first aspect, the first gate, the second gate, the first extended electrode, and the second extended electrode are made of the same material.
[0012] In conjunction with the first aspect, in some implementations of the first aspect, the semiconductor device further includes: an extended gate covering the second lead, the extended gate being modified with a detection connector for specifically binding to a target in a test sample.
[0013] In conjunction with the first aspect, in some implementations of the first aspect, the number of the second gate and the second extended electrode is multiple.
[0014] In conjunction with the first aspect, in some implementations of the first aspect, the number of the second gate, the second extended electrode, and the extended gate is multiple.
[0015] In conjunction with the first aspect, in some implementations of the first aspect, the detection connectors of the aforementioned multiple extended gate modifications are different.
[0016] In conjunction with the first aspect, in some implementations of the first aspect, when one of the multiple extended gates is used to detect a test sample, the second lead and the first lead covered by the remaining extended gates of the multiple extended gates are connected to an external power supply.
[0017] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned extended gate includes an inert metal.
[0018] In a second aspect, a detection chip is provided, comprising a semiconductor device in any possible implementation of the semiconductor device design described in the first aspect above.
[0019] Thirdly, a detection device is provided, comprising a detection chip in any possible implementation of the detection chip design as described in the second aspect above. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the structure of a TFT device suitable for electrochemical detection chips;
[0021] Figure 2 This is a schematic diagram of the structure of a semiconductor device 200 according to an embodiment of this application;
[0022] Figure 3 This is a schematic diagram of the charge distribution in a semiconductor device;
[0023] Figure 4 This is a schematic diagram of the structure of another semiconductor device 200 proposed in the embodiments of this application;
[0024] Figure 5 This is a schematic diagram of the charge distribution pattern inside a semiconductor device 200 according to an embodiment of this application;
[0025] Figure 6 This is a schematic diagram of the structure of another semiconductor device 200 proposed in the embodiments of this application;
[0026] Figure 7 This is a schematic diagram of the structure of another semiconductor device 200 proposed in the embodiments of this application;
[0027] Figure 8 This is a schematic diagram of the structure of another semiconductor device 200 proposed in the embodiments of this application;
[0028] Figure 9 This is a schematic flowchart of a semiconductor device fabrication method 900 proposed in an embodiment of this application. Detailed Implementation
[0029] The technical solutions in this application will now be described with reference to the accompanying drawings.
[0030] This application will present various aspects, embodiments, or features relating to a system comprising multiple devices, components, modules, etc. It should be understood and appreciated that individual systems may include additional devices, components, modules, etc., and / or may not include all the devices, components, modules, etc. discussed in conjunction with the accompanying drawings. Furthermore, combinations of these approaches are also possible.
[0031] Furthermore, in the embodiments of this application, the words "exemplary," "for example," etc., are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" in the embodiments of this application should not be construed as being better or more advantageous than other embodiments or design schemes. Specifically, the use of the term "exemplary" is intended to present the concept in a concrete manner.
[0032] The business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.
[0033] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0034] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.
[0035] In the description of the embodiments of this application, the terms "upper," "lower," "left," "right," "inner," "outer," "vertical," and "horizontal," etc., indicate the orientation or positional relationship relative to the orientation or position of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and not to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. They can change accordingly depending on the orientation of the components in the accompanying drawings, and therefore should not be construed as limiting this application.
[0036] In the embodiments of this application, the same reference numerals are used to denote the same component or part. For the same part in the embodiments of this application, only one part or component may be labeled with reference numerals in the figures. It should be understood that the reference numerals also apply to other identical parts or components. In addition, the various parts in the figures are not drawn to scale, and the dimensions and sizes of the parts shown in the figures are only exemplary and should not be construed as limiting this application.
[0037] An electrochemical detection chip is a miniaturized chip that uses electrochemical principles for information processing and sensing. It combines the advantages of electrochemistry and micro-nano technology, and by integrating electrochemical sensors and circuits on a tiny chip, it can detect, analyze or convert energy of specific chemical substances.
[0038] Electrochemical detection chips can achieve accurate detection of trace chemical substances, which makes them promising for applications in fields such as biological detection, environmental monitoring, and food safety.
[0039] In the field of biological detection, electrochemical detection chips can integrate biosensors to detect specific biomarkers in biological samples (such as blood, urine, and saliva), including proteins, hormones, and metabolites. These biomarkers are often closely related to the occurrence and development of diseases; therefore, electrochemical detection chips can be used for early disease diagnosis, buying patients valuable treatment time. Furthermore, through precise detection of biological samples using electrochemical detection chips, doctors can understand a patient's specific condition and physiological state, thereby developing personalized treatment plans to improve treatment effectiveness, reduce unnecessary drug use, and lower the economic burden and physical harm on patients. In addition, electrochemical detection chips can also be used to assess the immune response after vaccination. By detecting the level of antibodies produced in the recipient's body, the effectiveness of the vaccine and the recipient's immune status can be determined.
[0040] In the field of environmental monitoring, electrochemical detection chips can monitor the concentration of pollutants in the atmosphere in real time, such as sulfur dioxide, nitrogen oxides, and ozone. This helps in the timely detection of air pollution problems, providing environmental protection departments with scientific evidence to formulate effective control measures. Furthermore, electrochemical detection chips also have important applications in water quality monitoring. They can measure parameters such as conductivity, pH value, and dissolved oxygen in water, as well as detect harmful substances such as heavy metal ions and organic pollutants. This helps ensure drinking water safety, promptly detect and address water pollution problems, and protect public health. Electrochemical detection chips can also be used to monitor the composition and concentration of emissions from industrial waste gas and wastewater. This helps environmental protection departments strengthen supervision of enterprises, ensure compliant emissions, and reduce environmental pollution.
[0041] In the field of food safety, electrochemical detection chips, integrated with specific sensors, can detect pesticide residues in food, protecting consumer health. Simultaneously, these chips can also be used to accurately detect food additives, such as preservatives, colorings, and sweeteners, ensuring their levels comply with regulations. Regarding heavy metal contamination, electrochemical detection chips offer high sensitivity and selectivity for accurate detection of heavy metal content in food, allowing for timely responses to contamination issues. Furthermore, they can be used to detect food allergens, such as those found in peanuts and milk, meeting the dietary needs of specific populations and preventing allergic reactions. Electrochemical detection chips can also be used to assess food freshness by detecting indicators such as volatile compounds, helping manufacturers and consumers understand the state of food, ensuring its optimal consumption period, and improving its taste and nutritional value.
[0042] Electrochemical detection chips offer significant advantages in real-time monitoring and rapid diagnostics due to their rapid response capabilities, enabling the detection and analysis of chemical substances within a short time. Furthermore, their design and manufacturing emphasize low power consumption, ensuring performance while minimizing energy consumption. This makes them ideal for devices requiring long-term operation or portable devices. TFT electrochemical detection chips, with their high sensitivity, good selectivity, and rapid response characteristics, have become a research hotspot in recent years.
[0043] Figure 1 This is a schematic diagram of the structure of a TFT device suitable for electrochemical detection chips.
[0044] refer to Figure 1As shown, a TFT device includes a channel layer, a source (S), a gate (G), and a drain (D). The channel layer, also known as the channel layer, forms a conductive channel under the action of the gate voltage, allowing current to flow between the source and the drain. The source, as the current input terminal, is connected to the channel layer, thus forming the current input channel. The gate, as the control terminal, controls the conductivity state of the channel layer by applying a voltage. The gate and the channel layer are isolated by a gate insulating layer. The drain, as the current output terminal, is connected to the channel layer, thus forming the current output channel.
[0045] As explained above, a change in gate voltage leads to a change in the current between the source and drain. Based on this principle, detection units (e.g., different antibodies, enzymes, or deoxyribonucleic acid (DNA) chains) can be modified onto the gate. When the analyte (target or target molecule) in the test sample specifically binds to the detection unit, the induced charge on the gate changes, generating a gate voltage, which in turn causes a change in the current between the source and drain. As the concentration of the analyte in the test sample increases, the amount of analyte bound to the detection unit on the gate surface increases, leading to an increase in charge, gate voltage, and the change in current between the source and drain. Therefore, a correlation can be established between the change in current between the source and drain and the change in the concentration of the analyte, thus enabling the detection of the analyte.
[0046] The core advantage of TFT electrochemical detection chips lies in their high integration and controllability. Through the switching characteristics of thin-film transistors, the signal readout of the electrochemical sensing unit can be precisely controlled, achieving low-noise, high-sensitivity detection. For example, in medical diagnostics, TFT chips can rapidly detect metabolites such as glucose and lactic acid in blood, supporting personalized medicine. However, the complexity of TFT manufacturing processes has become a major obstacle to its development. The threshold voltage of thin-film transistors is easily affected by material defects, interface states, and process fluctuations, leading to significant performance differences between sensors. Furthermore, traditional single-gate structures cannot simultaneously meet the requirements of high sensitivity and wide dynamic range, necessitating the optimization of electric field distribution through dual-gate structures. This need has driven research into novel device architectures, among which dual-gate structures have attracted attention due to their ability to separate threshold voltage adjustment and signal detection functions.
[0047] The application of dual-gate structures in electrochemical detection chips primarily aims to enhance the chip's control over electrochemical processes, thereby improving detection accuracy and sensitivity. The following is a general introduction to dual-gate structures:
[0048] Dual-gate structures typically contain two gate electrodes located at different layers or positions on the chip, enabling independent regulation of electrochemical processes within the chip. This structure allows for more precise control of electrochemical reactions without affecting other properties, thereby improving detection accuracy. In dual-gate electrochemical detection chips, the two gate electrodes can be used to independently adjust the electric field distribution and charge carrier density within the chip by applying different voltages. This adjustability allows the chip to more flexibly address diverse detection needs, such as precise measurements of chemicals at varying concentrations. Furthermore, dual-gate structures can also lead to other performance improvements, such as enhanced chip stability and reduced noise interference. These performance enhancements contribute to improving the overall performance and reliability of electrochemical detection chips.
[0049] The dual-gate structures used in electrochemical detection chips mainly include top-gate and bottom-gate dual-gate structures and top-gate and liquid-gate dual-gate structures.
[0050] The top-gate and bottom-gate dual-gate structure theoretically significantly improves device performance by independently adjusting the threshold voltage and signal detection through two gates. The top gate dynamically adjusts the channel electric field, while the bottom gate amplifies the signal through an extended gate. The main technological challenges of this structure lie in three aspects: increased process complexity due to film layer stacking, limited compatibility of active layer materials, and step effects and ramp-up losses. For example, the introduction of the bottom gate leads to steps in the active layer, lengthening the carrier migration path, increasing energy loss, and potentially causing localized electric field concentration. Specifically, while multilayer thin-film technology is maturely applied in traditional display panel manufacturing, electrochemical detection chips have more stringent requirements for film thickness uniformity, interface passivation effects, and doping precision. This complexity makes yield control a challenge for top-gate and bottom-gate structures during mass production, especially when the choice of active layer materials is limited, such as low-temperature polycrystalline silicon or graphene, where only the surface active layer is effective. The introduction of the bottom gate structure can disrupt its electrical properties, further limiting the stability of device performance.
[0051] The top-gate liquid-gate dual-gate structure improves measurement accuracy by introducing a silver / silver chloride reference electrode (liquid gate) immersed in the electrolyte, eliminating electrostatic interference and polarization current. While this structure performs excellently in laboratory settings, practical applications face challenges related to electrolyte replenishment and volume limitations, poor process compatibility, and long-term stability. For example, the silver / silver chloride electrode requires periodic electrolyte replenishment to maintain potential stability, and its relatively large size makes integration into miniaturized chips difficult. This issue is particularly pronounced in miniaturized detection devices, where space constraints necessitate miniaturized electrode dimensions, and frequent electrolyte replenishment is clearly unsuitable for large-scale production applications.
[0052] In view of this, embodiments of this application propose a semiconductor device, a detection chip, and a detection apparatus. The semiconductor device has a simple structure, is relatively easy to improve in terms of manufacturing process, and is easy to mass-produce and integrate.
[0053] Figure 2 This is a schematic diagram of the structure of a semiconductor device 200 according to an embodiment of this application. Figure 2 (a) in the figure is a perspective side view of semiconductor device 200. Figure 2 (b) is a perspective top view of semiconductor device 200.
[0054] Semiconductor device 200 includes:
[0055] Source 210, which is located inside semiconductor device 200.
[0056] Drain 220, which is located inside semiconductor device 200.
[0057] The first gate 230 is located between the source 210 and the drain 220. The first gate 230 has a first lead-out terminal 231 extending from inside the semiconductor device 200 and is connected to an external power supply.
[0058] The first extension electrode 240 is connected to the first lead-out terminal 231.
[0059] The second gate 250 is connected to the first gate 230 inside the semiconductor device 200.
[0060] The second extended electrode 260 is connected to the second lead 251 of the second gate 250 that is led out from inside the semiconductor device 200, and the first extended electrode 240 is adjacent to the second extended electrode 260 but not in contact.
[0061] As can be seen from the above-described structural form, the semiconductor device 200 proposed in this application embodiment is a transistor with a dual-gate structure.
[0062] In some possible embodiments, reference Figure 2As shown, the first gate 230 and the second gate 250 can be the top gate of the semiconductor device 200. Therefore, the issue of limited fabrication materials for the semiconductor device 200 due to the introduction of a bottom gate, as mentioned in the previous description, is not involved. Since both gates are bottom gates, there is no need to fabricate a film structure for the bottom gate, ensuring a relatively simple fabrication process. Of course, in some specific applications of semiconductor devices, to adapt the semiconductor device to specific circuits, the first gate 230 and the second gate 250 in the semiconductor device 200 can be designed as a double bottom gate structure or a top gate and a bottom gate structure.
[0063] In some possible embodiments, the semiconductor device 200 may include the following film structure:
[0064] Basal layer 201.
[0065] The channel layer (or active layer) 202 is located above the base layer 201, and the source electrode 210 and drain electrode 220 are respectively connected to the channel layer 202.
[0066] The first dielectric layer 203 covers the channel layer 202. The first gate 230 is located on the first dielectric layer 203, and the second gate 250 is connected to the first gate 230, so the second gate 250 is also located on the first dielectric layer 203.
[0067] The second dielectric layer 204 is located above the first dielectric layer 203 and is used to isolate the first gate 230 and the second gate 250 from the channel layer 202 respectively, while also providing support for the source 210 and the drain 220.
[0068] The dielectric protection layer 205, located above the second dielectric layer 204, protects the hardware structure in the semiconductor device 200.
[0069] In some possible embodiments, the source 210, drain 220, first gate 230, and second gate 250 described above can be led out from the dielectric protective layer 205. Specifically, the first lead-out terminal 231 of the first gate 230 and the second lead-out terminal 251 of the second gate 250 can be led out from the top surface of the dielectric protective layer 205.
[0070] In some possible embodiments, the first lead 231 and the second lead 251 can be disposed on the same side of the semiconductor device 200, or they can be disposed on opposite sides of the semiconductor device 200. Figure 2 The structure shown is the structure set on the opposite side.
[0071] In some possible embodiments, reference Figure 2As shown, the first extension electrode 240 and the second extension electrode 260 can be elongated electrodes, and the first extension electrode 240 and the second extension electrode 260 are adjacent and parallel.
[0072] In some possible embodiments, the materials of the first gate 230, the second gate 250, the first extension electrode 240, and the second extension electrode 260 may be the same. Of course, in specific application scenarios, the materials of the first gate 230, the second gate 250, the first extension electrode 240, and the second extension electrode 260 may also be different from each other or partially the same.
[0073] In some possible embodiments, the first gate 230 and the first extended electrode 240 may be formed in the same fabrication process step based on the same deposition or growth process, and there is a connection between the first gate 230 and the first extended electrode 240. Therefore, the first gate 230 and the first extended electrode 240 may be integrally formed, presenting an independent and complete composite structure. Similarly, the second gate 250 and the second extended electrode 260 may also be formed in the same fabrication process step based on the same deposition or growth process, and there is a connection between the second gate 250 and the second extended electrode 260. Therefore, the second gate 250 and the second extended electrode 260 may be integrally formed, presenting an independent and complete composite structure.
[0074] In summary, the process for fabricating the first gate 230, the second gate 250, the first extension electrode 240, and the second extension electrode 260 is relatively simple.
[0075] Figure 3 This is a schematic diagram of the charge distribution in a semiconductor device.
[0076] For the first gate 230 and its connected first extended electrode 240, since the first extended electrode 240 is an elongated electrode structure, after the first extended electrode 240 is powered by an external power source, the voltage applied to the first gate 230 and the first extended electrode 240 will form a symmetrical electric field distribution on the surface of the active layer. According to Gaussian electric field theory, the electric field strength decreases normally with distance from the center of the gate. This symmetry makes the conductive channel exhibit a uniform conduction state in space, consistent with the characteristics of a normally distributed bell curve. At this time, the migration path of charge carriers (electrons or holes) is mainly dominated by the central electric field, forming a stable channel current.
[0077] Figure 3Image (a) shows the charge distribution inside a semiconductor device with a single gate structure, which includes a first gate 230 and a first extended electrode 240. The horizontal axis of the image is used to represent the positional relationship between the first gate 230 (including the first extended electrode 240) and the source and drain, and the vertical axis is used to represent the conduction state of the device, or may represent the charge distribution or electric field strength.
[0078] refer to Figure 3 As shown in (a), the semiconductor device exhibits three operating states based on the first gate 230 (connected to an external power supply) and the first extended electrode 240:
[0079] In the fully on state, the voltage (Vg) input to the first gate 230 is higher than the threshold voltage (Vth) of the device, and the electric field completely covers the active layer, forming a continuous conductive channel, so that the semiconductor device is in the fully on state.
[0080] In the partially on state, Vg is slightly higher than Vth. The electric field activates the active layer only in a part of the region near the first gate 230 and the first extended electrode 240, forming a discontinuous conductive channel, which makes the device in a partially on state.
[0081] In the completely non-conductive state, Vg is lower than Vth, the distance between the source / drain and the gate exceeds the electron diffusion distance, the electric field strength is insufficient to induce carrier migration, the active layer is in an insulating state, and the device is in a completely non-conductive state.
[0082] Figure 3 (b) shows the charge distribution pattern inside a semiconductor device with another single-gate structure, which includes a second gate 250 and a second extended electrode 260; the horizontal axis of the coordinate system in the image is used to represent the positional relationship between the second gate 250 (including the second extended electrode 260) and the source and drain, and the vertical axis is used to represent the charge distribution or electric field intensity inside the device.
[0083] Assuming that the second gate 250 can generate induced charge, refer to Figure 3 As shown in (b) in the figure, the charge distribution inside the active layer also presents a relatively flat normal distribution.
[0084] Figure 3 (c) in the figure shows the charge distribution inside the semiconductor device 200; the horizontal axis of the coordinate system in the figure is used to represent the positional relationship between the overall structure of the first gate 230, the first extended electrode 240, the second gate 250 and the second extended electrode 260 and the source 210 and the drain 220, and the vertical axis is used to represent the charge distribution or electric field intensity inside the device.
[0085] The first gate 230 is connected to an external power supply, and the second gate 250 is capable of generating induced charges. Figure 3 As shown in (c), the voltage signal input to the first gate 230 is superimposed on the induced charge generated by the second gate 250, producing a superposition effect, which is equivalent to... Figure 3 The curve in (a) and Figure 3 Adding the curves in (b) in the figure, even if the amount of induced charge generated by the second gate 250 is small, it can still raise the peak value of the charge distribution inside the semiconductor device 200, making the spacing range corresponding to the full conduction of the semiconductor device 200 wider, improving the conduction effect of the semiconductor device 200, and the current between the source 210 and the drain 220 will also increase when the semiconductor device 200 is turned on.
[0086] Based on the above technical solution, by adding adjacent, non-conductive additional gates to the two gates in the dual-gate structure, the charges of the two gates are superimposed. This superposition effect effectively improves the conduction of the semiconductor device, making it easier to conduct and thus enhancing its conduction stability and sensitivity. Furthermore, the structure of this semiconductor device is relatively simple. Especially with the design of a double-top-gate structure, the film structure of the semiconductor device is not increased due to the special gate design, and there are no limitations on the fabrication materials caused by the introduction of a bottom gate. This makes the semiconductor device fabrication process less difficult, and when applied to detection chips, it facilitates the large-scale mass production and integration of detection chips.
[0087] In transistor device design, the spacing between the gate and source / drain electrodes typically requires consideration of the interaction between physical dimensions and diffusion effects. As the core of electric field control, the gate's physical size is usually smaller than the source / drain electrode spacing. This reduces parasitic capacitance between the gate and source / drain, thereby improving the transistor's high-frequency response. Furthermore, doped ions in the gate (such as in low-temperature polysilicon (LTPS)) diffuse under an electric field, forming an effective control region. The voltage applied to the gate creates an electric field in the substrate, driving doped ions to migrate towards the source / drain region. For example, in LTPS gates, the doping concentration is typically high (e.g., 10⁻⁶). 2The diffusion distance under electric field driving can reach the micrometer level (on the order of 0 cm⁻³). If the gate-to-source-drain distance is too large, the diffused dopant ions may exceed the control range, resulting in the inability to form an effective electric field between the source and drain or the generation of leakage current. Through process simulation and experimental verification, for an LTPS gate, with 200 nm silicon oxide and 200 nm silicon nitrogen as the gate dielectric layers, the diffusion length of dopant ions in this structure is approximately 5 μm. This means that the effective control region of the gate extends to the 5 μm range. If the source-drain distance exceeds this value, the gate electric field may not be able to fully modulate the carrier transport between the source and drain, leading to threshold voltage drift or an increase in subthreshold leakage current.
[0088] In view of the above description, in the semiconductor device 200 proposed in the embodiments of this application, the distance between the first gate 230 and the source 210 or the drain 220 is less than or equal to the electron diffusion distance, which is the distance by which the first gate or the second gate affects the electron transport inside the semiconductor device; the distance between the second gate 250 and the source 210 or the drain 220 is less than or equal to the electron diffusion distance; thereby ensuring that the first gate 230 and the second gate 250 can normally control the conduction or cutoff between the source 210 and the drain 220.
[0089] In addition, referring to the above Figure 3 As shown, since the first gate 230 is connected to the first extended electrode 240 and the second gate 250 is connected to the second extended electrode 260, the first extended electrode 240 can be considered as an extension of the first gate 230, and the second extended electrode 260 as an extension of the second gate 250. Therefore, the overall structure formed by the first extended electrode 240 and the second extended electrode 260 must also satisfy the aforementioned distance condition between the gate and the source / drain.
[0090] In some possible embodiments, the projection of the overall structure formed by the first extended electrode 240 and the second extended electrode 260 into the semiconductor device 200 is located between the source electrode 210 and the drain electrode 220. That is, the source electrode 210 and the drain electrode 220 are distributed on both sides of the overall structure formed by the first extended electrode 240 and the second extended electrode 260.
[0091] Furthermore, the distance between the first extended electrode 240 and the source electrode 210 or the drain electrode 220 is also less than or equal to the electron diffusion distance; the distance between the second extended electrode 260 and the source electrode 210 or the drain electrode 220 is also less than or equal to the electron diffusion distance.
[0092] Based on the above technical solution, the gate is positioned at a distance from the source and drain that is less than the electron diffusion distance, which ensures the control of the gate electric field on the electrons in the channel region, thereby helping to improve the performance of semiconductor devices.
[0093] Figure 4 This is a schematic diagram of the structure of another semiconductor device 200 proposed in the embodiments of this application.
[0094] Compared to Figure 3 The semiconductor device 200 shown, Figure 4 The difference between the semiconductor device 200 shown lies in the structural design of the first extended electrode 240 and the second extended electrode 260.
[0095] refer to Figure 4 As shown, the first extended electrode 240 is a finger electrode, including a first body 241 and at least one first sub-electrode 242, and the at least one first sub-electrode 242 is connected to the first body 241.
[0096] The aforementioned second extended electrode 260 is a finger electrode, including a second body 261 and at least one second sub-electrode 262, wherein at least one second sub-electrode 262 is connected to the second body 261.
[0097] The first main body 241 and the second main body 261 are arranged in parallel, and the first sub-electrode 242 and the second sub-electrode 262 are arranged alternately to form an interdigitated structure.
[0098] In some possible embodiments, reference Figure 4 As shown in (a), the first extension electrode 240 may include a first sub-electrode 242, and the second extension electrode 260 may include a second sub-electrode 262.
[0099] In some possible embodiments, reference Figure 4 As shown in (b), the first extension electrode 240 may include one first sub-electrode 242, and the second extension electrode 260 may include multiple (e.g., two) second sub-electrodes 262.
[0100] In some possible embodiments, reference Figure 4 As shown in (c), the first extension electrode 240 may include N first sub-electrodes 242, and the second extension electrode 260 may include M second sub-electrodes 262, where N and M are positive integers greater than 1 and N = M.
[0101] In some possible embodiments, reference Figure 4 As shown in (d), the first extension electrode 240 may include N first sub-electrodes 242, and the second extension electrode 260 may include M second sub-electrodes 262, where N is a positive integer greater than 1 and N < M, for example, N = M-1.
[0102] In some possible embodiments, reference Figure 4As shown in (e), the first extension electrode 240 may include N first sub-electrodes 242, and the second extension electrode 260 may include M second sub-electrodes 262, where N and M are positive integers, and N > M, for example, N = M + 1.
[0103] In some possible embodiments, the projection of the interdigitated structure formed by the first extended electrode 240 and the second extended electrode 260 into the interior of the semiconductor device 200 is located between the source 210 and the drain 220. Based on this, it is possible to ensure more precise control of the current switching on and off through the first extended electrode 240 and the second extended electrode 260.
[0104] Figure 5 This is a schematic diagram of the charge distribution pattern inside a semiconductor device 200 according to an embodiment of this application.
[0105] The semiconductor device 200 in this example is Figure 4 Semiconductor device 200 is shown in (e) in the diagram.
[0106] refer to Figure 5 As shown in (a), since the first extended electrode 240 includes multiple first sub-electrodes 242, under the influence of one first sub-electrode 242, the charge distribution inside the active layer also presents a normal distribution. Then, after the superposition of the influence of multiple first sub-electrodes 242, the charge distribution curve inside the active layer presents a wavy line. Based on this curve, it can be seen that this structure helps to further widen the spacing range corresponding to the complete conduction of the semiconductor device 200.
[0107] In practical applications, the first gate 230 is connected to an external power supply, so that the charge distribution curve inside the active layer appears as a wavy line. At this time, the current conduction between the source 210 and the drain 220 is limited to the lower end of the wavy line. At this time, there is a small amount of charge transfer between the source 210 and the drain 220, and the current is small.
[0108] Similarly, refer to Figure 5 As shown in (b), after induced charge is generated in the second gate 250, without considering the influence of the first gate 230, although the amount of induced charge is small and less than the influence of the external power supply, the charge distribution curve inside the active layer can still present a relatively flat wavy line.
[0109] refer to Figure 5As shown in (c), since the two extended electrodes are arranged in an interdigitated structure, the lower limit of the charge distribution inside the semiconductor device 200 is increased under the superposition effect of the electric fields of the first extended electrode 240 and the second extended electrode 260 distributed in a wavy line. Furthermore, the spacing range corresponding to the semiconductor device 200 being fully turned on is further widened, that is, the conduction effect of the semiconductor device 200 is further enhanced. At this time, the current between the source 210 and the drain 220 increases.
[0110] Based on the above technical solution, the first extension electrode 240 and the second extension electrode 260 are designed as an interdigitated structure. When the number of sub-electrodes of the first extension electrode 240 and / or the second extension electrode 260 is greater than 1, the lower limit of the charge distribution inside the semiconductor device 200 is raised, which makes the spacing range corresponding to the semiconductor device 200 fully conducting further wider. Therefore, the semiconductor device 200 is easier to conduct, thereby improving the conduction stability and sensitivity of the semiconductor device 200.
[0111] In some possible embodiments, the semiconductor device 200 with a dual-gate structure proposed in this application can be applied to multiple fields, such as (electrochemical) detection, power electronics, and flexible electronics; among which, the detection field is an important application field of the semiconductor device 200 proposed in this application.
[0112] Figure 6 This is a schematic diagram of the structure of another semiconductor device 200 proposed in the embodiments of this application.
[0113] In order to apply the semiconductor device 200 proposed in this application embodiment to the detection field, and to enable the semiconductor device 200 to be integrated into a detection chip, compared with any of the semiconductor devices 200 proposed in the foregoing embodiments, Figure 6 The semiconductor device 200 shown also includes:
[0114] An extended gate 270 covers a second lead 251 and is modified with a detection connector for specific binding to a target in a test sample.
[0115] In some possible embodiments, considering that the aforementioned semiconductor device 200 is used in an electrochemical detection chip, the extended gate 270 will come into direct contact with biomolecules or cells. Inert metals have good biocompatibility, reducing non-specific adsorption or denaturation of biomolecules, thereby maintaining the activity of biomolecules and improving detection accuracy. Therefore, the extended gate 270 includes an inert metal, such as gold (Au) or platinum (Pt). Furthermore, the extended gate 270 based on an inert metal exhibits high chemical stability in the electrochemical environment and is less likely to react with ions or other chemicals in the electrolyte solution, thus avoiding corrosion or denaturation of the gate material. This helps ensure the long-term stability and reliability of the semiconductor device 200 used in the detection chip.
[0116] In some possible embodiments, when the semiconductor device 200 is applied to an electrochemical sensing scenario, when the test sample covers the extended gate 270, the detection connector modified on the extended gate 270 specifically binds to the detection unit in the test sample. Then, when phosphate buffered saline (PBS) covers the specifically bound extended gate 270, the detection unit becomes charged in the solution, thereby generating induced charges on the second gate 250 and the second extended electrode 260. Simultaneously, the first gate 230 is connected to an external power supply, and the two electric fields superimpose, enhancing the conduction of the semiconductor device 200. At this time, the current between the source 210 and the drain 220 increases, based on which a correlation between the current signal and the concentration of the detection unit can be established, thereby realizing electrochemical sensing.
[0117] In some possible embodiments, when there are multiple first sub-electrodes 242, the spacing between two adjacent first sub-electrodes 242 in the first extended electrode 240 is greater than or equal to the electron diffusion distance and less than or equal to twice the electron diffusion distance. For example, the spacing may be equal to 1.5 times the electron diffusion distance. When there are multiple second sub-electrodes 262, the spacing between two adjacent second sub-electrodes 262 in the second extended electrode 260 is greater than or equal to the electron diffusion distance and less than or equal to twice the electron diffusion distance. For example, the spacing may be equal to 1.5 times the electron diffusion distance.
[0118] Based on the above technical solution, by designing the spacing between two adjacent first sub-electrodes 242 in the first extended electrode 240 and the spacing between two adjacent second sub-electrodes 262 in the second extended electrode 260, the spacing between two adjacent sub-electrodes belonging to one extended electrode can be located in the region where the charge distribution curve decreases rapidly. This makes the electrical signal of the sub-electrode belonging to another extended electrode located between these two sub-electrodes significantly affected. Even if there is a small amount of charge transfer, a large change in electrical signal will be generated, thereby improving the detection sensitivity of the semiconductor device 200.
[0119] Figure 7 This is a schematic diagram of the structure of another semiconductor device 200 proposed in the embodiments of this application.
[0120] refer to Figure 7 As shown, the semiconductor device 200 has multiple second gate 250 and second extended electrode 260.
[0121] In some possible embodiments, the number of second gates 250 and second extended electrodes 260 are equal and they are connected in a one-to-one correspondence.
[0122] In some possible embodiments, reference Figure 7 As shown, all of the multiple second extension electrodes 260 can be finger electrodes.
[0123] In some possible embodiments, the plurality of second extension electrodes 260 described above may be disposed on the same side of the semiconductor device 200 or disposed on multiple sides of the semiconductor device 200.
[0124] Considering that the semiconductor device 200, which includes a plurality of second gates 250 and a plurality of second extended electrodes 260, can be applied in the field of detection, the semiconductor device 200 can be improved as follows.
[0125] Figure 8 This is a schematic diagram of the structure of another semiconductor device 200 proposed in the embodiments of this application.
[0126] refer to Figure 8 As shown, the semiconductor device 200 includes not only a plurality of second gates 250 and a plurality of second extended electrodes 260, but also a plurality of extended gates 270, which correspond one-to-one with the second leads 251 extending from the plurality of second gates 250.
[0127] In some possible embodiments, the detection connectors modified by the aforementioned plurality of extended gates 270 are different. Based on this, it is possible to realize the multi-detection function of a single semiconductor device 200 for different detection units in the test sample.
[0128] In some possible embodiments, when one of the extended gates 270 is used to detect a test sample, the second lead 251 and the first lead 231 covered by the remaining extended gates 270 are connected to an external power source.
[0129] For example, with Figure 8 Taking the semiconductor device 200 shown as an example, the semiconductor device 200 has three second gates 250, two extended electrodes 260, and extended gates 270. For ease of description, this example refers to the first gate 230 as G1, and the three second gates 250 as G2, G3, and G4, respectively.
[0130] During the detection process of the semiconductor device 200, when the extended gate 270 covering G2 detects the test sample, G1, G3, and G4 are connected to an external power supply, maintaining a high conduction state in the overlapping region of G1, G3, and G4. In this state, the conduction state between the source 210 and the drain 220 is determined by the amount of charge distributed in the corresponding region of G2. Subsequently, when the extended gate 270 covering G2 is covered by PBS reaction solution, the detection units specifically bound on it generate induced charges, thereby increasing the conduction state of the semiconductor device 200 and increasing the current between the source 210 and the drain 220. The concentration of the detection units on the extended gate 270 covering G2 is calculated by the increased current difference. Similarly, the detection of the concentration of the detection units on the extended gates 270 covering G3 and G4 is realized sequentially, thereby realizing the multi-detection electrochemical detection function of a single semiconductor device 200.
[0131] Furthermore, this application also proposes a method for fabricating a semiconductor device, which is used to fabricate a semiconductor device including a double-top gate structure as proposed in this application.
[0132] Figure 9 This is a schematic flowchart of a semiconductor device fabrication method 900 proposed in an embodiment of this application.
[0133] refer to Figure 9 As shown, the method 900 includes the following steps:
[0134] S910: Prepare the base layer.
[0135] S920: An active layer is prepared on the substrate layer.
[0136] S930: A dielectric layer is covered on the active layer, and holes are drilled at a first position and a second position in the dielectric layer to obtain a first hole and a second hole, wherein the first position corresponds to the source position and the second position corresponds to the drain position.
[0137] S940: Ions are implanted into the first and second holes to deposit the source and drain electrodes.
[0138] S950: Photolithography of the gate on the dielectric layer.
[0139] The photolithographic pattern of the gate is detailed in the gate structure of any of the semiconductor device 200 structural schematic diagrams proposed in the foregoing embodiments of this application.
[0140] S960: A protective layer is covered on the dielectric layer, and the source, first gate, second gate and drain are brought out from the overall device, wherein the lead of the first gate is connected to an external power supply.
[0141] In some possible embodiments, when the semiconductor device is used for electrochemical detection, the following steps may also be performed:
[0142] S970: An extended gate is plated on the lead-out terminal of the second gate.
[0143] S980: Detection connectors are modified on the extended gate.
[0144] At this point, the fabrication of the semiconductor device, including the double-top-gate structure, is complete.
[0145] Based on the same inventive concept, this application also provides a detection chip, which includes any of the semiconductor devices proposed in the embodiments of this application.
[0146] In this semiconductor device, the second lead of the second gate is covered by an extended gate, which is decorated with a detection connector.
[0147] In addition, this application also provides a detection device, which includes any of the detection chips proposed in this application.
[0148] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0149] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0150] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A semiconductor device, characterized in that, include: Source, which is located inside the semiconductor device; Drain, wherein the drain is located inside the semiconductor device; A first gate is located between the source and the drain, and a first lead of the first gate extending from inside the semiconductor device is connected to an external power supply. A first extension electrode is connected to the first lead-out terminal; A second gate, which is internally connected to the first gate in the semiconductor device; The second extended electrode is connected to the second lead of the second gate extending from the inside of the semiconductor device, and the first extended electrode is adjacent to the second extended electrode but not in contact with it.
2. The semiconductor device according to claim 1, characterized in that, The first extended electrode is a finger electrode, comprising a first body and at least one first sub-electrode, wherein the at least one first sub-electrode is connected to the first body; The second extended electrode is a finger electrode, comprising a second body and at least one second sub-electrode, wherein the at least one second sub-electrode is connected to the second body; The first main body and the second main body are arranged in parallel, and the first sub-electrode and the second sub-electrode are arranged alternately to form an interdigitated structure.
3. The semiconductor device according to claim 2, characterized in that, The distance between the first gate and the source or the drain is less than or equal to the electron diffusion distance, which is the distance by which the first gate or the second gate affects the electron transport inside the semiconductor device; The distance between the second gate and the source or the drain is less than or equal to the electron diffusion distance; When there are multiple first sub-electrodes, the spacing between two adjacent first sub-electrodes in the first extended electrode is greater than or equal to the electron diffusion distance and less than or equal to twice the electron diffusion distance; When there are multiple second sub-electrodes, the spacing between two adjacent second sub-electrodes in the second extended electrode is greater than or equal to the electron diffusion distance and less than or equal to twice the electron diffusion distance.
4. The semiconductor device according to claim 2 or 3, characterized in that, The projection of the interdigitated structure vertically into the interior of the semiconductor device is located between the source and the drain.
5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The first gate is integrally formed with the first extended electrode; the second gate is integrally formed with the second extended electrode.
6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The first gate, the second gate, the first extended electrode, and the second extended electrode are made of the same material.
7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The semiconductor device further includes: An extended gate covering the second lead-out terminal is provided, and the extended gate is modified with a detection connector for specific binding to a target in the test sample.
8. The semiconductor device according to any one of claims 1 to 6, characterized in that, The number of the second gate and the second extended electrode is multiple.
9. The semiconductor device according to claim 7, characterized in that, The number of the second gate, the second extended electrode, and the extended gate is multiple.
10. The semiconductor device according to claim 9, characterized in that, The detection connectors of the multiple extended gate modifications are different.
11. The semiconductor device according to claim 9 or 10, characterized in that, When one of the extended gates is used to detect the test sample, the second lead and the first lead covered by the remaining extended gates are connected to an external power source.
12. The semiconductor device according to any one of claims 7, 9 to 11, characterized in that, The extended gate comprises an inert metal.
13. A detection chip, characterized in that, Includes the semiconductor device as described in any one of claims 1 to 12.
14. A detection device, characterized in that, Includes the detection chip as described in claim 13.