Method for improving gray scale performance of high-voltage driving chip and high-voltage driving chip

Abstract

The application provides a method for improving the gray scale performance of a high-voltage driving chip and the high-voltage driving chip. The method comprises the following steps: providing a semiconductor substrate; forming a well region in the semiconductor substrate; performing a plurality of first ion implantation processes on the well region to implant first doping ions; and performing a second ion implantation process on the well region to implant second doping ions. The atomic mass of the second doping ions is greater than the atomic mass of the first doping ions, and the diffusion coefficient of the second doping ions in the semiconductor substrate is less than the diffusion coefficient of the first doping ions. By introducing heavy-mass and low-diffusion-coefficient doping ions (such as indium ions), more stable doping distribution, higher carrier mobility and stronger high-voltage resistance can be obtained, so that the gray scale uniformity, response speed and stability of the high-voltage driving chip are significantly improved, and the product yield is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving the grayscale performance of a high-voltage driver chip and the high-voltage driver chip itself. Background Technology

[0002] In the field of display technology, the grayscale performance of high-voltage driver chips (HV chips) directly determines the level of detail in different brightness levels that a display device can present. Grayscale control is mainly achieved by adjusting the amplitude of the driving voltage. During chip manufacturing, the core indicators affecting grayscale performance mainly include grayscale uniformity, response speed, and long-term operational stability.

[0003] In traditional high-voltage driver chip manufacturing processes, boron (B) ions are typically used as dopants in the input / output P-type well regions (IO PW) or medium-voltage well regions (MW Well). Existing standard process flows usually include multiple boron ion implantation processes, such as: first and second boron ion implantations to prevent latch-up, a third boron ion implantation to prevent source-drain punch-through, and a fourth boron ion implantation to regulate the threshold voltage (VT).

[0004] However, as display panels increasingly demand higher grayscale detail and refresh rates, traditional manufacturing processes have revealed the following technical bottlenecks:

[0005] First, boron ions have a relatively high diffusion coefficient in silicon substrates, making them prone to diffusion during subsequent thermal annealing processes and hindering the formation of a steep doping distribution. This gentle doping distribution results in poor electric field uniformity within the well region, which in turn affects the linearity of grayscale voltage, leading to a decrease in grayscale uniformity.

[0006] Secondly, the acceptor energy level of boron ions is relatively shallow. Under the high-voltage operating environment of the chip, thermal excitation loss of charge carriers is easily generated, which leads to limited hole mobility and affects the response speed and voltage driving accuracy of the chip.

[0007] Finally, under high-voltage electric fields, the traditional boron-doped well regions have limited high-voltage resistance, easily triggering carrier injection effects. This leads to grayscale voltage degradation after long-term operation, affecting chip stability. In actual mass production data, chips manufactured using traditional processes have a grayscale-related defect rate as high as 1.49%, indicating a bottleneck in overall yield improvement.

[0008] Therefore, a new well injection process is urgently needed to obtain a more stable doping distribution, higher carrier mobility, and stronger high voltage resistance, thereby fundamentally improving the grayscale performance of high voltage driver chips and increasing product yield. Summary of the Invention

[0009] The purpose of this invention is to provide a method and a high-voltage driver chip to improve the grayscale performance of the high-voltage driver chip, so as to solve the technical problems of poor grayscale uniformity, slow response speed and insufficient long-term working stability caused by the use of single light mass ions (such as boron ions) for implantation in the traditional high-voltage driver chip manufacturing process.

[0010] To achieve the above objectives, the present invention provides a method for improving the grayscale performance of a high-voltage driver chip, comprising:

[0011] Step 1: Provide a semiconductor substrate;

[0012] Step 2: Form a well region in the semiconductor substrate;

[0013] Step 3: Perform the first ion implantation process multiple times on the well region to implant the first dopant ions;

[0014] Step 4: Perform a second ion implantation process on the well region to implant second doped ions;

[0015] Wherein, the atomic mass of the second doped ion is greater than that of the first doped ion, and the diffusion coefficient of the second doped ion in the semiconductor substrate is less than that of the first doped ion in the semiconductor substrate.

[0016] Preferably, in step two, the well region includes a medium-pressure well region or an input-output P-type well region.

[0017] Preferably, in step three, the first doped ion includes boron ions.

[0018] Preferably, in step three, the multiple first ion implantation processes include an ion implantation process to prevent latch-up, an ion implantation process to prevent source-drain punch-through, and an ion implantation process to adjust the threshold voltage.

[0019] Preferably, in step three, the implantation energy and implantation dose of the ion implantation process used to prevent source-drain punch-through are adjusted.

[0020] Preferably, in step four, the second doped ion includes indium ions.

[0021] Preferably, in step four, the second ion implantation process is used to adjust the threshold voltage.

[0022] Preferably, in steps three and four, the second ion implantation process is performed after the multiple first ion implantation processes.

[0023] The present invention also provides a high-voltage driver chip, manufactured using the method described above, comprising:

[0024] Semiconductor substrate;

[0025] The well region is located in the semiconductor substrate;

[0026] The well region is doped with a first dopant ion and a second dopant ion, wherein the atomic mass of the second dopant ion is greater than that of the first dopant ion, and the diffusion coefficient of the second dopant ion in the semiconductor substrate is less than that of the first dopant ion in the semiconductor substrate.

[0027] Preferably, the first dopant ion includes boron ions, and the second dopant ion includes indium ions.

[0028] As described above, the method for improving the grayscale performance of a high-voltage driver chip and the high-voltage driver chip of the present invention have the following beneficial effects:

[0029] This invention overcomes the thermal diffusion problem of a single first dopant ion (such as boron ion) by introducing a second dopant ion (such as indium ion) with a larger atomic mass and lower diffusion coefficient into the well region implantation process. The low diffusion characteristics of the second dopant ion help to form an extremely steep doping distribution, thereby significantly improving the electric field uniformity of the well region and optimizing the linearity of gray-level voltage. Its deep energy level characteristics can effectively reduce the thermal excitation loss of charge carriers, locally change the band structure of silicon to improve hole mobility, and give the chip faster response speed and more precise voltage driving capability. At the same time, this deep energy level characteristic also improves the physical stability of the chip under high voltage electric field, reduces the carrier injection effect, and avoids the degradation of gray-level voltage after long-term operation. Actual mass production data shows that after adopting the method of this invention, the gray-level defect rate of high-voltage drive chips is significantly reduced, and the overall yield is significantly improved. Attached Figure Description

[0030] Figure 1 The diagram shows a process flow diagram of the method for improving the grayscale performance of a high-voltage driver chip according to the present invention.

[0031] Figure 2 The diagram shows the wafer defect distribution in the conventional process of this invention.

[0032] Figure 3 The diagram shows the wafer defect distribution in the optimized process of this invention. Detailed Implementation

[0033] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] High-voltage driver chips are commonly used in various advanced display devices, such as liquid crystal displays (LCDs), organic light-emitting diode (OLED) displays, or micro LED displays. In these display applications, grayscale performance directly determines the color depth and brightness level of the screen, which is primarily achieved through the precise voltage amplitude output by the digital-to-analog converter circuit within the high-voltage driver chip. In semiconductor manufacturing processes, the physical factors affecting the final chip's grayscale performance mainly include the uniformity of the transistor's grayscale voltage, the device's turn-on and turn-off response speed, and the device's stability under long-term high-voltage electric field stress.

[0035] The method disclosed herein overcomes the drawback of thermal diffusion of traditional lightweight doped ions by optimizing the ion implantation process combination in the trap region during front-end fabrication, thereby achieving a more stable and steeper doping concentration distribution. This optimized distribution not only provides higher carrier mobility but also endows the device with stronger resistance to high-voltage breakdown, thus improving the overall grayscale performance of the high-voltage driver chip from the underlying device physics level. The manufacturing equipment performing the various process steps of this disclosure may include standard semiconductor process equipment in an integrated circuit manufacturing plant, such as high-energy ion implanters, medium-current ion implanters, rapid thermal annealing furnaces, laser annealing equipment, and related photolithography and cleaning equipment.

[0036] A method for improving the grayscale performance of a high-voltage driver chip includes the following steps:

[0037] Step 1: Provide a semiconductor substrate.

[0038] The semiconductor substrate can be a silicon substrate, and may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. An SOI substrate includes an insulating layer beneath a thin semiconductor layer serving as the active layer. The semiconductor in the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates. In some embodiments, the process of providing the semiconductor substrate may also include epitaxially growing one or more layers of semiconductor material, such as an epitaxial silicon layer, on a base substrate to provide a purer active region for the device. A series of pretreatment steps are typically performed on the semiconductor substrate before subsequent ion implantation processes. These pretreatment steps may include a wet cleaning process using standard cleaning solutions to remove organic matter, particles, and metallic contaminants from the surface. After cleaning, a thin sacrificial oxide layer or pad oxide layer can be grown on the semiconductor substrate surface through a thermal oxidation process. This oxide layer can act as a buffer during subsequent ion implantation, reducing direct damage to the semiconductor lattice by high-energy ions and preventing channeling effects. Furthermore, shallow trench isolation structures or deep trench isolation structures can be pre-formed during the semiconductor substrate provision stage to define individual active regions and achieve electrical isolation between different high-voltage devices.

[0039] Step 2: Form a well region in the semiconductor substrate.

[0040] The formation of well regions typically relies on photolithography to define the implantation area. Specifically, a photoresist layer is spin-coated onto the semiconductor substrate, followed by pre-baking to remove solvents. Next, a patterned mask is used to expose the photoresist layer using deep ultraviolet or extreme ultraviolet light. After exposure, the photoresist layer undergoes post-exposure baking and development processes to remove soluble portions, thus patterning the photoresist layer and precisely exposing the semiconductor substrate area where the well region needs to be formed. Unexposed areas are covered by the retained photoresist layer, serving as a barrier layer for subsequent ion implantation. As the core operating region of a semiconductor device, the doping concentration and depth distribution of the well region directly determine key electrical characteristics of the transistor, such as threshold voltage, breakdown voltage, and leakage current. After ion implantation of the well region, a plasma stripping process combined with wet cleaning is typically used to remove the surface photoresist layer.

[0041] In some embodiments, in step two, the well region includes a medium-pressure well region or an input / output P-type well region.

[0042] In complex mixed-signal integrated circuits, devices operating at different voltages are typically integrated. Medium-voltage well regions are generally used to support medium-voltage devices operating between a few volts and tens of volts, while input / output P-type well regions are specifically used for input / output interface circuits connecting the chip to external circuits; these regions often need to withstand operating voltages of tens of volts or even higher. Applying the optimized injection method of this disclosure to medium-voltage well regions or input / output P-type well regions can specifically improve the internal charge distribution in these regions subjected to higher electric fields. By forming a more reasonable electric field gradient, the breakdown resistance of these high-voltage or medium-voltage devices can be effectively improved, preventing avalanche breakdown under high-voltage operation, while ensuring good electric field uniformity throughout the entire voltage regulation range.

[0043] Step 3: Perform the first ion implantation process multiple times on the well region to implant the first dopant ions.

[0044] Multiple first-stage ion implantation processes can be performed using beam-type ion implanters or plasma immersion ion implantation equipment. In actual semiconductor manufacturing, a single implantation is often insufficient to meet the complex physics requirements of a high-performance well region. By performing multiple implantations at different stages using different implantation energies and doses, a specific stepped or reverse concentration gradient distribution can be formed within the well region from deep within the substrate to the surface. This multiple implantation strategy can independently optimize the device's deep isolation performance, subsurface punch-through resistance, and surface turn-on characteristics.

[0045] In some embodiments, in step three, the first dopant ion includes boron ions.

[0046] Boron ions are the most basic and widely used p-type dopant impurity in silicon-based semiconductor manufacturing. Due to their small atomic radius, boron ions have high solid solubility in the silicon lattice. In other embodiments, to achieve a shallower implantation depth or reduce channeling effects, the first dopant ion may also include boron difluoride ions, carbon-doped boron ions, or other suitable lightweight p-type dopant ion clusters. Using boron difluoride ions allows for a lower equivalent implantation energy than pure boron ions at the same accelerating voltage, thereby confining the impurity more tightly to a region closer to the surface.

[0047] In some embodiments, in step three, the multiple first ion implantation processes include an ion implantation process for preventing latch-up, an ion implantation process for preventing source-drain punch-through, and an ion implantation process for adjusting the threshold voltage.

[0048] These three different implantation processes collectively form the basic electrical framework of the well region. Ion implantation to prevent latch-up typically uses high implantation energy to implant impurity ions deep into the semiconductor substrate, forming a high-concentration buried layer. This buried layer effectively reduces the base resistance and current gain of parasitic bipolar transistors, thereby cutting off the positive feedback loop and preventing destructive latch-up under transient high voltage. Ion implantation to prevent source-drain punch-through uses medium energy to form a slightly more concentrated barrier layer directly beneath the future transistor channel. This barrier layer increases the depletion layer extension resistance between the source and drain, suppresses short-channel effects, and significantly reduces the subthreshold leakage current between the source and drain in the off state. Ion implantation to adjust the threshold voltage typically uses lower implantation energy to precisely place impurities in the channel region close to the semiconductor substrate surface. This allows for fine-tuning of the Fermi level on the semiconductor surface, thereby precisely controlling the gate voltage required for the device to switch from off to on.

[0049] In some embodiments, in step three, the implantation energy and implantation dose of the ion implantation process used to prevent source-drain punch-through are adjusted.

[0050] In traditional standard process flows, the parameters for punch-through prevention implantation are set based on a diffusion model of a single lightweight ion. Because this disclosure introduces new dopant ions with different physical properties in subsequent processes, the original overall doping profile will be superimposed and altered. To avoid the introduction of new ions leading to excessively high or low effective doping concentration below the channel, the original punch-through prevention implantation parameters need to be recalibrated. By adjusting the energy and dose of the ion implantation process used to prevent source-drain punch-through, the charge distribution within the well region can be rebalanced, ensuring that the device's punch-through capability is not only unaffected but also synergistically enhanced with the newly introduced heavyweight ions, jointly optimizing the overall device performance.

[0051] Step 4: Perform a second ion implantation process on the well region to implant a second dopant ion.

[0052] The second ion implantation process can also be performed using high-precision ion implantation equipment. During this step, the photoresist can be recoated and patterned as needed, or the mask layer retained from the previous step can be used directly. The core purpose of introducing the second dopant ion is to compensate for the rapid diffusion tendency of the single first dopant ion during thermal processing and the physical limitations imposed by its shallow energy level, thereby introducing a more stable and less mobile dopant component into the critical region of the well.

[0053] In some embodiments, in step four, the second dopant ion includes an indium ion.

[0054] Indium ions, as a relatively heavy p-type dopant, possess a significantly higher atomic mass and a deeper acceptor level than boron ions. Specifically, the acceptor level of indium ions is closer to the valence band edge in the band gap of silicon. This deep energy level characteristic means that indium ions are less prone to complete thermal ionization at room temperature or under conditions of chip heat generation, thus effectively reducing thermal excitation losses of charge carriers and lowering device background noise. Furthermore, the larger atomic radius of indium ions generates localized lattice stress upon entering the silicon lattice. This stress can locally alter the band structure of silicon, reducing the effective mass of holes and thereby increasing hole mobility in the channel. Improved hole mobility directly translates to faster switching response and more precise voltage driving capability, which is crucial for high-frequency refresh rate display driver chips. Simultaneously, the deep energy level characteristic and low diffusion of indium ions enhance the physical stability of high-voltage driver chips under continuous high-voltage electric fields, significantly reducing interface state generation caused by hot carrier injection effects and preventing threshold drift or degradation of grayscale voltage after long-term operation. In other embodiments, depending on different process nodes and cost considerations, the second dopant ion may also include other relatively heavy P-type dopant ions such as gallium ions and aluminum ions, or carbon ions and nitrogen ions may be mixed and implanted with conventional dopant ions using co-implantation technology to achieve similar effects of suppressing diffusion and regulating the energy band.

[0055] In some embodiments, in step four, the second ion implantation process is used to adjust the threshold voltage.

[0056] The second ion implantation process is specifically applied to the threshold voltage adjustment region, utilizing the extremely low diffusion coefficient of the second dopant ions in silicon. In subsequent rapid thermal annealing or spike annealing processes to activate impurities, conventional light ions undergo significant transient enhanced diffusion, resulting in a broadened and flattened doping distribution. However, due to their large mass and difficulty in movement, the second dopant ions maintain a very steep and precise reverse doping distribution near their original implantation location. This steep distribution formed on the channel surface allows for more precise control of the threshold voltage, reducing the interference of short-channel effects on the threshold voltage, thereby significantly improving the linearity and consistency of different grayscale voltage outputs.

[0057] In some embodiments, in steps three and four, the second ion implantation process is performed after multiple first ion implantation processes.

[0058] Performing the second ion implantation process after multiple first ion implantation processes allows for precise modification of the surface or specific shallow depths based on the already established doped distribution in the deep and middle well regions. This sequential arrangement helps reduce the damage to the shallow heavy ion distribution caused by subsequent high-energy implantation, ensuring that lattice damage in the surface channel region can be effectively controlled. In other embodiments, to optimize production cycle time or utilize specific mask combinations, the second ion implantation process can also be interspersed between multiple first ion implantation processes, or in certain specific cases, shallow implantation of heavy ions can be performed first, followed by high-energy deep implantation of light ions.

[0059] The atomic mass of the second doped ion is greater than that of the first doped ion, and the diffusion coefficient of the second doped ion in the semiconductor substrate is less than that of the first doped ion in the semiconductor substrate.

[0060] Because the diffusion coefficient of the second dopant ions in the semiconductor substrate is extremely low, they are less likely to undergo large-scale lateral or vertical diffusion during subsequent high-temperature thermal cycling processes such as source-drain activation annealing and silicide formation annealing. This maintains the steep doping distribution formed during implantation. This steep doping distribution significantly improves the electric field uniformity within the well region, especially near the gate oxide layer, thereby optimizing the linearity of grayscale voltage in the digital-to-analog converter circuit and making the display screen switch more smoothly between low and high grayscale levels.

[0061] To more intuitively illustrate the beneficial effects of the embodiments disclosed herein, please refer to the following references. Figure 2 and Figure 3 . Figure 2 The image shows a defect distribution map of a wafer manufactured using a conventional single boron ion implantation process. Figure 3 A defect distribution map of a wafer manufactured using an indium ion implantation process introduced according to embodiments of this disclosure is shown. Figure 2 and Figure 3 In the image, the black stripe markings distributed on the wafer surface represent the locations of failed chips detected during wafer-level testing. (Comparison) Figure 2 and Figure 3 It can be clearly seen that, Figure 2 There are numerous dense failure markers, primarily attributed to poor grayscale uniformity caused by boron ion diffusion in traditional processes, i.e., Bin54 grayscale failure. Figure 3In this study, the number of failure markers on the wafer was significantly reduced after adopting the method disclosed herein. Actual wafer fab mass production test data further confirms this improvement: after adopting the optimized process flow of this disclosure, the defect rate of the high-voltage driver chip in grayscale-related tests was significantly improved. Specifically, the Bin54 defect rate, representing grayscale failure, decreased dramatically from 1.49% in the traditional process to 0.35%, while the overall wafer yield steadily increased from 96.36% to 97.29%, fully demonstrating the reliability of this method in improving product quality and economic efficiency in actual large-scale manufacturing.

[0062] A high-voltage driver chip, manufactured using the method of any of the above embodiments, includes:

[0063] Semiconductor substrate; well region located in semiconductor substrate; wherein the well region is doped with a first dopant ion and a second dopant ion, the atomic mass of the second dopant ion is greater than the atomic mass of the first dopant ion, and the diffusion coefficient of the second dopant ion in the semiconductor substrate is less than the diffusion coefficient of the first dopant ion in the semiconductor substrate.

[0064] High-voltage driver chips can include display driver integrated circuits for controlling various display panels, such as source drivers or gate drivers. The specific structure, material selection, and physical properties of the semiconductor substrate and well region are described in detail in the preceding method embodiments. After the well region is formed, the manufacturing of the high-voltage driver chip involves a series of subsequent processes, including but not limited to: growing or depositing a gate dielectric layer on the surface of the semiconductor substrate, such as a thicker high-voltage silicon dioxide layer or a high-k dielectric material layer; depositing and patterning gate electrodes, such as polysilicon gates or metal gates, on the gate dielectric layer; performing lightly doped drain implantation and heavily doped source-drain implantation on the semiconductor substrate on both sides of the gate; performing high-temperature annealing to activate all implanted impurities; forming self-aligned silicides on the source-drain and gate surfaces to reduce contact resistance; and forming multilayer metal interconnect structures and interlayer dielectric layers, ultimately completing the manufacturing of the entire chip. Because the well region simultaneously contains a first dopant ion with a large diffusion coefficient and light mass, and a second dopant ion with a small diffusion coefficient and heavy mass, the well region exhibits a unique composite doping concentration gradient in the depth direction. This composite doping structure cleverly combines the advantages of two types of ions, ensuring both the anti-penetration and anti-latch-up capabilities of the deep regions at the bottom of the well, while significantly optimizing the electric field distribution and carrier mobility on the semiconductor surface. This results in a transistor device that can withstand high voltage while possessing excellent switching characteristics.

[0065] In some embodiments, the first dopant ion includes boron ions and the second dopant ion includes indium ions.

[0066] The combination of boron and indium ions exhibits high compatibility in modern silicon-based semiconductor manufacturing processes, requiring no large-scale hardware modifications to existing production lines. The presence of indium ions enables high-voltage driver chips to maintain extremely stable grayscale voltage output when processing complex and frequently changing high-voltage analog signals. This effectively reduces device performance drift caused by long-term heat generation or electric field stress, thereby extending the overall lifespan of display devices and maintaining long-term consistent display quality.

[0067] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0068] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving the grayscale performance of a high-voltage driver chip, characterized in that, At least including: Step 1: Provide a semiconductor substrate; Step 2: Form a well region in the semiconductor substrate; Step 3: Perform the first ion implantation process multiple times on the well region to implant the first dopant ions; Step 4: Perform a second ion implantation process on the well region to implant second doped ions; Wherein, the atomic mass of the second doped ion is greater than that of the first doped ion, and the diffusion coefficient of the second doped ion in the semiconductor substrate is less than that of the first doped ion in the semiconductor substrate.

2. The method for improving the grayscale performance of a high-voltage driver chip according to claim 1, characterized in that: In step two, the well region includes a medium-pressure well region or an input-output P-type well region.

3. The method for improving the grayscale performance of a high-voltage driver chip according to claim 1, characterized in that: In step three, the first doped ion includes boron ions.

4. The method for improving the grayscale performance of a high-voltage driver chip according to claim 1, characterized in that: In step three, the multiple first ion implantation processes include an ion implantation process to prevent latch-up, an ion implantation process to prevent source-drain punch-through, and an ion implantation process to adjust the threshold voltage.

5. The method for improving the grayscale performance of a high-voltage driver chip according to claim 4, characterized in that: In step three, the implantation energy and implantation dose of the ion implantation process used to prevent source-drain punch-through are adjusted.

6. The method for improving the grayscale performance of a high-voltage driver chip according to claim 1, characterized in that: In step four, the second doped ion includes indium ions.

7. The method for improving the grayscale performance of a high-voltage driver chip according to claim 1, characterized in that: In step four, the second ion implantation process is used to adjust the threshold voltage.

8. The method for improving the grayscale performance of a high-voltage driver chip according to claim 1, characterized in that: In steps three and four, the second ion implantation process is performed after the multiple first ion implantation processes.

9. A high-voltage driver chip, manufactured using the method described in any one of claims 1 to 8, characterized in that, include: Semiconductor substrate; The well region is located in the semiconductor substrate; The well region is doped with a first dopant ion and a second dopant ion, wherein the atomic mass of the second dopant ion is greater than that of the first dopant ion, and the diffusion coefficient of the second dopant ion in the semiconductor substrate is less than that of the first dopant ion in the semiconductor substrate.

10. The high-voltage driver chip according to claim 9, characterized in that: The first doped ion includes boron ions, and the second doped ion includes indium ions.

Images