A method for optimizing the performance of Gr / h-BN / MoS2 floating gate memory based on annealing process

Abstract

This invention discloses a method for optimizing the performance of Gr / h-BN / MoS2 floating-gate memory based on annealing process, belonging to the field of semiconductor devices. 2 The fabrication method of the heterojunction floating gate memory is as follows: First, the SiO2 layer on the surface of the silicon substrate is treated with ultraviolet ozone technology. Then, Gr, h-BN, and MoS2 thin films obtained by mechanical exfoliation are sequentially and directionally stacked and transferred using dry transfer technology. This is followed by a layer-by-layer vacuum annealing process to obtain a Gr / h-BN / MoS2 heterojunction with a clean interface. Finally, the device structure is etched using photolithography, and a bismuth / gold composite electrode is deposited. This fabrication method effectively eliminates interface polymer residues and stress wrinkles, blocks defect-assisted tunneling leakage paths, and the fabricated floating gate memory exhibits extremely low interface defect state density, a large storage window, and long-term room-temperature data retention.

Description

Technical Field

[0001] This invention relates to a method for optimizing the performance of Gr / h-BN / MoS2 floating gate memory based on annealing process, belonging to the field of semiconductor devices. Background Technology

[0002] Non-volatile memories, represented by floating-gate transistors, are core components of modern electronic systems. However, as the feature size of traditional silicon-based flash memory continues to shrink, the short-channel effect and quantum tunneling leakage current in the gate oxide layer become increasingly severe, and its physical scaling is approaching its limit. In recent years, two-dimensional van der Waals materials, represented by graphene, hexagonal boron nitride, and molybdenum disulfide, have provided a new path to overcome this bottleneck due to their atomic-level thickness, absence of dangling bonds on the surface, and excellent electrical properties. In particular, two-dimensional van der Waals heterojunction floating-gate memories based on Gr / h-BN / MoS2 have the theoretical potential to achieve large storage windows and long-term data retention capabilities because the MoS2 channel can provide a high on / off ratio, h-BN can serve as an ideal tunneling insulation layer, and Gr can serve as a highly efficient charge storage layer.

[0003] However, in the process of moving from theoretical conception to actual micro- and nano-fabrication, the actual performance of such devices has always been constrained by the fundamental problem of interface quality.

[0004] First, mainstream mechanical exfoliation and polymer-assisted dry transfer technologies introduce significant contamination at the interfaces of two-dimensional materials. Since the layers of two-dimensional materials are held together only by weak van der Waals forces, residual oligomers in the transfer medium and water and oxygen molecules from the environment are easily trapped at the heterojunction interface. These contaminants introduce high-density parasitic interface states and defect states with complex energy level distributions within the wide bandgap of h-BN. After high-voltage writing is completed, the charge stored in the Gr floating gate undergoes defect-assisted tunneling through these defect energy levels, leading to extremely rapid charge leakage at room temperature and a sharp degradation in data retention time. More critically, there is a technological blind spot regarding the aforementioned interface contamination problem that is not yet fully understood: during the layer-by-layer stacking of heterojunctions, the contaminants and stress introduced by the first stacked bottom layer interface are permanently sealed inside the interface by the subsequently transferred upper layer material. This means that after all devices are stacked, the interlayer impurities between the bottom Gr layer and the substrate, and between Gr and h-BN, are actually in a physically sealed state. This "interlayer impurity sealing" effect makes it difficult for any subsequent holistic treatment to reach and effectively remove these sources of pollution that are deeply buried under the multi-layered structure.

[0005] Secondly, the surface physicochemical state of the underlying substrate has a decisive influence on the leakage characteristics of the device, but this issue has long been underestimated in current processes. Many fabrication processes only perform conventional solvent ultrasonic cleaning on silicon-based substrates with SiO2, resulting in a surface that remains hydrophobic and contains numerous microscopic organic pinning points. This surface state makes it impossible for Gr transferred directly onto it to achieve large-area uniform adhesion, thus generating dense stress wrinkles and microbubbles. Under high write voltages, the tips of these micro-wrinkles generate strong local electric field distortions, causing the h-BN tunneling layer, which is only a few nanometers thick, to be subjected to electric field strengths far exceeding the design values ​​at local locations. This easily leads to local breakdown or accelerates charge leakage, physically compromising the non-volatility of the memory.

[0006] To address the aforementioned interface contamination problem, existing technologies generally employ a comprehensive high-temperature annealing process after all material transfer is completed. However, this comprehensive annealing approach has inherent drawbacks: firstly, because the impurities at the bottom interface are sealed off by the upper material, the heat energy from comprehensive annealing is insufficient to effectively expel them. Instead of being expelled, bubbles and contaminants in the interlayer may diffuse laterally within the enclosed space, causing interface defects over a larger area. Secondly, the high-temperature conditions (typically above 300°C) used to achieve impurity decomposition can easily lead to severe oxidation and etching of the edges of MoS2 and Gr under conventional rough or low vacuum conditions. This not only damages the intrinsic transport characteristics of the semiconductor channel but also introduces denser edge leakage channels, resulting in a significant deterioration in memory performance.

[0007] In summary, the fabrication of floating-gate memories based on two-dimensional material heterojunctions currently faces a systemic charge leakage problem stemming from a combination of factors: interfacial organic contamination, substrate-induced stress wrinkling, and annealing process mismatch. Existing technologies have not yet provided an effective means to proactively and systematically eliminate interfacial defects, suppress local electric field distortion, and optimize interlayer van der Waals bonding quality throughout the entire device fabrication process. This has resulted in such devices struggling to simultaneously achieve both a large storage window and long-term room-temperature retention. This situation constitutes a critical technological bottleneck that urgently needs to be overcome in this field. Summary of the Invention

[0008] To address the aforementioned technical problems, the present invention aims to provide a method for fabricating a Gr / h-BN / MoS2 heterojunction floating gate memory. After precisely treating a silicon substrate with ultraviolet ozone, a few-layer graphene (Gr), boron nitride (h-BN), and molybdenum sulfide (MoS2) thin films are sequentially and orientedly stacked on the silicon substrate using a dry transfer technique. Low-vacuum annealing is performed after each film transfer to completely remove impurities before they are physically sealed by the upper layers. This method solves the serious charge leakage problem faced by existing Gr / h-BN / MoS2 heterojunction floating gate memories due to interface organic contamination, stress wrinkling, and mismatched annealing processes.

[0009] To achieve the above objectives, the present invention first provides a method for preparing a Gr / h-BN / MoS2 heterojunction. The method includes first treating the SiO2 layer on the surface of a silicon substrate with ultraviolet ozone, then sequentially transferring the few layers of Gr, h-BN and MoS2 thin films obtained by mechanical exfoliation using a dry transfer technique, and performing vacuum annealing after transferring each thin film to obtain the Gr / h-BN / MoS2 heterojunction.

[0010] In one embodiment of the present invention, the preparation method of the Gr / h-BN / MoS2 heterojunction specifically includes the following steps: (1) The silicon substrate is placed in an ultraviolet ozone cleaner for pretreatment to obtain a pretreated silicon substrate; (2) A few-layer Gr film is obtained by mechanical peeling technology, and the few-layer Gr film is transferred to the surface of the silicon substrate pretreated in step (1) by PDMS dry transfer technology to obtain the Gr film; (3) The silicon substrate with the underlying Gr thin film is placed in an annealing furnace for annealing; (4) A few-layer h-BN film is obtained by mechanical exfoliation and the few-layer h-BN film is transferred to the Gr film that has been annealed in step (3) by PDMS dry transfer technology to obtain Gr / h-BN heterojunction; (5) The Gr / h-BN heterojunction obtained in step (4) is placed in an annealing furnace for annealing; (6) A few-layer MoS2 film is obtained by mechanical exfoliation and transferred to the Gr / h-BN heterojunction that has been annealed in step (5) by PDMS dry transfer technology to obtain Gr / h-BN / MoS2 heterojunction. (7) The Gr / h-BN / MoS2 heterojunction obtained in step (6) is placed in an annealing furnace for annealing to obtain a silicon-based Gr / h-BN / MoS2 heterojunction.

[0011] In one embodiment of the present invention, before the silicon substrate pretreatment described in step (1), a step of cleaning the silicon substrate is further included, wherein the cleaning is performed by sequentially placing the silicon substrate in acetone, ethanol and deionized water for ultrasonic cleaning, and then drying it.

[0012] In one embodiment of the present invention, step (1) specifically includes: first, placing the silicon substrate into acetone solution, ethanol solution and deionized water in sequence, cleaning it for 5 minutes under ultrasonic (frequency of 25KHz) conditions, then drying it with a nitrogen gun, and then cleaning it in an ultraviolet ozone cleaner for 5 minutes.

[0013] In one embodiment of the present invention, the silicon substrate in step (1) comprises a heavily doped silicon wafer (P) with a standard thermal oxide layer. ++ Si), whose original SiO2 layer on the surface is 285 nm or 300 nm thick.

[0014] In one embodiment of the present invention, in step (2), the few-layer Gr film is 20 to 30 layers, the total thickness of the Gr film is 7 to 10 nm, and the heating parameters when using PDMS dry transfer are: place the sample on the transfer heating stage, raise it from room temperature to 60 to 80°C at a rate of 1 to 1.5°C / s, hold for 3 to 5 minutes, and then allow it to cool naturally to release the two-dimensional material from the PDMS to the target location.

[0015] In one embodiment of the present invention, in step (4), the few-layer h-BN film has 20 to 40 layers, and the total thickness of the h-BN film is 8 to 15 nm. This thickness can effectively block direct electron tunneling while ensuring Fowler-Nordheim tunneling injection at a higher gate voltage. The heating parameters for dry transfer using PDMS are as follows: the sample is placed on the transfer heating stage, and the temperature is raised from room temperature to 60 to 80°C at a rate of 1 to 1.5°C / s. After holding for 3 minutes, the temperature is allowed to cool naturally, releasing the two-dimensional material from the PDMS to the target location.

[0016] In one embodiment of the present invention, in step (6), the few-layer MoS2 film is 15 to 30 layers, the total thickness of the MoS2 film is 10 to 25 nm, and the heating parameters for dry transfer using PDMS are as follows: place the sample on the transfer heating stage, raise the temperature from room temperature to 60 to 80°C at a rate of 1 to 1.5°C / s, hold for 3 minutes, and then allow it to cool naturally to release the two-dimensional material from the PDMS to the target location.

[0017] In one embodiment of the present invention, in steps (3), (5) and (7), the parameters of the annealing treatment are set as follows: the sample is placed in the vacuum quartz tube of the annealing furnace and the vacuum degree is evacuated to below 10 Pa; the temperature is uniformly raised from 20°C to 180~200°C within 60 minutes, and after being kept in a vacuum environment below 10 Pa for 1~1.5 hours, it is naturally cooled to room temperature with the furnace.

[0018] The present invention also provides a silicon-based Gr / h-BN / MoS2 heterojunction prepared according to the above preparation method.

[0019] The present invention also provides a method for fabricating a Gr / h-BN / MoS2 heterojunction floating gate memory. The method involves photolithographically etching a device structure on the surface of the aforementioned silicon-based Gr / h-BN / MoS2 heterojunction and depositing electrodes to obtain the Gr / h-BN / MoS2 heterojunction floating gate memory.

[0020] In one embodiment of the present invention, the specific steps of photolithography to form the device structure are as follows: placing the silicon-based Gr / h-BN / MoS2 heterojunction on a maskless photolithography stage, aligning the electrode pattern on both ends of the top layer MoS2 surface under a microscope, exposing the electrode area, masking the channel area, retaining the MoS2 channel 15 μm, and obtaining the device structure using photolithography.

[0021] In one embodiment of the present invention, the vapor-deposited electrode is a bismuth / gold composite metal electrode deposited using thermal evaporation technology, and the vacuum degree during electrode deposition is 1×10⁻⁶. -4 When the pressure is below Pa, the deposition rate of bismuth metal is 0.15~0.20 Å / s, the time is 4~5 minutes, and the thickness of the bismuth metal is 5 nm; when the gold metal is deposited, the deposition rate is 0.20~0.25 Å / s, the time is 30~35 minutes, and the thickness of the obtained electrode material is 50 nm.

[0022] The present invention also provides a Gr / h-BN / MoS2 heterojunction floating gate memory prepared according to the above preparation method.

[0023] Beneficial effects: (1) The present invention innovatively adopts the process of "layer-by-layer transfer combined with layer-by-layer vacuum annealing", which effectively avoids the problem of interlayer impurities being sealed off by the traditional "overall annealing". After each layer transfer, the polymer residue and water vapor are discharged in time, which fundamentally eliminates interface traps and parasitic defect states, and greatly improves the intrinsic cleanliness of the heterojunction. Its effect is far superior to the overall annealing method.

[0024] (2) Before transferring the underlying graphene (Gr), the present invention uses ultraviolet ozone (UV-Ozone) to precisely clean the silicon substrate. This step removes surface hydrocarbon contaminants without damage and constructs an extremely hydrophilic high surface energy substrate without destroying the roughness of the oxide layer, which greatly enhances the van der Waals adsorption force between the graphene and the substrate.

[0025] (3) Thanks to the highly hydrophilic substrate and the layer-by-layer annealing process, the present invention effectively eliminates the stress wrinkles and micro bubbles of the bottom graphene, avoids local field distortion under high electric field, protects the upper h-BN tunneling insulating layer from local high field breakdown, and significantly enhances the device's tolerance and service life.

[0026] (4) By constructing an ultra-clean van der Waals interface, this invention significantly reduces the shallow level trap density at the h-BN layer and interface, effectively blocking the defect-assisted tunneling (TAT) leakage path of electrons, fundamentally solving the problem of rapid charge leakage in traditional devices, and achieving long-term data retention and a stable storage window.

[0027] (5) The present invention strictly controls the thickness of the h-BN tunneling layer to 10 nm. This parameter can effectively block the direct tunneling leakage of charge under zero gate voltage, and ensure that electrons are efficiently injected through the FN tunneling effect under the write voltage, thus achieving a perfect balance between write efficiency and non-volatile storage.

[0028] (6) The present invention uses specific vacuum annealing parameters of less than 10 Pa and 200°C, which not only efficiently removes impurities but also perfectly avoids the risk of oxidation and etching at the material edges. The overall process is simple to operate, highly controllable, and highly compatible with existing silicon-based CMOS processes, making it easy to achieve large-scale integration of multiple devices. Attached Figure Description

[0029] Figure 1 This is a flowchart illustrating the fabrication process of the Gr / h-BN / MoS2 heterojunction floating gate memory in Example 1; Figure 2 These are the temperature-time curves of the annealing process used in steps (3), (5), and (7) of Example 1; Figure 3 (a) is a schematic diagram of the gate voltage scan curve of the heterojunction floating gate memory in Example 1. Figure 3 (b) is a schematic diagram of the storage time after applying the gate voltage pulse; Figure 4 (a) is a schematic diagram of the gate voltage scan curve of the heterojunction floating gate memory in Comparative Example 1. Figure 4 (b) is a schematic diagram of the storage time after applying the gate voltage pulse; Figure 5(a) is a schematic diagram of the gate voltage scan curve of the heterojunction floating gate memory in Comparative Example 2. Figure 5 (b) is a schematic diagram of storage time; Figure 6 (a) is a schematic diagram of the gate voltage scan curve of the heterojunction floating gate memory in Comparative Example 3. Figure 6 (b) is a schematic diagram of storage time; Detailed Implementation The preferred embodiments of the present invention are described below. It should be understood that the embodiments are for better explanation of the present invention and are not intended to limit the present invention.

[0030] Test method: Electrical performance testing: The source meter used for testing was a Keithley 2634 test source meter. The specific testing method is as follows: Set the source-drain voltage to 1V, and the gate voltage to ±20V, ±30V, and ±40V respectively, and cyclically scan the device's storage characteristics; after applying a 30V 1s gate pulse voltage, set the source-drain voltage to 1V and test the source-drain current; after applying a -30V 1s gate pulse voltage, set the source-drain voltage to 0.5V and test the source-drain current. Raw materials used in the examples: Gr thin films are prepared by mechanical exfoliation. The specific steps are as follows: First, a portion of the sample is adhered to the surface of the Gr crystal using a special blue film for mechanical exfoliation. Then, the tapes are torn apart from each other and repeated ten times. When the sample remaining on the tapes turns gray, a few layers of Gr thin film are obtained. h-BN thin films are prepared by mechanical exfoliation. The specific steps are as follows: First, a portion of the sample is adhered to the surface of the h-BN crystal using a special blue film for mechanical exfoliation. Then, the tapes are torn apart from each other and repeated ten times. When the sample remaining on the tapes is nearly transparent, a few-layer h-BN thin film is obtained. MoS2 thin films are prepared by mechanical exfoliation. The specific steps are as follows: First, a portion of the sample is adhered to the surface of the MoS2 crystal using a special blue film for mechanical exfoliation. Then, the tapes are peeled off one by one. This process is repeated ten times until the sample remaining on the tapes turns gray, at which point a few layers of MoS2 thin film are obtained. PDMS dry transfer technology: A Gr-containing tape is applied to the PDMS surface. After standing for 1-2 hours, the tape is peeled off, leaving the Gr sample on the polydimethylsiloxane (PDMS) surface. The sample is placed on a transfer heating stage, and the PDMS with the Gr sample is then bonded to the treated silicon substrate surface using the transfer platform. The temperature is raised from room temperature to 80°C at a rate of 1°C / s, held for 3 minutes, and then allowed to cool naturally, releasing the Gr from the PDMS to the target location. The Gr sample is then transferred to the substrate surface. Alternatively, an h-BN-containing tape is applied to the PDMS surface. After standing for 1-2 hours, the tape is peeled off, leaving the h-BN sample on the PDMS surface. The sample is then placed on a transfer heating stage, and the PDMS with the h-BN sample is then bonded to the already transferred substrate surface using the transfer platform. On the silicon substrate surface of Gr, the temperature was heated from room temperature to 80°C at a rate of 1°C / s, held for 3 minutes, and then allowed to cool naturally. This released h-BN from PDMS onto Gr, thus transferring the h-BN sample to the Gr surface. A tape containing MoS2 was then applied to the PDMS surface and left to stand for 1-2 hours before being peeled off, leaving the MoS2 sample on the polydimethylsiloxane (PDMS) surface. The sample was then placed on a transfer heating stage, and the PDMS containing the MoS2 sample was then bonded to the silicon substrate surface on which Gr / h-BN had already been transferred using the transfer platform. The temperature was then heated from room temperature to 80°C at a rate of 1°C / s, held for 3 minutes, and then allowed to cool naturally. This released MoS2 from the PDMS onto the overlapping portion of Gr and h-BN, thus transferring the MoS2 sample to the Gr / h-BN heterojunction surface. The PDMS substrate used was prepared in-house. During preparation, Dow Corning SYLGARD 184 silicone rubber and curing agent were first mixed at a weight ratio of 10:1 and stirred evenly. After all the bubbles disappeared, the mixture was placed in a heated vacuum drying oven and baked at 60°C for 10 hours to achieve deep cross-linking, resulting in a transparent film with a dry surface and extremely low oligomer residue. The electrodes are prepared by vapor deposition, specifically including bismuth and gold metals prepared by thermal vapor deposition; wherein, when preparing bismuth metal by thermal vapor deposition, the vacuum conditions of the vapor deposition machine must meet 1×10⁻⁶. -4 For deposition rates below Pa, the deposition rate is 0.15–0.20 Å / s, the deposition time is 4–5 minutes, and the resulting electrode material thickness is 5 nm. When preparing gold metal by thermal evaporation, the vacuum conditions of the evaporation machine must meet 1 × 10⁻⁶ Å / s. -4 Below Pa, the deposition rate used was 0.20~0.25 Å / s, the time was 30~35 minutes, and the thickness of the obtained electrode material was 50 nm.

[0031] Example 1 A method for fabricating Gr / h-BN / MoS2 heterojunction floating gate memory, the process is as follows: Figure 1It includes the following steps: (1) Substrate cleaning: A silicon wafer coated with a 300nm silicon dioxide layer was used as the substrate. The substrate was placed in acetone, anhydrous ethanol and deionized water for ultrasonic cleaning for 5 minutes each to remove organic matter on the surface. The ultrasonic frequency was 25KHz. After that, it was dried with a nitrogen gun and placed in an ultraviolet ozone cleaner to clean the surface of the silicon substrate with ozone. The reaction time was 5min. (2) A few-layer Gr film is obtained by mechanical peeling and then rapidly transferred to the surface of the silicon substrate pretreated in step (1) by PDMS dry transfer technology to obtain a Gr film; (3) Place the transferred bottom Gr film into an annealing furnace for annealing; (4) A few-layer h-BN film is obtained by mechanical peeling technology and the few-layer h-BN film is transferred to the Gr film that has been annealed in step (4) by PDMS dry transfer technology to obtain Gr / h-BN heterojunction; (5) Place the transferred Gr / h-BN heterojunction into an annealing furnace for annealing; (6) A few-layer MoS2 film was obtained by mechanical exfoliation and the few-layer MoS2 was transferred to the Gr / h-BN that had been annealed in step (5) by PDMS dry transfer technology to obtain Gr / h-BN / MoS2 heterojunction; (7) Place the transferred Gr / h-BN / MoS2 heterojunction into an annealing furnace for annealing; (8) Place the silicon-based Gr / h-BN / MoS2 heterojunction obtained in step (7) on a photolithography stage, use photolithography to etch the device structure, evaporate the electrode, and obtain the Gr / h-BN / MoS2 heterojunction floating gate memory. The annealing process parameters in steps (3), (5), and (7) are as follows: Figure 2 As shown, the sample is first placed in the vacuum quartz tube of the annealing furnace, and the vacuum degree is evacuated to below 10 Pa. The temperature is then uniformly increased from 20℃ to 200℃ within 60 minutes, and maintained in a vacuum environment below 10 Pa for 1 hour before being naturally cooled to room temperature with the furnace.

[0032] Comparative Example 1 The difference between Comparative Example 1 and Example 1 is that steps (3), (5) and (7) are omitted, that is, no annealing is performed after each transfer, resulting in Gr / h-BN / MoS2 heterojunction floating gate memory.

[0033] Comparative Example 2 The difference between Comparative Example 2 and Example 1 is that the annealing parameters in steps (3), (5), and (7) are changed, i.e., the vacuum degree is reduced to below 10 Pa; the temperature is uniformly increased from 20°C to 200°C within 15 minutes, maintained in a vacuum environment below 10 Pa for 1 hour, and then cooled to room temperature. Everything else is the same as in Example 1, resulting in a Gr / h-BN / MoS2 heterojunction floating gate memory.

[0034] Comparative Example 3 The difference between Comparative Example 3 and Example 1 is that steps (8) and (11) are omitted, and only step (5) is retained. That is, Gr is placed in an annealing furnace for high-temperature annealing only after the Gr transfer stacking is completed. The annealing parameters and other steps are the same as in Example 1. Then, h-BN and / MoS2 are stacked and transferred in sequence to obtain Gr / h-BN / MoS2 heterojunction floating gate memory.

[0035] The electrical performance of the Gr / h-BN / MoS2 heterojunction floating-gate memories prepared in Example 1 and Comparative Examples 1-4 was tested, and the test results are as follows: Figures 3-6 As shown in Table 1. Figure 3 (a) is the gate voltage cycle scan curve of the device prepared in Example 1, from... Figure 3 (a) It can be seen that the device has a good storage effect and a large storage window, with an on / off ratio of approximately 10. 6 . Figure 3 (b) shows the change in current after applying positive and negative gate voltage pulses, from... Figure 3 (b) It can be seen that the device has good retention characteristics within 1000s.

[0036] Figure 4 (a) Gate voltage cycle scan curve of the device prepared without annealing treatment, from... Figure 4 (a) It can be seen that the device has a good storage effect and a large storage window, with an on / off ratio of approximately 10. 6 . Figure 4 (b) shows the change in current after applying positive and negative gate voltage pulses, from... Figure 4 (b) It can be seen that after the gate voltage pulse is removed, the device experiences rapid current leakage within 10 seconds.

[0037] Figure 5 (a) is the gate voltage cycle scan curve of the device prepared by rapid heating annealing. Figure 5 (a) It can be seen that the device has a good storage effect and a large storage window, with an on / off ratio of approximately 10. 3 . Figure 5 (b) shows the change in current after applying positive and negative gate voltage pulses, from... Figure 5 (b) It can be seen that the device leaks current rapidly within 10 seconds after the gate voltage pulse is removed.

[0038] Figure 6 (a) is the gate voltage cycle scan curve of the device prepared by a single annealing process, from... Figure 6 (a) It can be seen that the device has a good storage effect and a large storage window, with an on / off ratio of approximately 10. 6 . Figure 6 (a) shows the change in current after applying positive and negative gate voltage pulses, from Figure 6 (b) It can be seen that after the gate voltage pulse is removed, the leakage current in the high-resistivity state stabilizes at the level of -13, and the source leakage current in the low-resistivity state decreases from the level of -6 to the level of -8 within 1000s.

[0039] Table 1. Performance comparison of devices under different processes

[0040] Table 1 compares the performance of devices under different processes. The table shows significant variations in the storage window across different processes. This is because the size of the storage window is not only related to the thickness of materials such as boron nitride and molybdenum sulfide, but also closely related to the annealing process. When the device undergoes an annealing process at an appropriate rate, the graphene interface becomes clean and tidy, resulting in lower and more stable leakage current, which is more conducive to achieving a larger on / off ratio. In terms of storage time, only devices that have undergone three-layer annealing exhibit the most stable storage. Devices that are not sufficiently annealed (such as those with only annealed graphene or no annealing) show a large storage window in initial tests, but this is mainly due to spurious windows contributed by numerous interface defect states participating in charging and discharging. These spurious windows are prone to defect-assisted tunneling under high gate voltage pulses, leading to rapid charge leakage. The three-layer annealing process effectively eliminates parasitic interface states, and the measured window is the intrinsic, long-term stable true storage window of the device.

[0041] The embodiments provided above are not intended to limit the scope of the invention, nor are the described steps intended to limit the order of execution. Any obvious modifications made to the invention by those skilled in the art based on existing common knowledge also fall within the scope of protection defined by the claims.

Claims

1. A method for preparing a Gr / h-BN / MoS2 heterojunction, characterized in that, The method includes first treating the SiO2 layer on the surface of a silicon substrate with ultraviolet ozone, then sequentially transferring the few-layer Gr, h-BN and MoS2 films obtained by mechanical exfoliation using a dry transfer technique, and performing vacuum annealing after transferring each film to obtain a Gr / h-BN / MoS2 heterojunction.

2. The preparation method according to claim 1, characterized in that, The preparation method of the Gr / h-BN / MoS2 heterojunction specifically includes the following steps: (1) The silicon substrate is placed in an ultraviolet ozone cleaner for pretreatment to obtain a pretreated silicon substrate; (2) A few-layer Gr film is obtained by mechanical peeling technology, and the few-layer Gr film is transferred to the surface of the silicon substrate pretreated in step (1) by PDMS dry transfer technology to obtain the Gr film; (3) The silicon substrate with the underlying Gr thin film is placed in an annealing furnace for annealing; (4) A few-layer h-BN film is obtained by mechanical exfoliation and the few-layer h-BN film is transferred to the Gr film that has been annealed in step (3) by PDMS dry transfer technology to obtain Gr / h-BN heterojunction; (5) The Gr / h-BN heterojunction obtained in step (4) is placed in an annealing furnace for annealing; (6) A few-layer MoS2 film is obtained by mechanical exfoliation and transferred to the Gr / h-BN heterojunction that has been annealed in step (5) by PDMS dry transfer technology to obtain Gr / h-BN / MoS2 heterojunction. (7) The Gr / h-BN / MoS2 heterojunction obtained in step (6) is placed in an annealing furnace for annealing to obtain a silicon-based Gr / h-BN / MoS2 heterojunction.

3. The preparation method according to claim 2, characterized in that, Before the silicon substrate pretreatment described in step (1), a cleaning step is also included, wherein the silicon substrate is ultrasonically cleaned sequentially by placing it in acetone, ethanol, and deionized water, and then dried; the silicon substrate includes a heavily doped silicon wafer (P) with a standard thermal oxide layer. ++ Si), whose original SiO2 layer on the surface is 285 nm or 300 nm thick.

4. The preparation method according to claim 2, characterized in that, In steps (2), (4) and (6), the heating parameters for dry transfer using PDMS are as follows: place the sample on the transfer heating stage, raise the temperature from room temperature to 60~80℃ at a rate of 1~1.5℃ / s, hold for 3~5 minutes, and then allow it to cool naturally to release the two-dimensional material from the PDMS to the target location.

5. The preparation method according to claim 2, characterized in that, In steps (3), (5) and (7), the parameters for annealing are set as follows: the sample is placed in the vacuum quartz tube of the annealing furnace and the vacuum degree is evacuated to below 10 Pa; the temperature is raised from 20°C to 180~200°C at a constant rate within 60 minutes, and after being kept in a vacuum environment below 10 Pa for 1~1.5 hours, it is naturally cooled to room temperature with the furnace.

6. A silicon-based Gr / h-BN / MoS2 heterojunction prepared by the preparation method according to any one of claims 1 to 5.

7. A method for fabricating a Gr / h-BN / MoS2 heterojunction floating gate memory, characterized in that, The device structure is photolithographically etched on the surface of the silicon-based Gr / h-BN / MoS2 heterojunction as described in claim 6, and electrodes are deposited by vapor deposition to obtain the Gr / h-BN / MoS2 heterojunction floating gate memory.

8. The preparation method according to claim 7, characterized in that, The specific steps for photolithography to create the device structure are as follows: a silicon-based Gr / h-BN / MoS2 heterojunction is placed on a maskless photolithography stage. Under a microscope, the electrode pattern is aligned with both ends of the top layer MoS2 surface to expose the electrode area and mask the channel area, leaving the MoS2 channel at 15 μm. The device structure is then obtained using photolithography.

9. The preparation method according to claim 7, characterized in that, The vapor-deposited electrode is a bismuth / gold composite metal electrode deposited using thermal evaporation technology, with a vacuum degree of 1×10⁻⁶ during electrode deposition. -4 When the pressure is below Pa, the deposition rate of bismuth metal is 0.15~0.20 Å / s, the time is 4~5 minutes, and the thickness of the bismuth metal is 5 nm; when the gold metal is deposited, the deposition rate is 0.20~0.25 Å / s, the time is 30~35 minutes, and the thickness of the obtained electrode material is 50 nm.

10. The Gr / h-BN / MoS2 heterojunction floating gate memory prepared by the preparation method according to any one of claims 7 to 9.

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