Semiconductor device and semiconductor memory device

Abstract

A semiconductor device and a semiconductor memory device capable of reducing a parasitic capacitance between electrodes are provided. The semiconductor device includes a plurality of oxide semiconductors having a first end and a second end, extending in a first direction from the second end toward the first end; a plurality of first electrodes respectively connected to the first end of the plurality of oxide semiconductors; a plurality of second electrodes respectively connected to the second end of the plurality of oxide semiconductors; a gate electrode extending in a second direction intersecting the first direction, and surrounding the oxide semiconductors with a first insulating film interposed between the first end and the second end of each of the plurality of oxide semiconductors arranged along the second direction; and a cavity portion provided at least partially between two adjacent second electrodes.

Description

Technical Field

[0001] This embodiment relates to a semiconductor device and a semiconductor memory device. Background Technology

[0002] Among semiconductor devices, there are semiconductor devices formed from oxide semiconductors.

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2024-31350 Summary of the Invention

[0004] The industry is demanding a technology that can reduce parasitic capacitance between electrodes.

[0005] The purpose of this invention is to provide a semiconductor device and a semiconductor memory device that can reduce the parasitic capacitance between electrodes.

[0006] The semiconductor device of the present invention comprises: a plurality of oxide semiconductors having a first end and a second end, extending in a first direction from the second end toward the first end; a plurality of first electrodes respectively connected to the first ends of the plurality of oxide semiconductors; a plurality of second electrodes respectively connected to the second ends of the plurality of oxide semiconductors; a gate electrode extending along a second direction intersecting the first direction, and the oxide semiconductors are surrounded by a first insulating film between the first ends and the second ends of the plurality of oxide semiconductors disposed along the second direction; and a cavity portion at least partially disposed between two adjacent second electrodes. Attached Figure Description

[0007] Figure 1 This is a circuit diagram used to illustrate an example of the circuit configuration of the memory cell array in the first embodiment.

[0008] Figure 2 This is a cross-sectional schematic diagram used to illustrate a construction example of the semiconductor memory device of the first embodiment, showing a cross-sectional view parallel to the ZX plane.

[0009] Figure 3 This is a detailed cross-sectional view of the semiconductor device 30 as viewed along a section 70ZA parallel to the ZA plane and contained within the oxide semiconductor layer 70.

[0010] Figure 4 This is a detailed cross-sectional view of the semiconductor device 30 as viewed along a section 70YZ parallel to the YZ plane and contained within the oxide semiconductor layer 70.

[0011] Figure 5 yes Figure 3 and Figure 4 The cross-sectional view shown at the cut line VV.

[0012] Figure 6 yes Figure 3 and Figure 4 The sectional view shown at the cut line VI-VI.

[0013] Figure 7 This is a cross-sectional view parallel to plane ZA, showing the manufacturing process of the semiconductor device 30 of the first embodiment.

[0014] Figure 8 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device 30 of the first embodiment.

[0015] Figure 9 yes Figure 7 and Figure 8 The cross-sectional view at the cut line IX-IX shown.

[0016] Figure 10 yes Figure 7 and Figure 8 The sectional view shown at the cut line XX.

[0017] Figure 11 This is a cross-sectional view parallel to plane ZA, showing the first manufacturing process of the semiconductor device 30 according to the first embodiment.

[0018] Figure 12 This is a cross-sectional view parallel to the YZ plane, showing the first manufacturing process of the semiconductor device 30 according to the first embodiment.

[0019] Figure 13 yes Figure 11 and Figure 12 The cross-sectional view shown at the cut line XIII-XIII.

[0020] Figure 14 yes Figure 11 and Figure 12 The cross-sectional view shown at the cut line XIV-XIV.

[0021] Figure 15 This is a cross-sectional view parallel to plane ZA, showing the first manufacturing process of the semiconductor device 30 according to the first embodiment.

[0022] Figure 16 This is a cross-sectional view parallel to the YZ plane, showing the first manufacturing process of the semiconductor device 30 according to the first embodiment.

[0023] Figure 17 This is a cross-sectional view parallel to plane ZA, showing the first manufacturing process of the semiconductor device 30 according to the first embodiment.

[0024] Figure 18 This is a cross-sectional view parallel to the YZ plane, showing the first manufacturing process of the semiconductor device 30 according to the first embodiment.

[0025] Figure 19 This is a cross-sectional view parallel to plane ZA, showing the first manufacturing process of the semiconductor device 30 according to the first embodiment.

[0026] Figure 20 This is a cross-sectional view parallel to the YZ plane, showing the first manufacturing process of the semiconductor device 30 according to the first embodiment.

[0027] Figure 21 This is a cross-sectional view parallel to plane ZA, showing the first manufacturing process of the semiconductor device 30 according to the first embodiment.

[0028] Figure 22 This is a cross-sectional view parallel to the YZ plane, showing the first manufacturing process of the semiconductor device 30 according to the first embodiment.

[0029] Figure 23 yes Figure 21 and Figure 22 The cross-sectional view shown at the cut line XXIII-XXIII.

[0030] Figure 24 This is a cross-sectional view parallel to plane ZA, showing the second manufacturing process of the semiconductor device 30B according to the first embodiment.

[0031] Figure 25 This is a cross-sectional view parallel to the YZ plane, showing the second manufacturing process of the semiconductor device 30B according to the first embodiment.

[0032] Figure 26 yes Figure 24 and Figure 25 The sectional view shown at the cut line XXVI-XXVI.

[0033] Figure 27 yes Figure 24 and Figure 25 The sectional view shown at the cut line XXVII-XXVII.

[0034] Figure 28 This is a cross-sectional view parallel to plane ZA, showing the second manufacturing process of the semiconductor device 30B according to the first embodiment.

[0035] Figure 29 This is a cross-sectional view parallel to the YZ plane, showing the second manufacturing process of the semiconductor device 30B according to the first embodiment.

[0036] Figure 30 yes Figure 28 and Figure 29 The sectional view shown at the cut line XXX-XXX.

[0037] Figure 31This is a cross-sectional view parallel to plane ZA, showing the second manufacturing process of the semiconductor device 30B according to the first embodiment.

[0038] Figure 32 yes Figure 31 The sectional view shown at the cut line XXXII-XXXII.

[0039] Figure 33 yes Figure 31 The sectional view shown at the cut line XXXIII-XXXIII.

[0040] Figure 34 This is a cross-sectional view parallel to plane ZA, showing the second manufacturing process of the semiconductor device 30B according to the first embodiment.

[0041] Figure 35 This is a cross-sectional view parallel to plane ZA, showing the second manufacturing process of the semiconductor device 30B according to the first embodiment.

[0042] Figure 36 yes Figure 34 and Figure 35 The sectional view shown is taken at the cut line XXXVI-XXXVI.

[0043] Figure 37 yes Figure 34 and Figure 35 The sectional view shown at the cut line XXXVII-XXXVII.

[0044] Figure 38 This is a cross-sectional view parallel to plane ZA, showing the second manufacturing process of the semiconductor device 30B according to the first embodiment.

[0045] Figure 39 This is a cross-sectional view parallel to plane ZA, showing the second manufacturing process of the semiconductor device 30B according to the first embodiment.

[0046] Figure 40 yes Figure 38 and Figure 39 The cross-sectional view shown at the cut line XL-XL.

[0047] Figure 41 yes Figure 38 and Figure 39 The cross-sectional view shown at the cut line XLI-XLI.

[0048] Figure 42 This is a cross-sectional view parallel to plane ZA, showing the second manufacturing process of the semiconductor device 30B according to the first embodiment.

[0049] Figure 43 This is a cross-sectional view parallel to the YZ plane, showing the second manufacturing process of the semiconductor device 30B according to the first embodiment.

[0050] Figure 44 yes Figure 42 and Figure 43 The cross-sectional view shown at the cut line XLIV-XLIV.

[0051] Figure 45 This is a detailed cross-sectional view of the semiconductor device 30C as viewed along a section 70ZA that is parallel to the ZA plane and contained within the oxide semiconductor layer 70.

[0052] Figure 46 yes Figure 45 The sectional view shown is taken at the cut line XLVI-XLVI.

[0053] Figure 47 This is a detailed cross-sectional view of the semiconductor device 30D as viewed along a section 70ZA that is parallel to the ZA plane and contained within the oxide semiconductor layer 70.

[0054] Figure 48 This is a detailed cross-sectional view of the semiconductor device 30D as viewed along a section 70YZ parallel to the YZ plane and contained within the oxide semiconductor layer 70.

[0055] Figure 49 yes Figure 47 and Figure 48 The cross-sectional view shown at the cut line XLIX-XLIX.

[0056] Figure 50 This is a detailed cross-sectional view of the semiconductor device 30E as viewed along a section 70ZA parallel to the ZA plane and contained within the oxide semiconductor layer 70.

[0057] Figure 51 This is a detailed cross-sectional view of the semiconductor device 30E as viewed along a section 70YZ parallel to the YZ plane and contained within the oxide semiconductor layer 70.

[0058] Figure 52 yes Figure 50 and Figure 51 The cross-sectional view shown at the cut line LII-LII.

[0059] Figure 53 This is a detailed cross-sectional view of the semiconductor device 30F as viewed along a section 70ZA that is parallel to the ZA plane and contained within the oxide semiconductor layer 70.

[0060] Figure 54 yes Figure 53 The cross-sectional view shown at the cut line LV-LV.

[0061] Figure 55This is a detailed cross-sectional view of the semiconductor device 30G as viewed along a section 70ZA parallel to the ZA plane and contained within the oxide semiconductor layer 70. Detailed Implementation

[0062] Hereinafter, this embodiment will be described with reference to the accompanying drawings. For ease of understanding, the same symbols will be used to label the same components in each drawing as much as possible, and repeated descriptions will be omitted.

[0063] [First Implementation]

[0064] The configuration of the semiconductor memory device according to the first embodiment will be described. The X-axis, Y-axis, and Z-axis are sometimes shown in the accompanying drawings. The X-axis, Y-axis, and Z-axis form a right-handed three-dimensional orthogonal coordinate system. Hereinafter, the direction of the arrow on the X-axis is sometimes referred to as the X-axis+ direction, and the direction opposite to the arrow is sometimes referred to as the X-axis- direction; the same applies to the other axes. Furthermore, the Z-axis+ direction and Z-axis- direction are sometimes referred to as "above" and "below," respectively. Additionally, the plane orthogonal to the X-axis, Y-axis, or Z-axis is sometimes referred to as the YZ plane, ZX plane, or XY plane. Furthermore, the Z-axis direction is sometimes referred to as the "vertical direction." "Above," "below," and "vertical direction" are merely terms indicating relative positional relationships within the accompanying drawings and do not necessarily refer to orientations based on the vertical direction.

[0065] In addition, unless otherwise specifically stated, the dimensions of the constituent elements shown in the accompanying drawings are sometimes expressed differently from the actual dimensions for ease of understanding.

[0066] In this specification, "connection" includes not only physical connections but also electrical connections, and unless otherwise specified, it includes not only direct connections but also indirect connections.

[0067] In this specification, "formed above" includes not only the case where it is formed in contact with the ground above, but also, unless otherwise specified, the case where it is formed above, separating other objects. The same applies to cases such as "formed below".

[0068] The semiconductor memory device 101 of the first embodiment is an OCTRAM (Oxide semiconductor Channel Transistor RAM) and includes a memory cell array.

[0069] like Figure 1 As shown, the memory cell array includes multiple memory cells (MC), multiple word lines (WL), and multiple bit lines (BL).

[0070] Figure 1In the example of multiple word lines WL, word line WL is shown. n 、Word line WL n+1 WL (with character line) n+2 (Here, n is a positive integer). Additionally... Figure 1 In the example shown, the bit line BL is illustrated. m Bitline BL m+1 and position line BL m+2 (Here, m is a positive integer). Furthermore, the number of memory cells (MCs) is not limited to... Figure 1 The number shown.

[0071] Multiple memory cells (MCs) can be arranged in a matrix to form a memory cell array. A memory cell (MC) includes a memory transistor (MTR) that functions as a field-effect transistor (FET) and a memory capacitor (MCP).

[0072] A series of memory cells MC arranged along the row direction are connected to the word line WL (e.g., word line WL) corresponding to their respective row (e.g., the nth row). n A series of memory cells MC arranged along the column direction are connected to the bit line BL corresponding to their respective column (e.g., the (m+2)th column). m+2 ).

[0073] In detail, the gate of the memory transistor MTR contained in the memory cell MC is connected to the word line WL corresponding to the row to which the memory cell MC belongs. One of the source or drain of the memory transistor MTR is connected to the bit line BL corresponding to the column to which the memory cell MC belongs.

[0074] One electrode of the memory capacitor MCP contained in the memory cell MC is connected to the other electrode of the memory transistor MTR contained in the memory cell MC. The other electrode of the memory cell MC is connected to a power supply line (not shown) that provides a specific potential.

[0075] The memory cell MC is configured such that by switching the memory transistor MTR based on the potential of the corresponding word line WL, the current flowing through the corresponding bit line BL is used to accumulate charge in the memory capacitor MCP, thereby enabling data storage.

[0076] like Figure 2As shown, the semiconductor memory device 101 includes: a semiconductor substrate 10, a circuit 11 (an example of a "semiconductor circuit"), a capacitor 20, a semiconductor device 30, a conductor 33, and insulating layers 34, 35 and 63.

[0077] The capacitor 20 includes: an insulating film 22 (an example of a “dielectric film”), a conductor 23, a capacitor electrode 24 (an example of a “first capacitor electrode”), and a capacitor electrode 25 (an example of a “second capacitor electrode”).

[0078] The semiconductor device 30 includes: a plurality of field-effect transistors 40 (an example of a “semiconductor element”), a plurality of upper electrodes 50 disposed above the field-effect transistors 40 (an example of a “first electrode”), a plurality of lower electrodes 32 disposed below the field-effect transistors 40 (an example of a “second electrode”), and a plurality of conductive layers 51 (an example of a “bit electrode”).

[0079] The field-effect transistor 40 includes: an oxide semiconductor layer 70 (an example of "oxide semiconductor"), a gate insulating film 43 (an example of "first insulating film"), a conductive layer 42 (an example of "gate electrode"), and an insulating layer 45. The field-effect transistor 40 corresponds to the memory transistor MTR of the memory cell MC (see reference). Figure 1 ).

[0080] An oxide semiconductor layer 70 is formed in the insulating layer 45, having an upper end 70a (an example of a "first end") and a lower end 70b (an example of a "second end"). The oxide semiconductor layer 70 is a columnar body extending in the Z-axis+ direction (an example of a "first direction") from the lower end 70b toward the upper end 70a. The oxide semiconductor layer 70 forms the channel of the field-effect transistor 40. The oxide semiconductor layer 70 has an amorphous structure.

[0081] The oxide semiconductor layer 70 is a semiconductor with oxygen vacancies as donors. The oxide semiconductor layer 70 contains at least one of indium (In), gallium (Ga), aluminum (Al), zinc (Zn), tin (Sn), titanium (Ti), tungsten (W), molybdenum (Mo), iridium (Ir), and ruthenium (Ru), as well as oxygen.

[0082] In this embodiment, the oxide semiconductor layer 70 contains indium, zinc, and gallium as metal elements. Specifically, the oxide semiconductor layer 70 is an oxide of indium, gallium, and zinc, namely IGZO (InGaZnO). Alternatively, the oxide semiconductor layer 70 can also be other types of oxide semiconductors.

[0083] The field-effect transistor 40 is a so-called vertical transistor having a channel extending in the Z-axis direction (vertical direction) that is substantially perpendicular to the surface of the semiconductor substrate 10.

[0084] The upper electrode 50 is formed above the oxide semiconductor layer 70. The plurality of upper electrodes 50 are respectively connected to the upper ends 70a of the plurality of oxide semiconductor layers 70.

[0085] The conductive layer 51 is connected to the upper end 70a of the oxide semiconductor layer 70 via the upper electrode 50. The conductive layer 51 contains, for example, tungsten (W).

[0086] Conductive layer 51 extends above conductive layer 42 along the X-axis. Multiple conductive layers 51 are provided. Multiple conductive layers 51 are repeatedly provided along the Y-axis. Multiple conductive layers 51 are separated from each other along the Y-axis. Conductive layer 51 corresponds to bit line BL (see reference). Figure 1 In this embodiment, the width of the conductive layer 51 in the Y-axis direction is approximately fixed.

[0087] A lower electrode 32 is formed beneath the oxide semiconductor layer 70. Multiple lower electrodes 32 are respectively connected to the lower ends 70b of multiple oxide semiconductor layers 70. The lower electrodes 32 comprise conductive oxides. Specifically, the lower electrodes 32 are formed, for example, of a metal oxide comprising indium and tin as metal elements. In this embodiment, the lower electrodes 32 are formed of indium-tin oxide (ITO).

[0088] Circuit 11 comprises peripheral circuitry such as a decoder for selecting a specific memory cell MC from among the plurality of memory cells MC in the semiconductor memory device 101 (i.e., capacitors 20 and field-effect transistors 40), a sense amplifier connected to the bit line BL, and a register containing SRAM. Circuit 11 may include CMOS circuitry with field-effect transistors having P-channel field-effect transistors (Pch-FETs) and N-channel field-effect transistors (Nch-FETs) formed by CMOS process.

[0089] The field-effect transistor in circuit 11 can be formed using a semiconductor substrate 10, such as a single-crystal silicon (Si) substrate. P-FETs and N-FETs are so-called horizontal field-effect transistors, meaning that the semiconductor substrate 10 has a channel region, a source region, and a drain region, and has channels near the surface of the semiconductor substrate 10 for allowing carriers to flow in the X-axis or Y-axis direction, which is approximately parallel to the surface of the semiconductor substrate 10. Furthermore, the semiconductor substrate 10 can also have P-type or N-type conductivity. Figure 2For convenience, an example of the field-effect transistor of circuit 11 is shown in the figure.

[0090] Capacitor 20 is the memory capacitor MCP included in the memory cell MC (refer to...). Figure 1 ). Figure 2 The diagram shows four capacitors 20, but the number of capacitors 20 is not limited to four.

[0091] In this embodiment, capacitor 20 is disposed above semiconductor substrate 10. Capacitor electrode 24 in capacitor 20 is disposed below lower electrode 32. Capacitor electrode 24 is connected to lower electrode 32 via conductor 21.

[0092] Capacitor electrode 25 faces capacitor electrode 24. Insulating film 22 is disposed between capacitor electrode 24 and capacitor electrode 25.

[0093] Capacitor 20 is a three-dimensional capacitor such as a pillar capacitor. Alternatively, other capacitors with a configuration capable of storing charge may also be used as the capacitor in this embodiment.

[0094] Specifically, capacitor electrode 24 is located below lower electrode 32. Capacitor electrode 24 has an upper end facing the lower end face of lower electrode 32, separated from conductor 21, and has a columnar shape extending downward from this upper end. Conductor 21 is formed to cover both lower electrode 32 and capacitor electrode 24.

[0095] The insulating film 22 is formed to cover the conductor 21. The capacitor electrode 25 surrounds a portion below the insulating film 22 and has a lower end that abuts against the upper end face of the conductor 23. The upper end of the capacitor electrode 25 is located below the upper end of the lower electrode 32. That is, between two adjacent lower electrodes 32, in addition to the conductor 21 covering the lower electrode 32, a portion not covered by the conductor is formed.

[0096] The capacitor electrode 24 may contain silicon (Si) and germanium (Ge), etc. Specifically, the capacitor electrode 24 may contain SiGe.

[0097] The insulating film 22 has a high dielectric constant. In this embodiment, the insulating film 22 may contain zirconium (Zr), aluminum, and oxygen. Specifically, the insulating film 22 may contain alternating Zr-O and Al-O films (ZAZ). Furthermore, the insulating film 22 is not limited to a ZAZ composition, but may also contain at least one of Hf-Zr-O (HZO), Zr-Nb-O (ZNO), and Hf-Al-O (HAO).

[0098] Conductor 21 is, for example, a barrier metal. Conductor 21 may contain titanium nitride, titanium, or tungsten. Conductor 23 and capacitor electrode 25 may contain tungsten and titanium nitride.

[0099] Conductor 33 includes wiring that electrically connects circuit 11 to semiconductor device 30. Conductor 33 may include via wiring, for example, having... Figure 2 As shown, a through-hole wiring extends in the Z-axis direction, connecting the conductive layer 42, which functions as a word line WL, to the circuit 11 disposed on the semiconductor substrate 10. The conductor 33 contains, for example, copper.

[0100] An insulating layer 34 is disposed between the plurality of capacitors 20. The insulating layer 34 is, for example, a silicon oxide film containing silicon and oxygen.

[0101] An insulating layer 35 is disposed above the insulating layer 34. The insulating layer 35 is, for example, a silicon nitride film containing silicon and nitrogen.

[0102] Here, the axis that intersects the Z-axis perpendicularly and, when viewed from above, intersects the X-axis at a counterclockwise angle of 30 degrees is defined as the A-axis. Sometimes, the plane parallel to both the Z-axis and the A-axis is called the ZA plane. Conversely, the axis that intersects the Z-axis perpendicularly and, when viewed from above, intersects the X-axis at a clockwise angle of 30 degrees is defined as the B-axis.

[0103] Figure 3 This is a detailed cross-sectional view of the semiconductor device 30 as viewed along a section 70ZA parallel to the ZA plane and contained within the oxide semiconductor layer 70. Figure 4 This is a detailed cross-sectional view of the semiconductor device 30 as viewed along a section 70YZ parallel to the YZ plane and contained within the oxide semiconductor layer 70. Figure 5 yes Figure 3 and Figure 4 The cross-sectional view shown at the cut line VV. Figure 6 yes Figure 3 and Figure 4 The sectional view shown at the cut line VI-VI.

[0104] like Figures 3-6 As shown, in this embodiment, the upper electrode 50 has a columnar shape extending from the upper end 70a of the oxide semiconductor layer 70 connected to it toward the Z-axis + direction. Specifically, the upper electrode 50 has a fixed cross-section and an axis that is substantially parallel to the Z-axis. The cross-section of the upper electrode 50 is an elongated circle with a major axis that is substantially parallel to the Y-axis.

[0105] Furthermore, the upper electrode 50 may also have a tapered shape that tapers upwards or downwards. Additionally, the cross-section of the upper electrode 50 is not limited to an oblong shape; it may also be circular.

[0106] The lower electrode 32 has a columnar shape extending from the lower end 70b of the oxide semiconductor layer 70 adjacent to it in the opposite direction to the Z-axis + direction. Specifically, the lower electrode 32 has a cylindrical shape including an axis that is substantially parallel to the Z-axis. The sides and bottom surface of the lower electrode 32 are covered by a conductor 21.

[0107] Furthermore, the lower electrode 32 is not limited to a cylindrical shape, but may also be a conical shape that tapers upwards or downwards. Additionally, the cross-section of the lower electrode 32 is not limited to a circle, but may also be oblong.

[0108] The gate insulating film 43 surrounds the sidewalls of the oxide semiconductor layer 70. In this embodiment, the gate insulating film 43 includes insulating films 43a and 43b.

[0109] In detail, the insulating film 43b comprises, for example, silicon and nitrogen. Specifically, the insulating film 43b comprises, for example, a silicon nitride film (Si3N4). The insulating film 43a comprises, for example, silicon and oxygen. Specifically, the insulating film 43a comprises a silicon oxide film (SiO2). The insulating film 43a is disposed between the insulating film 43b and the oxide semiconductor layer 70, and is formed in a manner that covers the entire circumference of the side surface of the oxide semiconductor layer 70.

[0110] Furthermore, the gate insulating film 43 is not limited to a configuration containing two insulating films, but may also be a configuration containing one or more insulating films. In addition, the gate insulating film 43 is not limited to a silicon nitride film or a silicon oxide film, but may also be a high-k insulating film with a large dielectric constant (e.g., an insulating film containing Hf-O, Al-O, Hf-Al-O, Zr-O, Hf-Zr-O, or Zr-Nb-O).

[0111] Here, columnar body 201 is defined. Columnar body 201 includes: an oxide semiconductor layer 70, a gate insulating film 43 surrounding the oxide semiconductor layer 70, and a lower electrode 32 and an upper electrode 50 connected to the oxide semiconductor layer 70. Columnar body 201 has a columnar shape that extends entirely along the vertical direction. Columnar bodies 201a and 201b are examples of columnar body 201.

[0112] Hereinafter, the group comprising the oxide semiconductor layer 70 and the upper electrode 50 contained in the columnar body 201 is sometimes referred to as group 211.

[0113] Multiple columnar elements 201 are arranged along a third direction, such as the A-axis+ direction or the B-axis+ direction, which intersects the Z-axis+ direction and the Y-axis+ direction. Specifically, when viewed from above, one of the multiple columnar elements 201 is surrounded by the six columnar elements 201 in the closest position.

[0114] More specifically, when viewed from above, the oxide semiconductor layer 70 contained in the single column 201 is located at the center of the regular hexagon, and the six oxide semiconductor layers 70 contained in each of the six column 201 are located at the vertices of the regular hexagon. That is to say, the column 201 is configured as a hexagonal densest structure.

[0115] Multiple oxide semiconductor layers 70 are arranged in a generally parallel manner at equal intervals along the Y-axis+ direction. Alternatively, multiple oxide semiconductor layers 70 may be arranged at the same equal intervals along the A-axis+ direction or the B-axis+ direction. Furthermore, the arrangement direction or spacing of the multiple oxide semiconductor layers 70 may be offset to the extent of manufacturing error.

[0116] The conductive layer 42 extends along a second direction intersecting the Z-axis + direction, such as the Y-axis + direction. Furthermore, between the upper end 70a and lower end 70b of each of the plurality of oxide semiconductor layers 70 disposed along the Y-axis direction, a gate insulating film 43 surrounds the oxide semiconductor layer 70.

[0117] In detail, the oxide semiconductor layer 70 and the gate insulating film 43 penetrate the conductive layer 42. The oxide semiconductor layer 70 and the gate insulating film 43 protrude above and below the conductive layer 42. That is, the conductive layer 42 separates the multiple oxide semiconductor layers 70 between their upper ends 70a and lower ends 70b along the Y-axis direction, with multiple gate insulating films 43 surrounding the multiple oxide semiconductor layers 70.

[0118] The conductive layer 42 functions as the gate electrode of the field-effect transistor 40. The conductive layer 42 contains, for example, tungsten (W). However, the conductive layer 42 is not limited to a composition containing tungsten, and may also contain molybdenum (Mo), titanium nitride (TiN), cobalt (Co), or ruthenium (Ru).

[0119] Multiple conductive layers 42 are provided. The multiple conductive layers 42 are repeatedly arranged in the X-axis direction. The multiple conductive layers 42 are separated from each other in the X-axis direction. Insulating layers 45 are provided above and below the conductive layers 42 and between two conductive layers 42. That is, two adjacent conductive layers 42 are separated by a portion of the insulating layer 45. The insulating layer 45, for example, contains silicon and oxygen. The conductive layers 42 correspond to word lines WL (see reference). Figure 1 ).

[0120] In this embodiment, the upper electrode 50 includes a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c.

[0121] The metal oxide layer 50a in the upper electrode 50 comprises a conductive oxide. Specifically, the metal oxide layer 50a is a metal oxide comprising indium and tin as metal elements. More specifically, the metal oxide layer 50a is formed of indium tin oxide (ITO). The metal oxide layer 50a is disposed above the oxide semiconductor layer 70. The metal oxide layer 50a has a thin film shape extending along a plane parallel to the XY plane.

[0122] Furthermore, the lower electrode 32 and the metal oxide layer 50a are not limited to ITO, but may also be composed of at least one element selected from indium, tin, zinc, cadmium (Cd), gold, silver, platinum, lead, copper, nickel (Ni), tungsten and iron.

[0123] Specifically, the lower electrode 32 and the metal oxide layer 50a may also be composed of at least one of In-Sn-ON (ITON), In-Ga-O (IGO), Al-Zn-O (AZO), Ga-Zn-O (GZO), Sn-O, Sn-Nb-O, Sn-Ta-O, Sn-OF (FTO), Ti-O, Ti-Nb-O (TNO), Ti-WO, Mo-O and WO.

[0124] The barrier metal layer 50b is deposited above the metal oxide layer 50a. In this embodiment, the barrier metal layer 50b has a thin film shape extending along a surface parallel to the XY plane.

[0125] The barrier metal layer 50b comprises titanium, oxygen, and nitrogen. Specifically, the barrier metal layer 50b has a laminated structure of titanium oxide (TiO) and titanium nitride (TiN).

[0126] Furthermore, the barrier metal layer 50b can also be formed of Ti-ON (TiON). Additionally, the barrier metal layer 50b can also be composed of titanium and one of oxygen and nitrogen. Furthermore, the barrier metal layer 50b can also be composed of metal elements other than titanium. Specifically, the barrier metal layer 50b can, for example, also contain tungsten.

[0127] A metal film 50c is deposited over a metal oxide layer 50a. In this embodiment, the metal film 50c has a thin film shape extending along a plane parallel to the XY plane. The metal film 50c contains, for example, tungsten.

[0128] In this embodiment, the insulating layer 45 has a thin film shape extending along a surface parallel to the XY plane. A conductive layer 42 is formed in the insulating layer 45. A columnar body 201 penetrates the insulating layer 45.

[0129] In detail, the insulating layer 45 includes insulating films 45a, 45b, and 45c (an example of the "second insulating film"). Insulating films 45a and 45b are respectively disposed above and below the conductive layer 42. Insulating films 45a and 45b extend together with the conductive layer 42 along the Y-axis + direction. Insulating films 45a and 45b, together with the conductive layer 42, surround the oxide semiconductor layer 70 and the gate insulating film 43.

[0130] The insulating film 45c includes an insulating portion 501 (an example of “Part 1”) and an insulating portion 502 (an example of “Part 2”).

[0131] The insulating portion 502 is located between two adjacent groups 211 in the A-axis+ direction or the B-axis+ direction. In this embodiment, the insulating portion 502 includes insulating portions 502a and 502b.

[0132] An insulating portion 502b is disposed above the insulating film 45a, surrounding the sides of the plurality of upper electrodes 50. In other words, the upper electrodes 50 penetrate the insulating portion 502a in the vertical direction. The surface above the metal film 50c of the plurality of upper electrodes 50 is exposed above the surface above the insulating portion 502b.

[0133] Insulating portion 502a and insulating portion 502b are continuous and are embedded between insulating films 45a and 45b that are adjacent to each other in the X-axis direction and conductive layer 42.

[0134] An insulating portion 501 is disposed below the insulating film 45b. The insulating portion 501 is continuous with the insulating portion 502. The insulating portion 501 is disposed in a layer 511 containing a plurality of lower electrodes 32. The layer 511 is disposed between the insulating film 45b and the insulating film 22.

[0135] Below the insulating film 45b, the lower electrode 32, which is covered by the conductor 21 on the side, and the insulating layer 35 penetrate the layer 511 in the vertical direction.

[0136] At least a portion of the void 401 is disposed between two adjacent lower electrodes 32. In this embodiment, the void 401 extends between two adjacent groups 211 in the A-axis+ direction or the B-axis+ direction. In other words, the void 401 is disposed spanning between two adjacent lower electrodes 32 and between two adjacent groups 211 in the A-axis+ direction or the B-axis+ direction.

[0137] At least a portion of the cavity 401 is surrounded by the insulating portion 501. Specifically, between two adjacent lower electrodes 32 in the Y-axis+ direction, the cavity 401 is a tunnel 401a with the insulating portion 501 as its inner wall.

[0138] The cavity portion 401 is provided extending from the insulating portion 501 and across the insulating portion 502. The cavity portion 401 surrounds the side of the lower electrode 32.

[0139] In detail, in layer 511, an insulating layer 35 is disposed between two adjacent lower electrodes 32 in the Y-axis+ direction. The sides of the insulating layer 35 are surrounded by insulating portions 501. The sides of the conductor 21 are also surrounded by insulating portions 501.

[0140] Between two adjacent lower electrodes 32 in the A-axis+ direction and between two adjacent lower electrodes 32 in the B-axis+ direction, there are portions where no insulating layer 35 is provided.

[0141] The tunnel 401a is arranged circumferentially with the axis of the lower electrode 32 (oxide semiconductor layer 70) as the center. The insulating portion 501 surrounding the insulating layer 35 and the insulating portion 501 surrounding the conductor 21 respectively become the inner wall of the outer side and the inner wall of the inner side of the tunnel 401a.

[0142] Between two adjacent groups 211 in the A-axis+ direction or the B-axis+ direction, a cavity portion 401 is provided below the insulating portion 502a. The cavity portion 401 in the insulating portion 502a is continuous with the cavity portion 401 in the insulating portion 501.

[0143] (Effect)

[0144] For example, when a dielectric material is filled between two adjacent lower electrodes 32, the parasitic capacitance between the two lower electrodes 32 increases. In particular, when an insulating film 22 with a large dielectric constant is provided between the two lower electrodes 32, or when the lower electrodes 32 are designed with a hexagonal close-packed structure and the distance between the two lower electrodes 32 is short, the parasitic capacitance increases significantly.

[0145] When the parasitic capacitance is large, the time required to charge the parasitic capacitance increases, and the operation of the semiconductor device 30 becomes slower, which is therefore not preferable.

[0146] As described above, by including at least a portion of the cavity portion 401 within the insulating portion 501, a cavity portion 401 with a low dielectric constant can be provided between the two lower electrodes 32, thereby reducing the parasitic capacitance between the two lower electrodes 32. This shortens the time required to charge the parasitic capacitance, thus enabling faster operation of the semiconductor device 30 and, consequently, the OCTRAM.

[0147] Furthermore, by configuring the cavity portion 401 to surround the side of the lower electrode 32, the lower electrode 32 can receive oxygen supply from all directions through the cavity portion 401.

[0148] [First Manufacturing Method of Semiconductor Device 30]

[0149] Hereinafter, as an example of a method for manufacturing a semiconductor device according to the first embodiment, a first method for manufacturing a semiconductor device 30 will be described. In the first manufacturing method, a conductive layer 42 is formed in a self-aligned manner around an oxide semiconductor layer 70 and a gate insulating film 43.

[0150] First, such as Figures 7-10 As shown, for example, there is an area layer insulating film 301 above the upper electrode 50. The insulating film 301 functions as a hard mask for the upper electrode 50, for example. With the columnar body 201 having a through insulating layer 45 and conductive layer 42 formed, a spacer film 50e is formed on the side of the upper electrode 50, the surface above the insulating film 301, and the surface above the insulating film 45a by atomic layer deposition.

[0151] Next, as Figures 11-14 As shown, the trench 45ca is formed by reactive ion etching, followed by cleaning. The trench 45ca extends approximately parallel to the XY plane, separating the conductive layer 42 and the insulating layer 45. Near the bottom of the trench 45ca, the insulating layer 35 and the insulating film 22 are exposed. The sidewalls of the trench 45ca are formed with irregularities along the outer contour of the spacer film 50e when viewed from above.

[0152] Next, as Figure 15 and Figure 16 As shown, the spacer membrane 50e was removed by reactive ion etching, followed by washing.

[0153] Next, as Figure 17 and Figure 18 As shown, a portion of the insulating film 22 is removed, for example, by wet etching. As a result, the conductor 21 is exposed in the cavity portion 401 within layer 511. The cavity portion 401 surrounds the conductor 21.

[0154] Next, as Figure 19 and Figure 20 As shown, an insulating film 45c is formed, for example, by atomic deposition. At this time, a cavity portion 401 is formed, corresponding to the ease of embedding the insulating film 45c. The ease of embedding the insulating film 45c can be adjusted, for example, according to the process conditions during the formation of the insulating film 45c. For example, if the ease of embedding the insulating film 45c is increased, the volume of the cavity portion 401 can be reduced. Conversely, if the ease of embedding the insulating film 45c is decreased, the volume of the cavity portion 401 can be increased.

[0155] Next, as Figures 21-23As shown, a portion of the insulating film 301 and the insulating film 45c are removed by chemical mechanical polishing, thereby exposing the surface above the metal film 50c in the upper electrode 50 from the insulating film 45c, and aligning the vertical positions of the surfaces above the insulating film 45c and the metal film 50c. A conductive layer 51 extending along the X-axis + direction and in contact with the metal film 50c is formed on this smoothed surface.

[0156] [Second Manufacturing Method for Semiconductor Device 30B]

[0157] Hereinafter, as another example of the semiconductor device manufacturing method of the first embodiment, a second manufacturing method for the semiconductor device 30B will be described. The second manufacturing method differs from the first manufacturing method in that the sidewall of the groove portion 45ca is formed to be smooth.

[0158] First, such as Figures 24-27 As shown, the insulating layer 45 in semiconductor device 30B, compared to the insulating layer 45 in semiconductor device 30, includes an insulating film 45c instead of insulating films 45a and 45b. For example, a columnar body 201 is embedded in the insulating film 45d. Multiple conductive layers 42 are repeatedly disposed in the X-axis+ direction. Each conductive layer 42 extends in the Y-axis+ direction. The cross-section of the upper electrode 50 is approximately circular.

[0159] Next, as Figures 28-30 As shown, multiple mask layers 81 are formed by photolithography on the surface above the insulating film 45d, followed by resist coating, exposure, development, and stripping. The multiple mask layers 81 are repeatedly arranged in the X-axis+ direction. Each mask layer 81 extends in the Y-axis+ direction. When viewed from above, the mask layers 81 overlap with the metal film 50c.

[0160] Next, as Figures 31-33 As shown, the trench 45ca is formed by reactive ion etching, followed by cleaning. The trench 45ca extends approximately parallel to the XY plane, dividing the insulating film 45d. Near the bottom of the trench 45ca, the insulating layer 35 and the insulating film 22 are exposed. The sidewalls of the trench 45ca are formed smoothly along the outer contour of the mask layer 81 when viewed from above. Furthermore, the cross-section 70YZ in the semiconductor device 30B is consistent with... Figure 29 The cross section 70YZ in the semiconductor device 30 shown is the same.

[0161] Next, as Figures 34-37 As shown, for example, a portion of the insulating film 22 is removed by wet etching. Thus, in layer 511, the conductor 21 is exposed in the cavity portion 401. The cavity portion 401 surrounds the conductor 21.

[0162] Next, as Figures 38-41 As shown, for example, an insulating film 45c is formed by atomic deposition. The ease of embedding the insulating film 45c at this time is similar to... Figure 21 The ease of embedding the insulating film 45c is the same in the cases shown.

[0163] Next, as Figures 42-44 As shown, a portion of the insulating films 45c and 45d is removed by chemical mechanical polishing, thereby exposing the surfaces above the insulating films 45c and 45d and the metal film 50c, with these surfaces aligned vertically. A conductive layer 51 extending along the X-axis + direction and in contact with the metal film 50c is formed on these smoothed surfaces.

[0164] [Second Implementation]

[0165] The semiconductor device 30C according to the second embodiment will be described. Following the second embodiment, descriptions of matters common to the first embodiment are omitted; only the differences will be described. In particular, the same effects resulting from the same configuration will not be mentioned individually in each embodiment.

[0166] Figure 45 This is a detailed cross-sectional view of the semiconductor device 30C as viewed along a section 70ZA that is parallel to the ZA plane and contained within the oxide semiconductor layer 70. Figure 46 yes Figure 45 The sectional view shown is taken at the cut line XLVI-XLVI.

[0167] Furthermore, the cross section 70YZ in the semiconductor device 30C and Figure 4 The cross section 70YZ in the semiconductor device 30 shown is the same. Figure 46 The cross-section of the semiconductor device 30C at the cut line VV shown is... Figure 5 The cross-section of the semiconductor device 30 at the cut line VV shown is the same.

[0168] like Figure 4 , Figure 5 , Figure 45 and Figure 46 As shown, the semiconductor device 30C of the second embodiment differs from the semiconductor device 30 of the first embodiment in that the cavity portion 401 is disposed between two adjacent groups 211 in the A-axis+ direction or the B-axis+ direction.

[0169] The cavity portion 401 in the semiconductor device 30C is manufactured, for example, by ratio manufacturing. Figure 4 and Figure 5 The semiconductor device 30 shown is formed by reducing the ease of embedding the insulating film 45c.

[0170] In the semiconductor device 30C, a cavity 401 that allows gases such as oxygen to flow at high energy rates is disposed from near the lower electrode 32 to near the metal oxide layer 50a.

[0171] With this configuration, for example, when heating the semiconductor device 30C in an oxygen atmosphere, oxygen can be effectively supplied to the metal oxide layer 50a and the lower electrode 32 through the cavity portion 401. This reduces the time required to supply oxygen to the metal oxide layer 50a and the lower electrode 32.

[0172] Furthermore, since the oxygen supply to the metal oxide layer 50a and the lower electrode 32 can be kept consistent, the carrier concentrations in the metal oxide layer 50a and the lower electrode 32 can be made to the same level, thereby making the electrical characteristics of the metal oxide layer 50a and the lower electrode 32 to the same level. Therefore, the current can flow approximately symmetrically when current flows from the lower electrode 32 to the metal oxide layer 50a and when current flows from the metal oxide layer 50a to the lower electrode 32.

[0173] [Third Implementation]

[0174] The semiconductor device 30D of the third embodiment will be described. Figure 47 This is a detailed cross-sectional view of the semiconductor device 30D as viewed along a section 70ZA that is parallel to the ZA plane and contained within the oxide semiconductor layer 70. Figure 48 This is a detailed cross-sectional view of the semiconductor device 30D as viewed along a section 70YZ parallel to the YZ plane and contained within the oxide semiconductor layer 70. Figure 49 yes Figure 47 and Figure 48 The cross-sectional view shown at the cut line XLIX-XLIX.

[0175] also, Figure 47 and Figure 48 The cross-section of the semiconductor device 30D at the cut line VV shown is... Figure 5 The cross-section of the semiconductor device 30 at the cut line VV shown is the same.

[0176] like Figure 5 and Figures 47-49 As shown, the semiconductor device 30D of the third embodiment differs from the semiconductor device 30C of the second embodiment in that the cavity portion 401 surrounds the side of the upper electrode 50.

[0177] Semiconductor device 30D is manufactured, for example, by the first manufacturing method. In detail, such as... Figure 19 and Figure 20As shown, when the insulating film 45c is formed by atomic deposition, the ease of embedding the insulating film 45c is reduced, and the film thickness of the insulating film 45c is made thinner.

[0178] Under these process conditions, a cavity 401 without an insulating film 45c is formed between two adjacent upper electrodes 50 in the Y-axis+ direction. This cavity 401 is continuous with the cavity 401 between two adjacent upper electrodes 50 in the A-axis+ or B-axis+ direction. In other words, the cavity 401 surrounds the side of the upper electrode 50.

[0179] With this configuration, the metal oxide layer 50a can receive oxygen from all directions through the cavity 401.

[0180] [Fourth Implementation]

[0181] The semiconductor device 30E of the fourth embodiment will be described. Figure 50 This is a detailed cross-sectional view of the semiconductor device 30E as viewed along a section 70ZA parallel to the ZA plane and contained within the oxide semiconductor layer 70. Figure 51 This is a detailed cross-sectional view of the semiconductor device 30E as viewed along a section 70YZ parallel to the YZ plane and contained within the oxide semiconductor layer 70. Figure 52 yes Figure 50 and Figure 51 The cross-sectional view shown at the cut line LII-LII.

[0182] also, Figure 50 and Figure 51 The cross-section of semiconductor device 30E at the cut line XLIX-XLIX shown is... Figure 49 The cross-section of semiconductor device 30D at the cut line XLIX-XLIX shown is the same.

[0183] like Figures 49-52 As shown, the semiconductor device 30E of the fourth embodiment differs from the semiconductor device 30D of the third embodiment in that the insulating portion 501 is connected to the side of the lower electrode 32.

[0184] In the semiconductor device 30D, the upper end of the conductor 21 is located below the upper end of the lower electrode 32. Furthermore, the upper ends of the conductor 21, the upper ends of the insulating film 22, and the upper ends of the insulating layer 35 are aligned vertically.

[0185] A portion of the upper side of the lower electrode 32 is not covered by the conductor 21. This portion is in contact with the insulating portion 501.

[0186] Semiconductor device 30E, for example, in Figure 17 and Figure 18 or Figure 34 and Figure 35 The wet etching shown is formed by further removing a portion above the conductor 21 and a portion above the insulating layer 35.

[0187] [Fifth Implementation]

[0188] The semiconductor device 30F of the fifth embodiment will be described. Figure 53 This is a detailed cross-sectional view of the semiconductor device 30F as viewed along a section 70ZA that is parallel to the ZA plane and contained within the oxide semiconductor layer 70. Figure 54 yes Figure 53 The cross-sectional view shown at the cut line LV-LV.

[0189] Furthermore, the cross section 70YZ in the semiconductor device 30F and Figure 4 The cross section 70YZ in the semiconductor device 30 shown is the same. Figure 53 The cross-section of semiconductor device 30F at cut line VI-VI shown is... Figure 6 The cross-section of the semiconductor device 30 at the cut line VI-VI shown is the same.

[0190] like Figure 4 , Figure 6 , Figure 53 and Figure 54 As shown, the semiconductor device 30F of the fifth embodiment differs from the semiconductor device 30 of the first embodiment in that the cavity portion 401 is entirely surrounded by the insulating portion 501.

[0191] Semiconductor device 30F, for example, in Figure 19 and Figure 20 or Figure 38 and Figure 39 The insulating film 45c shown is formed by increasing the ease of embedding the insulating film 45c.

[0192] [Sixth Implementation]

[0193] The semiconductor device 30G of the sixth embodiment will be described. Figure 55 This is a detailed cross-sectional view of the semiconductor device 30G as viewed along a section 70ZA parallel to the ZA plane and contained within the oxide semiconductor layer 70.

[0194] like Figure 55 As shown, the semiconductor device 30G of the sixth embodiment differs from the semiconductor device 30E of the fourth embodiment in that the cavity portion 401 is connected to the side of the lower electrode 32.

[0195] Semiconductor device 30G, for example, in Figure 19 and Figure 20 or Figure 38and Figure 39 In the formation of the insulating film 45c shown by atomic deposition, the ease of embedding the insulating film 45c is reduced. Furthermore, the semiconductor device 30G can also be formed by sputtering, thus replacing atomic deposition.

[0196] In the semiconductor device 30G, the insulating film 45c is formed by sealing the space between the two pillars 201. Specifically, in layer 511, a cavity 401 is formed between the two lower electrodes 32. A cavity 401 is formed between the two insulating films 45b, the two conductive layers 42, and the two insulating films 45a. A cavity 401 is formed below the space between the two upper electrodes 50.

[0197] Furthermore, while each embodiment describes an example where the A-axis + direction is the third direction, it is not limited to this. An example where the B-axis + direction is the third direction could also be used.

[0198] (a) A semiconductor device comprising:

[0199] A plurality of oxide semiconductors having a first end and a second end, extending in a first direction from the second end toward the first end;

[0200] A plurality of first electrodes are respectively connected to the first terminals of a plurality of oxide semiconductors;

[0201] A plurality of second electrodes are respectively connected to the second terminals of a plurality of oxide semiconductors;

[0202] Multiple gate electrodes extend along a second direction orthogonal to the first direction and are repeatedly arranged in a fourth direction orthogonal to both the first and second directions;

[0203] A plurality of first insulating films respectively surround the sides of a plurality of the oxide semiconductors; and

[0204] The cavity portion is at least partially disposed between two adjacent second electrodes;

[0205] The plurality of the oxide semiconductors are repeatedly arranged along the second direction and also repeatedly arranged along a third direction that intersects the first and second directions.

[0206] The gate electrode is provided with a plurality of first insulating films separating the plurality of oxide semiconductors between the first end and the second end of each of the plurality of oxide semiconductors disposed along the second direction.

[0207] (b) The oxide semiconductor and the first electrode, which are connected to each other, are arranged along a third direction that intersects the first direction and the second direction.

[0208] The cavity extends between two adjacent groups in the third direction.

[0209] (c) The oxide semiconductor and the first electrode, which are connected to each other, are arranged along a third direction that intersects the first direction and the second direction.

[0210] The cavity portion is disposed between two adjacent second electrodes and between two adjacent groups in the third direction.

[0211] The embodiments described above have been illustrated with reference to specific examples. However, the present invention is not limited to these specific examples. Any design modifications made by those skilled in the art to these specific examples that possess the features of the present invention are also included within the scope of the present invention. The elements, configurations, conditions, shapes, etc., of each specific example are not limited to those illustrated and can be appropriately modified. The elements of each specific example can be appropriately combined as long as there is no technical contradiction.

[0212] [Explanation of Symbols]

[0213] 10: Semiconductor substrate

[0214] 11: Circuit

[0215] 20: Capacitor

[0216] 21,23: Conductors

[0217] 22: Insulating film

[0218] 24, 25: Capacitor electrodes

[0219] 30, 30B, 30C, 30D, 30E, 30F, 30G: Semiconductor devices

[0220] 32: Lower electrode

[0221] 33: Conductor

[0222] 34, 35: Insulation layer

[0223] 40: Field-Effect Transistor

[0224] 42: Conductive layer

[0225] 43: Gate insulating film

[0226] 43a, 43b: Insulating film

[0227] 45: Insulation layer

[0228] 45a, 45b, 45c, 45d: Insulating film

[0229] 45ca: Groove

[0230] 50: Upper electrode

[0231] 50a: Metal oxide layer

[0232] 50b: Barrier metal layer

[0233] 50c: Metallic film

[0234] 50e: septum membrane

[0235] 51: Conductive layer

[0236] 70: Oxide semiconductor layer

[0237] 70a: Upper end

[0238] 70b: Lower end

[0239] 81: Mask layer

[0240] 101: Semiconductor memory devices

[0241] 201, 201a, 201b: columnar body

[0242] 211: Group

[0243] 301: Insulating film

[0244] 401: Cavity

[0245] 401a: Tunnel

[0246] 501, 502, 502a, 502b: Insulation parts

[0247] 511: Layer.

Claims

1. A semiconductor device comprising: A plurality of oxide semiconductors having a first end and a second end, extending in a first direction from the second end toward the first end; A plurality of first electrodes are respectively connected to the first terminals of a plurality of oxide semiconductors; A plurality of second electrodes are respectively connected to the second terminals of a plurality of oxide semiconductors; A gate electrode extends along a second direction intersecting the first direction, and a first insulating film surrounds the oxide semiconductors between the first and second ends of each of the plurality of oxide semiconductors disposed along the second direction; and The cavity portion is at least partially disposed between two adjacent second electrodes.

2. The semiconductor device according to claim 1, wherein The oxide semiconductor and the first electrode, which are connected to each other, are arranged along a third direction that intersects the first direction and the second direction. The cavity extends between two adjacent groups in the third direction.

3. The semiconductor device according to claim 1, wherein The semiconductor device It also includes a second insulating film, which comprises a first portion disposed in a layer containing a plurality of the second electrodes. At least a portion of the cavity is surrounded by the first part.

4. The semiconductor device according to claim 3, wherein Between two adjacent second electrodes in the second direction, the cavity is a tunnel with the first part as its inner wall.

5. The semiconductor device according to claim 3, wherein The oxide semiconductor and the first electrode, which are connected to each other, are arranged along a third direction that intersects the first direction and the second direction. The second insulating film It also includes a second part, which is located between two adjacent groups in the third direction and is continuous with the first part. The cavity portion is arranged such that it extends from the first portion to the second portion.

6. The semiconductor device according to claim 5, wherein The cavity portion is disposed between two adjacent groups in the third direction.

7. The semiconductor device according to claim 2 or 6, wherein The first electrode has a columnar shape extending from the first end in the first direction. The cavity surrounds the side of the first electrode.

8. The semiconductor device according to claim 1 or 3, wherein The second electrode has a columnar shape extending in the opposite direction from the second end to the first direction. The cavity surrounds the side of the second electrode.

9. The semiconductor device according to claim 1, wherein The second electrode has a columnar shape extending in the opposite direction from the second end to the first direction. The cavity portion is connected to the side of the second electrode.

10. The semiconductor device according to claim 3, wherein The second electrode has a columnar shape extending in the opposite direction from the second end to the first direction. The first part is connected to the side of the second electrode.

11. The semiconductor device of claim 1, wherein The oxide semiconductor comprises at least one of indium, gallium, aluminum, zinc, tin, titanium, tungsten, and molybdenum, as well as oxygen.

12. A semiconductor memory device comprising: The semiconductor device according to claim 1; The first capacitor electrode is connected to the second electrode; The second capacitor electrode faces the first capacitor electrode; and A dielectric film is disposed between the first capacitor electrode and the second capacitor electrode.

13. The semiconductor memory device according to claim 12, wherein The first capacitor electrode is disposed below the second electrode. The upper end of the second capacitor electrode is located below the upper end of the second electrode.

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