TVS diode with asymmetric breakdown voltage and method of forming the same

Abstract

This invention discloses a TVS diode with asymmetric breakdown voltage and a method for forming the same. In one embodiment, the asymmetric transient voltage suppression (TVS) device may include a semiconductor substrate having an internal region having a first polarity and a first surface region disposed on a first surface of the semiconductor substrate and having a second polarity opposite to the first polarity. The device may further include: a second surface region having a second polarity and disposed on a second surface of the semiconductor substrate opposite to the first surface, wherein the first surface region has a first doping concentration and the second surface region has a second doping concentration less than the first doping concentration; and a first channel region disposed adjacent to the outer edge of the first surface region, the first channel region having the second polarity, wherein the first channel region extends below the first surface to a channel depth greater than a first depth of the first surface region.

Description

Technical Field

[0001] The embodiments relate to the field of surge protection devices, and more particularly to transient voltage suppression devices. Background Technology

[0002] Transient voltage suppression (TVS) devices operate to limit the voltage across a circuit, system, or component to be protected. Specifically, a TVS device comprises one or more diodes that clamp the voltage across the device or circuit at the maximum voltage set by the design of the individual diodes in the TVS diode configuration. Voltage clamping can occur when the diode is subjected to a voltage exceeding its breakdown voltage, at which point a large current is generated across the diode, limiting any further voltage increase. Asymmetric TVS devices can be constructed by providing two different diodes within a semiconductor die, where the different diodes are designed to clamp at different voltages. Therefore, asymmetric TVS diodes provide bidirectional protection, where the component to be protected can operate at either positive or negative voltage within the design voltage range, while simultaneously being protected against overvoltage in both positive and negative directions.

[0003] Asymmetric TVS devices can therefore be characterized by: a high-voltage side, wherein breakdown occurs at a relatively high voltage; and a low-voltage side, characterized by a relatively low breakdown voltage. In the prior art, the reliability of such asymmetric TVS devices may still warrant further improvement. As an example, the low-voltage side of an asymmetric TVS can be formed with a relatively high doping level and a relatively shallow P / N junction. In such structures, the device may be relatively more susceptible to edge termination defects.

[0004] This disclosure provides for these and other considerations. Summary of the Invention

[0005] In one embodiment, an asymmetric transient voltage suppression (TVS) device is provided. The asymmetric TVS device may include a semiconductor substrate including an internal region having a first polarity. The asymmetric TVS device may include a first surface region disposed on a first surface of the semiconductor substrate, the first surface region including a second polarity opposite to the first polarity. The asymmetric TVS device may further include a second surface region including a second polarity and disposed on a second surface of the semiconductor substrate opposite to the first surface, wherein the first surface region includes a first doping concentration, and wherein the second surface region includes a second doping concentration less than the first doping concentration. The asymmetric TVS device may include a first channel region disposed adjacent to the outer edge of the first surface region, the first channel region including a second polarity, wherein the first channel region extends below the first surface to a channel depth greater than a first depth of the first surface region.

[0006] In another embodiment, a method for forming an asymmetric TVS device is provided. The method may include: providing a semiconductor substrate including an internal region having a first polarity; and forming a first surface region on a first surface of the semiconductor substrate, the first surface region including a second polarity opposite to the first polarity. The method may further include forming a second surface region including a second polarity on a second surface of the semiconductor substrate opposite to the first surface, wherein the first surface region includes a first doping concentration, and wherein the second surface region includes a second doping concentration greater than the first doping concentration. The method may further include forming a first channel region adjacent to the outer edge of the first surface region, the first channel region including the second polarity, wherein the first channel region extends below the first surface to a channel depth greater than a first depth of the first surface region.

[0007] In another embodiment, an asymmetric transient voltage suppression (TVS) device is provided. The asymmetric TVS device may include: a semiconductor substrate including an inner region having P-type polarity; and a first surface region disposed on a first surface of the semiconductor substrate, the first surface region having N-type polarity. The asymmetric TVS device may further include a second surface region having N-type polarity and disposed on a second surface of the semiconductor substrate opposite to the first surface, wherein the first surface region has a first doping concentration, and wherein the second surface region has a second doping concentration less than the first doping concentration. The asymmetric TVS device may further include a highly doped layer disposed between a first surface layer and an inner layer, the highly doped layer having P-type polarity and a first doping concentration greater than the second doping concentration of the inner layer. The asymmetric TVS device may further include a first channel region disposed adjacent to the outer edge of the first surface region, the first channel region having N-type polarity, wherein the first channel region extends below the first surface to a channel depth greater than a first depth of the first surface region. Attached Figure Description

[0008] Figure 1 An asymmetric TVS device according to an embodiment of the present disclosure is described;

[0009] Figure 2 Another asymmetric TVS device according to other embodiments of this disclosure is depicted;

[0010] Figure 3 Further asymmetric TVS devices according to further embodiments of the present disclosure are depicted;

[0011] Figure 4 An additional asymmetric TVS device according to an embodiment of the present disclosure is described;

[0012] Figure 5A A side sectional view of yet another TVS device according to an embodiment of the present disclosure is depicted;

[0013] Figure 5B Depicting Figure 5A Top view of the TVS device;

[0014] Figure 6A A side sectional view of yet another TVS device according to an embodiment of the present disclosure is depicted;

[0015] Figure 6B Depicting Figure 6A Top view of the TVS device;

[0016] Figure 7 A top plan view of a channel structure according to some embodiments is depicted;

[0017] Figure 8 A top plan view of a channel structure according to other embodiments is depicted;

[0018] Figure 9 A top plan view of the channel structure according to an additional embodiment is depicted;

[0019] Figure 10 An exemplary process flow is described; and

[0020] Figure 11 Another exemplary process flow is described. Detailed Implementation

[0021] This embodiment provides an architecture and techniques for synthesizing asymmetric TVS devices with improved performance.

[0022] Figure 1 An asymmetric TVS device 100 according to an embodiment of the present disclosure is depicted. The asymmetric TVS device 100 is designed as a bidirectional asymmetric TVS device, wherein the low-voltage side ( Figure 1 The upper surface (lower surface) is designed to clamp at a relatively low voltage, while the high-voltage side (lower surface) is designed to clamp at a relatively high voltage. The asymmetric TVS device 100 includes a substrate 102, which will have a first polarity, and in various embodiments may be formed of a doped single-crystal semiconductor, such as silicon. For illustrative purposes, the first polarity can be considered to correspond to a P-type substrate, wherein a P / N junction is formed on the low-voltage side and the high-voltage side by providing an N-type surface layer. It is understood that additional embodiments may cover TVS devices in which the substrate has an N-type first polarity and the surface layer is P-type.

[0023] After the TVS device 100 is formed, as follows Figure 1 As shown, the semiconductor substrate has an internal region 103, which is further defined by including a first surface region 104 disposed on a first surface of the substrate 102. Figure 1 The upper surface of the surface (in the middle), the first surface region 104 includes a second polarity opposite to the first polarity. According to Figure 1 According to convention, the second polarity will be N-type.

[0024] The asymmetric TVS device 100 is further characterized by a second surface region 106, which includes a second polarity and is disposed on a second surface of the substrate 102 opposite to the first surface. Figure 1(The lower surface of the surface). According to various embodiments, the first surface region 104 is characterized by a first doping concentration, while the second surface region 106 is characterized by a second doping concentration less than the first doping concentration. Thus, in some embodiments, the first surface region 104 may be designated as an N+ base region, while the second surface region 106 is designated as an N base region.

[0025] The asymmetric TVS device 100 is further characterized by a first channel region 108 disposed adjacent to the outer edge of the first surface region 104. This first channel region 108 is further characterized by having a second polarity, such as N-type. As shown, the first channel region 108 is located on the first surface (…). Figure 1 The upper surface of the channel extends below the channel to a depth d. c The depth of the trench is d c The first depth d1 is greater than that of the first surface region 104. The provision of the first channel region 108 can improve the reliability of the TVS device 100 and, in particular, suppress edge termination defects.

[0026] Note that the breakdown voltage of the first channel region 108 is higher than that of the N+ region due to light doping. Therefore, when the device operates in this direction, the main leakage current flows in the N+ region, rather than in the edge channel region. In this case, the device properties are relatively less sensitive to edge termination defects.

[0027] It can be understood that the first channel region 108 can surround the first surface region 104 in the main plane of the substrate 102, as described below. Figures 5A to 9 As detailed above.

[0028] Note that while the first channel region 108 may be deeper than the first surface region 104 in the various embodiments depicted herein, in some embodiments the first channel region 108 does not need to be deeper than the first surface region 104, as long as the first channel region overlaps with the first surface region 104 and is lightly doped, thereby exhibiting a higher breakdown voltage compared to the first surface region. It can be understood that a workaround for generating less heavily doped regions is to drive the dopant into the substrate to a deeper depth, thus resulting in a relatively deeper depth of the channel region 108.

[0029] Figure 2Another asymmetric TVS device according to an embodiment of the present disclosure is depicted, shown as TVS device 200. TVS device 200 can be designed similarly to TVS device 100, wherein the same regions are labeled as identical. The difference between TVS device 200 and TVS device 100 is that a highly doped layer 112 is provided adjacent to the first surface region 104. The highly doped layer 112 will have the same polarity as the substrate 102, such as a P+ layer, and is used to adjust the properties of the P / N diode formed utilizing the first surface region 104. Figure 1 Similar to the previous embodiment, the first surface region 104 is relatively shallow, and the provision of the first channel region 108 will help improve resistance to edge termination defects.

[0030] Figure 3 Another asymmetric TVS device according to an embodiment of the present disclosure is depicted, shown as TVS device 300. TVS device 300 can be designed similarly to TVS device 100, wherein the same regions are labeled as the same. TVS device 300 differs from TVS device 100 in that it provides a second channel region 110 disposed adjacent to the outer edge of the second surface region 106. The second channel region 110 is characterized by having a second polarity, which is N-type in the illustrated example. Again, the second channel region 110 extends below the second surface (meaning from the lower surface into the substrate 102 in the figure) to a second channel depth d. c2 The second channel depth d c2 The second depth d2 is greater than that of the second surface region 106. Therefore, the TVS device 300 provides protection against edge termination defects on both the high-voltage side (lower surface) and the low-voltage side of the TVS device 300.

[0031] Figure 4 Another asymmetric TVS device according to an embodiment of the present disclosure is depicted, shown as TVS device 400. TVS device 400 can be designed similarly to TVS device 300, wherein the same regions are labeled as identical. The difference between TVS device 400 and TVS device 300 is that a highly doped layer 112 is provided adjacent to the first surface region 104. The highly doped layer 112 will have the same polarity as the substrate 102, such as a P+ layer, and is used to adjust the properties of the P / N diode formed using the first surface region 104, as discussed above. Figure 2 Similar to the previous embodiment, the first surface region 104 is relatively shallow, and the provision of the first channel region 108 helps to improve resistance to edge termination defects, while the second channel region 110 provides additional resistance to edge termination defects.

[0032] For illustrative purposes, and with particular reference Figure 2 or Figure 4 Table I presents some exemplary features of a TVS device arranged according to this embodiment, including some non-limiting values ​​for such features.

[0033] feature Typical range <![CDATA[Original silicon concentration (carriers / cm 3 )]]> <![CDATA[1E14~5E19 / cm 3 ]]> Original silicon thickness (µm) 200～400 <![CDATA[N-channel concentration (carriers / cm 3 )]]> <![CDATA[1E19 1.5E21 / cm 3 cm 2 ]]> N-channel depth (µm) 10～100 <![CDATA[Backside N-type base region concentration (carriers / cm 3 )]]> <![CDATA[1E19~1.5E21 / cm 3 ]]> Backside N-base region thickness (µm) 5～80 <![CDATA[Top P+ concentration (carriers / cm 3 )]]> 1E15~3E20 Top P + thickness (um) 5～50 <![CDATA[Concentration of the top N+ base region (carriers / cm 3 )]]> 1E19~1.5E21 Depth of the top N+ base region (um) 2～40

[0034] Table I

[0035] As shown in Table I, the carrier concentration in the substrate (such as in the internal region 103) can range from 1E14 to 5E19 / cm². 3 The wafer thickness for TVS devices can be approximately 200 μm to 400 μm. When the N-type channel is formed on the low-voltage side (and optionally on the high-voltage side), the channel concentration can be 1E19 to 1.5E21 / cm². 3 Within a certain range. In different non-limiting embodiments, the channel depth of the first channel can be in the range of 10 μm to 100 μm.

[0036] The concentration of the second surface layer (the base layer of the high-voltage diode) can be approximately 1E19 to 1.5E21 / cm³. 3 The N-type dopant. In various non-limiting embodiments, the thickness of the second surface layer can range from 5 μm to 80 μm. Highly doped layers (e.g., P-type doped layers in low-voltage diodes) + The concentration of the layer can be approximately 1E15 to 3E20 / cm³. 3 The N-type dopant is used. In various non-limiting embodiments, the thickness of the highly doped layer can range from 5 μm to 50 μm. The concentration of the first surface layer (e.g., the N-layer of a low-voltage diode) can be approximately 1E19 to 1.5E21 / cm². 3 N-type dopant.

[0037] The properties of the P / N diodes formed in the asymmetric TVS device can be adjusted accordingly by adjusting the doping concentration and thickness in each region, as outlined in Table I. Table II provides examples of device properties for four exemplary TVS devices arranged according to embodiments of the present disclosure. The first device, labeled PN1, exhibits a high-voltage-side cutoff voltage of 15V, a minimum breakdown voltage of 16.7V, and a maximum breakdown voltage of 18.5V. The low-voltage-side cutoff voltage is 5V, the minimum breakdown voltage is 6.82V, and the maximum breakdown voltage is 7.48V.

[0038] The second device, labeled PN2, exhibits a high-voltage side cutoff voltage of 19V, a minimum breakdown voltage of 21.1V, and a maximum breakdown voltage of 23.3V.

[0039] The third device, designated PN3, exhibits a high-voltage side cutoff voltage of 24V, a minimum breakdown voltage of 26.6V, and a maximum breakdown voltage of 29.4V.

[0040] The fourth device, designated PN4, exhibits a high-voltage side cutoff voltage of 36V, a minimum breakdown voltage of 40V, and a maximum breakdown voltage of 44.2V.

[0041] Note that in the experimental results, for asymmetric TVS wafers fabricated without using the channel structure of this embodiment, a low probe yield was observed on the low voltage side due to poor edge termination, while the yield was improved after adding the channel structure.

[0042]

[0043] Table II

[0044] Figure 5A A side sectional view of yet another TVS device according to an embodiment of the present disclosure is depicted. Figure 5B Depicting Figure 5A A top view of the TVS device. TVS device 500 can be designed similarly to TVS device 200, with identical areas labeled as the same. The difference between TVS device 500 and TVS device 200 is that recessed regions 116 are provided on both the upper and lower surfaces of the substrate 102. Recessed regions 116 may include etched substrate recesses and passivation covering the etched substrate recesses, giving TVS device 500 a mesa structure. Figure 5B As shown, the channel region 108B can form a rectangular boundary around the first surface region 104 (the N+ base region in this figure).

[0045] In various non-limiting embodiments, the first surface region 104 may have a rectangular shape, a hexagonal shape, an elliptical shape, or an oval shape.

[0046] like Figure 5A As further shown, the channel region 108B can be configured to be adjacent to the heavily doped layer 112 and adjacent to the first surface region 104. For example... Figure 5A As further shown, the recessed region 116 can extend from the first surface of the substrate 102 to a depth greater than the depth of the channel region 108B. Note that, according to various embodiments, the channel region 108B is formed before mesa etching is performed. Figure 5AIn certain chip structures, the N+ base region photolithography and etching processes, in which the N+ base region (first surface region 104) is globally formed, can be skipped, while still retaining the channel structure (channel region 108B) and the advantages provided by the channel structure. The mesa etched region (recessed region 116) provides edge termination to protect the PN junction after the substrate is diced to form a single chip. Note that it is necessary to form the recessed region 116 to a depth greater than the channel region 108B and also deeper than the first surface region 104. Only in this case will the channel-sub-NP junction edge be passivated after being diced into a chip. The same applies to the passivation of the back side (meaning the second surface region 106).

[0047] Figure 6A A side sectional view of yet another TVS device according to an embodiment of the present disclosure is depicted. Figure 6B Depicting Figure 6A A top view of the TVS device 600. The TVS device 600 can be designed similarly to the TVS device 200, where identical areas are labeled identically. The TVS device 600 can be considered a variant of the TVS device 200, wherein the first channel region 108C has a square racetrack shape, such as... Figure 6B As shown. The TVS device 600 also includes a passivation layer 118 above the outer edges of the first surface region 104 and the second surface region 106.

[0048] Figure 7 A top plan view of a channel structure 108D according to some embodiments is depicted. In this example, the channel structure 108D defines a square shape suitable for serving as the boundary region of a square semiconductor chip.

[0049] Figure 8 A top plan view of a channel structure 108E according to another embodiment is depicted. In this example, the channel structure 108E defines an elongated rectangular shape suitable for use in a rectangular semiconductor chip.

[0050] Figure 9 A top plan view of a channel structure according to another embodiment is depicted. In this example, the channel structure 108F has a hexagonal shape. Note that in some packages, hexagonal chips are more suitable for multi-chip stacking assemblies. The channel structure 108F with a hexagonal shape would then be suitable for such hexagonal chips.

[0051] Figure 10 An exemplary process flow 1000 according to some embodiments of the present disclosure is depicted. At block 1002, a substrate is provided. In one example, the substrate is a P-type silicon semiconductor wafer.

[0052] At frame 1004, a photolithography process is provided to define a first channel region on a first surface of a substrate. This surface can be considered as the low-voltage side of the device to be formed. The photolithography process may include photolithographic exposure of a patterned layer formed only on the first surface of the substrate to define the first channel region. This photolithographic exposure may be followed by selective etching of the patterned layer to define an exposed region on the first surface of the substrate, which corresponds to the channel region to be formed. According to various embodiments, the exposed region may have a shape in a plan view suitable for the shape of the diode to be formed, such as a square ring shape, a rectangular ring shape, a hexagonal ring shape, etc.

[0053] At frame 1006, a channel diffusion process is performed to form a first channel region. Note that during the channel diffusion process, a first surface of the substrate may be covered by a patterned mask (first patterned layer) such that just the first channel region is exposed to the environment. As an example, the channel diffusion process may involve exposure to a phosphorus-containing material at elevated temperatures to form an N-type channel.

[0054] Advantageously, in some embodiments, the second surface of the substrate opposite to the first surface may be left uncovered during the channel diffusion process, allowing the channel diffusion process to function to form a doped surface layer with the opposite polarity to the substrate, such as an N-type surface layer in the case of a P-type substrate.

[0055] At frame 1008, an enhanced doped layer formation photolithography process is performed to define a low-voltage diode on the front side of the substrate. The photolithography process may involve patterning a patterned layer in a diode region on a first surface of the substrate located within an annular shape defined by a first channel region. After photolithographic exposure, the patterned layer may be etched to expose the first surface of the substrate in regions corresponding to the diode regions (such as square regions, rectangular regions, etc.).

[0056] At box 1010, an enhancement doped layer diffusion process is performed. The diode diffusion process may involve exposing the substrate to a boron-containing material at elevated temperatures to form a P+ surface layer that is shallower than the N-doping depth in the channel region surrounding the P+ surface layer. Note that the second surface of the substrate may be covered to prevent exposure to P- dopant during this operation.

[0057] At block 1012, a low-voltage diode-forming photolithography process is performed to define a low-voltage diode on the front side of the substrate. The photolithography process may involve patterning a patterned layer over a diode region on a first surface of the substrate located within an annular shape defined by a first channel region. After photolithographic exposure, the patterned layer may be etched to expose the first surface of the substrate in regions corresponding to the diode regions (such as square regions, rectangular regions, etc.). In some examples, the exposed region in the operation at block 1012 may substantially overlap with the region exposed in block 1008.

[0058] At box 1014, a diode diffusion process is performed. The diode diffusion process may involve exposing the substrate to a phosphorus-containing material at an elevated temperature to form an N+ surface layer, shallower than the N-doping depth in the channel region surrounding the N+ surface layer. The N+ surface layer may compensate for any p-type doping from the initial substrate and from the formation of the P+ layer, such that the N+ layer is disposed at the outer surface of the substrate, above the P+ layer. Note that the second surface of the substrate may be covered to prevent exposure to N- dopant during this operation.

[0059] According to additional embodiments of this disclosure, the order of some operations in the operation of exemplary process flow 1000 may be changed. In some cases, the relative positions of N-channel diffusion (or second layer formation (N-base region diffusion)) and top-side P+ diffusion (enhanced doping layer diffusion) may be exchanged in the process sequence.

[0060] Figure 11 Another exemplary process flow 1100 is described. At box 1102, a substrate is provided. In one example, the substrate is a P-type silicon semiconductor wafer.

[0061] At frame 1104, a set of photolithography processes is performed to define a first channel region on a first surface of the substrate and a second channel region on a second surface of the substrate. This set of photolithography processes may include photolithographic exposure of two separate patterned layers formed on the first and second surfaces of the substrate to define the first and second channel regions, respectively. The photolithographic exposure of the two patterned layers may be followed by selective etching of the two patterned layers to define a first exposed region on the first surface of the substrate and a second exposed region on the second surface of the substrate, the first and second exposed regions corresponding to the channel region to be formed and the second channel region to be formed, respectively. According to various embodiments, the first and second exposed regions may have shapes suitable for the diode shape to be formed in a plan view, such as a square ring shape, a rectangular ring shape, a hexagonal ring shape, etc.

[0062] At frame 1106, a channel diffusion process is performed to form a first channel region and a second channel region. Note that during the channel diffusion process, the first surface and the second surface of the substrate may each be covered by a patterned mask (a first patterned layer and a second patterned layer), such that just the first and second channel regions are exposed to the environment. As an example, the channel diffusion process may involve exposure to a phosphorus-containing material at elevated temperatures to form an N-type channel.

[0063] Advantageously, in some embodiments, the channel diffusion process can be performed simultaneously on both the first and second surfaces.

[0064] At frame 1108, a base region diffusion process is performed to form a second surface layer on a second side of the substrate. During this stage, the patterned layer can be removed from the second surface while the front surface is covered by a protective layer, such that the entire surface of the second surface is exposed to a dopant, such as an N-type dopant, while the front surface is not exposed to a dopant.

[0065] At block 1110, an enhancement doped layer formation photolithography process is performed to define a low-voltage diode on the front side of the substrate. The photolithography process may involve patterning a patterned layer in a diode region on a first surface of the substrate located within an annular shape defined by a first channel region. After photolithographic exposure, the patterned layer may be etched to expose the first surface of the substrate in regions corresponding to the diode regions (such as square regions, rectangular regions, etc.).

[0066] At box 1112, an enhancement doped layer diffusion process is performed. The diode diffusion process may involve exposing the substrate to a boron-containing material at elevated temperatures to form a P+ surface layer that is shallower than the N-doping depth in the channel region surrounding the P+ surface layer. Note that the second surface of the substrate may be covered to prevent exposure to P- dopant during this operation.

[0067] At block 1114, a low-voltage diode-forming photolithography process is performed to define a low-voltage diode on the front side of the substrate. The photolithography process may involve patterning a patterned layer over a diode region on a first surface of the substrate located within an annular shape defined by a first channel region. After photolithographic exposure, the patterned layer may be etched to expose the first surface of the substrate in regions corresponding to the diode regions (such as square regions, rectangular regions, etc.). In some examples, the exposed region in the operation at block 1114 may substantially overlap with the region exposed in block 1106.

[0068] At box 1116, a diode diffusion process is performed. The diode diffusion process may involve exposing the material to a phosphorus-containing substance at an elevated temperature to form an N+ surface layer, shallower than the N-doping depth in the channel region surrounding the N+ surface layer. The N+ surface layer may compensate for any p-type doping from the initial substrate and from the formation of the P+ layer, such that the N+ layer is disposed at the outer surface of the substrate, above the P+ layer. Note that the second surface of the substrate may be covered to prevent exposure to N- dopant during this operation.

[0069] According to other embodiments of this disclosure, the order of some operations in the exemplary process flow 1100 can be changed. In some cases, the relative positions of N-channel diffusion (or second layer formation (N-base region diffusion)) and top-side P+ diffusion (enhanced doped layer diffusion) can be exchanged in the process sequence.

[0070] While this embodiment has been disclosed with reference to certain embodiments, many modifications, alterations, and variations of the described embodiments are possible without departing from the field and scope of this disclosure as defined by the appended claims. Therefore, this embodiment is not limited to the described embodiments and may have the full scope defined by the language of the following claims and their equivalents.

Claims

1. An asymmetric transient voltage suppression (TVS) device, comprising: A semiconductor substrate, the semiconductor substrate including an internal region having a first polarity; A first surface region is disposed on a first surface of the semiconductor substrate, and the first surface region includes a second polarity opposite to the first polarity; A second surface region, comprising the second polarity, is disposed on a second surface of the semiconductor substrate opposite to the first surface. Wherein, the first surface region includes a first doping concentration, and wherein the second surface region includes a second doping concentration less than the first doping concentration; and A first channel region is disposed adjacent to the outer edge of the first surface region, the first channel region includes a second polarity, wherein the first channel region extends below the first surface to a channel depth greater than a first depth of the first surface region.

2. The asymmetric TVS device according to claim 1, wherein, The first surface region defines the low-voltage side of the semiconductor substrate.

3. The asymmetric TVS device according to claim 1, wherein, The semiconductor substrate includes a p-type substrate, and wherein the first surface region and the second surface region include n-type regions.

4. The asymmetric TVS device according to claim 1, further comprising a second channel region disposed adjacent to the outer edge of the second surface region, the second channel region including the second polarity, wherein, The second channel region extends below the second surface to a second channel depth greater than the second depth of the second surface region.

5. The asymmetric TVS device according to claim 1, wherein, The first surface region has a rectangular shape, a hexagonal shape, an elliptical shape, or an oval shape.

6. The asymmetric TVS device according to claim 1, wherein, The semiconductor substrate includes an n-type substrate, and wherein the first surface region and the second surface region include p-type regions.

7. The asymmetric TVS device according to claim 1 further includes a highly doped layer disposed between the first surface region and the inner region, the highly doped layer comprising a dopant of the first polarity and having a first doping concentration greater than the second doping concentration of the inner layer.

8. The asymmetric TVS device according to claim 1, further comprising a recessed region circumferentially disposed around the first channel region, wherein, Compared to the depth of the first channel, the recessed region extends from the first surface to a deeper depth.

9. The asymmetric TVS device of claim 8 further includes a second recessed region, the second recessed region being circumferentially disposed around the second surface region and extending from the second surface to a deeper depth than a second depth of the second surface region.

10. A method for forming an asymmetric TVS device, comprising: A semiconductor substrate is provided, the semiconductor substrate including an internal region having a first polarity; A first surface region is formed on a first surface of the semiconductor substrate, the first surface region including a second polarity opposite to the first polarity; A second surface region comprising the second polarity is formed on a second surface of the semiconductor substrate opposite to the first surface. Wherein, the first surface region includes a first doping concentration, and wherein the second surface region includes a second doping concentration greater than the first doping concentration; and A first channel region is formed adjacent to the outer edge of the first surface region, the first channel region including the second polarity, wherein the first channel region extends below the first surface to a channel depth greater than the first depth of the first surface region.

11. The method according to claim 10, wherein, The formation of the first surface region and the formation of the second surface region are performed separately.

12. The method according to claim 10, wherein, The second surface region is formed simultaneously with the formation of the first channel region.

13. The method of claim 10, further comprising forming a second channel region adjacent to the outer edge of the second surface region, the second channel region including the second polarity, wherein, The second channel region extends below the second surface to a channel depth greater than the second depth of the second surface region.

14. The method of claim 10, wherein, The semiconductor substrate includes an n-type substrate, and wherein the first surface region and the second surface region include p-type regions.

15. The method of claim 10, further comprising forming a highly doped layer disposed between the first surface region and the inner region, the highly doped layer comprising a dopant of the first polarity and having a first doping concentration greater than the second doping concentration of the inner layer.

16. The method of claim 10, further comprising forming a recessed region circumferentially around the first channel region, wherein, Compared to the depth of the first channel, the recessed region extends from the first surface to a deeper depth.

17. The method of claim 16, further comprising forming a second recessed region circumferentially around the second surface region, and extending from the second surface to a deeper depth than a second depth of the second surface region.

18. An asymmetric transient voltage suppression (TVS) device, comprising: A semiconductor substrate, the semiconductor substrate including an internal region having a P-type polarity; A first surface region is disposed on a first surface of the semiconductor substrate, and the first surface region includes N-type polarity. A second surface region, comprising the N-type polarity and disposed on a second surface of the semiconductor substrate opposite to the first surface. Wherein, the first surface region includes a first doping concentration, and wherein the second surface region includes a second doping concentration less than the first doping concentration; A highly doped layer, disposed between the first surface region and the inner region, the highly doped layer comprising p-type polarity and having a first doping concentration greater than the second doping concentration of the inner region; and A first channel region is disposed adjacent to the outer edge of the first surface region, the first channel region includes the N-type polarity, wherein the first channel region extends below the first surface to a channel depth greater than a first depth of the first surface region.

19. The asymmetric TVS device of claim 18, further comprising a second channel region disposed adjacent to the outer edge of the second surface region, the second channel region including the N-type polarity, wherein, The second channel region extends below the second surface to a second channel depth greater than the second depth of the second surface region.

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