Method for forming a saboridation layer
Patent Information
- Application Number
- CN202610780789.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-01
- Publication Date
- 2026-09-22
AI Technical Summary
所以，现有工艺中，SAB氧化层的漏电性能和生产效率无法同时满足
[0024]本发明对SAB氧化层的形成工艺做了特别设置，且是设置为先进行较低的第一沉积速率的第一沉积工艺，再进行较高的第二沉积速率的第二沉积工艺，第一沉积工艺中，利用较低的第一沉积速率来增加第一氧化层的致密性，在结合对第一氧化层的厚度设置能使半导体器件的漏电满足要求；在满足漏电的基础上，本发明通过第二沉积工艺形成的第二氧化层能增加整个SAB氧化层的厚度，使得SAB氧化层在形成金属硅化物之后能作为场板，由于作为场板的厚度较厚，如果采用第一沉积速率进行沉积的话，会大大影响生产效率，故本发明通过单独设置第二沉积速率的第二沉积工艺，能大大提高生产效率，所以本发明能同时满足漏电要求以及提高生产效率。
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Figure CN122803355A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a method for forming a self-aligned metal silicide barrier (SAB) oxide layer. Background Technology
[0002] In self-aligned metal silicide processes, an SAB oxide layer is required. In some devices, such as LDMOS, an SAB oxide layer is also needed as a field plate after the self-aligned metal silicide process. In current processes, the SAB oxide layer used as the field plate typically requires an 1150 Å thick OTS layer formed using the SACVD TEOS process, where the silicon source uses a TEOS SACVD process. However, leakage current can occur in large-size LDMOS test structures that use an OTS layer as the SAB oxide layer as the field plate.
[0003] By replacing the SAB oxide layer used as the field plate with a furnace tube (FUR) TEOS process, the leakage current in the large-size LDMOS test structure disappears. However, the production efficiency of the furnace tube TEOS process is relatively low. FUR TEOS is also known as LPCVD TEOS. Therefore, in existing processes, the leakage current performance and production efficiency of the SAB oxide layer cannot be simultaneously satisfied. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide a method for forming an SAB oxide layer that can simultaneously meet leakage current requirements and improve production efficiency.
[0005] To solve the above-mentioned technical problems, the method for forming a SAB oxide layer provided by the present invention includes the following steps: A semiconductor substrate on which a semiconductor device is formed is provided, and a first oxide layer is formed on the surface of the semiconductor substrate using a first deposition process at a first deposition rate. The density of the first oxide layer is increased by reducing the first deposition rate, and the thickness of the first oxide layer meets the leakage current requirements of the semiconductor device.
[0006] A second oxide layer is formed on the top surface of the first oxide layer using a second deposition process with a second deposition rate. The first oxide layer and the second oxide layer are stacked to form an SAB oxide layer. The thickness of the second oxide layer is such that the thickness of the SAB oxide layer meets the requirements of the SAB oxide layer as a field plate. The second deposition rate is greater than the first deposition rate to improve the growth efficiency of the SAB oxide layer.
[0007] A further improvement is that the first deposition rate is below 2.8 Å / s.
[0008] A further improvement is that the first deposition process includes either SACVD TEOS process or furnace tube TEOS process.
[0009] A further improvement is that the second deposition rate is above 28 Å / s.
[0010] A further improvement is that the second deposition process includes the SACVD TEOS process.
[0011] A further improvement is that the semiconductor device includes LDMOS.
[0012] A further improvement is that the thickness of the first oxide layer is 650 Å or more.
[0013] A further improvement is that the thickness of the SAB oxide layer is 1150 Å or more.
[0014] A further improvement is that the semiconductor substrate comprises a silicon substrate.
[0015] A further improvement is that the LDMOS includes: a gate structure, a source region heavily doped with a first conductivity type, a channel region doped with a second conductivity type, a drift region doped with a first conductivity type, a drift region field oxygen, and a drain region heavily doped with a first conductivity type.
[0016] The source region is formed in the surface region of the channel region and is self-aligned with the first side of the gate structure.
[0017] The gate structure covers the top surface of the channel region and the second side of the gate structure extends to the top surface of the drift region.
[0018] The leak region is formed on the top surface of the drift region and aligned with the second side of the drift region's field oxygen.
[0019] After the second deposition process, the SAB oxide layer covers the top surface of the source region, the side and top surfaces of the gate structure, the top surface of the drift region field oxygen outside the second side of the gate structure, and the top surface of the drain region. The SAB oxide layer located on the top surface of the drift region field oxygen serves as the field plate.
[0020] Further improvements include: The SAB oxide layer is patterned and etched to expose the top surface of the source region, the top surface of the gate structure, and the top surface of the drain region.
[0021] Metal silicides are self-aligned and formed on the top surfaces of the exposed source region, gate structure, and drain region.
[0022] A further improvement is that the gate structure includes a gate dielectric layer and a gate conductive material layer stacked sequentially.
[0023] A further improvement is that the material of the gate conductive material layer includes polycrystalline silicon.
[0024] This invention features a specially designed SAB oxide layer formation process. It employs a first deposition process with a lower first deposition rate, followed by a second deposition process with a higher second deposition rate. In the first deposition process, the lower first deposition rate increases the density of the first oxide layer. Combined with the controlled thickness of the first oxide layer, this ensures that the leakage current of the semiconductor device meets the requirements. Furthermore, by forming the second oxide layer through the second deposition process, this invention increases the overall thickness of the SAB oxide layer. This allows the SAB oxide layer to function as a field plate after the metal silicide is formed. Since the field plate is relatively thick, using the first deposition rate would significantly impact production efficiency. Therefore, this invention, by separately setting the second deposition rate, greatly improves production efficiency. Thus, this invention simultaneously meets the leakage current requirements and improves production efficiency. Attached Figure Description
[0025] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a flowchart of the method for forming the SAB oxide layer according to an embodiment of the present invention; Figures 2-6 This is a schematic diagram of the device structure in each step of the method for forming the SAB oxide layer according to an embodiment of the present invention. Detailed Implementation
[0026] like Figure 1 The diagram shown is a flowchart of a method for forming the SAB oxide layer 203 according to an embodiment of the present invention; as shown Figures 2 to 6 The diagram shown is a schematic representation of the device structure in each step of the method for forming the SAB oxide layer 203 according to an embodiment of the present invention. The method for forming the SAB oxide layer 203 according to an embodiment of the present invention includes the following steps: Step S101, as follows Figure 2 As shown, a semiconductor substrate 101 on which semiconductor devices are formed is provided.
[0027] exist Figure 2 In one example, the semiconductor substrate 101 includes a silicon substrate.
[0028] The semiconductor device includes LDMOS.
[0029] The LDMOS includes: a gate structure, a source region 104 heavily doped with a first conductivity type, a channel region 103 doped with a second conductivity type, a drift region 102 doped with a first conductivity type, a drift region field oxygen 106, and a drain region 105 heavily doped with a first conductivity type. Figure 2 The region of the semiconductor substrate 101 shown is the region where the drift region 102 is formed.
[0030] The gate structure includes a gate dielectric layer 107 and a gate conductive material layer 108 stacked sequentially.
[0031] The material of the gate conductive material layer 108 includes polycrystalline silicon.
[0032] The source region 104 is formed in the surface region of the channel region 103 and is self-aligned with the first side of the gate structure.
[0033] The gate structure covers the top surface of the channel region 103 and the second side of the gate structure extends to the top surface of the drift region 102.
[0034] The leak area 105 is formed on the top surface of the drift area 102 and aligned with the second side of the drift area field oxygen 106.
[0035] like Figure 3 As shown, a first oxide layer 201 is formed on the surface of the semiconductor substrate 101 using a first deposition process with a first deposition rate. The density of the first oxide layer 201 is increased by reducing the first deposition rate, and the thickness of the first oxide layer 201 meets the leakage current requirements of the semiconductor device.
[0036] In this embodiment of the invention, the first deposition rate is below 2.8 Å / s.
[0037] The first deposition process uses either SACVD TEOS or furnace tube TEOS.
[0038] Step S102, as follows Figure 4 As shown, a second oxide layer 202 is formed on the top surface of the first oxide layer 201 using a second deposition process with a second deposition rate. The first oxide layer 201 and the second oxide layer 202 are stacked to form an SAB oxide layer 203. The thickness of the second oxide layer 202 is such that the thickness of the SAB oxide layer 203 meets the requirements of the SAB oxide layer 203 as a field plate. The second deposition rate is greater than the first deposition rate to improve the growth efficiency of the SAB oxide layer 203.
[0039] In this embodiment of the invention, the second deposition rate is 28 Å / s or higher.
[0040] The second deposition process uses the SACVD TEOS process.
[0041] In this embodiment of the invention, the thickness of the first oxide layer 201 is 650 Å or more. The thickness of the SAB oxide layer 203 is 1150 Å or more. Further experiments show that when the thickness of the first oxide layer 201 is 650 Å and the thickness of the second oxide layer 202 is 500 Å, the low leakage current requirement is met. Furthermore, when the thickness of the first oxide layer 201 is 700 Å and the thickness of the second oxide layer 202 is 450 Å, leakage current can be completely avoided.
[0042] like Figure 4 As shown, after the second deposition process, the SAB oxide layer 203 covers the top surface of the source region 104, the side and top surfaces of the gate structure, the top surface of the drift region field oxygen 106 outside the second side of the gate structure, and the top surface of the drain region 105. The SAB oxide layer 203 located on the top surface of the drift region field oxygen 106 serves as the field plate.
[0043] The following also includes: like Figure 5 As shown, the SAB oxide layer 203 is patterned and etched to expose the top surface of the source region 104, the top surface of the gate structure, and the top surface of the drain region 105.
[0044] like Figure 6 As shown, metal silicide 204 is formed by self-alignment on the top surfaces of the exposed source region 104, the gate structure, and the drain region 105.
[0045] In this embodiment of the invention, the formation process of the SAB oxide layer 203 is specially configured, specifically by performing a first deposition process at a lower first deposition rate followed by a second deposition process at a higher second deposition rate. In the first deposition process, the lower first deposition rate is used to increase the density of the first oxide layer 201. Combined with the thickness setting of the first oxide layer 201, the leakage current of the semiconductor device can meet the requirements. On the basis of meeting the leakage current requirements, the second oxide layer 202 formed by the second deposition process in this embodiment of the invention can increase the thickness of the entire SAB oxide layer 203, so that the SAB oxide layer 203 can serve as a field plate after the metal silicide 204 is formed. Since the thickness of the field plate is relatively thick, if the first deposition rate is used for deposition, it will greatly affect the production efficiency. Therefore, this embodiment of the invention can greatly improve the production efficiency by setting a second deposition process with a separate second deposition rate. Thus, this embodiment of the invention can simultaneously meet the leakage current requirements and improve the production efficiency.
[0046] Existing SACVD processes using high deposition rates produce SAB oxide layers with porous film that easily adsorbs impurities, leading to leakage current when the layer is thick. This invention, however, implements a low-to-high rate stepwise SAB oxide deposition process. For devices where SAB oxide is used as a field plate, the SAB oxide formed in this invention exhibits better leakage current resistance compared to existing high-dep-rate SACVD processes, and higher production efficiency compared to existing low-dep-rate processes such as FUR.
[0047] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A method for forming an SAB oxide layer, characterized in that, Including the following steps: A semiconductor substrate on which a semiconductor device is formed is provided, and a first oxide layer is formed on the surface of the semiconductor substrate using a first deposition process at a first deposition rate. The density of the first oxide layer is increased by reducing the first deposition rate, and the thickness of the first oxide layer meets the leakage current requirements of the semiconductor device. A second oxide layer is formed on the top surface of the first oxide layer using a second deposition process with a second deposition rate. The first oxide layer and the second oxide layer are stacked to form an SAB oxide layer. The thickness of the second oxide layer is such that the thickness of the SAB oxide layer meets the requirements of the SAB oxide layer as a field plate. The second deposition rate is greater than the first deposition rate to improve the growth efficiency of the SAB oxide layer.
2. The method for forming the SAB oxide layer as described in claim 1, characterized in that: The first deposition rate is below 2.8 Å / s.
3. The method for forming the SAB oxide layer as described in claim 2, characterized in that: The first deposition process includes SACVD TEOS process or furnace tube TEOS process.
4. The method for forming a SAB oxide layer as described in claim 1, characterized in that: The second deposition rate is above 28 Å / s.
5. The method for forming the SAB oxide layer as described in claim 4, characterized in that: The second deposition process includes the SACVD TEOS process.
6. The method for forming a SAB oxide layer as described in claim 1, characterized in that: The semiconductor device includes LDMOS.
7. The method for forming a SAB oxide layer as described in claim 6, characterized in that: The thickness of the first oxide layer is 650 Å or more.
8. The method for forming a SAB oxide layer as described in claim 7, characterized in that: The thickness of the SAB oxide layer is greater than 1150 Å.
9. The method for forming a SAB oxide layer as described in claim 6, characterized in that: The semiconductor substrate includes a silicon substrate.
10. The method for forming a SAB oxide layer as described in claim 6, characterized in that: The LDMOS includes: a gate structure, a source region heavily doped with a first conductivity type, a channel region doped with a second conductivity type, a drift region doped with a first conductivity type, a drift region field oxygen, and a drain region heavily doped with a first conductivity type. The source region is formed in the surface region of the channel region and is self-aligned with the first side of the gate structure; The gate structure covers the top surface of the channel region and the second side of the gate structure extends to the top surface of the drift region; The leak area is formed on the top surface of the drift region and aligned with the second side of the drift region's field oxygen; After the second deposition process, the SAB oxide layer covers the top surface of the source region, the side and top surfaces of the gate structure, the top surface of the drift region field oxygen outside the second side of the gate structure, and the top surface of the drain region. The SAB oxide layer located on the top surface of the drift region field oxygen serves as the field plate.
11. The method for forming a SAB oxide layer as described in claim 10, characterized in that, The following also includes: The SAB oxide layer is patterned and etched to expose the top surface of the source region, the top surface of the gate structure, and the top surface of the drain region; Metal silicides are self-aligned and formed on the top surfaces of the exposed source region, gate structure, and drain region.
12. The method for forming a SAB oxide layer as described in claim 10, characterized in that: The gate structure includes a gate dielectric layer and a gate conductive material layer stacked sequentially.
13. The method for forming a SAB oxide layer as described in claim 12, characterized in that: The material of the gate conductive material layer includes polycrystalline silicon.