Trench gate manufacturing method

Abstract

The application discloses a trench gate manufacturing method, comprising the following steps: 1) depositing silicon atoms in a trench with a gate oxide layer and simultaneously performing N-type doping to form a doped polysilicon layer; 2) performing annealing treatment on the doped polysilicon layer to activate the doped impurities; 3) selectively performing pre-etching on the doped polysilicon layer at the top of the trench according to a gate resistance target value; 4) introducing an N-type impurity source into the trench after pre-etching to perform re-doping; 5) performing annealing treatment on the polysilicon after re-doping to activate the re-doped impurities according to the gate resistance target value; and 6) removing the excess polysilicon outside the trench through a back-etching process to form a trench gate. The application can directionally control the gate resistance, improve the in-plane uniformity of Rg and improve the product yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a method for manufacturing a trench gate for trench gate power devices. Background Technology

[0002] Power devices are the core components of modern power electronic systems, often referred to as the "heart" of power electronic equipment. They undertake crucial functions in power conversion, control, and transmission, and their performance directly determines the efficiency, reliability, and cost of the entire power electronic system. Currently, power devices are widely used in key sectors of the national economy, including new energy power generation, smart grids, rail transportation, new energy vehicles, industrial frequency converters, servo drives, white goods, and consumer electronics. As their application scenarios continue to expand, the demands on device performance are also constantly increasing.

[0003] In power devices, the gate, as the core electrode controlling the device's turn-on and turn-off, directly determines the device's dynamic switching performance and static conduction capability. Among these, the gate resistance (Rg) is a key parameter affecting the device's operating characteristics: an excessively large Rg leads to slower switching speeds and increased switching losses; an excessively small Rg easily causes oscillations, increased noise, and affects system stability. Especially in high-power, high-frequency, and multi-transistor parallel applications, the consistency of gate resistance among devices is crucial. Excessive differences in Rg can cause uneven current distribution, device stress imbalance, and in severe cases, even device failure. Therefore, how to precisely control the gate resistance and ensure its in-plane uniformity has become a core requirement for the development and mass production of high-performance power devices.

[0004] The current gate fabrication process for trench gate power devices typically involves: forming a trench structure on a silicon substrate and growing a gate oxide layer on the inner wall of the trench; then depositing silicon atoms in the trench to form a polycrystalline silicon layer, with N-type impurity doping occurring simultaneously during the deposition process to obtain a certain level of conductivity; performing an annealing process after deposition to activate the doped impurities; and finally, removing excess polycrystalline silicon from the outside of the trench through a single etch-back process, retaining only the polycrystalline silicon inside the trench as the gate, thus completing the gate fabrication.

[0005] However, this traditional process has significant limitations: the gate resistance value depends entirely on the impurity doping concentration and distribution during the polysilicon deposition stage, and the process adjustment methods are limited. To obtain different Rg values, it is usually necessary to change the doping conditions or growth mode of the deposition furnace tube, such as using special methods like spacer growth or spot doping. However, such adjustments significantly reduce equipment capacity and increase manufacturing costs, making it difficult to meet the needs of large-scale mass production. Under the constraints of existing mass production processes, the adjustable range of the gate resistance is narrow, and the control capability is limited. At the same time, affected by factors such as deposition uniformity, differences in doping distribution, and uneven furnace tube temperature field, the Rg at different locations within the wafer surface has large dispersion and poor uniformity, resulting in difficulty in ensuring device performance consistency and low yield, which seriously restricts the large-scale manufacturing and performance improvement of high-end trench gate power devices. Summary of the Invention

[0006] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0007] To address the shortcomings of existing trench gate power device gate manufacturing processes, such as limited gate resistance control capability, poor in-plane uniformity, and low product yield, this invention provides a trench gate manufacturing method that enables directional control of the gate resistance, improves the in-plane uniformity of Rg, and increases product yield.

[0008] To solve the above-mentioned technical problems, the present invention provides a trench gate manufacturing method, comprising the following steps: 1) Silicon atoms are deposited in trenches where gate oxide layers are grown, and N-type doping is performed simultaneously to form a doped polycrystalline silicon layer; 2) Anneal the doped polysilicon layer to activate the doped impurities; 3) Based on the target value of the gate resistance, selectively pre-etch the doped polysilicon layer at the top of the trench; 4) Introduce an N-type impurity source into the pre-etched trench for redoping; 5) Based on the target value of the gate resistance, the re-doped polysilicon is annealed to activate the re-doped impurities; 6) Remove excess polysilicon outside the trench through a back-etching process to form the trench gate.

[0009] Optionally, the trench gate manufacturing method can be further improved, in step 1), the silicon atom deposition thickness is 6000Å-14000Å.

[0010] Optionally, the trench gate manufacturing method can be further improved, wherein in step 1), the N-type doped impurity is phosphorus.

[0011] Optionally, the trench gate manufacturing method can be further improved by setting the annealing temperature in step 2) to 900℃-1200℃.

[0012] Optionally, the trench gate manufacturing method can be further improved, and in step 3), the pre-etching depth is 0 Å-10000 Å.

[0013] Optionally, the trench gate manufacturing method can be further improved by setting the annealing temperature in step 5) to 900℃-1200℃.

[0014] Optionally, the trench gate manufacturing method can be further improved by removing excess polysilicon outside the trench in step 6) through a secondary etch-back process.

[0015] The working principle of this invention is as follows: Based on the existing gate fabrication process for trench gate power devices, this invention adds three key process steps: pre-etching of polysilicon at the top of the trench, re-doping of N-type impurities, and targeted annealing activation, thus constructing a process link in which the gate resistance can be independently and flexibly adjusted.

[0016] By adjusting the pre-etching depth of the polysilicon at the top of the trench, the effective conductive cross-sectional area of ​​the polysilicon gate in the trench can be precisely changed, thereby directly controlling the basic resistance value of the gate resistor. By adjusting the annealing time and annealing temperature after redoping, the doping concentration and longitudinal / lateral diffusion depth of N-type impurities in the polycrystalline silicon layer can be precisely controlled, effectively improving the uniformity of impurity distribution inside the polycrystalline silicon and on the wafer surface. The two control methods mentioned above work together and are independently adjustable. They can control the gate resistance value in a directional and quantitative manner according to the target value of the gate resistance in different application scenarios. At the same time, they can significantly optimize the uniformity of the overall doping distribution in the wafer plane, thus solving the technical bottleneck of single control and poor uniformity in traditional processes from the root of the process.

[0017] Based on the above working principle, the present invention can achieve at least the following technical effects compared with the prior art: (1) The present invention does not require any changes to the core growth process and capacity configuration of the polysilicon deposition furnace tube. It can precisely match the target gate resistance requirements under different power levels, different switching frequencies and different parallel quantities of application scenarios by adjusting the combination of pre-etching depth, re-doping conditions and annealing parameters.

[0018] Compared to existing processes that rely solely on one-time doping during the deposition stage, have limited control methods, narrow adjustable range, and limited production capacity, this invention overcomes the rigid constraints of the deposition process on the gate resistance, significantly improves the degree of control freedom, has strong process compatibility, and is suitable for large-scale mass production needs.

[0019] (2) Existing processes lack secondary compensation and control methods, which cannot effectively improve the doping dispersion during the deposition stage. The in-plane Rg difference is large and the consistency is poor, which cannot achieve the uniformity level of the present invention.

[0020] The pre-etching process introduced in this invention can modify the morphology of polysilicon at the top of the trench and improve the local electric field distribution; the re-doping process can perform secondary compensation doping for doping unevenness during the deposition stage; and targeted annealing promotes uniform diffusion of impurities and reduces local concentration differences. The three processes work synergistically to optimize the uniformity of impurity distribution in the polysilicon layer from three dimensions: morphology, doping, and activation.

[0021] Experimental test data show that after the re-annealing process of this invention, the overall gate resistance is significantly reduced by about 40%, and the gate resistance difference (Range) within the wafer plane is reduced by about 70%.

[0022] (3) Existing processes have poor controllability of Rg and large in-plane fluctuations, resulting in low yield and insufficient batch stability in mass production, which makes it difficult to meet the mass production requirements of high-end power devices. This invention effectively solves the above problems through process optimization, and provides reliable technical support for high-performance and high-yield mass production of trench gate power devices.

[0023] The increased flexibility in gate resistance adjustment makes it easier to accurately match the device's Rg parameter to the design target; the improved in-plane uniformity significantly reduces the dispersion of device performance within the wafer, reduces the number of defective products caused by Rg exceeding the standard or poor consistency, and significantly improves product yield. Attached Figure Description

[0024] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0025] Figure 1 This is a schematic diagram of the existing technology process.

[0026] Figure 2 This is a schematic diagram of the process of this invention.

[0027] Figure 3 This is a schematic diagram of the pre-etching depth control Rg of the present invention.

[0028] Figure 4 This is a schematic diagram of Rg regulation during re-annealing.

[0029] Figure 5 This is a schematic diagram illustrating the Rg regulation effect of the present invention. Detailed Implementation

[0030] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements. Example

[0031] This embodiment provides a method for manufacturing a trench gate for a trench gate power device, such as... Figure 2 As shown, it includes the following steps: 1) A trench is formed on a silicon substrate, and a gate oxide layer is grown on the inner wall of the trench. Silicon atoms are deposited in the trench using a deposition process with a thickness of 6000Å-14000Å. During the deposition process, phosphorus elements are simultaneously injected for N-type doping to form a doped polycrystalline silicon layer. 2) Perform initial annealing on the doped polycrystalline silicon layer at a temperature of 900℃-1200℃ to activate the initial doped phosphorus impurities; 3) Based on the target gate resistance, pre-etch the doped polysilicon layer at the top of the trench, with a pre-etch depth of 0 Å-10000 Å; if the target Rg is small, increase the pre-etch depth; if the target Rg is large, decrease or cancel the pre-etch. 4) Introduce a phosphorus impurity source into the pre-etched trench to perform N-type redoping on the polysilicon layer in the trench, thereby increasing the local impurity concentration. 5) The re-doped polycrystalline silicon layer is then subjected to re-annealing treatment at a temperature of 900℃-1200℃. The annealing time is adjusted according to the target Rg. The longer the annealing time, the more complete the impurity diffusion and the smaller the Rg. 6) A two-stage etching process is used to remove excess doped polysilicon layers outside the trench, leaving the polysilicon inside the trench as the gate, thus completing the gate fabrication.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0033] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing a trench gate, characterized in that, Includes the following steps: 1) Silicon atoms are deposited in trenches where gate oxide layers are grown, and N-type doping is performed simultaneously to form a doped polycrystalline silicon layer; 2) Anneal the doped polysilicon layer to activate the doped impurities; 3) Based on the target value of the gate resistance, selectively pre-etch the doped polysilicon layer at the top of the trench; 4) Introduce an N-type impurity source into the pre-etched trench for redoping; 5) Based on the target value of the gate resistance, the re-doped polysilicon is annealed to activate the re-doped impurities; 6) Remove excess polysilicon outside the trench through a back-etching process to form the trench gate.

2. The method for manufacturing a trench grid according to claim 1, characterized in that: In step 1), the silicon atom deposition thickness is 6000Å-14000Å.

3. The method for manufacturing a trench grid according to claim 1, characterized in that: In step 1), the N-type doped impurity is phosphorus.

4. The method for manufacturing a trench grid according to claim 1, characterized in that, In step 2), the annealing temperature is 900℃-1200℃.

5. The method for manufacturing a trench grid according to claim 1, characterized in that, In step 3), the pre-etching depth is 0 Å-10000 Å.

6. The method for manufacturing a trench grid according to claim 1, characterized in that, In step 5), the annealing temperature is 900℃-1200℃.

7. The method for manufacturing a trench grid according to claim 1, characterized in that, In step 6), excess polysilicon outside the trench is removed by a secondary etch-back process.

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