A power module package structure

Abstract

The application provides a power module packaging structure, comprising a substrate and a plurality of chip units. The substrate comprises a conductive layer; wherein the conductive layer has a plurality of conductive areas; the plurality of chip units are arranged on the conductive layer, and the plurality of chip units and the plurality of conductive areas form a full-bridge topology; wherein the full-bridge topology comprises a first bridge arm and a second bridge arm, the first bridge arm and the second bridge arm each comprise an upper bridge arm and a lower bridge arm arranged in series, the upper bridge arm and the lower bridge arm have a connection node connected to an alternating current connection end; and the upper bridge arm and the lower bridge arm each comprise two chip units arranged in series, and the power source poles of the two chip units are short-circuited. Through the above arrangement, the full-bridge topology is integrated in the power module packaging structure, the overall volume is smaller, the power density is significantly improved, the assembly process is simplified, and the mass production cost is lower. Moreover, the power source poles of the two chip units in the upper bridge arm and the lower bridge arm are short-circuited, which reduces the parasitic parameters such as loop stray inductance, and thus the switching frequency can be improved.

Description

Technical Field

[0001] This application relates to the field of packaging technology, and in particular to a power module packaging structure. Background Technology

[0002] With the rapid development of high-voltage energy storage, vehicle-mounted high-power conversion equipment, and industrial bidirectional power supplies, the full-bridge power conversion topology (hereinafter referred to as full-bridge topology) has been widely used.

[0003] In related technologies, if a common source module is to be formed into a full-bridge topology, it is generally formed by using single transistors to form a common source and then forming a full-bridge topology. Such solutions have dispersed device layout, large footprint, and low system integration and power density. Summary of the Invention

[0004] To address the aforementioned issues, this application provides a power module packaging structure that can resolve the problems of low integration and power density in common-source full-bridge topology systems.

[0005] To address the aforementioned problems, the first technical solution provided in this application is: to provide a power module packaging structure, comprising: A substrate includes an insulating layer and a conductive layer located on one surface of the insulating layer; wherein the conductive layer has a plurality of conductive regions; Multiple chip units are disposed on the conductive layer, and the multiple chip units and the multiple conductive regions form a full-bridge topology; The full-bridge topology includes a first bridge arm and a second bridge arm. Both the first bridge arm and the second bridge arm include an upper bridge arm and a lower bridge arm connected in series. The upper bridge arm and the lower bridge arm have a connection node, which is connected to an AC connection terminal. Furthermore, both the upper bridge arm and the lower bridge arm include two chip units connected in series, and the power source terminals of the two chip units are short-circuited.

[0006] In one embodiment, the upper bridge arm of the first bridge arm includes: The region comprises a first positive electrode conductive region, a first AC conductive region, a first gate conductive region, a second gate conductive region, and a first intermediate conductive region. The first chip unit has its drain electrically connected to the first positive conductive region; its power source electrically connected to the first intermediate conductive region; and its gate electrically connected to the first gate conductive region. The second chip unit has its drain electrically connected to the first AC conductive region; its power source electrically connected to the first intermediate conductive region; and its gate electrically connected to the second gate conductive region. The lower arm of the first bridge arm includes: The first AC conductive region, the third gate conductive region, the fourth gate conductive region, the second intermediate conductive region, and the first negative electrode conductive region; The third chip unit has its drain electrically connected to the first AC conductive region; its power source electrically connected to the second intermediate conductive region; and its gate electrically connected to the third gate conductive region. The fourth chip unit has its drain electrically connected to the first negative conductive region; its power source electrically connected to the second intermediate conductive region; and its gate electrically connected to the fourth gate conductive region.

[0007] In one embodiment, the upper bridge arm of the second bridge arm includes: The second positive electrode conductive region, the second AC conductive region, the fifth gate conductive region, the sixth gate conductive region, and the third intermediate conductive region; The fifth chip unit has its drain electrically connected to the second positive conductive region; its power source electrically connected to the third intermediate conductive region; and its gate electrically connected to the fifth gate conductive region. The sixth chip unit has its drain electrically connected to the second AC conductive region; its power source electrically connected to the third intermediate conductive region; and its gate electrically connected to the sixth gate conductive region. The lower arm of the second bridge arm includes: The second AC conductive region, the seventh gate conductive region, the eighth gate conductive region, the fourth intermediate conductive region, and the second negative electrode conductive region; A seventh chip unit, wherein the drain of the seventh chip unit is electrically connected to the second AC conductive region; the power source of the seventh chip unit is electrically connected to the fourth intermediate conductive region; and the gate of the seventh chip unit is electrically connected to the seventh gate conductive region. The eighth chip unit has its drain electrically connected to the second negative conductive region; its power source electrically connected to the fourth intermediate conductive region; and its gate electrically connected to the eighth gate conductive region.

[0008] In one embodiment, the first bridge arm and the second bridge arm are symmetrically arranged along a first central axis in a first direction of the substrate.

[0009] In one embodiment, in the first bridge arm, the first positive conductive region and the first negative conductive region are symmetrically arranged along a second central axis of the substrate in a second direction; wherein, the second direction intersects the first direction; The first intermediate conductive region and the second intermediate conductive region are disposed on the side of the first positive electrode conductive region away from the second bridge arm, and the first intermediate conductive region and the second intermediate conductive region are symmetrically arranged along the second central axis; The first AC conductive region is located on the side of the first intermediate conductive region away from the second bridge arm; At least a portion of the first gate conductive region is located between the first positive electrode conductive region and the first intermediate conductive region; at least a portion of the second gate conductive region is located between the first AC conductive region and the first intermediate conductive region; and the first gate conductive region and the second gate conductive region are symmetrically disposed on both sides of the first intermediate conductive region along the second direction. At least a portion of the third gate conductive region is located between the first AC conductive region and the second intermediate conductive region; at least a portion of the fourth gate conductive region is located between the first negative electrode conductive region and the second intermediate conductive region; and the third gate conductive region and the fourth gate conductive region are symmetrically arranged on both sides of the second intermediate conductive region along the second direction; and the first gate conductive region and the fourth gate conductive region are symmetrically arranged along the second direction; the second gate conductive region and the third gate conductive region are symmetrically arranged along the second direction.

[0010] In one embodiment, the first chip unit and the second chip unit are symmetrically disposed on both sides of the first intermediate conductive region along the second direction; The third chip unit and the fourth chip unit are symmetrically disposed on both sides of the second intermediate conductive region along the second direction.

[0011] In one embodiment, the first positive conductive region and the second positive conductive region are integrally formed; and / or The first negative electrode conductive region and the second negative electrode conductive region are integrally formed.

[0012] In one embodiment, the plurality of conductive regions further include a first resistive conductive region and a second resistive conductive region; The power module packaging structure also includes a thermistor, which is connected across the first resistive conductive region and the second resistive conductive region.

[0013] In one embodiment, each chip unit includes two semiconductor chips arranged in parallel.

[0014] In one embodiment, the surface of the substrate facing away from the conductive layer further has a heat dissipation layer; The power module packaging structure also includes: Multiple wiring terminals are electrically connected to multiple of the aforementioned conductive areas; The housing, a portion of the substrate, and the chip unit are disposed within the housing, and at least a portion of the heat dissipation layer and at least a portion of the plurality of interconnect terminals are exposed within the housing; An insulating medium is filled inside the housing.

[0015] The beneficial effects of this application are that, unlike existing technologies, the power module packaging structure provided in this application integrates the full-bridge topology into the power module packaging structure, replacing multiple discrete single-transistor construction schemes. This results in a smaller overall size, significantly improved power density, simplified assembly processes, and lower mass production costs. Furthermore, the short-circuiting of the power source electrodes of the two chip units in the upper and lower bridge arms achieves common node equipotentiality, greatly shortening the power commutation path, eliminating the need for external interconnect conductors, reducing parasitic parameters such as stray inductance, and thus increasing the switching frequency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is a schematic diagram of the power module packaging structure provided in one embodiment of this application; Figure 2 This is a schematic diagram of the structure of a substrate provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of the insulating layer and the conductive layer provided in the first embodiment of this application; Figure 4 This is a schematic diagram of the structure of the insulating layer and the conductive layer provided in the second embodiment of this application; Figure 5 This is a schematic diagram of the structure of the insulating layer and the heat dissipation layer provided in an embodiment of this application; Figure 6 A schematic diagram of the internal layout of the power module packaging structure provided in the first embodiment of this application from one perspective; Figure 7 for Figure 6 A structural schematic diagram of the internal layout shown from another perspective; Figure 8 for Figure 6The circuit topology diagram of the internal layout shown is shown. Figure 9 A schematic diagram of the internal layout of the power module packaging structure provided in the second embodiment of this application from one perspective; Figure 10 for Figure 9 The circuit topology diagram shown is for the internal layout. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0018] The terms "first," "second," and "third," etc., used in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movement of components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0019] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0020] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0021] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0022] The power module packaging structure provided in this application mainly consists of a substrate, multiple semiconductor chips, bonding wires (or micron-sized bonding wires), a thermistor (NTC resistor), an insulating dielectric, a housing, and connection terminals (i.e., pins). The substrate can be fixed inside the housing using methods such as dispensing or snap-fitting. The NTC resistor, connection terminals, and multiple semiconductor chips are soldered onto the substrate; and the surface electrodes of the multiple semiconductor chips are electrically connected to the substrate via bonding wires.

[0023] See Figures 1-5 , Figure 1 This is a schematic diagram of the power module packaging structure provided in one embodiment of this application; Figure 2 This is a schematic diagram of the structure of a substrate provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of the insulating layer and the conductive layer provided in the first embodiment of this application; Figure 4 This is a schematic diagram of the structure of the insulating layer and the conductive layer provided in the second embodiment of this application; Figure 5 This is a schematic diagram of the structure of the insulating layer and the heat dissipation layer provided in an embodiment of this application.

[0024] In this embodiment, the substrate 24 is a ceramic copper-clad substrate (DBC). The substrate 24 includes an insulating layer 24a and a lower copper foil layer and an upper copper foil layer disposed on two opposite surfaces of the insulating layer 24a.

[0025] In this application, since the lower copper foil layer is mainly connected to the system heat sink by applying thermal grease, it is named heat dissipation layer 24b. Since the upper copper foil layer is mainly used to solder semiconductor chips and connect terminals, thereby connecting to external circuits, it is named conductive layer 24c.

[0026] That is, the conductive layer 24c is disposed on one surface of the substrate 24, and the heat dissipation layer 24b is located on the surface of the substrate 24 opposite to the conductive layer 24c.

[0027] The insulating layer 24a possesses high thermal conductivity and insulation properties, providing mechanical support, heat transfer, and insulation for the heat dissipation layer 24b and the conductive layer 24c. In this embodiment, the insulating layer 24a is a ceramic substrate 24, and the material includes, but is not limited to, alumina, aluminum nitride, zirconium-doped alumina, and silicon nitride. Since aluminum nitride has the highest thermal conductivity, it is preferred as the material for the insulating layer 24a to improve the heat dissipation performance of the package structure. The materials for the heat dissipation layer 24b and the conductive layer 24c can be conductive metals, such as copper and aluminum. The conductive layer 24c is divided into multiple conductive regions, and the gaps between the multiple conductive regions meet the requirements of electrical insulation. Multiple semiconductor chips are soldered on at least a portion of the conductive regions to be electrically connected to the corresponding conductive regions. The multiple semiconductor chips are also electrically connected to other conductive regions through micron-sized bonding wires to form a corresponding circuit topology. At least a portion of the heat dissipation layer 24b is exposed to the outer shell 44. The heat dissipation layer 24b can also be connected to the system heat sink by applying thermal grease, thermal cloth, or other materials. The heat from the multiple semiconductor chips and the conductive layer 24c can be transferred to the heat dissipation layer 24b through the insulating layer 24a and then dissipated.

[0028] In some embodiments, multiple conductive regions are designed with minimal electrical clearance to reduce parasitic inductance in the circuit topology and achieve current consistency. Furthermore, the corners of the multiple conductive regions are arc-shaped, which helps reduce localized stress relative to the ceramic insulating layer 24a during copper foil soldering. Additionally, multiple through-holes H (e.g., dimple holes) are provided on some conductive regions and the heat dissipation layer 24b, which can also reduce stress concentration.

[0029] In some embodiments, depending on actual manufacturability and insulation withstand voltage requirements, the multiple conductive areas and the heat dissipation layer 24b are all at a certain distance from the edge of the insulating layer 24a. This distance can be controlled according to actual insulation creepage requirements.

[0030] In some embodiments, a portion of the substrate 24 is disposed within the housing 44 and fixed together with it. For example, a portion of the insulating layer 24a and the conductive layer 24c of the substrate 24 are disposed within the housing 44, while the heat dissipation layer 24b of the substrate 24 is exposed within the housing 44. Since the semiconductor chip is soldered onto the conductive layer 24c, the semiconductor chip is also located within the housing 44. Further, the housing 44 has a potting port 46, through which an insulating medium is filled into the space between the housing 44 and the conductive layer 24c. The insulating medium typically includes insulating glue or insulating varnish (e.g., epoxy resin). The insulating medium can cover the semiconductor chip, the conductive layer 24c, and the arcing height of the micron-sized bonding wires, ensuring that the three are not contaminated by the external environment. A protective protrusion 45 is provided on the top of the housing 44 to facilitate connection and positioning of external devices such as circuit boards. The housing 44 is made of a material with resistance to plastic deformation, heat deformation, and electrical insulation, such as polybutylene terephthalate (PBT).

[0031] Specifically, the power module packaging structure provided in this application embodiment can adopt the Easy 2B standard packaging, which is highly versatile and can significantly reduce equipment modification costs and R&D cycle.

[0032] See Figures 6-10 , Figure 6 A schematic diagram of the internal layout of the power module packaging structure provided in the first embodiment of this application from one perspective; Figure 7 for Figure 6 A structural schematic diagram of the internal layout shown from another perspective; Figure 8 for Figure 6 The circuit topology diagram of the internal layout shown is shown. Figure 9 A schematic diagram of the internal layout of the power module packaging structure provided in the second embodiment of this application from one perspective; Figure 10 for Figure 9 The circuit topology diagram shown is for the internal layout.

[0033] In some embodiments, the semiconductor chip is a power semiconductor chip, such as a MOSFET chip (metal-oxide-semiconductor field-effect transistor chip), an IGBT chip (insulated-gate bipolar transistor chip), etc., and the material of the semiconductor chip includes silicon carbide (SiC). Specifically, compared with silicon (Si) chips, SiC chips have lower power losses, faster switching speeds, and higher operating temperatures, thereby improving chip performance.

[0034] In this embodiment, every two semiconductor chips are connected in parallel to form a chip unit, which can improve the rectification and current-carrying capacity of the packaging structure, thereby improving the product performance of the packaging structure.

[0035] Of course, in other embodiments, the chip unit may include three, four or other semiconductor chips connected in parallel. This is not a limitation and the design will be based on the size limitations of the packaging structure, the thermal coupling between chips, and the complexity of the layout.

[0036] In this embodiment, multiple chip units also form a full-bridge topology with multiple conductive regions. The full-bridge topology includes a first bridge arm and a second bridge arm. Both the first and second bridge arms include an upper bridge arm and a lower bridge arm connected in series. The upper and lower bridge arms have connection nodes connected to AC connection terminals. Furthermore, both the upper and lower bridge arms include two chip units connected in series, with the power source terminals of the two chip units short-circuited.

[0037] Specifically, in the power module packaging structure provided in this application, all semiconductor chips are uniformly arranged on the conductive layer 24c of the same substrate 24 to form a complete full-bridge topology, replacing the multiple discrete single-tube construction scheme; reducing the transition copper busbars and mounting structural components between multiple single tubes, the overall size is smaller, the power density is significantly improved, and the assembly process is simplified, resulting in lower mass production costs.

[0038] In addition, the power source terminals of the two chip units in the upper and lower bridge arms are shorted to achieve common node equipotentiality, which greatly shortens the power commutation path, eliminates the need for external interconnect conductors, reduces parasitic parameters such as loop stray inductance, and thus can improve the switching frequency.

[0039] Furthermore, all semiconductor chips are cooled centrally on the same substrate 24, resulting in a small temperature difference between chips and better static and dynamic current sharing, avoiding overload aging of individual semiconductor chips and improving long-term operational reliability.

[0040] See Figure 3 and Figure 4 In this embodiment of the application, the multiple conductive regions in the conductive layer 24c include a first positive conductive region 17a, a second positive conductive region 17b, a first negative conductive region 20a, a second negative conductive region 20b, a first AC conductive region 19a, a second AC conductive region 19b, a first gate conductive region 21b, a second gate conductive region 21a, a third gate conductive region 21e, a fourth gate conductive region 21f, a fifth gate conductive region 21c, a sixth gate conductive region 21d, a seventh gate conductive region 21h, an eighth gate conductive region 21g, a first intermediate conductive region 18a, a second intermediate conductive region 18c, a third intermediate conductive region 18b, and a fourth intermediate conductive region 18d.

[0041] The first AC conductive region 19a and its connecting terminals serve as the AC connection terminals of the first bridge arm, and the second AC conductive region 19b and its connecting terminals serve as the AC connection terminals of the second bridge arm.

[0042] The first positive conductive region 17a and the second positive conductive region 17b can be integrally molded, or they can be designed independently. This results in different full-bridge topologies, which are designed according to the actual application scenario.

[0043] In this embodiment of the application, the first positive electrode conductive region 17a and the second positive electrode conductive region 17b are integrally formed as an example.

[0044] The first negative conductive region 20a and the second negative conductive region 20b can be integrally molded, or they can be designed independently. This results in different full-bridge topologies, which are designed according to the specific application scenario.

[0045] Combination Figure 3 , Figure 6 and Figure 8 The first negative electrode conductive region 20a and the second negative electrode conductive region 20b are integrally molded.

[0046] Combination Figure 4 , Figure 9 and Figure 10 The first negative electrode conductive region 20a and the second negative electrode conductive region 20b are designed independently, thereby decoupling the first bridge arm and the second bridge arm and expanding the applicable scenarios of the module.

[0047] Multiple chip units include a first chip unit Q1, a second chip unit Q2, a third chip unit Q3, a fourth chip unit Q4, a fifth chip unit Q5, a sixth chip unit Q6, a seventh chip unit Q7, and an eighth chip unit Q8.

[0048] It should be noted that, as Figures 6-8 As shown, numbers 1 to 16 represent 16 semiconductor chips. Semiconductor chip 1 and semiconductor chip 2 are connected in parallel to form the first chip unit Q1; semiconductor chip 5 and semiconductor chip 6 are connected in parallel to form the second chip unit Q2; semiconductor chip 7 and semiconductor chip 8 are connected in parallel to form the third chip unit Q3; semiconductor chip 13 and semiconductor chip 14 are connected in parallel to form the fourth chip unit Q4; semiconductor chip 3 and semiconductor chip 4 are connected in parallel to form the fifth chip unit Q5; semiconductor chip 9 and semiconductor chip 10 are connected in parallel to form the sixth chip unit Q6; semiconductor chip 11 and semiconductor chip 12 are connected in parallel to form the seventh chip unit Q7; and semiconductor chip 15 and semiconductor chip 16 are connected in parallel to form the eighth chip unit Q8.

[0049] In this context, labels 1a to 16a represent the gate drive bonding lines of 16 semiconductor chips, and labels 1b to 16b represent the power source bonding lines of 16 semiconductor chips.

[0050] Among them, number 26 is the connection terminal on the first positive conductive region 17a and the second positive conductive region 17b, number 27 is the connection terminal on the first negative conductive region 20a and the second negative conductive region 20b, number 28 is the connection terminal on the first AC conductive region 19a, number 29 is the connection terminal on the second AC conductive region 19b, numbers 30a to 37a are 8 connection terminals that are one-to-one arranged in the above eight gate conductive regions, and numbers 38 to 41 are 8 connection terminals that are arranged in pairs in the above four intermediate conductive regions.

[0051] The wiring terminals can be soldered to the corresponding conductive areas using high-temperature solder or ultrasonic welding. At least a portion of the wiring terminals is exposed outside the housing 44 to facilitate electrical connection to external circuitry.

[0052] Furthermore, the surface of the wiring terminals is also plated with nickel and / or gold to resist moisture, mold and salt spray, thereby enhancing service life.

[0053] The upper arm of the first bridge arm includes a first positive conductive region 17a, a first AC conductive region 19a, a first gate conductive region 21b, a second gate conductive region 21a, and a first intermediate conductive region 18a; and the upper arm of the first bridge arm also includes a first chip unit Q1 and a second chip unit Q2.

[0054] Specifically, the drain of the first chip unit Q1 is electrically connected to the first positive conductive region 17a; the power source of the first chip unit Q1 is electrically connected to the first intermediate conductive region 18a; and the gate of the first chip unit Q1 is electrically connected to the first gate conductive region 21b. The drain of the second chip unit Q2 is electrically connected to the first AC conductive region 19a; the power source of the second chip unit Q2 is electrically connected to the first intermediate conductive region 18a, so as to achieve common source connection by shorting it with the power source of the first chip unit Q1; and the gate of the second chip unit Q2 is electrically connected to the second gate conductive region 21a.

[0055] The lower arm of the first bridge arm includes a first AC conductive region 19a, a third gate conductive region 21e, a fourth gate conductive region 21f, a second intermediate conductive region 18c, and a first negative conductive region 20a; and the lower arm of the first bridge arm also includes a third chip unit Q3 and a fourth chip unit Q4.

[0056] Specifically, the drain of the third chip unit Q3 is electrically connected to the first AC conductive region 19a; the power source of the third chip unit Q3 is electrically connected to the second intermediate conductive region 18c; the gate of the third chip unit Q3 is electrically connected to the third gate conductive region 21e; ​​the drain of the fourth chip unit Q4 is electrically connected to the first negative conductive region 20a; the power source of the fourth chip unit Q4 is electrically connected to the second intermediate conductive region 18c, so as to achieve common source connection with the power source of the third chip unit Q3 by shorting it; the gate of the fourth chip unit Q4 is electrically connected to the fourth gate conductive region 21f.

[0057] The upper arm of the second bridge arm includes a second positive conductive region 17b, a second AC conductive region 19b, a fifth gate conductive region 21c, a sixth gate conductive region 21d, and a third intermediate conductive region 18b; and the upper arm of the second bridge arm also includes a fifth chip unit Q5 and a sixth chip unit Q6.

[0058] Specifically, the drain of the fifth chip unit Q5 is electrically connected to the second positive conductive region 17b; the power source of the fifth chip unit Q5 is electrically connected to the third intermediate conductive region 18b; the gate of the fifth chip unit Q5 is electrically connected to the fifth gate conductive region 21c; the drain of the sixth chip unit Q6 is electrically connected to the second AC conductive region 19b; the power source of the sixth chip unit Q6 is electrically connected to the third intermediate conductive region 18b, so as to achieve common source connection by shorting it with the power source of the fifth chip unit Q5; the gate of the sixth chip unit Q6 is electrically connected to the sixth gate conductive region 21d.

[0059] The lower arm of the second bridge arm includes a second AC conductive region 19b, a seventh gate conductive region 21h, an eighth gate conductive region 21g, a fourth intermediate conductive region 18d, and a second negative conductive region 20b; and the lower arm of the second bridge arm also includes a seventh chip unit Q7 and an eighth chip unit Q8.

[0060] Specifically, the drain of the seventh chip unit Q7 is electrically connected to the second AC conductive region 19b; the power source of the seventh chip unit Q7 is electrically connected to the fourth intermediate conductive region 18d; the gate of the seventh chip unit Q7 is electrically connected to the seventh gate conductive region 21h; the drain of the eighth chip unit Q8 is electrically connected to the second negative conductive region 20b; the power source of the eighth chip unit Q8 is electrically connected to the fourth intermediate conductive region 18d, so as to achieve common source connection by shorting it with the power source of the seventh chip unit Q7; the gate of the eighth chip unit Q8 is electrically connected to the eighth gate conductive region 21g.

[0061] Since the first and second bridge arms have the same topology, the following explanation uses the first bridge arm as an example. See details below. Figure 3 , Figures 6-8 .

[0062] The main power circuit of the first bridge arm: The drain of semiconductor chips (1, 2) is soldered to the first positive conductive region 17a and connected to the external circuit through the wiring terminal (26). Its power source is connected to the first intermediate conductive region 18a through bonding wires (1b, 2b) and led out through the wiring terminal (38). The first intermediate conductive region 18a is also connected to the power source of semiconductor chips (5, 6) through bonding wires (5b, 6b) to realize the common source connection of semiconductor chips (1, 2) and semiconductor chips (5, 6). The drains of semiconductor chips (5, 6, 7, 8) are all soldered to the first AC conductive region 19a and connected to the external circuit through the wiring terminal (28). The power source of semiconductor chips (7, 8) is connected to the second intermediate conductive region 18c through bonding wires (7b, 8b) and led out through the wiring terminal (39). The second intermediate conductive region 18c is connected to the power source of the semiconductor chip (13, 14) via bonding wires (13b, 14b) to achieve common source connection between the semiconductor chip (7, 8) and the semiconductor chip (13, 14); the drain of the semiconductor chip (13, 14) is soldered to the first negative conductive region 20a and connected to the external circuit via the wiring terminal (27).

[0063] Specifically, the first bridge arm acts as a common source pole unit, which combines with the second bridge arm on the other side to ultimately form a common source pole full bridge topology.

[0064] The drive circuit of the first bridge arm: Semiconductor chips (1, 2) are connected to the first gate conductive region 21b and the connection terminal (30a) through bonding lines (1a, 2a); Semiconductor chips (5, 6) are connected to the second gate conductive region 21a and the connection terminal (32a) through bonding lines (5a, 6a); Semiconductor chips (7, 8) are connected to the third gate conductive region 21e and the connection terminal (36a) through bonding lines (7a, 8a); Semiconductor chips (13, 14) are connected to the fourth gate conductive region 21f and the connection terminal (34a) through bonding lines (13a, 14a).

[0065] In operation, the external circuit controls the gates of the first chip unit Q1 and the third chip unit Q3 to be turned on, and controls the gates of the second chip unit Q2 and the fourth chip unit Q4 to be turned off. A positive voltage is input to the connection terminal (26), flowing into the power source of the second chip unit Q2 through the turned-on first chip unit Q1, then into the drain of the third chip unit Q3 through the body diode of the second chip unit Q2, then into the power source of the fourth chip unit Q4 through the turned-on third chip unit Q3, and finally into the connection terminal (27) through the body diode of the fourth chip unit Q4. The reverse is also true.

[0066] In this embodiment of the application, the substrate 24 has a first central axis X extending along a first direction and a second central axis Y extending along a second direction, wherein the first direction and the second direction intersect.

[0067] For example, the first direction is the width direction, and the second direction is the length direction. Or, the first direction is the length direction, and the second direction is the width direction.

[0068] The first bridge arm and the second bridge arm are symmetrically arranged along the first central axis X of the first direction of the substrate 24.

[0069] It should be noted that in this application, the first bridge arm and the second bridge arm are symmetrically arranged. This can mean that the two bridge arms are completely symmetrically arranged along the first central axis X of the first direction of the substrate 24; or that at least 90% of the two bridge arms are symmetrically arranged along the first central axis X of the first direction of the substrate 24.

[0070] See also: Figure 3 and Figure 7 In the left-hand region where the first bridge arm is located, multiple conductive regions include a first resistive conductive region 22a and a second resistive conductive region 22b. The power module packaging structure also includes a thermistor 43, which is connected across the first resistive conductive region 22a and the second resistive conductive region 22b. However, in the right-hand region where the second bridge arm is located, the first resistive conductive region 22a, the second resistive conductive region 22b, and the thermistor 43 are not provided. This results in a slight difference in shape between the first AC conductive region 19a and the second AC conductive region 19b. Nevertheless, the general structure of the first and second bridge arms is substantially symmetrical along the first central axis X of the substrate 24 in the first direction.

[0071] Among them, labels 42a and 42b are two connecting terminals disposed on the first resistive conductive region 22a and the second resistive conductive region 22b.

[0072] The thermistor 43 can be electrically connected to the first resistive conductive region 22a and the second resistive conductive region 22b by means of welding or sintering. The thermistor 43 is electrically connected to the external circuit through the connection terminal (42a) provided on the first resistive conductive region 22a and the connection terminal (42b) provided on the second resistive conductive region 22b.

[0073] Specifically, in the symmetrical layout, the semiconductor chips in the first and second bridge arms are evenly arranged on the substrate 24, and there are no local hot spots in the heat distribution; the temperature rise and thermal resistance of the semiconductor chips on the two bridge arms are basically the same, and the stray inductance, loop impedance and conduction voltage drop on the two bridge arms are highly consistent, so that the dynamic and static current distribution is balanced, which can effectively improve the overall current sharing capability of the packaging structure, thereby improving the overall reliability of the module.

[0074] In one embodiment, in the first bridge arm, the first positive electrode conductive region 17a and the first negative electrode conductive region 20a are symmetrically arranged along the second central axis Y of the second direction of the substrate 24. The first intermediate conductive region 18a and the second intermediate conductive region 18c are disposed on the side of the first positive electrode conductive region 17a away from the second bridge arm, and are symmetrically arranged along the second central axis Y. The first AC conductive region 19a is disposed on the side of the first intermediate conductive region 18a away from the second bridge arm. At least a portion of the first gate conductive region 21b is located between the first positive electrode conductive region 17a and the first intermediate conductive region 18a. At least a portion of the second gate conductive region 21a is located between the first AC conductive region 19a and the first intermediate conductive region 18a. The first gate conductive region 21a and the second intermediate conductive region 18a are symmetrically arranged along the second direction on both sides of the first intermediate conductive region 18a; at least a portion of the third gate conductive region 21e is located between the first AC conductive region 19a and the second intermediate conductive region 18c; at least a portion of the fourth gate conductive region 21f is located between the first negative electrode conductive region 20a and the second intermediate conductive region 18c; and the third gate conductive region 21e and the fourth gate conductive region 21f are symmetrically arranged along the second direction on both sides of the second intermediate conductive region 18c; and the first gate conductive region 21b and the fourth gate conductive region 21f are symmetrically arranged along the second direction; the second gate conductive region 21a and the third gate conductive region 21e are symmetrically arranged along the second direction.

[0075] Furthermore, the first chip unit Q1 and the second chip unit Q2 are symmetrically disposed on both sides of the first intermediate conductive region 18a along the second direction; the third chip unit Q3 and the fourth chip unit Q4 are symmetrically disposed on both sides of the second intermediate conductive region 18c along the second direction.

[0076] That is, the topology of the upper and lower bridge arms of the first bridge arm is also symmetrically arranged, which can further improve the current sharing capability of the packaging structure.

[0077] In the second bridge arm, the second positive conductive region 17b and the second negative conductive region 20b are symmetrically arranged along the second central axis Y of the second direction of the substrate 24. The third intermediate conductive region 18b and the fourth intermediate conductive region 18d are disposed on the side of the second positive conductive region 17b away from the first bridge arm, and are symmetrically arranged along the second central axis Y. The second AC conductive region 19b is disposed on the side of the third intermediate conductive region 18b away from the first bridge arm. At least a portion of the fifth gate conductive region 21c is located between the second positive conductive region 17b and the third intermediate conductive region 18b. At least a portion of the sixth gate conductive region 21d is located between the second AC conductive region 19b and the third intermediate conductive region 18b. The gate conductive regions 21c and 21g are symmetrically arranged on both sides of the third intermediate conductive region 18b along the second direction; at least a portion of the seventh gate conductive region 21h is located between the second AC conductive region 19b and the fourth intermediate conductive region 18d; at least a portion of the eighth gate conductive region 21g is located between the second negative electrode conductive region 20b and the fourth intermediate conductive region 18d; and the seventh gate conductive region 21h and the eighth gate conductive region 21g are symmetrically arranged on both sides of the fourth intermediate conductive region 18d along the second direction; and the fifth gate conductive region 21c and the eighth gate conductive region 21g are symmetrically arranged along the second direction; the sixth gate conductive region 21d and the seventh gate conductive region 21h are symmetrically arranged along the second direction.

[0078] Furthermore, the fifth chip unit Q5 and the sixth chip unit Q6 are symmetrically arranged on both sides of the third intermediate conductive region 18b along the second direction; the seventh chip unit Q7 and the eighth chip unit Q8 are symmetrically arranged on both sides of the fourth intermediate conductive region 18d along the second direction.

[0079] That is, the topology of the upper and lower bridge arms of the second bridge arm is also symmetrically arranged, which can further improve the current sharing capability of the packaging structure.

[0080] Specifically, the power module packaging structure provided in this application has the following advantages: 1. It adopts the standard Easy 2B package, which is highly versatile and can be adapted to relevant applications of the conventional Easy 2B package.

[0081] 2. Adding the common-source topology to the full-bridge structure reduces the footprint, increases power density, reduces parasitic parameters, and increases the switching frequency.

[0082] 3. The conductive layer pattern adopts a symmetrical design, which can effectively improve the overall current sharing capability of the module, thereby improving the overall reliability of the module.

[0083] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A power module packaging structure, characterized in that, include: A substrate includes an insulating layer and a conductive layer located on one surface of the insulating layer; wherein the conductive layer has a plurality of conductive regions; Multiple chip units are disposed on the conductive layer, and the multiple chip units and the multiple conductive regions form a full-bridge topology; The full-bridge topology includes a first bridge arm and a second bridge arm. Both the first bridge arm and the second bridge arm include an upper bridge arm and a lower bridge arm connected in series. The upper bridge arm and the lower bridge arm have a connection node, which is connected to an AC connection terminal. Furthermore, both the upper bridge arm and the lower bridge arm include two chip units connected in series, and the power source terminals of the two chip units are short-circuited.

2. The power module packaging structure according to claim 1, characterized in that, The upper arm of the first bridge arm includes: The region comprises a first positive electrode conductive region, a first AC conductive region, a first gate conductive region, a second gate conductive region, and a first intermediate conductive region. The first chip unit has its drain electrically connected to the first positive conductive region; its power source electrically connected to the first intermediate conductive region; and its gate electrically connected to the first gate conductive region. The second chip unit has its drain electrically connected to the first AC conductive region; its power source electrically connected to the first intermediate conductive region; and its gate electrically connected to the second gate conductive region. The lower arm of the first bridge arm includes: The first AC conductive region, the third gate conductive region, the fourth gate conductive region, the second intermediate conductive region, and the first negative electrode conductive region; The third chip unit has its drain electrically connected to the first AC conductive region; its power source electrically connected to the second intermediate conductive region; and its gate electrically connected to the third gate conductive region. The fourth chip unit has its drain electrically connected to the first negative conductive region; its power source electrically connected to the second intermediate conductive region; and its gate electrically connected to the fourth gate conductive region.

3. The power module packaging structure according to claim 2, characterized in that, The upper arm of the second bridge arm includes: The second positive electrode conductive region, the second AC conductive region, the fifth gate conductive region, the sixth gate conductive region, and the third intermediate conductive region; The fifth chip unit has its drain electrically connected to the second positive conductive region; its power source electrically connected to the third intermediate conductive region; and its gate electrically connected to the fifth gate conductive region. The sixth chip unit has its drain electrically connected to the second AC conductive region; its power source electrically connected to the third intermediate conductive region; and its gate electrically connected to the sixth gate conductive region. The lower arm of the second bridge arm includes: The second AC conductive region, the seventh gate conductive region, the eighth gate conductive region, the fourth intermediate conductive region, and the second negative electrode conductive region; A seventh chip unit, wherein the drain of the seventh chip unit is electrically connected to the second AC conductive region; the power source of the seventh chip unit is electrically connected to the fourth intermediate conductive region; and the gate of the seventh chip unit is electrically connected to the seventh gate conductive region. The eighth chip unit has its drain electrically connected to the second negative conductive region; its power source electrically connected to the fourth intermediate conductive region; and its gate electrically connected to the eighth gate conductive region.

4. The power module packaging structure according to claim 3, characterized in that, The first bridge arm and the second bridge arm are symmetrically arranged along the first central axis of the first direction of the substrate.

5. The power module packaging structure according to claim 4, characterized in that, In the first bridge arm, the first positive electrode conductive region and the first negative electrode conductive region are symmetrically arranged along the second central axis of the second direction of the substrate; wherein, the second direction intersects the first direction; The first intermediate conductive region and the second intermediate conductive region are disposed on the side of the first positive electrode conductive region away from the second bridge arm, and the first intermediate conductive region and the second intermediate conductive region are symmetrically arranged along the second central axis; The first AC conductive region is located on the side of the first intermediate conductive region away from the second bridge arm; At least a portion of the first gate conductive region is located between the first positive electrode conductive region and the first intermediate conductive region; at least a portion of the second gate conductive region is located between the first AC conductive region and the first intermediate conductive region; and the first gate conductive region and the second gate conductive region are symmetrically disposed on both sides of the first intermediate conductive region along the second direction. At least a portion of the third gate conductive region is located between the first AC conductive region and the second intermediate conductive region; at least a portion of the fourth gate conductive region is located between the first negative electrode conductive region and the second intermediate conductive region; and the third gate conductive region and the fourth gate conductive region are symmetrically arranged on both sides of the second intermediate conductive region along the second direction; and the first gate conductive region and the fourth gate conductive region are symmetrically arranged along the second direction; the second gate conductive region and the third gate conductive region are symmetrically arranged along the second direction.

6. The power module packaging structure according to claim 5, characterized in that, The first chip unit and the second chip unit are symmetrically disposed on both sides of the first intermediate conductive region along the second direction; The third chip unit and the fourth chip unit are symmetrically disposed on both sides of the second intermediate conductive region along the second direction.

7. The power module packaging structure according to any one of claims 3-6, characterized in that, The first positive conductive region and the second positive conductive region are integrally formed; and / or The first negative electrode conductive region and the second negative electrode conductive region are integrally formed.

8. The power module packaging structure according to any one of claims 3-6, characterized in that, The plurality of conductive regions further include a first resistive conductive region and a second resistive conductive region; The power module packaging structure also includes a thermistor, which is connected across the first resistive conductive region and the second resistive conductive region.

9. The power module packaging structure according to claim 1, characterized in that, Each of the chip units comprises two semiconductor chips arranged in parallel.

10. The power module packaging structure according to claim 8, characterized in that, The surface of the substrate opposite to the conductive layer also has a heat dissipation layer; The power module packaging structure also includes: Multiple wiring terminals are electrically connected to multiple of the aforementioned conductive areas; The housing, a portion of the substrate, and the chip unit are disposed within the housing, and at least a portion of the heat dissipation layer and at least a portion of the plurality of interconnect terminals are exposed within the housing; An insulating medium is filled inside the housing.

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