Semiconductor device

Abstract

A semiconductor device capable of maintaining a low resistance of a diode portion and making a threshold value of a transistor portion a prescribed value. The semiconductor device includes a first electrode, a semiconductor portion disposed on the first electrode, a first conductive type, a first trench and a second trench formed on an upper surface in a mutually isolated manner, a conductive metal oxide film disposed on at least a side surface of the first trench, in contact with the semiconductor portion, a second electrode disposed in the first trench and on the semiconductor portion, in contact with the conductive metal oxide film, and including a metal, an insulating member disposed in the second trench, and a third electrode disposed in the insulating member.

Description

[0001] [Linked Application]

[0002] This application enjoys priority to Japanese Patent Application No. 2025-047421 (filed on March 21, 2025) and Japanese Patent Application No. 2025-090563 (filed on May 30, 2025). This application incorporates the entire contents of the basic applications by reference to them. Technical Field

[0003] The implementation involves a semiconductor device. Background Technology

[0004] In recent years, semiconductor devices have been developed that incorporate semiconductor-based transistor sections and Schottky junction-based diode sections by embedding metal components within source trenches. In such semiconductor devices, it is required to maintain a low resistance in the diode section and set a predetermined threshold value for the transistor section. Summary of the Invention

[0005] An embodiment provides a semiconductor device capable of maintaining a low resistance in the diode section and setting the threshold value of the transistor section to a predetermined value.

[0006] The semiconductor device of the embodiment includes: a first electrode; a semiconductor portion disposed on the first electrode, having a first conductivity type, and having a first trench and a second trench formed on its upper surface in a mutually isolated manner; a conductive metal oxide film disposed at least on the side surface of the first trench and in contact with the semiconductor portion; a second electrode disposed in the first trench and on the semiconductor portion, in contact with the conductive metal oxide film, and comprising metal; an insulating member disposed in the second trench; and a third electrode disposed in the insulating member. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0008] Figure 2 yes Figure 1 The cross-sectional view of line A-A' shown.

[0009] Figure 3 This is a process cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0010] Figure 4 This is a process cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0011] Figure 5 This is a process cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0012] Figure 6 This is a process cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0013] Figure 7 This is a process cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0014] Figure 8 This is a cross-sectional view of a semiconductor device representing a comparative example.

[0015] Figure 9 This is a cross-sectional view showing the semiconductor device according to the second embodiment.

[0016] Figure 10 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0017] Figure 11 This is a cross-sectional view showing the semiconductor device according to the third embodiment.

[0018] Figure 12 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the third embodiment.

[0019] Figure 13 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the third embodiment.

[0020] Figure 14 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the third embodiment.

[0021] Figure 15 This is a cross-sectional view showing the semiconductor device according to the fourth embodiment.

[0022] Figure 16 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the fourth embodiment.

[0023] Figure 17 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the fifth embodiment.

[0024] Figure 18 This is a cross-sectional view showing the semiconductor device according to the sixth embodiment.

[0025] Figure 19 It means Figure 18 A magnified sectional view of region C.

[0026] Figure 20 This is a cross-sectional view showing the semiconductor device according to the seventh embodiment.

[0027] Figure 21 yes Figure 20 The cross-sectional view of line D-D' shown.

[0028] Figure 22 This is a cross-sectional view showing the semiconductor device according to the eighth embodiment.

[0029] Figure 23 It means Figure 22 A partially enlarged sectional view of region E. Detailed Implementation

[0030] <First Implementation Method>

[0031] The semiconductor device in this embodiment is a semiconductor device for power control, such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a built-in Schottky barrier diode.

[0032] Figure 1 This is a cross-sectional view showing the semiconductor device of this embodiment.

[0033] Figure 2 yes Figure 1 The cross-sectional view of line A-A' shown.

[0034] also, Figure 1 yes Figure 2 The cross-sectional view of line B-B' shown.

[0035] like Figure 1 and Figure 2 As shown, in the semiconductor device 1 of this embodiment, a drain electrode 10 (first electrode), a silicon portion 20 (semiconductor portion), a titanium oxide film 30 (conductive metal oxide film), a source electrode 40 (second electrode), an insulating component 50, a gate electrode 60 (third electrode), and a field plate electrode 70 (hereinafter referred to as "FP electrode 70") are provided.

[0036] For ease of explanation, the following description uses an XYZ orthogonal coordinate system. The direction from the drain electrode 10 toward the source electrode 40 is defined as the "Z direction," the direction in which the gate electrode 60 and the FP electrode 70 extend is defined as the "Y direction" (second direction), and the direction orthogonal to the Z and Y directions is defined as the "X direction" (first direction). The Z direction is also referred to as "up," and its opposite direction as "down," but this is for convenience and is independent of the direction of gravity.

[0037] In the drain electrode 10, a silver layer 11, a nickel layer 12, and a titanium layer 13 are stacked sequentially from bottom to top. The silver layer 11 contains silver (Ag). The nickel layer 12 contains nickel (Ni). The titanium layer 13 contains titanium (Ti). However, the structure of the drain electrode 10 is not limited to this.

[0038] The silicon portion 20 is disposed on the drain electrode 10 and is connected to the titanium layer 13 of the drain electrode 10. The silicon portion 20 is made of single-crystal silicon (Si) and has an n-type conductivity (first conductivity type). A source trench 21 (first trench) and a gate trench 22 (second trench) extending along the Y direction are formed on the upper surface of the silicon portion 20. In the X direction, the source trench 21 and the gate trench 22 are alternately arranged separately from each other. The gate trench 22 is deeper than the source trench 21.

[0039] In the silicon portion 20, a drain layer 23 (first layer), a drift layer 24 (second layer), and a source layer 25 (third layer) are sequentially stacked. The conductivity type of the drain layer 23 is n. + The silicon portion 20 is connected to the titanium layer 13 of the drain electrode 10. Thus, the silicon portion 20 is connected to the drain electrode 10. Furthermore, in this specification, "connection" refers to electrical connection.

[0040] Drift layer 24 is disposed on drain layer 23, and its conductivity type is n. - The impurity concentration of the drift layer 24 is lower than that of the drain layer 23. The source layer 25 is disposed on the drift layer 24, and its conductivity type is n. + In this case, the impurity concentration of the source layer 25 is higher than that of the drift layer 24.

[0041] The source trench 21 extends through the source layer 25, and its lower end is located within the drift layer 24. The gate trench 22 also extends through the source layer 25, and its lower end is located within the drift layer 24. Therefore, the upper portion of the drift layer 24 and the source layer 25 are disposed between the source trench 21 and the gate trench 22. Hereinafter, the portion of the drift layer 24 located between the source trench 21 and the gate trench 22 will be referred to as the "upper portion 24a" (first portion), and the remaining portion will be referred to as the "lower portion 24b". The upper portion 24a of the drift layer 24 and the source layer 25 are strips extending along the Y direction.

[0042] An insulating component 50 is disposed within the gate trench 22. The insulating component 50 is made of an insulating material, such as silicon oxide (SiO2). The insulating component 50 is integrally contacted with the inner surface of the gate trench 22.

[0043] The gate electrode 60 is disposed within the insulating component 50. The gate electrode 60 is cylindrical in shape, extending along the Y direction. The gate electrode 60 is composed of p-type electrodes. + It is made of polysilicon. The gate electrode 60 is opposite to the upper part 24a of the drift layer 24 through a portion of the insulating member 50.

[0044] The FP electrode 70 is disposed below the gate electrode 60 within the insulating member 50. The FP electrode 70 is a strip-shaped electrode extending along the Y direction. The FP electrode 70 is separated from the gate electrode 60 and faces the lower portion 24b of the drift layer 24 across a portion of the insulating member 50. The FP electrode 70 is made of p-type... + It is composed of polycrystalline silicon. The FP electrode 70 is connected to the source electrode 40.

[0045] The titanium oxide film 30 is disposed on the entire inner surface of the source trench 21, namely on the side surface 21a and the bottom surface 21b. Additionally, the titanium oxide film 30 is also disposed on the insulating component 50 and the silicon portion 20. The titanium oxide film 30 is in contact with the upper portion 24a and the lower portion 24b of the drift layer 24, the source layer 25, and the insulating component 50.

[0046] Titanium oxide film 30 is a conductive metal oxide film. The composition of the titanium oxide film can be TiO2. x The value of x is, for example, 0.5 to 2.5, or 1.8 to 2.2. The resistivity of the titanium oxide film 30 is, for example, about 0.1 Ω·cm. The thickness of the titanium oxide film 30 is preferably 20 nm or less. Alternatively, a conductive metal oxide film of other compositions may be used instead of the titanium oxide film. In this case, the resistivity of the conductive metal oxide film is preferably 1 kΩ·cm or less. The conductive metal oxide film preferably contains, for example, titanium oxide (TiO₂). x It is one or more metal oxides in the group consisting of zinc oxide (ZnO), magnesium oxide (MgO), and aluminum oxide (Al2O3).

[0047] In the source electrode 40, a platinum layer 41 (first metal layer), a tungsten layer 42, and an aluminum layer 43 are sequentially stacked. The platinum layer 41 contains platinum (Pt) and is disposed on the titanium oxide film 30. The platinum layer 41 is in contact with the titanium oxide film 30 and is disposed across the titanium oxide film 30 on the entire inner surface of the source trench 21, the upper surface of the silicon portion 20, and the upper surface of the insulating component 50. The work function of the platinum layer 41 is approximately 5.7 eV. Alternatively, a layer composed of other metals, metal nitrides, or metal oxides may be provided instead of the platinum layer 41, but its work function is preferably 4.7 eV or higher. Other metals include, for example, iridium, nickel, cobalt, or tungsten. Metal nitrides include, for example, vanadium nitride, molybdenum nitride, and titanium nitride.

[0048] A tungsten layer 42, comprising tungsten (W), is disposed on a platinum layer 41. The tungsten layer 42 is adjacent to the platinum layer 41 and is disposed within the source trench 21, on the silicon portion 20, and on the insulating component 50. The work function of the tungsten layer 42 is approximately 4.7 eV, which is lower than that of the platinum layer 41. An aluminum layer 43, comprising aluminum (Al), is disposed on the tungsten layer 42. The aluminum layer 43 is adjacent to the tungsten layer 42.

[0049] With this structure, the interior of the source trench 21 is filled with a portion of the titanium oxide film 30, a portion of the platinum layer 41, and a portion of the tungsten layer 42. On the silicon portion 20 and the insulating component 50, another portion of the titanium oxide film 30, another portion of the platinum layer 41, another portion of the tungsten layer 42, and an aluminum layer 43 are sequentially stacked.

[0050] On the upper surface of the silicon portion 20, the titanium oxide film 30 is ohmically connected to the source layer 25 of the silicon portion 20. The source layer 25 is connected to the upper portion 24a of the drift layer 24. Thus, the source electrode 40, the gate electrode 60, the insulating component 50, and the upper portion 24a of the drift layer 24 constitute a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

[0051] Furthermore, the titanium oxide film 30 is Schottky bonded to the drift layer 24 on the side surface 21a and bottom surface 21b of the source trench 21. Thus, a Schottky barrier diode is formed with the source electrode 40 as the anode and the drift layer 24 as the cathode.

[0052] Next, the manufacturing method of the semiconductor device 1 of this embodiment will be described.

[0053] Figures 3-7 This is a process cross-sectional view showing the manufacturing method of the semiconductor device according to this embodiment.

[0054] First, such as Figure 3 As shown, a 20W silicon wafer is prepared. The lower part (not shown) of the 20W silicon wafer has an n-type conductivity. + Type, the conductivity type of the upper part is n. - Next, impurities that serve as donors are implanted into the upper layer of the silicon wafer 20w. This forms the source layer 25. Next, a plurality of gate trenches 22 are formed on the upper surface of the silicon wafer 20w. Each gate trench 22 extends along the Y direction, and the plurality of gate trenches 22 are arranged separately from each other in the X direction. Next, insulating components 50, FP electrodes 70, and gate electrodes 60 are formed within the gate trenches 22. Next, source trenches 21 are formed on the upper surface of the silicon wafer 20w between adjacent gate trenches 22. The source trenches 21 are isolated from the gate trenches 22 and are formed in a manner extending in the Y direction.

[0055] Next, as Figure 4 As shown, for example, titanium oxide is deposited on the entire surface using the ALD (Atomic Layer Deposition) method. As a result, a titanium oxide film 30 is formed in layers on the upper surface of the silicon wafer 20w, the upper surface of the insulating component 50, and the inner surface of the source trench 21.

[0056] Next, as Figure 5 As shown, platinum is deposited over the entire surface, for example, using the ALD method. This forms a layered platinum layer 41 on the titanium oxide film 30. As a result, a double-layer film consisting of the titanium oxide film 30 and the platinum layer 41 covers the entire upper surface of the silicon wafer 20w, the upper surface of the insulating component 50, and the inner surface of the source trench 21. At this point, the titanium oxide film 30 and the platinum layer 41 are not completely embedded within the source trench 21, leaving a residual space inside the source trench 21.

[0057] Next, as Figure 6 As shown, tungsten is deposited over the entire surface, for example, using CVD (Chemical Vapor Deposition). The amount of tungsten deposited is set to the total amount embedded within the interior of the source trench 21. Thus, a tungsten layer 42 is formed on the platinum layer 41. The interior of the source trench 21 is partially filled by the tungsten layer 42, separated by the titanium oxide film 30 and the platinum layer 41.

[0058] Next, as Figure 7 As shown, for example, aluminum is deposited over the entire surface by sputtering. This forms an aluminum layer 43 on the tungsten layer 42. As described above, the interior of the source trench 21 is already filled with the titanium oxide film 30, the platinum layer 41, and a portion of the tungsten layer 42, so the aluminum layer 43 is not disposed within the source trench 21. The source electrode 40 is formed by the platinum layer 41, the tungsten layer 42, and the aluminum layer 43.

[0059] Next, as Figure 2 As shown, the lower surface of the silicon wafer 20w is thinned by grinding. Next, a titanium layer 13, a nickel layer 12, and a silver layer 11 are sequentially formed on the lower surface of the silicon wafer 20w. This forms the drain electrode 10. Then, the silicon wafer 20w is diced, monolithically dividing it into multiple silicon portions 20. At this point, the lowermost part of the silicon wafer 20w becomes the drain layer 23, the uppermost part becomes the source layer 25, and the portion between the drain layer 23 and the source layer 25 becomes the drift layer 24. In this way, the semiconductor device 1 is manufactured.

[0060] Next, the operation of the semiconductor device 1 in this embodiment will be explained.

[0061] A higher potential than that of the source electrode 40 is applied to the drain electrode 10. At this time, the potential of the FP electrode 70 is equal to that of the source electrode 40. In this state, if the same potential as that of the source electrode 40 is applied to the gate electrode 60, the depletion layer extends from the interface between the titanium oxide film 30 and the drift layer 24 and the interface between the insulating member 50 and the drift layer 24, and the upper part 24a of the drift layer 24 is completely depleted. As a result, the semiconductor device 1 is in a cutoff state.

[0062] When a potential higher than the threshold Vth is applied to the gate electrode 60, an accumulation layer is formed in the portion of the upper part 24a of the drift layer 24 that is in contact with the insulating member 50, and current flows. As a result, current flows through the path of the drain electrode 10, the drain layer 23 of the silicon portion 20, the lower part 24b of the drift layer 24, the accumulation layer of the upper part 24a of the drift layer 24, the source layer 25, and the source electrode 40, and the semiconductor device 1 becomes conductive.

[0063] When the semiconductor device 1 is switched from the on state to the off state, electrons present in the drift layer 24 are discharged to the drain electrode 10 through the drain layer 23. In addition, when an avalanche breakdown occurs, the generated electrons are discharged to the drain electrode 10 through the drain layer 23, and the generated holes are discharged to the source electrode 40 through the side surface 21a and bottom surface 21b of the source trench 21.

[0064] When a higher potential than that of the drain electrode 10 is applied to the source electrode 40, current flows through the Schottky barrier diode formed on the bottom surface 21b of the source trench 21, via the path of the source electrode 40, the titanium oxide film 30, the lower part 24b of the drift layer 24, the drain layer 23, and the drain electrode 10. Thus, for example, a return current can flow.

[0065] Next, the effects of this embodiment will be explained.

[0066] In this embodiment, the conductivity type of the upper part 24a of the drift layer 24 is set to n. - In this design, a depletion layer is formed on the upper part 24a by the source electrode 40 and the gate electrode 60, thereby setting the MOSFET of the semiconductor device 1 to normally off. Furthermore, the conduction of the MOSFET is controlled by controlling the potential of the gate electrode 60. Therefore, there is no pn junction in the silicon portion 20, and no hole injection occurs during reverse recovery operation, thus reducing reverse recovery charge.

[0067] Furthermore, in this embodiment, a platinum layer 41 is provided on the side 21a of the source trench 21. Since platinum has a higher work function than tungsten, the platinum layer 41 can be used as a high work function component, increasing the barrier height between the platinum layer 41 and the drift layer 24. Increasing the barrier height enhances the depletion effect of the drift layer 24, thereby increasing the MOSFET threshold. However, if the platinum layer 41 is in direct contact with the drift layer 24, the barrier height between them becomes lower than the value expected based on the work function of platinum due to Fermi-level pinning.

[0068] Therefore, in this embodiment, a titanium oxide film 30 is positioned between the platinum layer 41 and the drift layer 24. The presence of the titanium oxide film 30 mitigates the Fermi-level pinning of the platinum layer 41, adjusting the barrier height between the platinum layer 41 and the drift layer 24 to a value corresponding to the work function of platinum. This allows the MOSFET threshold to be adjusted to the desired value.

[0069] Furthermore, since the titanium oxide film 30 is conductive, the resistance of the Schottky barrier diode can be reduced. Thus, according to this embodiment, the resistance of the Schottky barrier diode can be maintained at a low level, and the threshold of the MOSFET can be adjusted to a predetermined value.

[0070] Furthermore, by placing the titanium oxide film 30 between the platinum layer 41 and the silicon portion 20, crystal defects in the silicon portion 20 caused by thermal stress between the platinum layer 41 and the silicon portion 20 can be suppressed. Additionally, it can prevent platinum atoms contained in the platinum layer 41 from being trapped by crystal defects originally present in the silicon portion 20. Thus, leakage current between the drain and source can be suppressed. Furthermore, by placing the titanium oxide film 30 between the platinum layer 41 and the insulating member 50, the adhesion between the platinum layer 41 and the insulating member 50 can be improved.

[0071] Furthermore, in this embodiment, an FP electrode 70 is disposed within the insulating member 50 and below the gate electrode 60. As a result, it is difficult to apply an electric field to the upper portion 24a of the drift layer 24, and the upper portion 24a is prone to depletion. Consequently, the threshold voltage of the MOSFET is increased.

[0072] <Comparative Example>

[0073] Figure 8 This is a cross-sectional view of a semiconductor device representing a comparative example.

[0074] like Figure 8 As shown, the semiconductor device 101 of this comparative example differs from the semiconductor device 1 of the first embodiment in that it does not have a titanium oxide film 30.

[0075] In semiconductor device 101, since there is no titanium oxide film 30, the platinum layer 41 of the source electrode 40 is in contact with the silicon portion 20 and the insulating component 50. Consequently, the barrier height between the platinum layer 41 and the drift layer 24 becomes lower than the value assumed based on the work function of platinum due to the effect of Fermi-level pinning. As a result, the effect of extending the depletion layer is weakened, and the threshold of the MOSFET becomes lower.

[0076] Alternatively, Fermi-level pinning can be mitigated by providing an insulating film, such as a silicon oxide film or a silicon nitride film, between the platinum layer 41 and the silicon portion 20. However, in this case, the resistance of the Schottky barrier diode becomes high on the bottom surface 21b of the source trench 21.

[0077] Furthermore, due to thermal stress between the platinum layer 41 and the silicon portion 20, crystal defects are easily generated in the silicon portion 20. Consequently, platinum atoms contained in the platinum layer 41 are easily captured by the crystal defects in the silicon portion 20, increasing the leakage current between the drain and source. Furthermore, due to the poor adhesion between the platinum layer 41 and the insulating component 50, the platinum layer 41 is easily peeled off from the insulating component 50.

[0078] <Second Implementation Method>

[0079] Figure 9 This is a cross-sectional view showing the semiconductor device of this embodiment.

[0080] like Figure 9 As shown, the semiconductor device 2 of this embodiment differs from the semiconductor device 1 of the first embodiment in that the titanium oxide film 30 is not disposed on the bottom surface 21b of the source trench 21, the insulating component 50, or the silicon portion 20.

[0081] Therefore, on the bottom surface 21b of the source trench 21, the platinum layer 41 of the source electrode 40 is in contact with the lower part 24b of the drift layer 24. In addition, the platinum layer 41 is also in contact with the source layer 25 and the insulating component 50.

[0082] Next, the manufacturing method of the semiconductor device 2 in this embodiment will be described.

[0083] Figure 10 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to this embodiment.

[0084] First, implementation Figure 3 and Figure 4 The process shown.

[0085] Next, as Figure 10 As shown, for example, anisotropic etching such as RIE (Reactive Ion Etching) is performed to remove portions of the titanium oxide film 30 deposited on the bottom surface 21b of the source trench 21, the portion deposited on the silicon wafer 20w, and the portion deposited on the insulating component 50. At this time, a portion of the titanium oxide film 30 deposited on the side surface 21a of the source trench 21 remains.

[0086] The subsequent procedures are the same as in the first implementation method. That is, the implementation and Figures 5-7 The same process as shown, then, as Figure 9 As shown, the lower surface of the silicon wafer 20w is ground to thin it, forming the drain electrode 10, and the silicon wafer 20w is cut to monolithize it. In this way, the semiconductor device 2 of this embodiment is manufactured.

[0087] In this embodiment, since a titanium oxide film 30 is sandwiched between the upper part 24a of the drift layer 24 and the platinum layer 41, the Fermi-level pinning effect on the platinum layer 41 can be mitigated, and the MOSFET threshold can be adjusted to the desired value. On the other hand, since there is no titanium oxide film 30 between the platinum layer 41 and the source layer 25, the Fermi-level pinning effect is not mitigated, the barrier height is lower, and the platinum layer 41 and the source layer 25 can easily form an ohmic connection. As a result, the on-resistance of the MOSFET can be reduced.

[0088] Furthermore, since there is no titanium oxide film 30 sandwiched between the lower part 24b of the drift layer 24 and the platinum layer 41, the effect of mitigating Fermi-level pinning cannot be obtained, and the barrier height between the platinum layer 41 and the lower part 24b of the drift layer 24 becomes lower. However, since the lower part 24b of the drift layer 24 is a part that constitutes a Schottky barrier diode rather than a MOSFET, it does not affect the threshold voltage of the MOSFET, and the forward voltage (Vf) of the Schottky barrier diode is reduced. As a result, the conduction loss of the Schottky barrier diode can be reduced. The structure, manufacturing method, operation, and effects other than those described above in this embodiment are the same as in the first embodiment.

[0089] <Third Implementation Method>

[0090] Figure 11 This is a cross-sectional view showing the semiconductor device of this embodiment.

[0091] like Figure 11 As shown, the semiconductor device 3 of this embodiment differs from the semiconductor device 1 of the first embodiment in that: the titanium oxide film 30 is not disposed on the insulating component 50 and the silicon portion 20, and a titanium layer 44 (second metal layer) and a titanium nitride layer 45 are disposed on the source electrode 40.

[0092] The titanium layer 44 comprises titanium and is disposed on the portion of the source electrode 40 disposed within the source trench 21, on the silicon portion 20, and on the insulating component 50. The titanium layer 44 is in contact with the tungsten layer 42, the platinum layer 41, the titanium oxide film 30, the source layer 25, and the insulating component 50. The titanium nitride layer 45 comprises titanium nitride (TiN) and is disposed on the titanium layer 44. The titanium layer 44 and the titanium nitride layer 45 are generally planar and parallel to the XY plane. A tungsten layer 42 is disposed on the titanium nitride layer 45, and an aluminum layer 43 is disposed thereon.

[0093] Next, the manufacturing method of the semiconductor device 3 of this embodiment will be described.

[0094] Figures 12-14 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to this embodiment.

[0095] First, implementation Figures 3-6 The process shown.

[0096] Next, as Figure 12 As shown, planarization processes such as RIE (etching) or CMP (Chemical Mechanical Polishing) are performed to remove portions of the tungsten layer 42, platinum layer 41, and titanium oxide film 30 deposited on the silicon portion 20 and the insulating component 50. This exposes the upper surfaces of the silicon portion 20 and the insulating component 50. Additionally, the titanium oxide film 30, platinum layer 41, and tungsten layer 42 remain within the source trench 21.

[0097] Next, as Figure 13 As shown, titanium layer 44 is formed, for example, by sputtering. Then, titanium nitride is deposited, for example, by sputtering, to form titanium nitride layer 45.

[0098] Next, as Figure 14 As shown, tungsten is deposited, for example, by CVD, thereby forming a tungsten layer 42 on the titanium nitride layer 45. Thus, the tungsten layer 42 is formed separately on top of the titanium layer 44 and the titanium nitride layer 45. That is, in Figure 6 Deposited in the process shown and in Figure 12 In the process shown, a portion of the tungsten layer 42 that is removed is disposed below the titanium layer 44 and the titanium nitride layer 45. Figure 14 In the process shown, the tungsten layer 42 deposited is disposed above the titanium layer 44 and the titanium nitride layer 45.

[0099] The subsequent procedures are the same as in the first embodiment. That is, as follows: Figure 7 As shown, aluminum layer 43 is formed, such as Figure 11 The lower surface of the silicon wafer 20w is ground to thin it, forming a drain electrode 10, and the silicon wafer 20w is cut to monolithize it. In this way, the semiconductor device 3 of this embodiment is manufactured.

[0100] In this embodiment, n + The source layer 25, made of silicon, is connected to the titanium layer 44. Since the work function of titanium (e.g., about 4.3 eV) is lower than that of platinum (e.g., about 5.7 eV), the source electrode 40 and the source layer 25 can easily form an ohmic connection. This reduces the on-resistance of the MOSFET. On the other hand, due to the n... - The upper portion 24a of the silicon-based drift layer 24 is positioned opposite the platinum layer 41, separated by a titanium oxide film 30. Platinum has a higher work function than tungsten, thus increasing the MOSFET threshold. The structure, manufacturing method, operation, and effects in this embodiment, other than those described above, are the same as in the first embodiment.

[0101] <Fourth Implementation Method>

[0102] Figure 15This is a cross-sectional view showing the semiconductor device of this embodiment.

[0103] like Figure 15 As shown, the semiconductor device 4 of this embodiment differs from the semiconductor device 3 of the third embodiment in that a titanium oxide film 30 is provided on the silicon portion 20 and the insulating member 50. In the semiconductor device 4, the titanium layer 44 is separated from the silicon portion 20 and the insulating member 50 through the titanium oxide film 30. Furthermore, in the titanium oxide film 30, the portion disposed on the silicon portion 20 and opposite the source layer 25 is in contact with the titanium layer 44, and the portion disposed in the source trench 21 and opposite the drift layer 24 is in contact with the platinum layer 41.

[0104] Next, the manufacturing method of the semiconductor device 4 in this embodiment will be described.

[0105] Figure 16 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to this embodiment.

[0106] First, implementation Figures 3-6 The process shown.

[0107] Next, as Figure 16 As shown, for example, RIE or CMP is performed to remove portions of the tungsten layer 42 and platinum layer 41 deposited on the silicon portion 20 and the insulating component 50. At this time, the titanium oxide film 30 remains on the silicon portion 20 and the insulating component 50. Thus, the titanium oxide film 30 is exposed on the silicon portion 20 and the insulating component 50. In addition, the titanium oxide film 30, platinum layer 41 and tungsten layer 42 remain in the source trench 21.

[0108] The subsequent procedures are the same as in the third embodiment. That is, as follows: Figure 13 As shown, a titanium layer 44 and a titanium nitride layer 45 are formed, as follows: Figure 14 As shown, a tungsten layer 42 is formed, as Figure 15 As shown, an aluminum layer 43 is formed, the lower surface of the silicon wafer 20w is ground to thin it, a drain electrode 10 is formed, and the silicon wafer 20w is cut to monolithize it. In this way, the semiconductor device 4 of this embodiment is manufactured.

[0109] In this embodiment, although the source layer 25 is in contact with the titanium oxide film 30, a titanium layer 44 and a titanium nitride layer 45 are present on the titanium oxide film 30. In the case of titanium, the barrier height is higher than the original work function matching due to Fermi-level pinning, but if the Fermi-level pinning is mitigated by the titanium oxide film 30, it becomes the barrier height with the original low work function matching of titanium. Therefore, the source electrode 40 and the source layer 25 can easily form an ohmic connection. As a result, the on-resistance of the MOSFET is reduced. The structure, manufacturing method, operation, and effects other than those described above in this embodiment are the same as in the third embodiment.

[0110] <Fifth Implementation Method>

[0111] Figure 17 This is a cross-sectional view showing the semiconductor device of this embodiment.

[0112] like Figure 17 As shown, the semiconductor device 5 of this embodiment differs from the semiconductor device 3 of the third embodiment in that a platinum layer 41 is not provided on the source electrode 40. In the semiconductor device 5, the titanium oxide film 30 is in contact with the tungsten layer 42. In the semiconductor device 5, the titanium oxide film 30 can also be thicker than that of the semiconductor device 3. The manufacturing method of the semiconductor device 5 differs from that of the semiconductor device 3 of the third embodiment in that, without implementing... Figure 5 The process of forming the platinum layer 41 shown is different in this respect.

[0113] In this embodiment, a titanium oxide film 30 is used instead of a platinum layer 41 as a high work function component. The work function of titanium oxide is, for example, about 5.1 eV, which is higher than that of platinum. Since Fermi-level pinning is difficult to produce in the titanium oxide film 30, the same effect as in the third embodiment can be obtained. The structure, manufacturing method, operation, and effects in this embodiment other than those described above are the same as in the third embodiment.

[0114] <Sixth Implementation Method>

[0115] Figure 18 This is a cross-sectional view showing the semiconductor device of this embodiment.

[0116] Figure 19 It means Figure 18 A magnified sectional view of region C.

[0117] like Figure 18 and Figure 19 As shown, the semiconductor device 6 of this embodiment differs from the semiconductor device 3 of the third embodiment in that a source layer 25 is not disposed above the upper portion 24a arranged in the X direction at every other row in the drift layer 24. The upper surface of the upper portion 24a without the source layer 25 is in contact with the lower surface of the titanium layer 44 of the source electrode 40, and a Schottky junction is formed. That is, the contact surface 81 between the upper portion 24a of the drift layer 24 and the titanium layer 44 is a Schottky junction surface.

[0118] According to this embodiment, such as Figure 18 and Figure 19As shown in path H, during avalanche breakdown, the generated holes are discharged from the upper part 24a of the drift layer 24 to the source electrode 40 via the contact surface 81. Since the titanium oxide film 30, which has a higher resistivity than the source electrode 40, and the source layer 25, which has a higher impurity concentration than the drift layer 24, are not located in path H, the holes are easily discharged. As a result, the holes generated during breakdown are discharged more rapidly, and variations in the characteristics of the semiconductor device 6 can be suppressed. The structure, manufacturing method, operation, and effects other than those described above in this embodiment are the same as in the third embodiment.

[0119] <Seventh Implementation Method>

[0120] Figure 20 This is a cross-sectional view showing the semiconductor device of this embodiment.

[0121] Figure 21 yes Figure 20 The cross-sectional view of line D-D' shown.

[0122] like Figure 20 and Figure 21 As shown, the semiconductor device 7 of this embodiment differs from the semiconductor device 3 of the third embodiment in that the source layer 25 is discontinuously arranged along the Y direction. In the portion of the upper portion 24a of the drift layer 24 where the source layer 25 is not disposed, the upper surface of the upper portion 24a is in contact with the lower surface of the titanium layer 44, forming a Schottky bond. Viewed from the Z direction, the contact surfaces 81 between the upper portion 24a of the drift layer 24 and the titanium layer 44 are arranged in a matrix.

[0123] In this embodiment, similar to the sixth embodiment, when avalanche breakdown occurs, the generated holes are discharged directly from the upper part 24a of the drift layer 24 to the source electrode 40 via the contact surface 81, without passing through the titanium oxide film 30 and the source layer 25. This suppresses changes in the characteristics of the semiconductor device 7 during breakdown. The structure, manufacturing method, operation, and effects in this embodiment other than those described above are the same as in the third embodiment. Furthermore, when viewed from the Z direction, the contact surfaces 81 can also be arranged in an alternating pattern.

[0124] <Eighth Implementation Method>

[0125] Figure 22 This is a cross-sectional view showing the semiconductor device of this embodiment.

[0126] Figure 23 It means Figure 22 A partially enlarged sectional view of region E.

[0127] like Figure 22 and Figure 23As shown, the semiconductor device 8 of this embodiment differs from the semiconductor device 3 of the third embodiment in that the portions of the titanium oxide film 30, platinum layer 41, and tungsten layer 42 disposed below the titanium layer 44 and titanium nitride layer 45 are only disposed at the lower part of the source trench 21. A portion of the titanium layer 44, a portion of the titanium nitride layer 45, and a portion of the tungsten layer 42 disposed above the titanium layer 44 and titanium nitride layer 45 are disposed at the upper part of the source trench 21.

[0128] Thus, on a portion of the side surface 21a of the source trench 21, the titanium layer 44 and the upper portion 24a of the drift layer 24 form a contact surface 82. Contact surface 82 is a Schottky junction. Contact surface 82 is located below the contact surface 83 between the titanium layer 44 and the source layer 25, and above the contact surface 84 between the titanium oxide film 30 and the upper portion 24a. Contact surface 83 is an ohmic junction, and junction surface 84 is a Schottky junction.

[0129] Next, the manufacturing method of the semiconductor device 8 of this embodiment will be described.

[0130] First, implementation Figures 3-6 The process shown.

[0131] Next, implementation Figure 12 The process shown.

[0132] Next, the titanium oxide film 30, platinum layer 41, and tungsten layer 42 are etched and removed from the upper part of the source trench 21. At this time, the titanium oxide film 30, platinum layer 41, and tungsten layer 42 remain in the lower part of the source trench 21.

[0133] The subsequent procedures are the same as in the third embodiment. That is, as follows: Figure 13 As shown, a titanium layer 44 and a titanium nitride layer 45 are formed, as Figure 7 As shown, aluminum layer 43 is formed, such as Figure 11 The lower surface of the silicon wafer 20w is ground to thin it, forming a drain electrode 10, and the silicon wafer 20w is cut to monolithize it. In this way, the semiconductor device 8 of this embodiment is manufactured.

[0134] In this embodiment, similar to the sixth embodiment, when an avalanche breakdown occurs, the resulting holes are discharged to the source electrode 40 via the contact surface 82 between the upper part 24a of the drift layer 24 and the titanium layer 44. This suppresses variations in the characteristics of the semiconductor device 8. The structure, manufacturing method, operation, and effects in this embodiment other than those described above are the same as in the third embodiment.

[0135] According to the embodiments described above, a semiconductor device can be realized that maintains a low resistance in the diode section and makes the threshold value of the transistor section a predetermined value.

[0136] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope of the claims and their equivalents. Furthermore, the foregoing embodiments can also be combined with each other.

[0137] The present invention includes the following methods.

[0138] (Postscript 1)

[0139] A semiconductor device comprising:

[0140] First electrode;

[0141] The semiconductor portion is disposed on the first electrode and is of the first conductivity type. A first trench and a second trench are formed on the upper surface in a mutually isolated manner.

[0142] A conductive metal oxide film is disposed at least on the side of the first trench and is in contact with the semiconductor portion;

[0143] The second electrode is disposed in the first trench and on the semiconductor portion, is in contact with the conductive metal oxide film, and contains metal;

[0144] An insulating component is disposed within the second trench; and

[0145] The third electrode is disposed within the insulating component.

[0146] (Postscript 2)

[0147] According to the semiconductor device described in Appendix 1, the resistivity of the conductive metal oxide film is less than 1 kΩ·cm.

[0148] (Note 3)

[0149] According to the semiconductor device described in Appendix 1 or 2, the conductive metal oxide film comprises one or more metal oxides selected from the group consisting of titanium oxide, zinc oxide, magnesium oxide and aluminum oxide.

[0150] (Postscript 4)

[0151] According to the semiconductor device described in Appendix 3, the conductive metal oxide film comprises titanium oxide.

[0152] (Note 5)

[0153] The semiconductor device according to any one of Appendices 1 to 4, wherein the thickness of the conductive metal oxide film is less than 20 nm.

[0154] (Note 6)

[0155] The semiconductor device according to any one of Appendices 1 to 5, wherein the work function of at least the portion of the second electrode in contact with the conductive metal oxide film is 4.7 eV or higher.

[0156] (Note 7)

[0157] The semiconductor device according to any one of Appendices 1 to 6, wherein at least the portion of the second electrode in contact with the conductive metal oxide film comprises one or more materials selected from the group consisting of platinum, iridium, nickel, cobalt, tungsten, vanadium nitride, molybdenum nitride and titanium nitride.

[0158] (Postscript 8)

[0159] According to any one of Appendices 1 to 7, in the semiconductor device, the conductive metal oxide film is also disposed on the bottom surface of the first trench, and on the bottom surface of the first trench, the conductive metal oxide film is in contact with the semiconductor portion.

[0160] (Note 9)

[0161] The semiconductor device according to any one of Appendices 1 to 7, wherein the conductive metal oxide film is not disposed on the bottom surface of the first trench, and the second electrode is connected to the semiconductor portion on the bottom surface of the first trench.

[0162] (Postscript 10)

[0163] In any one of Appendices 1 to 9, the semiconductor device wherein the conductive metal oxide film is also disposed on the upper surface of the semiconductor portion and the upper surface of the insulating component.

[0164] (Postscript 11)

[0165] The semiconductor device according to any one of Appendices 1 to 10, wherein the second electrode has:

[0166] A first metal layer is disposed within the first trench and is in contact with the conductive metal oxide film; and

[0167] A second metal layer is disposed on the semiconductor portion and is in contact with the conductive metal oxide film.

[0168] The work function of the first metal layer is higher than that of the second metal layer.

[0169] (Postscript 12)

[0170] The semiconductor device according to any one of Appendices 1 to 11, wherein,

[0171] The semiconductor portion has:

[0172] The first layer is connected to the first electrode;

[0173] The second layer is disposed on top of the first layer, and its impurity concentration is lower than that of the first layer; and

[0174] The third layer, disposed on top of the second layer and connected to the second electrode, has a higher impurity concentration than the second layer.

[0175] In the second layer, a portion of the first portion between the first trench and the second trench is connected to the second electrode.

[0176] (Postscript 13)

[0177] According to the semiconductor device described in Note 12, the upper surface of the first portion, which is arranged at intervals along a first direction in which the first trench and the second trench are arranged, is in contact with the second electrode.

[0178] (Postscript 14)

[0179] According to the semiconductor device described in Note 12, the contact surfaces of the first portion and the second electrode are discontinuously arranged along a second direction extending from the first trench and the second trench.

[0180] (Postscript 15)

[0181] According to the semiconductor device described in Note 12, the contact surface between the first portion and the second electrode is a portion of the side surface of the first trench.

[0182] (Postscript 16)

[0183] The semiconductor device according to any one of Appendices 1 to 15, wherein a portion of the first portion of the semiconductor portion disposed between the first trench and the second trench is Schottky-junctioned with the second electrode.

[0184] [Explanation of reference numerals in the attached figures]

[0185] 1, 2, 3, 4, 5, 6, 7, 8 Semiconductor device 10 Drain electrode (first electrode)

[0186] 11 Silver layer

[0187] 12 nickel layers

[0188] 13 Titanium layers

[0189] 20. Silicon Section (Semiconductor Section)

[0190] 20W silicon wafer, 21 source trenches (first trench)

[0191] 21a Side view

[0192] 21b Bottom surface

[0193] 22 Gate trench (second trench)

[0194] 23 Drain layer (first layer)

[0195] 24. Drift Layer (Second Layer)

[0196] 24a Upper part (Part 1)

[0197] 24b lower part

[0198] 25. Source Layer (Third Layer)

[0199] 30 Titanium oxide film (conductive metal oxide film)

[0200] 40 Source electrode (second electrode)

[0201] 41 Platinum layer (first metal layer)

[0202] 42 Tungsten layer

[0203] 43 aluminum layers

[0204] 44 Titanium layer (second metal layer)

[0205] 45 Titanium nitride layer

[0206] 50 Insulating component 60 Gate electrode (third electrode)

[0207] 70 Field Plate Electrode (FP Electrode)

[0208] Contact surfaces 81, 82, 83, and 84

[0209] 101 The path of holes in semiconductor device H.

Claims

1. A semiconductor device comprising: First electrode; The semiconductor portion is disposed on the first electrode and is of the first conductivity type. A first trench and a second trench are formed on the upper surface in a mutually isolated manner. A conductive metal oxide film is disposed at least on the side of the first trench and is in contact with the semiconductor portion; The second electrode is disposed in the first trench and on the semiconductor portion, is in contact with the conductive metal oxide film, and contains metal; An insulating component is disposed within the second trench; and The third electrode is disposed within the insulating component.

2. The semiconductor device according to claim 1, wherein, The resistivity of the conductive metal oxide film is below 1 kΩ·cm.

3. The semiconductor device according to claim 1, wherein, The conductive metal oxide film comprises one or more metal oxides selected from the group consisting of titanium oxide, zinc oxide, magnesium oxide and aluminum oxide.

4. The semiconductor device according to claim 3, wherein, The conductive metal oxide film contains titanium oxide.

5. The semiconductor device according to claim 1, wherein, The thickness of the conductive metal oxide film is less than 20 nm.

6. The semiconductor device according to claim 1, wherein, The work function of at least the portion of the second electrode in contact with the conductive metal oxide film is 4.7 eV or higher.

7. The semiconductor device according to claim 1, wherein, The portion of the second electrode in contact with the conductive metal oxide film comprises one or more materials selected from the group consisting of platinum, iridium, nickel, cobalt, tungsten, vanadium nitride, molybdenum nitride, and titanium nitride.

8. The semiconductor device according to claim 1, wherein, The conductive metal oxide film is also disposed on the bottom surface of the first trench, and on the bottom surface of the first trench, the conductive metal oxide film is in contact with the semiconductor portion.

9. The semiconductor device according to claim 1, wherein, The conductive metal oxide film is not disposed on the bottom surface of the first trench, on which the second electrode is connected to the semiconductor portion.

10. The semiconductor device according to claim 1, wherein, The conductive metal oxide film is also disposed on the upper surface of the semiconductor portion and the upper surface of the insulating component.

11. The semiconductor device according to claim 1, wherein, The second electrode has: A first metal layer is disposed within the first trench and is in contact with the conductive metal oxide film; and A second metal layer is disposed on the semiconductor portion and is in contact with the conductive metal oxide film. The work function of the first metal layer is higher than that of the second metal layer.

12. The semiconductor device according to any one of claims 1 to 11, wherein, The semiconductor portion has: The first layer is connected to the first electrode; The second layer is disposed on top of the first layer, and the impurity concentration is lower than that of the first layer. and The third layer, disposed on top of the second layer and connected to the second electrode, has a higher impurity concentration than the second layer. In the second layer, a portion of the first portion between the first trench and the second trench is connected to the second electrode.

13. The semiconductor device according to claim 12, wherein, The upper surface of the first portion, which is arranged at every other groove along a first direction, is in contact with the second electrode.

14. The semiconductor device according to claim 12, wherein, The contact surfaces of the first portion and the second electrode are arranged discontinuously along a second direction extending from the first trench and the second trench.

15. The semiconductor device according to claim 12, wherein, The contact surface between the first portion and the second electrode is a portion of the side surface of the first trench.

16. The semiconductor device according to any one of claims 1 to 11, wherein, A portion of the first portion of the semiconductor section, configured between the first trench and the second trench, is Schottky-bonded to the second electrode.

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