SiC power mosfet device integrating jbs and self-clamp p-shield region and method of fabrication thereof

Abstract

This invention belongs to the field of power semiconductor device technology, and provides a SiC power MOSFET device integrating a JBS and a self-clamped P-Shield region, as well as its fabrication method, to solve the technical problem of existing SiC power MOSFETs struggling to balance reverse recovery capability and electrical performance. This invention introduces a self-clamping structure, including a deep trench self-clamping gate 9 and P-type sidewall injection regions 13 and N-type sidewall injection regions 14 disposed on its sidewalls. These three components together constitute a normally open P-channel MOSFET structure, enabling dynamic control of the P-type shield region potential, which reduces conduction losses and ensures device reliability. Simultaneously, this invention integrates a three-dimensional JBS structure within the MOSFET cell, providing a low-voltage-drop Schottky path for the reverse recovery current. In summary, this invention enhances reverse recovery capability while achieving dynamic control of the P-Shield region potential through the self-clamping structure, balancing low on-resistance and high gate oxide reliability, and solving the parasitic parameter problems caused by external discrete components.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, specifically relating to a device structure and fabrication method of a silicon carbide (SiC) power metal oxide semiconductor field-effect transistor (MOSFET) with enhanced reverse recovery capability. Background Technology

[0002] Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, possesses excellent characteristics such as a large bandgap, high critical breakdown electric field, and high thermal conductivity, enabling SiC power devices to achieve higher power density and operating temperature compared to traditional silicon-based devices. Among them, SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs) have been widely used in new energy vehicles, photovoltaic inverters, smart grids, and other fields due to their advantages such as high input impedance and low switching losses.

[0003] However, due to the inherent characteristics of SiC materials, SiC power MOSFETs still face a key technical bottleneck in practical applications: poor reverse recovery capability. When the device is in reverse conduction, current flows through its body diode. Since the forward voltage drop of the SiC body diode is as high as about 2.7V and there is a bipolar degradation effect, this not only increases the conduction loss of the device, but also seriously affects the switching characteristics and long-term reliability of the device.

[0004] To address the aforementioned issues, existing technologies typically employ an external anti-parallel Schottky barrier diode (SBD). This involves connecting a SiC SBD externally across the source and drain terminals of the SiC power MOSFET, utilizing its lower on-state voltage drop to guide the reverse recovery current, thereby avoiding body diode conduction. While this method improves reverse recovery capability to some extent, it suffers from the following drawbacks: First, the introduction of additional discrete components doubles the number of transistors in the inverter circuit, increasing circuit complexity and package size. Second, the external connection introduces additional parasitic capacitance and inductance, affecting high-frequency switching performance. Third, it increases system cost and power consumption.

[0005] In recent years, the academic community has proposed monolithic integration solutions, such as integrating a junction barrier Schottky diode (JBS) and a SiC MOSFET onto the same chip (JBSFET). By sharing the drift region and termination structure, reverse recovery capability is improved while chip area and parasitic parameters are reduced. However, such integrated structures still face many technical challenges in optimization: First, how to improve reverse conduction capability without sacrificing the device's forward conduction resistance and breakdown voltage; second, how to effectively protect the gate oxide layer from high electric field impacts in the off state to improve device reliability; third, the potential control method of the P-shield is relatively simple, making it difficult to simultaneously meet the requirements of low on-resistance in the on state and high withstand voltage in the off state.

[0006] Therefore, how to further enhance the reverse recovery capability of SiC MOSFETs while maintaining their excellent forward characteristics, and at the same time optimize the static and dynamic performance of the devices and improve gate oxide reliability, has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0007] This invention aims to solve the technical problem of existing SiC power MOSFETs in balancing reverse recovery capability and electrical performance. It provides a SiC power MOSFET device integrating JBS and self-clamped P-Shield region and its fabrication method. This enhances reverse recovery capability while achieving dynamic control of P-Shield region potential through self-clamping structure, balancing low on-resistance and high gate oxide reliability, and solving the parasitic parameter problem caused by external discrete components.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0009] A SiC MOSFET device integrating JBS and a self-clamping P-Shield region, characterized in that it comprises:

[0010] 2 N-type heavily doped substrate layer, 1 drain metal layer disposed under the N-type heavily doped substrate layer, and N-type drift region 3 and current spreading layer 4 disposed sequentially on the N-type heavily doped substrate layer.

[0011] The cell structure disposed on the current spreading layer 4 has a symmetrical structure, including: a P-type well region 5, an N+ source region 6, a P+ contact region 7, a shallow trench control gate 8, a deep trench self-clamping gate 9, a P-type shielding region 10, a source metal layer 11, an interlayer dielectric layer 12, a P-type sidewall injection region 13, and an N-type sidewall injection region 14.

[0012] P-type well region 5 is disposed on current extension layer 4. Two shallow trench control gates 8 and deep trench self-clamping gates 9 are disposed along the cell surface through P-type well region 5. Deep trench self-clamping gate 9 is located in the middle region of the cell, and two shallow trench control gates 8 are located on both sides of the cell.

[0013] N+ source region 6 and P+ contact region 7 are respectively set in the P-type trap region 5 on both sides of the deep trench self-clamping gate 9. The N+ source region 6 and P+ contact region 7 are arranged side by side in the transverse direction between the deep trench self-clamping gate 9 and the shallow trench control gate 8.

[0014] The source metal layer 11 covers the cell and forms an ohmic contact with the N+ source region and the P+ contact region, and an interlayer dielectric layer 12 is disposed between the source metal layer and the polysilicon gate.

[0015] The P-type shielding region 10 is disposed at the bottom of the deep trench self-clamping gate 9 and forms a surrounding structure. The two sidewalls of the deep trench self-clamping gate 9 are respectively provided with a P-type sidewall injection region 13 and an N-type sidewall injection region 14. The P-type sidewall injection region 13 and the N-type sidewall injection region 14 are arranged side by side in the transverse direction and are both disposed between the P-type well region 5 and the P-type shielding region 10. The self-clamping gate 9, the P-type sidewall injection region 13, and the N-type sidewall injection region 14 together constitute a normally open P-channel MOSFET structure.

[0016] Furthermore, the cell structure also embeds a junction barrier Schottky diode (JBS) structure in the Z-axis direction. The junction barrier Schottky diode (JBS) cell structure includes: a Schottky contact region 15, which is disposed between two deep trench self-clamping gates 9 arranged longitudinally (Z-axis direction). The Schottky contact region is electrically connected to the upper source metal layer and forms a Schottky contact with the lower current extension layer 4.

[0017] Furthermore, the metal material of the Schottky contact region 15 is titanium, and the barrier height is 0.8eV~1.2eV.

[0018] Furthermore, the doping concentration of the P-type sidewall implantation region 13 is 5 × 10⁻⁶. 16 cm -3 ~1×10 18 cm -3 The doping concentration of the N-type sidewall implantation region 14 is 1×10⁻⁶. 16 cm -3 ~8×10 17 cm -3 By adjusting the doping concentration and width of both, the threshold voltage of the normally open P-channel MOSFET is made to be between 0V and the device body threshold voltage.

[0019] Furthermore, the doping concentration of the N-type drift region 3 is 7 × 10⁻⁶. 15 cm -3~9×10 15 cm -3 The thickness is 9μm~11μm.

[0020] Furthermore, the peak doping concentration of the P-type shielding region 10 is 1×10⁻⁶. 18 cm -3 ~1×10 19 cm -3 .

[0021] Furthermore, the thickness of the gate oxide layer is 30nm~80nm.

[0022] Meanwhile, the present invention also provides a method for fabricating the above-mentioned SiC MOSFET device integrating JBS and self-clamping P-Shield region, characterized by comprising the following steps:

[0023] An N-type drift region and a current spreading layer are epitaxially grown sequentially on an N-type heavily doped substrate;

[0024] A P-type well region and a P+ contact region located in the middle region along the lateral direction, and an N+ source region located on both sides of the P+ contact region are formed in the current extension layer by ion implantation, and a Schottky contact region is reserved in the cell center region corresponding to the junction barrier Schottky diode (JBS) structure.

[0025] Deep trenches are formed longitudinally on both sides of the reserved Schottky contact area by etching. A P-type shielding area is formed at the bottom of the deep trench by ion implantation. Then, N-type impurities and P-type impurities are sequentially implanted on both sides of the deep trench by inclined sidewall implantation process to form N-type sidewall implantation area and P-type sidewall implantation area.

[0026] Shallow trenches are formed on both sides of the cell by etching, and impurities are injected after high-temperature annealing.

[0027] A gate oxide layer is formed simultaneously on the walls of both deep and shallow trenches by thermal growth, and polysilicon is deposited to fill the trenches; then an interlayer dielectric layer is deposited on the polysilicon.

[0028] Schottky metal is deposited in the reserved Schottky contact area to form a Schottky contact;

[0029] Finally, source and drain metal layers are deposited separately.

[0030] Furthermore, the inclined sidewall implantation process includes: first sidewall implantation: nitrogen ions are implanted at an inclined angle of 5 to 10 degrees to form an N-type sidewall implantation region; second sidewall implantation: aluminum ions are implanted at an inclined angle of 40 to 50 degrees to form a P-type sidewall implantation region; third sidewall implantation: aluminum ions are implanted again at an inclined angle of 8 to 15 degrees to compensate for the area in the P-type trap region affected by nitrogen ion implantation.

[0031] Furthermore, the Schottky metal is titanium, deposited by electron beam evaporation or sputtering processes.

[0032] Compared with the prior art, the present invention provides a SiC MOSFET device integrating JBS and self-clamping P-Shield region and its fabrication method, which has the following advantages:

[0033] 1) Significantly enhances reverse recovery capability and reduces reverse recovery charge;

[0034] This invention provides a low-voltage-drop Schottky path for reverse recovery current by three-dimensionally integrating a JBS structure within the MOSFET cell. Simulation results show that the reverse voltage drop is reduced to 1.48V, a 45.2% reduction compared to the typical 2.7V of a traditional SiC power MOSFET body diode. Furthermore, since the Schottky junction is a majority carrier device, there is no minority carrier storage effect, resulting in a high reverse recovery charge (Q... rr From the traditional device's 325nC / cm 2 Reduced to 6 nC / cm 2 The reduction reached 98.2%, which significantly suppressed the bipolar degradation effect, reduced switching losses, and improved the reliability of the device in high-frequency applications.

[0035] 2) Achieve self-clamping of the P-Shield region potential, balancing low on-resistance and high gate oxide reliability;

[0036] This invention achieves dynamic control of the P-type shielding region potential through a self-clamping structure formed by sidewall injection: during forward conduction, the P-type shielding region potential is floating, the parasitic JFET effect is weakened, and the specific on-resistance (R) is reduced. on,sp The value is 2.107 mΩ·cm 2 This is superior to the 2.125 mΩ·cm of traditional devices. 2 When the withstand voltage is interrupted, the potential of the P-type shielding area is automatically grounded, and the maximum electric field strength at the bottom of the gate oxide layer is 2.46MV / cm, which is lower than the critical value of 3MV / cm, effectively protecting the gate oxide from high electric field impact. This self-clamping structure solves the dilemma caused by the fixed potential of the P-type shielding area in the prior art, which reduces conduction loss and ensures device reliability.

[0037] 3) Eliminate external discrete components to reduce parasitic parameters and system cost;

[0038] This invention integrates the JBS structure directly into the MOSFET cell, with both sharing the drift region and termination structure, eliminating the need for an external anti-parallel Schottky diode. Compared to the traditional MOSFET and discrete SBD solution, this invention significantly reduces the number of transistors, avoids the parasitic capacitance and inductance introduced by external discrete components, simplifies the circuit topology, reduces the system size, and lowers packaging costs and system power consumption.

[0039] 4) Optimize static and dynamic performance to meet the needs of high-power applications;

[0040] The device of this invention meets or exceeds the design specifications in all key electrical parameters: threshold voltage (V) th The voltage is 3.75V, the breakdown voltage (BV) is 1498V, and the turn-on time (t) is... on The turn-off time is 16.13 ns, and the turn-off time (t) is 16.13 ns. off The time to reverse recovery is 42.09 ns. Compared with traditional devices without integrated JBS, this invention improves the reverse recovery capability without sacrificing the forward conduction and blocking characteristics, resulting in a comprehensive improvement in overall performance.

[0041] 5) The preparation process is simple and low-cost, which is conducive to industrial production and application;

[0042] This invention incorporates the constraints of existing fabrication processes into the above-mentioned device structure design, and simplifies the fabrication process based on the structural design, making it simple and low-cost, and promising for industrial production applications. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the three-dimensional cell structure of a SiC MOSFET device with integrated JFET in the prior art.

[0044] Figure 2 A schematic diagram of the three-dimensional cell structure of the SiC MOSFET device integrating JBS and self-clamping P-Shield region provided by the present invention.

[0045] Figure 3 for Figure 2 A schematic cross-sectional view of a SiC MOSFET device with integrated JBS and self-clamping P-Shield region along the dashed line AA′.

[0046] Figure 4 for Figure 2 A partially enlarged view of the self-clamping structure of a SiC MOSFET device with integrated JBS and self-clamping P-Shield region.

[0047] Figure 5The fabrication process flow diagram of the SiC MOSFET device integrating JBS and self-clamping P-Shield region provided by the present invention is shown.

[0048] Figure 6 The potential simulation test results of the P-type shield region of the SiC MOSFET device with integrated JBS and self-clamping P-Shield region provided by the present invention are shown in the figure. Detailed Implementation

[0049] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be noted that this section is based on simulation parameters and structural design; where there is no conflict, those skilled in the art can adjust the specific parameters according to actual process conditions.

[0050] Example 1

[0051] This embodiment provides a SiC MOSFET device integrating JBS and a self-clamping P-Shield region, such as Figure 2 and Figure 3 As shown, it specifically includes:

[0052] The semiconductor substrate includes: an N-type heavily doped substrate layer 2, a drain metal layer 1 disposed below the N-type heavily doped substrate layer, and an N-type drift region 3 and a current spreading layer 4 disposed sequentially on the N-type heavily doped substrate layer.

[0053] Multiple cell structures are formed on the current spreading layer 4; the cells adopt a symmetrical structure, including: P-type well region 5, N+ source region 6, P+ contact region 7, shallow trench control gate 8, deep trench self-clamping gate 9, P-type shielding region 10, source metal layer 11, interlayer dielectric layer 12, P-type sidewall injection region 13 and N-type sidewall injection region 14.

[0054] Among them, the P-type well region 5 is disposed on the current spreading layer 4, and the two shallow trench control gates 8 and the deep trench self-clamping gate 9 are disposed along the cell surface through the P-type well region 5. The deep trench self-clamping gate 9 is located in the middle region of the cell, and the two shallow trench control gates 8 are located in the two sides of the cell respectively. The shallow trench control gate 8 and the deep trench self-clamping gate 9 are both composed of a gate oxide layer located on the trench wall and a polysilicon gate filled in the trench.

[0055] N+ source region 6 and P+ contact region 7 are respectively set in the P-type trap region 5 on both sides of the deep trench self-clamping gate 9. The N+ source region 6 and P+ contact region 7 are arranged side by side in the transverse direction between the deep trench self-clamping gate 9 and the shallow trench control gate 8.

[0056] The source metal layer 11 covers the cell and forms an ohmic contact with the N+ source region and the P+ contact region. An interlayer dielectric layer 12 is disposed between the source metal layer and the polysilicon gate to form an isolation.

[0057] The P-type shielding region 10 is disposed at the bottom of the deep trench self-clamping gate 9 and surrounds the bottom area of ​​the deep trench self-clamping gate 9. The two sidewalls of the deep trench self-clamping gate 9 are respectively provided with a P-type sidewall injection region (P-Side) 13 and an N-type sidewall injection region (N-Side) 14. The P-type sidewall injection region 13 and the N-type sidewall injection region 14 are arranged side by side in the transverse direction and are both disposed between the P-type well region 5 and the P-type shielding region 10 (P-Shield region). The self-clamping gate 9, the P-type sidewall injection region 13, and the N-type sidewall injection region 14 together form a normally open P-channel MOSFET structure, which is used to control the electrical connection state between the P-type shielding region and the P-type well region according to the gate voltage.

[0058] The cell is embedded in a junction barrier Schottky diode (JBS) structure in the Z-axis direction. The junction barrier Schottky diode (JBS) cell structure includes: a Schottky contact region 15, which is disposed between two deep trench self-clamping gates 9 arranged in the longitudinal direction (Z-axis direction). The Schottky contact region is electrically connected to the upper source metal layer and forms a Schottky contact with the lower current extension layer 4.

[0059] Specifically, in this embodiment, the structural parameters and doping concentration of the SiC MOSFET device are as follows:

[0060] For the substrate and epitaxial layer parameters, this embodiment uses 4H-SiC material; the N-type heavily doped substrate layer has a thickness of approximately 350 μm and a doping concentration of 5 × 10⁻⁶. 18 cm -3 N-type drift region: formed on the substrate layer, with a thickness T N-Drift =9.8μm, doping concentration N N-Drift =8×10 15 cm -3 Current spreading layer (CSL): formed on the drift region, with a thickness T CSL =1.2μm, doping concentration N CSL =3×10 16 cm -3 ;

[0061] For cellular structure parameters, P-well region: thickness T P-well =0.5μm, width W P-well =0.5μm, doping concentration N P-well =1×10 17 cm -3 N+ source region: thickness 0.3 μm, width 0.25 μm, doping concentration 5 × 10⁻⁶18 cm -3 P+ contact region: thickness 0.3 μm, width 0.25 μm, doping concentration 5 × 10⁻⁶ 18 cm -3 Deep trench gate: depth D DG =2μm, width W DG =1μm; Shallow trench gate: depth D SG =1μm, width W SG =1μm; Gate oxide layer: approximately 50nm thick, formed using a thermal oxidation process; P-type shield: peak doping concentration N P-Shield =5×10 18 cm -3 ;

[0062] For self-clamping structure parameters, such as Figure 4 As shown, the P-type sidewall implantation region (P-Side) is distributed longitudinally along the deep trench gate sidewall, with a width comparable to the thickness of the deep trench gate sidewall, and a peak doping concentration N. P-Side =5×10 17 cm -3 N-type sidewall implantation region (N-Side): Arranged laterally alongside the P-type sidewall implantation region, with a peak doping concentration of N0. N-Side =6×10 17 cm -3 By adjusting the doping concentrations of the P-Side and N-Side regions, the threshold voltage V of the normally open P-channel MOSFET can be adjusted. P-th It is approximately 0.674V, which is between 0V and the device's body threshold voltage of 3.75V.

[0063] For JBS cell structure parameters, JBS cell gate spacing: W JBS =1μm, smaller than the spacing of the deep trench gate in the cell; Schottky contact region: located above the current extension layer 4 between the two deep trench gates in the longitudinal direction (Z-axis direction), the Schottky contact is formed by titanium (Ti), and the barrier height is about 1.0eV.

[0064] For the electrodes and dielectric layers, the interlayer dielectric layer (ILD) is made of silicon dioxide (SiO2) with a thickness of about 0.4 μm, located between the polysilicon gate and the source metal; the source metal is made of nickel (Ni) material, covering the cell and JBS structure, forming an ohmic contact with the N+ source region and P+ contact region; the drain metal is made of nickel (Ni) material, formed on the back side of the substrate.

[0065] Based on the above structural parameters and doping concentration, such as Figure 5 As shown, the SiC MOSFET device in this embodiment is fabricated through the following steps:

[0066] Step 1: Epitaxial growth, such as Figure 5 As shown in (a);

[0067] On an N-type heavily doped 4H-SiC substrate, an N-type drift region and a current spreading layer (CSL) were epitaxially grown sequentially. The drift region had a thickness of 9.8 μm and a doping concentration of 8 × 10⁻⁶. 15 cm -3 CSL thickness 1.2 μm, doping concentration 3 × 10⁻⁶ 16 cm -3 ;

[0068] Step 2: Form a P-type well region;

[0069] P-type wells (P-Wells) were formed in the epitaxial layer through multiple high-energy aluminum ion implantations. The implantation energy and dose were optimized to achieve a P-Well thickness of 0.5 μm and a doping concentration of 1 × 10⁻⁶. 17 cm -3 ;

[0070] Step 3: Form the N+ source region and the P+ contact region;

[0071] N+ source region and P+ contact region were formed by ion implantation, with a doping concentration of 5 × 10⁻⁶ for both. 18 cm -3 Thickness 0.3μm;

[0072] Step 4: Etch deep trench gates, such as... Figure 5 As shown in (b);

[0073] Dry etching is performed using a mask to form deep trench gates with a depth of 2μm and a width of 1μm. By adjusting the mask pattern, JBS cell regions are formed with spacing along the longitudinal direction (Z-axis).

[0074] Step 5: Form a P-type shielding area, such as Figure 5 As shown in (c);

[0075] A P-type shield was formed at the bottom of the deep trench gate by high-energy aluminum ion implantation, with a peak concentration of approximately 5 × 10⁻⁶ after implantation. 18 cm -3 ;

[0076] Step 6: Form a self-clamping structure;

[0077] The inclined sidewall injection process was employed, proceeding sequentially as follows: First sidewall injection: Nitrogen ions were injected at an inclination angle of approximately 7 degrees to form an N-type sidewall injection region, with a peak concentration of 6 × 10⁻⁶. 17 cm -3Second sidewall injection: Adjust the tilt angle to approximately 45 degrees, inject aluminum ions to form the upper part of the P-side injection region, with a peak concentration of 5 × 10⁻⁶. 17 cm -3 Third sidewall injection: Adjust the tilt angle to about 10 degrees, inject aluminum ions to compensate for the area in the P-type trap region affected by nitrogen ion injection;

[0078] Step 7: Etch shallow trenches, such as... Figure 5 As shown in (d);

[0079] Shallow trenches with a depth of 1μm and a width of 1μm are formed by dry etching;

[0080] Step 8: High-temperature annealing;

[0081] High-temperature annealing at temperatures above 1600℃ activates the implanted impurities and repairs lattice damage.

[0082] Step 9: Form the gate oxide layer and the polysilicon gate, such as Figure 5 As shown in (e);

[0083] A gate oxide layer with a thickness of approximately 50 nm is grown using a thermal oxidation process, followed by the deposition of N-type polysilicon to fill the trenches, and the removal of excess polysilicon from the surface by chemical mechanical polishing (CMP).

[0084] Step 10: Form an interlayer dielectric layer;

[0085] A 0.4 μm thick silicon dioxide layer is deposited as an interlayer dielectric (ILD) to isolate the gate and source.

[0086] Step 11: Form a Schottky contact;

[0087] The ILD and oxide layers of the JBS cell region are etched to expose the surface of the current extension layer, and metallic titanium (Ti) is deposited to form a Schottky contact;

[0088] Step 12: Form the source and drain, as follows Figure 5 As shown in (f);

[0089] A source metal layer is formed by depositing nickel (Ni) to cover the entire cell region; a drain metal layer is formed by depositing nickel on the back side of the substrate, followed by rapid thermal annealing to form an ohmic contact, thereby fabricating a SiC MOSFET device integrating JBS and self-clamping P-Shield region in this embodiment.

[0090] In terms of working principle:

[0091] For example, the literature “P. Li, J. Guo, Z. Lin, S. Hu, C. Shi and F. Tang, "A Novel Approach to Inactivate the Body pin Diode of SiC MOSFET by Using the Normally-OFF JFET," in IEEE Transactions on Electron Devices, vol. 68, no. 4, pp. 1784-1790, April 2021, doi: 10.1109 / TED.2021.3059393” provides a SiC MOSFET device with integrated JFET, such as... Figure 1 As shown, the device includes a P-Shield region connected to the source. This region can shield the high electric field near the gate oxide layer when the voltage is withstand. However, when the device is forward-biased, the P-Shield region potential is fixed to the ground potential by the source, which leads to enhanced depletion of the P-Shield region and the CSL region, narrowing the conduction path of the device current and causing degradation of the device's specific on-resistance.

[0092] To address the aforementioned issues, this embodiment proposes a SiC MOSFET device integrating a JBS and a self-clamping P-Shield region. A self-clamping structure is introduced. First, a self-clamping gate 9 connected to the control gate 8 is set in a deep trench in the central region. P-type sidewall injection regions (P-Side) 13 and N-type sidewall injection regions (N-Side) 14 are formed longitudinally (Z-axis direction) along the sidewalls of the self-clamping gate 9. The P-type sidewall injection regions 13 and N-type sidewall injection regions 14 are arranged side-by-side laterally (X-axis direction) and are both located between the P-type well region 5 and the P-type shield region 10 (P-Shield region). The self-clamping gate 9, P-type sidewall injection regions 13 and N-type sidewall injection regions 14 together constitute a normally open P-channel MOSFET structure. When the device is in a blocking voltage state, the self-clamping gate 9 is biased to 0, at which point the self-clamping structure is turned on, and the P-Shield region and P-Well region are at the same potential. The region is at ground potential. As the bias voltage of the self-clamping gate 9 gradually increases, the energy band near the self-clamping gate 9 in the semiconductor is pulled down, forming a hole barrier. The holes near the self-clamping gate 9 are gradually depleted. At the same time, mutual depletion also occurs between the N-Side region and the P-Side region. When the gate bias voltage increases to a certain level, it corresponds to the forward conduction state of the device. At this time, the holes in the P-Side region are completely depleted, and the conductive channel between the P-Well region and the P-Shield region is turned off. The P-Shield region is not connected to the P-Well region, and the potential of the P-Shield region rises to the floating potential. The potential difference between the P-Shield region and the CSL region is effectively reduced, and the depletion is weakened, thereby significantly alleviating the degradation problem of the specific on-resistance of the device caused by the P-Shield region.

[0093] like Figure 6 The figure shows the simulation test results of the potential of the P-type shield region of the SiC MOSFET device integrating JBS and self-clamping P-Shield region in this embodiment. As can be seen from the figure, the potential of the P-type shield region is floating when forward conduction (measured at about 0.52V), and the potential of the P-type shield region is grounded when blocking withstand voltage (measured at about -1.45V). The potential difference between the two is 1.97V, which effectively balances low on-resistance and high gate oxide reliability.

[0094] Furthermore, this embodiment explains the tolerance range of key parameters: P-type sidewall injection zone concentration: can be 5×10 16 cm -3 Up to 1×10 18 cm -3 Adjustable within the range, it still achieves self-clamping function; N-type sidewall injection zone concentration: can be adjusted to 1×10 16 cm -3 Up to 8×10 17 cm-3 Within the range of adjustment, by adjusting the injection dose and angle, V can be made... P-th Maintain from 0V to V th Between; drift zone concentration and thickness: can be within 5×10 15 cm -3 Up to 1×10 16 cm -3 The thickness of the gate oxide layer can be adjusted from 8μm to 15μm to meet different withstand voltage requirements; the gate oxide layer thickness can be adjusted from 30nm to 80nm to balance threshold voltage stability and gate oxide reliability.

[0095] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A SiC MOSFET device integrating JBS and a self-clamping P-Shield region, characterized in that, include: N-type heavily doped substrate (2), drain metal layer (1) disposed under N-type heavily doped substrate, N-type drift region (3) and current spread layer (4) disposed sequentially on N-type heavily doped substrate. The cell structure disposed on the current spreading layer (4) is symmetrical and includes: a P-type well region (5), an N+ source region (6), a P+ contact region (7), a shallow trench control gate (8), a deep trench self-clamping gate (9), a P-type shielding region (10), a source metal layer (11), an interlayer dielectric layer (12), a P-type sidewall injection region (13), and an N-type sidewall injection region (14). The P-type well region is set on the current spreading layer. The two shallow trench control gates and the deep trench self-clamping gate are all set along the cell surface and penetrate the P-type well region. The deep trench self-clamping gate is located in the middle region of the cell, and the two shallow trench control gates are located on both sides of the cell. An N+ source region and a P+ contact region are respectively set in the P-type trap regions on both sides of the deep trench self-clamping gate. The N+ source region and the P+ contact region are arranged side by side in the transverse direction between the deep trench self-clamping gate and the shallow trench control gate. The source metal layer covers the cell and forms an ohmic contact with the N+ source region and the P+ contact region. An interlayer dielectric layer is provided between the source metal layer and the polysilicon gate. The P-type shielding region is located at the bottom of the deep trench self-clamping gate and forms a surrounding structure. P-type sidewall injection regions and N-type sidewall injection regions are respectively provided on the two sidewalls of the deep trench self-clamping gate. The P-type sidewall injection regions and N-type sidewall injection regions are arranged side by side in the transverse direction and are both located between the P-type well region and the P-type shielding region. The self-clamping gate, the P-type sidewall injection region, and the N-type sidewall injection region together constitute a normally open P-channel MOSFET structure.

2. The SiC MOSFET device integrating JBS and self-clamping P-Shield region according to claim 1, characterized in that, The cell structure also embeds a junction barrier Schottky diode (JBS) structure in the Z-axis direction. The junction barrier Schottky diode (JBS) cell structure includes: a Schottky contact region (15), which is disposed between two deep trench self-clamping gates (9) arranged in the longitudinal direction (Z-axis direction). The Schottky contact region is electrically connected to the upper source metal layer and forms a Schottky contact with the lower current extension layer (4).

3. The SiC MOSFET device integrating JBS and self-clamping P-Shield region according to claim 2, characterized in that, The metal material of the Schottky contact region (15) is titanium, and the barrier height is 0.8eV~1.2eV.

4. The SiC MOSFET device integrating JBS and self-clamping P-Shield region according to claim 1, characterized in that, The doping concentration of the P-type sidewall implantation region (13) is 5 × 10⁻⁶. 16 cm -3 ~1×10 18 cm -3 The doping concentration of the N-type sidewall implantation region (14) is 1×10⁻⁶. 16 cm -3 ~8×10 17 cm -3 .

5. The SiC MOSFET device integrating JBS and self-clamping P-Shield region according to claim 1, characterized in that, The doping concentration of the N-type drift region (3) is 7 × 10⁻⁶. 15 cm -3 ~9×10 15 cm -3 The thickness is 9μm~11μm.

6. The SiC MOSFET device integrating JBS and self-clamping P-Shield region according to claim 1, characterized in that, The peak doping concentration of the P-type shielding region (10) is 1×10⁻⁶. 18 cm -3 ~1×10 19 cm -3 .

7. The SiC MOSFET device integrating JBS and self-clamping P-Shield region according to claim 1, characterized in that, The thickness of the gate oxide layer is 30 nm to 80 nm.

8. The method for fabricating a SiC MOSFET device integrating JBS and a self-clamping P-Shield region according to claim 1, characterized in that, Includes the following steps: An N-type drift region and a current spreading layer are epitaxially grown sequentially on an N-type heavily doped substrate; A P-type well region and a P+ contact region located in the middle region along the lateral direction, and an N+ source region located on both sides of the P+ contact region are formed in the current extension layer by ion implantation, and a Schottky contact region is reserved in the cell center region corresponding to the junction barrier Schottky diode (JBS) structure. Deep trenches are formed longitudinally on both sides of the reserved Schottky contact area by etching. A P-type shielding area is formed at the bottom of the deep trench by ion implantation. Then, N-type impurities and P-type impurities are sequentially implanted on both sides of the deep trench by inclined sidewall implantation process to form N-type sidewall implantation area and P-type sidewall implantation area. Shallow trenches are formed on both sides of the cell by etching, and impurities are injected after high-temperature annealing. A gate oxide layer is formed simultaneously on the walls of both deep and shallow trenches by thermal growth, and polysilicon is deposited to fill the trenches; then an interlayer dielectric layer is deposited on the polysilicon. Schottky metal is deposited in the reserved Schottky contact area to form a Schottky contact; Finally, source and drain metal layers are deposited separately.

9. The method for fabricating a SiC MOSFET device integrating JBS and a self-clamping P-Shield region according to claim 1, characterized in that, The tilted sidewall implantation process includes: first sidewall implantation: nitrogen ions are implanted at a tilt angle of 5 to 10 degrees to form an N-type sidewall implantation region; second sidewall implantation: aluminum ions are implanted at a tilt angle of 40 to 50 degrees to form a P-type sidewall implantation region; third sidewall implantation: aluminum ions are implanted again at a tilt angle of 8 to 15 degrees to compensate for the area in the P-type trap region affected by nitrogen ion implantation.

10. The method for fabricating a SiC MOSFET device integrating JBS and a self-clamping P-Shield region according to claim 1, characterized in that, The Schottky metal is titanium, which is deposited by electron beam evaporation or sputtering.

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