Gallium nitride-based electronic chip

Abstract

The present disclosure relates to gallium nitride-based electronic chips. The present disclosure relates to methods for manufacturing electronic chips. An example method includes the following consecutive steps: a) forming an interconnect structure on a top surface of a gallium nitride-based stack, the gallium nitride-based stack being arranged on a top surface of a semiconductor substrate; b) arranging a first insulating layer on a top surface of the interconnect structure; c) forming a resin etch mask on a top surface of the first insulating layer, and then etching the first insulating layer and the interconnect structure through the resin etch mask within a peripheral region of each electronic chip until exposing the top surface of the gallium nitride-based stack; d) etching the gallium nitride-based stack relative to the peripheral region using the first insulating layer as an etch mask until exposing the top surface of the semiconductor substrate; and e) dicing the semiconductor substrate to individualize the electronic chips.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to French patent application number 2502770, filed on March 19, 2025, entitled “PUCE ÉLECTRONIQUE À BASE DENITRURE DE GALLIUM”, which is hereby incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure relates generally to the field of electronic chips, and more specifically to the field of gallium nitride-based electronic chips. Background Technology

[0004] In industry, most electronic devices are mass-produced. Therefore, several electronic chips are currently manufactured on the same semiconductor substrate, such as a single plate or semiconductor wafer. The electronic chips can then be separated or singularized for use, for example, either individually or in an electronic device that includes other components. This singularization is typically performed by cutting, for example, using a saw.

[0005] During this individualization process, such as when dicing a semiconductor wafer, cracks may form at the edges of the electronic chip and propagate within the chip. Such cracks can lead to malfunctions in the electronic circuitry of the chip.

[0006] To protect electronic chips (especially during manufacturing, individualization, or use), components can be included around the chip to prevent cracks.

[0007] It is expected that some of the drawbacks of known embodiments of electronic chips will be overcome, at least in part. Summary of the Invention

[0008] For this purpose, one embodiment provides a method for manufacturing an electronic chip, the method comprising the following sequential steps:

[0009] a) An interconnect structure is formed on the top surface of a gallium nitride-based stack, which is sequentially arranged on the top surface of a semiconductor substrate;

[0010] b) A first insulating layer is disposed on the top surface of the interconnect structure;

[0011] c) A resin etching mask is formed on the top surface of the first insulating layer, and then the first insulating layer and interconnect structure are etched through the resin etching mask in the peripheral area of ​​each electronic chip until the top surface of the gallium nitride-based stack is exposed;

[0012] d) Using the first insulating layer as an etching mask, etch the gallium nitride-based stack relative to the surrounding area until the top surface of the semiconductor substrate is exposed;

[0013] e) Cutting semiconductor substrates to individualize electronic chips.

[0014] According to an embodiment, the manufacturing method includes the step of forming a second insulating layer on the top surface of the first insulating layer and on the side wings and bottom of the peripheral region between steps d) and e).

[0015] According to an embodiment, the first insulating layer is made of oxide.

[0016] According to an embodiment, during step b), a first insulating layer is deposited with a thickness ranging from 2µm to 4µm.

[0017] According to an embodiment, the interconnect structure has a thickness ranging from 10µm to 15µm.

[0018] According to an embodiment, each electronic chip includes a high electron mobility transistor formed within an interconnect structure, and formed in and on a gallium nitride-based stack.

[0019] According to an embodiment, each electronic chip includes a sealing ring.

[0020] According to an embodiment, the interconnect structure includes metal pads disposed on the side wings of the top surface of the interconnect structure, the metal pads being covered by a first insulating layer during step b).

[0021] According to an embodiment, the metal pad corresponds to the contact recovery pad of the transistor.

[0022] According to an embodiment, etching the first insulating layer and interconnect structure during step c) is anisotropic etching, and etching the gallium nitride-based stack during step d) is anisotropic etching.

[0023] According to an embodiment, etching the first insulating layer and interconnect structure during step c) is isotropic etching, and etching the gallium nitride-based stack during step d) is anisotropic etching.

[0024] Another embodiment provides an electronic chip, comprising:

[0025] An interconnect structure is disposed on the top surface of a gallium nitride-based stack, which is sequentially disposed on the top surface of a semiconductor substrate; and

[0026] - A first insulating layer, which is located on the top surface of the interconnect structure.

[0027] The electronic chip also includes an opening in the peripheral area that exposes the top surface of the semiconductor substrate.

[0028] According to an embodiment, in the opening, the side wings of the interconnect structure are aligned with the side wings of the gallium nitride-based stack. Attached Figure Description

[0029] Referring to the accompanying drawings, the foregoing features and advantages, as well as other features and advantages, will be described in detail below in a specific description of the particular embodiments given in an illustrative and non-limiting manner, in which:

[0030] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G and Figure 1H These are cross-sectional, partial, and schematic views of a structure obtained at the end of successive steps of an exemplary method for manufacturing an electronic chip according to the first embodiment;

[0031] Figure 2A and Figure 2B These are cross-sectional, partial, and schematic views of a structure obtained at the end of successive steps of an example method for manufacturing an electronic chip according to the second embodiment;

[0032] Figure 3A and Figure 3B These are cross-sectional, partial, and schematic views of the structure obtained at the end of successive steps of the example method for manufacturing an electronic chip according to the third embodiment; and

[0033] Figure 4A and Figure 4B These are cross-sectional, partial, and schematic views of the structure obtained at the end of successive steps of an example method for manufacturing an electronic chip according to the fourth embodiment. Detailed Implementation

[0034] Similar features have been indicated by similar reference numerals in the various figures. In particular, structural and / or functional features common to the various embodiments may have the same reference numerals and may be deployed with the same structure, dimensions, and material properties.

[0035] For clarity, only those operations and elements that are useful for understanding the embodiments described herein are illustrated and described in detail.

[0036] Unless otherwise stated, when referring to two elements connected together, it means a direct connection without any intermediate elements other than a conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0037] In the following disclosure, unless otherwise stated, reference to absolute position qualifiers (such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc.) or relative position qualifiers (such as the terms “above,” “below,” “higher,” “lower,” etc.) or orientation qualifiers (such as “horizontal,” “vertical,” etc.) refers to the orientation shown in the figure.

[0038] Unless otherwise specified, the expressions “approximately,” “about,” “substantially,” and “about” indicate within 10% or 10°, and preferably within 5% or 5°.

[0039] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G and Figure 1H These are cross-sectional, partial, and schematic views of a structure obtained at the end of successive steps of an example method for manufacturing an electronic chip according to the first embodiment.

[0040] Figure 1A The diagram illustrates a starting structure including a semiconductor substrate 11, a gallium nitride (GaN)-based stack 15 on the semiconductor substrate 11, and interconnect structures 13 on the GaN-based stack 15. As an example, the GaN-based stack 15 is arranged on the top surface of the semiconductor substrate 11 and in contact with the top surface of the semiconductor substrate 11. For example, the GaN-based stack 15 extends continuously over the entire top surface of the semiconductor substrate 11. For example, the interconnect structures are arranged on the top surface of the GaN-based stack 15 and in contact with the top surface of the GaN-based stack 15.

[0041] For example, substrate 11 is made of silicon, such as monocrystalline silicon, or silicon carbide. Alternatively, substrate 11 is made of aluminum nitride.

[0042] For example, the gallium nitride-based stack 15 includes several semiconductor layers. For example, the semiconductor layers of the stack 15 are made of a gallium nitride (GaN)-based III-V type semiconductor material, such as gallium nitride and / or aluminum gallium nitride (AlGaN). For example, the gallium nitride-based stack 15 has a thickness in the range of 2µm to 10µm, such as about 5µm.

[0043] For example, interconnect structure 13 corresponds to a stack of insulating layers (e.g., dielectric layers), in which metal traces or pads are formed in the region of electronic circuit 17. Figure 1AIn the diagram, four insulating layers are illustrated within the interconnect structure 13. In practice, the interconnect structure 13 may include more than four insulating layers. For example, the interconnect structure 13 has a thickness ranging from 10 µm to 30 µm, such as from 15 µm to 18 µm.

[0044] As an example, the initial structure includes multiple circuit regions 17 formed in the interconnect structure 13 and the GaN stack 15. Figure 1A The diagram illustrates a single circuit region 17. Each circuit region 17 may include multiple electronic components. As an example, each circuit region 17 includes a transistor T, which may be, for example, a high electron mobility transistor or a HEMT.

[0045] For example, transistors T are formed in and on the GaN stack 15 and in the interconnect structure 15. As an example, each transistor T includes a source contact S, a drain contact D, and a gate contact G formed on the GaN stack 15. As an example, these contacts are coupled to metal traces or pads 19 formed on and within the insulating layer of the interconnect structure 13. As an example, circuit region 17 includes one or more metal pads 21 formed on the surface of the interconnect structure 13. As an example, the metal pads 21 are made of aluminum, for example, of aluminum and copper.

[0046] As an example, each circuit region 17 is surrounded by a sealing ring 23, thereby allowing for the prevention and / or detection of potential cracks propagating within the circuit region 17. As an example, the sealing ring is formed within structure 13. As an example, the sealing ring 23 does not extend through the GaN stack 15.

[0047] As an example, each sealing ring 23 includes a plurality of metal layers 25 formed on the insulating layer of the interconnect structure 13 and coupled to each other through conductive vias. As an example, each sealing ring also includes a top metal layer 27 formed on the surface of the interconnect structure 13. As an example, the metal layer 27 is made of aluminum, for example, of aluminum and copper.

[0048] As an example, the circuit region 17 associated with the sealing ring 23 surrounding it defines an unindividualized electronic chip that remains integral with the adjacent electronic chip. As an example, in such... Figure 1A In the initial structure illustrated, each electronic chip is integrated with the others via a substrate 11, a GaN stack 15, and an interconnect structure 13. As an example, in... Figure 1A In the initial structure illustrated in the figure, the electronic chips are not electrically connected to each other.

[0049] Figure 1B The illustration shows the deposition of the insulating layer 30 for hard masking. Figure 1AThe structure obtained at the end of the steps on the top surface of the structure shown in the figure.

[0050] As an example, layer 30 is deposited in such a way as Figure 1A The entire top surface of the structure shown in the figure.

[0051] More specifically, during this step, layer 30 is deposited on the top surface of interconnect structure 13 and in contact with that top surface. Additionally, during this step, layer 30 is deposited, for example, on the top surfaces of pad 21 and layer 27. As an example, during this step, layer 30 is deposited in contact with pad 21 and layer 27.

[0052] Layer 30 is made of a dielectric material, such as an oxide, for example, tetraethyl orthosilicate or TEOS.

[0053] As an example, layer 30 is deposited conformally. It is deposited over its entire surface with a perceptibly constant thickness. As an example, layer 30 is deposited with a thickness ranging from 2µm to 4µm, such as approximately 3µm.

[0054] Figure 1C The diagram illustrates the use of in Figure 1B The structure obtained at the end of the step of forming a resin mask layer 32 on the top surface of the structure shown in the figure.

[0055] More specifically, during this step, layer 32 in Figure 1B The structure shown is formed over the entire top surface. As an example, layer 32 is formed in contact with layer 30.

[0056] The resin layer 32 is, for example, a photosensitive resin, such as a positive resin. For example, layer 32 is deposited with a thickness ranging from 10µm to 15µm, such as about 13µm.

[0057] As an example, after deposition, the resin layer 32 is locally removed relative to the peripheral portion of each unindividualized electronic chip by photolithography.

[0058] Figure 1D The illustration shows the etching process using mask layer 32. Figure 1C The structure obtained at the end of the steps of insulating layer 30 and interconnection structure 13 of the structure shown in the figure.

[0059] More specifically, during this step, layer 30 and structure 13 are etched to partially expose the top surface of the GaN stack 15.

[0060] As an example, in this embodiment, the etched layer 30 and structure 13 correspond to anisotropic dry etching.

[0061] During this step, the etching is, for example, plasma etching.

[0062] At the end of this step, the structure includes openings 34 formed to pass through the peripheral portion of each unindividualized electronic chip. The openings 34, for example, have flanks aligned with the flanks of the mask layer 32 above. As an example, at the end of this step, the openings 34 have perceptibly vertical flanks. As an example, at the end of this step, the openings 34 have a perceptibly constant width over their entire depth. The openings 34 have, for example, a width ranging from 15µm to 40µm, such as from 20µm to 25µm.

[0063] As an example, each chip includes an opening 34 in a ring shape with a circuit region 17 that completely surrounds the chip and a sealing ring 23 in the top view.

[0064] At the end of this step, mask layer 32 is removed, for example. After the step of removing layer 32, the surface of layer 30 is cleaned, for example.

[0065] Figure 1E The illustration shows the etching process using a mask insulating layer 30. Figure 1D The structure shown in the figure is the structure obtained at the end of step 15 of the gallium nitride stack. During this step, layer 30 is used as an etch mask for stack 15.

[0066] More specifically, during this step, stack 15 is etched to partially expose the top surface of substrate 11.

[0067] As an example, in this embodiment, the etch stack 15 corresponds to dry anisotropic etching.

[0068] During this step, the etching is, for example, plasma etching.

[0069] At the end of this step, the opening 34 formed during the etching step extends vertically through the stack 15 to the top surface of the substrate 11. The opening 34 is also referred to as TGV (Through GaN Via) because it also extends vertically through the GaN-based stack 15.

[0070] As an example, at the end of this step, the openings have straight flanks over their entire height. As an example, the openings 34 have no step between the stack 15 and the interconnect structure 13 on their side flanks. Therefore, the openings 34 are the same width in the plane of the top surface of the interconnect structure 13 as they are in the plane of the bottom surface of the GaN stack 15.

[0071] As an example, layer 30 is specifically consumed during the etching of the GaN stack 15. Therefore, at the end of this step, layer 30 has, for example, a remaining thickness in the range of 0.5µm to 3µm, which is, for example, about 1µm.

[0072] Figure 1F The diagram illustrates the use of in Figure 1E The structure is obtained at the end of the step of depositing another insulating layer 36 on the top surface of the structure illustrated in the figure.

[0073] More specifically, during this step, layer 36 is formed on the top surface of layer 30, and on the side wings and bottom of opening 34.

[0074] During this step, layer 36 is formed in contact with the top surface of layer 30. During this step, layer 36 also contacts the side wings of interconnect structure 13 and layer 30 in opening 34. During this step, layer 36 also contacts the top surface of substrate 11 within opening 34.

[0075] Layer 36 is, for example, a layer made of a dielectric material. As an example, layer 36 is made of an oxide (e.g., TEOS). Alternatively, layer 36 is made of silicon dioxide and silicon nitride.

[0076] As an example, a layer 36 is deposited with a thickness ranging from 2µm to 10µm, for example, about 5µm.

[0077] Figure 1G The diagram illustrates the use of in Figure 1F The structure is obtained at the end of the step of forming a layer 37 made of dielectric material and an encapsulation layer 38 on the top surface of the structure illustrated in the figure.

[0078] More specifically, during this step, in the first phase Figure 1F A dielectric material layer 37 is formed on the top surface of the structure illustrated in the figure, and more particularly, a dielectric material layer 37 is formed on the top surface of layer 36.

[0079] As an example, the dielectric material layer 37 is made of nitride, such as silicon nitride.

[0080] As an example, the dielectric material layer 37 has a thickness of less than 1.5µm, for example, less than 1µm.

[0081] In the second stage, an encapsulation layer 38 is formed on the top surface of the dielectric material layer 37. Thus, layer 38 covers layer 37 over the entire structure, and particularly covers layer 37 in the opening 34.

[0082] As an example, the encapsulation layer 38 is made of a dielectric material known as a low-temperature coating or LTC. As an example, the encapsulation layer 38 is made of polyamide, such as polyimide.

[0083] As an example, an encapsulation layer 38 is deposited with a thickness ranging from 5µm to 15µm, for example, about 7µm.

[0084] As an example, at the end of deposition layer 38, layer 38, as well as layers 30 and 36, are partially removed relative to some metal pads 21 to allow the restoration of electrical contacts on these pads. Additionally, encapsulation layer 38 is removed relative to future dicing paths that isolate the chips in the portion between peripheral openings 34 formed around adjacent chips.

[0085] As an example, at the end of these deposition and removal steps, a metal layer (not shown) is deposited on the top surface of the structure, such as on the encapsulation layer 38 and in the openings leading to the metal pads 21. As an example, the metal layer is made of aluminum, or for example, of aluminum and copper.

[0086] Figure 1H The diagram illustrates the cutting process. Figure 1G The structure shown in the figure is the structure obtained at the end of the step of forming a single electronic chip.

[0087] More specifically, during this step, dicing paths 39 are formed between each chip in the non-individualized chip. More specifically, during this step, dicing paths 39 are formed between peripheral openings 34 performed around adjacent chips.

[0088] As an example, cutting path 39 is performed by sawing. Alternatively, cutting path 39 is performed by laser cutting.

[0089] One advantage of this embodiment is that the opening 34 forms a further sealing ring, thereby allowing the prevention or limitation of crack propagation within the interconnect structure and the GaN stack.

[0090] Figure 2A and Figure 2B These are cross-sectional, partial, and schematic views of the structure obtained at the end of successive steps of an example method for manufacturing an electronic chip according to the second embodiment.

[0091] The method for manufacturing an electronic chip according to the second embodiment is similar to the method for manufacturing an electronic chip according to the first embodiment, except that in the second embodiment, the step of etching the layer 30 and the interconnect structure 13 is isotropic etching, while the step of etching the GaN stack 15 is anisotropic etching.

[0092] The method for manufacturing an electronic chip according to the second embodiment specifically includes combining... Figures 1A-1C The steps described herein will not be described again below.

[0093] Figure 2A The illustration shows an isotropic etching process using resin layer 32. Figure 1C The structure obtained at the end of the steps of insulating layer 30 and interconnection structure 13 of the structure shown in the figure.

[0094] More specifically, during this step, layer 30 and structure 13 are etched to partially expose the top surface of the GaN stack 15.

[0095] During this etching process, the etching is, for example, wet etching.

[0096] Alternatively, during this etching process, the etching is dry etching, such as plasma etching.

[0097] At the end of this step, the structure includes an opening 34 formed in the peripheral portion of each electronic chip in the unindividualized electronic chip. The opening 34 may be rounded or diagonal, for example. Figure 2A In the example shown, due to the isotropic nature of the etching, the tops of the flanks of the aperture 34 are misaligned with the flanks of the mask layer 32. In this example, each aperture 34 extends partially beneath the mask layer 32. As an example, at the end of this step, the width of the opening 34 decreases from the top surface of layer 30 to the bottom surface of structure 13. This means that the width of the openings in the plane of the top surface of layer 30 is greater than their width in the plane of the bottom surface of interconnect structure 13.

[0098] At the end of this step, the mask layer 32 is removed, for example. After the step of removing the mask layer 32, the surface of layer 30 is cleaned, for example.

[0099] Figure 2B The illustration shows the etching process through insulating layer 30. Figure 2B The structure shown in the figure is the structure obtained at the end of step 15 of the gallium nitride stacking process.

[0100] More specifically, during this step, stack 15 is etched to partially expose the top surface of substrate 11.

[0101] As an example, in this embodiment, the etching of stack 15 corresponds to anisotropic etching.

[0102] During this step, the etching is, for example, dry etching.

[0103] At the end of this step, from now on, the opening 34 formed during the etching step extends through the stack 15 to the top surface of the substrate 11.

[0104] As an example, at the end of this step, the bottom portion of each opening 34 has vertical side wings over its entire height. As an example, at the end of this step, the width of the opening 34 is perceptibly constant throughout the stack 15. This means that the width of the opening 34 obtained in the plane of the top surface of the stack 15 is perceptibly equal to the width of the opening 34 obtained in the plane of the bottom surface of the stack 15.

[0105] As an example, when the GaN stack 15 is etched, layer 30 is perceptibly consumed. Therefore, at the end of this step, layer 30 has, for example, a resulting width in the range of 0.5µm to 3µm, which is, for example, about 1µm.

[0106] After the step of etching the gallium nitride stack 15, the method continues to perform bonding. Figures 1F-1H The steps described are similar to those described in the first embodiment, except for the geometry of the opening 34.

[0107] Figure 3A and Figure 3B These are cross-sectional, partial, and schematic views of a structure obtained at the end of successive steps of an example method for manufacturing an electronic chip according to the third embodiment.

[0108] The method for manufacturing an electronic chip according to the third embodiment is similar to the method for manufacturing an electronic chip according to the first embodiment, except that in the third embodiment, the opening 34 has a higher width, such that the cutting path 39 for individualizing the chip passes through the opening 34.

[0109] The method for manufacturing an electronic chip according to the third embodiment specifically includes combining... Figures 1A-1C The steps described herein will not be described again below.

[0110] Figure 3A The illustration shows the etching process through resin layer 32. Figure 1C The structure obtained at the end of the steps of insulating layer 30 and interconnection structure 13 of the structure shown in the figure.

[0111] This step is similar to Figures 1C-1D The difference between the steps illustrated in the figure is that the openings 34 are not formed in the peripheral portion of each electronic chip in the unindividualized electronic chip, but rather they are formed between each electronic chip in the unindividualized electronic chip, and the openings extend from the peripheral portion of the electronic chip to the peripheral portion of the adjacent electronic chip.

[0112] Figure 3B The illustration shows the etching process through insulating layer 30. Figure 3A The structure shown in the figure is the structure obtained at the end of step 15 of the gallium nitride stacking process.

[0113] This step and Figure 1E The etching steps shown in the figure are the same.

[0114] After the step of etching the gallium nitride stack 15, the method continues to perform bonding. Figures 1F-1H The steps described are similar to those described in the first embodiment, except for the geometry of the opening 34. In this embodiment, the cutting path 39 for individualizing the electronic chip is thus formed in the opening 34.

[0115] Figure 4A and Figure 4B These are cross-sectional, partial, and schematic views of the structure obtained at the end of successive steps of an example method for manufacturing an electronic chip according to the fourth embodiment.

[0116] The method for manufacturing an electronic chip according to the fourth embodiment is similar to the method for manufacturing an electronic chip according to the first embodiment, except that in the fourth embodiment, the method includes forming a metal layer 40 on the top surface of a nitride layer 37 formed on the surface of an insulating layer 36 before forming an encapsulation layer 38.

[0117] The method for manufacturing an electronic chip according to the fourth embodiment specifically includes combining... Figures 1A-1F The steps described herein will not be described again below.

[0118] Figure 4A The diagram illustrates the use of in Figure 1F The structure shown in the figure is obtained at the end of the step of etching a nitride layer 37, a metal layer 40 and an encapsulation layer 38 on the top surface of the structure.

[0119] As an example, before depositing the metal layer 40, layers 30 and 36 can be partially removed relative to the metal pad 21 to expose the top surface of the metal pad 21 and ensure that the metal layer 40 is formed on the pad 21 and in contact with the pad 21.

[0120] After deposition, the metal layer 40 is, for example, partially removed so that it is left only at the desired location for connection to one or more external devices.

[0121] Metal layer 40 is made of, for example, copper.

[0122] also, Figure 4AThe structure illustrated includes metal bumps 42 or UBM (“under-bump metallization”). Bumps 42 are formed, for example, on and in contact with metal layer 40. Metal bumps 42 are, for example, titanium-based, nickel-based, silver-based, and / or gold-based. At the end of this step, layer 38 is formed, for example, on metal layer 40 and, for example, in contact with metal layer 40. As an example, layer 38 is removed from opening 34. Alternatively, layer 38 can be removed in the portion between peripheral openings 34 formed around adjacent chips, relative to a future dicing path that isolates the chip.

[0123] Figure 4B The illustration shows a sawing process. Figure 4A The structure shown in the figure is the structure obtained at the end of the step of forming a single electronic chip.

[0124] This step and combination Figure 1H The description is the same. Encapsulation layer 38 is partially removed, for example, to expose the top surface of metal layer 40.

[0125] Many applications are able to take advantage of the benefits offered by electronic chips, which can therefore be integrated into various types of components.

[0126] As an example, electronic chips can be integrated into components designed for use in the automotive industry. The electrification of motor vehicles has led to a significant increase in the number of electronic components in vehicles. These components include, for example, thyristors, rectifiers, high-voltage transient voltage protection diodes, modules, etc., designed to be integrated into vehicles. Furthermore, driver assistance and driving automation have also contributed to the increase in the number of electronic components within vehicles.

[0127] As an example, electronic chips can be integrated into components designed for industrial use. More specifically, the component may be used, for instance, in the development of green energy or in infrastructure electrification, such as for charging stations or solar energy collection. The component can also be used in the Internet of Things (IoT) or smart home sectors. For example, the component is designed to be implemented in circuits that power equipment, including transistors ranging from 30V to 1200V. The component can also be used in computing systems in the cloud, 5G RF communication networks, data centers, and servers. For example, the component may include wide-bandgap materials.

[0128] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will readily conceive of by those skilled in the art. In particular, the second and fourth embodiments, as well as the third and fourth embodiments, can be combined.

[0129] Furthermore, the embodiments are not limited to the example values ​​or example materials mentioned in this disclosure.

[0130] Finally, based on the functional descriptions provided above, the actual implementation of the embodiments and variants described herein is within the capabilities of those skilled in the art.

Claims

1. A method for manufacturing an electronic chip, comprising: a) An interconnect structure is formed on the top surface of a gallium nitride-based stack, wherein the gallium nitride-based stack is sequentially arranged on the top surface of a semiconductor substrate; b) A first insulating layer is disposed on the top surface of the interconnect structure; c) A resin etching mask is formed on the top surface of the first insulating layer, and then the first insulating layer and interconnect structure are etched through the resin etching mask in the peripheral area of ​​each electronic chip until the top surface of the gallium nitride-based stack is exposed; d) Using the first insulating layer as an etching mask, etch the gallium nitride-based stack relative to the peripheral region until the top surface of the semiconductor substrate is exposed; as well as e) Cutting the semiconductor substrate to individualize the electronic chip.

2. The method for manufacturing an electronic chip according to claim 1, comprising the step between steps d) and e) of forming a second insulating layer on the top surface of the first insulating layer and on one or more side wings and the bottom of the peripheral region.

3. The method for manufacturing an electronic chip according to claim 1, wherein the first insulating layer is made of oxide.

4. The method for manufacturing an electronic chip according to claim 1, wherein a first insulating layer is deposited during step b) with a thickness ranging from 2µm to 4µm.

5. The method for manufacturing an electronic chip according to claim 1, wherein the interconnect structure has a thickness in the range of 10µm to 15µm.

6. The method for manufacturing an electronic chip according to claim 1, wherein each electronic chip includes a high electron mobility transistor formed within an interconnect structure and formed in and on a gallium nitride-based stack.

7. The method for manufacturing electronic chips according to claim 1, wherein each electronic chip includes a sealing ring.

8. The method for manufacturing an electronic chip according to claim 6, wherein the interconnect structure includes metal pads disposed on the side wings of the top surface of the interconnect structure, the metal pads being covered by a first insulating layer during step b).

9. The method for manufacturing an electronic chip according to claim 8, wherein the metal pads correspond to the contact recovery pads of the high electron mobility transistor.

10. The method for manufacturing an electronic chip according to claim 1, wherein etching the first insulating layer and interconnect structure during step c) is anisotropic etching, and etching the gallium nitride-based stack during step d) is anisotropic etching.

11. The method for manufacturing an electronic chip according to claim 1, wherein etching the first insulating layer and interconnect structure during step c) is isotropic etching, and etching the gallium nitride-based stack during step d) is anisotropic etching.

12. An electronic chip, comprising: An interconnect structure is disposed on the top surface of a gallium nitride-based stack, which is sequentially disposed on the top surface of a semiconductor substrate; as well as - A first insulating layer, which is located on the top surface of the interconnect structure. The electronic chip also includes an opening in the peripheral region that exposes the top surface of the semiconductor substrate.

13. The electronic chip according to claim 12, wherein, In the opening, the side wings of the interconnect structure are aligned with the side wings of the gallium nitride-based stack.

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