Semiconductor structure and method of fabricating the same

Abstract

The application relates to a semiconductor structure and a manufacturing method thereof. The manufacturing method forms a first recess by etching a substrate, performs ion implantation on the sidewall of the first recess, forms a blocking area on the sidewall of the first recess, continues to etch the substrate based on the first recess, forms a second recess, uses the blocking area as a barrier, etches the sidewall of the first recess and the second recess in a horizontal direction, increases the width of the first recess above the blocking area and the width of the second recess below the blocking area, forms a stress groove with a double-sigma shape, the stress groove includes two pairs of sharp corners, points to a channel region below a gate structure, and an epitaxial structure formed in a subsequent epitaxial process can apply stress to the channel below the gate structure through the two sharp corners, thereby increasing the total stress applied to the channel.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] As integrated circuits evolve to smaller nodes, the feature size of metal-oxide-semiconductor field-effect transistors (MOSFETs) continues to shrink, and the power supply voltage decreases accordingly, leading to a decrease in drive current. Simply scaling down the size of MOSFET devices proportionally is no longer sufficient to meet the performance requirements of MOSFETs. To maintain or improve circuit performance, the industry has introduced strain engineering techniques to enhance the mobility of carriers in the channel region, thereby increasing drive current and switching speed.

[0003] Patent 201310113296.3 provides a method for fabricating a PMOS transistor and an NMOS transistor. This method increases the volume of stress material in the source and drain regions by forming double sigma trenches, while the tip of the lower sigma trench is further from the channel to avoid channel damage, thus achieving a balance between stress intensity and device reliability. However, to protect the morphology of the upper sigma trench, this approach requires repeated filling, etching, and removal of the dielectric, significantly increasing process complexity and cost. It also easily introduces particulate contamination, leading to epitaxial voids and high dislocation density, and potentially even leakage. Secondly, the lower sigma trench is far from the channel, limiting the stress exerted on the channel by its tip. Repeated cleaning and etching processes can damage or passivate the tip of the upper sigma trench, negating the stress gain resulting from the increased volume. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problems in the existing technology.

[0005] To achieve the above objectives, in a first aspect, this application provides a method for fabricating a semiconductor structure, comprising the following steps:

[0006] A substrate is provided on which a gate structure is formed;

[0007] The substrate at least one side of the gate structure is etched to form a first groove in the substrate;

[0008] Ion implantation is performed into the sidewall of the first groove to form a barrier region on the sidewall of the first groove, wherein the top surface of the barrier region is lower than the top surface of the substrate;

[0009] Based on the first groove, the substrate is etched further to form a second groove;

[0010] Using the blocking area as a barrier, the sidewalls of the first groove and the second groove are etched in the horizontal direction to increase the width of the first groove above the blocking area and the width of the second groove below the blocking area, thus forming a stress groove.

[0011] In one embodiment, prior to etching the substrate on at least one side of the gate structure, the method further includes forming a buffer dielectric layer covering the gate structure and the exposed surface of the substrate.

[0012] In one embodiment, etching the substrate on at least one side of the gate structure includes:

[0013] Remove the buffer dielectric layer on the substrate on at least one side of the gate structure to expose the substrate located on at least one side of the gate structure;

[0014] The exposed substrate is etched to form the first groove at a first depth, the ratio of the first depth to the stress groove depth being (2~3):5.

[0015] In one embodiment, the step of continuing to etch the substrate based on the first groove includes:

[0016] The substrate exposed by etching the bottom surface of the first groove is then etched to a second depth to form the second groove;

[0017] Wherein, the first depth is greater than the second depth.

[0018] In one embodiment, the ion implantation into the sidewall of the first groove includes:

[0019] Doped ions are implanted at an angle into the sidewall of the first groove to amorphize the substrate in the implantation region, thereby forming the barrier region in the sidewall of the first groove.

[0020] In one embodiment, the dopant ion includes at least one of germanium, carbon, or nitrogen.

[0021] In one embodiment, the horizontal etching of the sidewalls of the first and second grooves includes:

[0022] The sidewalls of the first and second grooves are wet-etched; wherein the wet etchant used has a high etching selectivity to the substrate.

[0023] In one embodiment, the manufacturing method further includes:

[0024] An epitaxial structure is formed in the stress groove, the epitaxial structure having a double sigma profile.

[0025] In one embodiment, the blocking region is an amorphized implantation region, which recrystallizes into a crystallized implantation region during the epitaxial formation of the epitaxial structure in the stress groove.

[0026] Secondly, this application provides a semiconductor structure, comprising:

[0027] Substrate;

[0028] A gate structure is disposed on the substrate;

[0029] An epitaxial structure is disposed in the substrate on at least one side of the gate structure. The epitaxial structure has a double sigma profile. The epitaxial structure includes a first stress structure and a second stress structure disposed below the first stress structure. The first stress structure includes a first sharp corner extending to both sides in a horizontal direction, and the second stress structure includes a second sharp corner extending to both sides in a horizontal direction.

[0030] In one embodiment, along the horizontal direction, the maximum horizontal width of the first stress structure is the same as the maximum horizontal width of the second stress structure, and the horizontal width of the first sharp corner is the same as that of the second sharp corner.

[0031] In one embodiment, the height of the first stress structure is greater than the height of the second stress structure in a direction perpendicular to the substrate.

[0032] In one embodiment, it further includes:

[0033] The crystallization implantation region is located between the first sharp corner and the second sharp corner in a direction perpendicular to the substrate.

[0034] The semiconductor structure and fabrication method of this application have the following unexpected effects: a first groove is formed by etching the substrate; ion implantation is performed into the sidewalls of the first groove to form a barrier region; based on the first groove, the substrate is further etched to form a second groove; using the barrier region as a barrier, the sidewalls of the first and second grooves are etched horizontally to increase the width of the first groove above the barrier region and the width of the second groove below the barrier region, forming a stress groove with a double-sigma morphology. The stress groove includes two pairs of sharp corners, pointing towards the gate structures on both sides, in subsequent epitaxy... The epitaxial structure formed by the process can apply stress to the channel below the gate structure through two sharp corners, thereby increasing the total stress applied to the channel. Compared with the traditional single-sigma structure, the sharp corners of the double-sigma structure formed in this application have a compact shape, which can increase the stress without increasing or even decreasing the lateral size and overall volume of the double-sigma structure. This is beneficial for further miniaturization of device feature size and meets the requirements of high-density integration. At the same time, the shape of the double-sigma sharp corners helps to suppress the generation of dislocations during the epitaxial growth process of the stress layer, thereby avoiding leakage and reliability degradation caused by dislocations. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a process flow diagram of a method for fabricating a semiconductor structure provided in one embodiment;

[0037] Figure 2 This is a schematic diagram of the structure after the buffer medium layer is formed, as provided in one embodiment;

[0038] Figure 3 This is a schematic diagram of the structure after a patterned photoresist layer has been formed, as provided in one embodiment.

[0039] Figure 4 This is a schematic diagram of the structure after the first groove is formed, provided in one embodiment;

[0040] Figure 5 This is a schematic diagram of the structure after ion implantation to form a barrier region, as provided in one embodiment.

[0041] Figure 6 This is a schematic diagram of the structure after the second groove is formed, provided in one embodiment;

[0042] Figure 7This is a schematic diagram of the structure after stress grooves are formed by wet etching in one embodiment;

[0043] Figure 8 This is a schematic diagram of the structure after the epitaxial structure is formed, as provided in one embodiment;

[0044] Figure 9 This is a schematic diagram of the structure after removing the buffer medium layer in one embodiment.

[0045] Explanation of reference numerals in the attached figures:

[0046] 21. Substrate; 22. Gate structure; 221. Gate dielectric layer; 222. Gate conductive layer; 231. First insulating layer; 232. Second insulating layer; 24. Photoresist layer; 25. Buffer dielectric layer; 26. First trench; 27. Second trench; 28. Stress trench; 29. ​​Barrier region; 29a. Crystallization implantation region; 29b. Amorphization implantation region; 30. Epitaxial structure; 33. First sharp corner; 34. Second sharp corner. Detailed Implementation

[0047] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0049] In the semiconductor field, stress engineering has been introduced to enhance the mobility of charge carriers in the channel region, thereby increasing drive current and switching speed. Embedded germanium-silicon source / drain technology is typically employed, utilizing the lattice mismatch between the germanium-silicon material and the silicon substrate to introduce compressive stress into the channel region, thus improving the hole mobility of PMOS devices.

[0050] In related technologies, embedded germanium-silicon source / drain technology typically forms trenches with a single-sigma (Sigma) profile, with an epitaxial layer of stress material inside and outside the single-sigma trench. However, in single-sigma germanium-silicon source / drain processes, the stress increase applied to the channel by the germanium-silicon epitaxial layer has approached its limit, and it is difficult to further increase the stress applied to the channel, making it difficult to meet the higher carrier mobility requirements of next-generation high-performance devices.

[0051] According to an exemplary embodiment, this embodiment provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the method for fabricating a semiconductor structure includes the following steps:

[0052] Step S101: Provide a substrate 21, on which a gate structure 22 is formed.

[0053] Reference Figure 2 The substrate 21 can be a semiconductor substrate, and the material of the semiconductor substrate can include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other III / V or II / VI semiconductor materials. Alternatively, for example, the semiconductor substrate can be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator. In this embodiment, the substrate 21 is a silicon substrate.

[0054] Reference Figure 2 The gate structure 22 is disposed on the substrate 21. The gate structure 22 may include a gate dielectric layer 221 and a gate conductive layer 222 stacked on the substrate 21. For example, the material of the gate dielectric layer 221 may include silicon oxide; the gate conductive layer 222 may be made of a low-resistance metal material such as tungsten (W), aluminum (Al), or copper (Cu).

[0055] In some other embodiments, a high-k dielectric layer is further disposed between the gate dielectric layer 221 and the gate conductive layer 222, wherein the material of the high-k dielectric layer may include hafnium oxide (HfO2) or hafnium silicon oxide (HfSiO2). x ), hafnium zirconium oxide (HfZrO) x Materials with high dielectric constants, such as alumina (AlO).

[0056] Furthermore, the gate structure 22 is covered by an insulating layer, which may be covered with a single layer or multiple layers of insulating layers. The material of each insulating layer may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0057] In this embodiment, refer to Figure 2 A first insulating layer 231 and a second insulating layer 232 are sequentially covered on the gate structure 22. The first insulating layer 231 is made of silicon nitride, and the second insulating layer 232 is made of silicon oxide.

[0058] In this embodiment, a plurality of gate structures 22 may be disposed on the substrate 21 at intervals, and the substrate 21 between two adjacent gate structures 22 is exposed.

[0059] Step S102: Etch at least one side of the substrate 21 of the gate structure 22 to form a first groove 26 on the substrate 21.

[0060] Reference Figure 2 , Figure 3 , Figure 4 The substrate 21 on at least one side of the gate structure 22 is etched away, forming a first groove 26 on at least one side of the gate structure 22. Further, in this embodiment, both sides of the gate structure 22 are etched to form a first groove 26 on each side of the gate structure 22.

[0061] For example, a dry etching process can be used to etch the substrate 21 to form the first groove 26.

[0062] Step S103: Ion implantation is performed on the sidewall of the first groove 26 to form a barrier region 29 on the sidewall of the first groove 26. The top surface of the barrier region 29 is lower than the top surface of the substrate 21.

[0063] In this embodiment, refer to Figure 5 Ion implantation is performed on the sidewall of the first groove 26 to dopants, thereby changing the amorphization of the implanted region to form a barrier region 29. The barrier region 29 has different etching characteristics from the crystalline silicon material of the substrate 21.

[0064] Specifically, ion implantation can be performed on the corner area where the sidewall and bottom surface of the first groove 26 meet, thereby ensuring that the top surface of the formed barrier region 29 is lower than the top surface of the substrate 21.

[0065] Step S104: Continue etching the substrate 21 based on the first groove 26 to form the second groove 27.

[0066] In this embodiment, refer to Figure 6 The substrate 21 exposed at the bottom of the first groove 26 is etched away, the groove depth of the first groove 26 is increased, and a second groove 27 is formed below the first groove 26.

[0067] For example, an anisotropic dry etching process can be used to form the second groove 27.

[0068] In some embodiments, refer to Figure 5 , Figure 6 During the ion implantation process in step S103, some ions may be implanted into the bottom surface of the first groove 26, causing the bottom surface of the first groove 26 to change to amorphous. In this step, the amorphous part of the bottom surface of the first groove 26 can be etched away, and then the substrate 21 below the bottom surface of the first groove 26 can be etched.

[0069] Step S105: Using the blocking area 29 as a barrier, the sidewalls of the first groove 26 and the second groove 27 are etched in the horizontal direction to increase the width of the first groove 26 above the blocking area 29 and the width of the second groove 27 below the blocking area 29, forming a stress groove 28.

[0070] In this embodiment, refer to Figure 7 The substrate 21 located on the side of the barrier region 29 in the horizontal direction is protected by a barrier region 29 as a mask. The sidewalls of the first groove 26 and the second groove 27 are etched using a wet etching process. Etching solution is injected into the grooves, and the etching solution contacts the substrate 21 on the sidewalls of the grooves and the barrier region 29. Since the etching characteristics of the barrier region 29 and the substrate 21 are different, the etching rate of the etching solution on the substrate 21 is much greater than that on the barrier region 29. Therefore, with the barrier region 29 as the boundary, the substrate 21 exposed on the sidewall of the first groove above the barrier region 29 is removed laterally in the horizontal direction, and the width of the first groove 26 increases, forming two sharp corners extending to both sides in the horizontal direction; the substrate 21 exposed on the sidewall of the second groove 27 below the barrier region 29 is removed laterally in the horizontal direction, and the width of the second groove 27 increases, forming two sharp corners extending to both sides in the horizontal direction. Thus, the groove with smooth sidewalls is transformed into a stress groove 28 with two horizontal sharp corners on each sidewall.

[0071] The semiconductor structure fabrication method of this embodiment involves etching a substrate 21 to form a first groove 26, performing ion implantation into the sidewalls of the first groove 26 to form a barrier region 29, and continuing to etch the substrate 21 to form a second groove 27. Using the barrier region 29 as a barrier, the sidewalls of the first groove 26 and the second groove 27 are etched horizontally to increase the width of the first groove 26 above the barrier region 29 and the width of the second groove 27 below the barrier region 29, forming a stress groove 28 with a double sigma profile. The stress groove 28 includes two pairs of sharp corners, one above and one below, pointing to the gate structures 22 on both sides. The epitaxial structure 30 formed in the subsequent epitaxial process can apply stress to the channel region below the gate structure 22 through the two sharp corners, thereby increasing the total stress applied to the channel region.

[0072] In some embodiments, before step S102 etching at least one side of the substrate 21 of the gate structure 22, the following steps are also performed: S100-1: forming a buffer dielectric layer 25 to cover the exposed surfaces of the gate structure 22 and the substrate 21.

[0073] In this embodiment, refer to Figure 2 , Figure 3 A buffer dielectric layer 25 is deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The buffer dielectric layer 25 covers the insulating layer on the surface of the gate structure 22 and the exposed surface of the substrate 21.

[0074] The material of the buffer dielectric layer 25 has a high etch selectivity relative to the second insulating layer 232 on the surface of the gate structure 22; for example, the material of the buffer dielectric layer 25 may include silicon nitride.

[0075] To improve control accuracy and ensure that the horizontal width of the formed stress groove 28 meets design expectations, this embodiment deposits a thicker buffer medium layer 25 compared to the scheme of forming a single-sigma trench. Generally, the thickness of the buffer medium layer 25 formed in a single-sigma trench is d0. In this embodiment, the thickness of the buffer medium layer 25 is 1.3 times d0 to 1.8 times d0. For example, it can be 1.3 times d0, 1.4 times d0, 1.5 times d0, 1.6 times d0, 1.7 times d0, or 1.8 times d0.

[0076] In some embodiments, step S102 etching the substrate 21 on at least one side of the gate structure 22 includes steps S1021-S1023.

[0077] Step S1021: Remove the buffer dielectric layer 25 on at least one side of the substrate 21 of the gate structure 22 to expose the substrate 21 located on at least one side of the gate structure 22.

[0078] In this embodiment, refer to Figure 3 First, a photoresist material is coated to cover the buffer dielectric layer 25, forming a photoresist layer 24. The photoresist layer 24 is then patterned and developed to expose the areas that need to be etched to form stress grooves 28. Then, referring to… Figure 3 The patterned buffer dielectric layer 25 is etched using an anisotropic etching process. The buffer dielectric layer 25 located on the substrate 21 between the gate structures 22 and the buffer dielectric layer 25 on the top surface of the gate are also etched. Because the etching process is anisotropic, the buffer dielectric layer 25 on the sidewall of the gate structure 22 is retained.

[0079] For example, the buffer dielectric layer 25 is etched using a dry process.

[0080] Step S1022: Etch the exposed substrate 21 to form a first groove 26 of a first depth, the ratio of the first depth to the depth of the stress groove 28 is (2~3):5.

[0081] In this embodiment, refer to Figure 4 Using the buffer dielectric layer 25 retained on the sidewall of the gate structure 22 as a self-aligned hard mask, the exposed substrate 21 is subjected to a first dry etching. By controlling the etching time and process parameters, the substrate 21 is etched vertically to a first depth to form a first groove 26. The first groove 26 has a sidewall morphology that is substantially perpendicular to the surface of the substrate 21.

[0082] For example, the first dry etching can be performed using a reactive ion etching process with a fluorine-based gas, and the etching gas can be selected from at least one of sulfur hexafluoride (SF6) and carbon tetrafluoride (CF4).

[0083] The first depth is determined based on the total depth of the stress groove 28 to be formed. For example, the first depth is two-fifths to three-fifths of the total depth of the stress groove 28, i.e., the ratio of the first depth to the total depth of the stress groove 28 is (2~3):5. In this embodiment, the first depth is approximately three-fifths of the total depth of the stress groove 28.

[0084] It is understandable that if the first depth is too shallow and the sidewall size of the first groove 26 is small, then in the subsequent step of ion implantation to form the barrier region 29, it will be difficult to form the top surface of the barrier region 29 to be lower than the top surface of the substrate 21, or it will be difficult to ensure that the formed barrier region 29 has sufficient barrier effect, which is not conducive to the formation of a double sigma profile; if the first depth is too deep, the depth margin left for the second dry etching is too small, which is not conducive to the formation and extension of the tip of the lower sigma profile.

[0085] In some embodiments, refer to Figure 5 Step S103 involves ion implantation into the sidewall of the first groove 26, including: tilting the implantation of doped ions into the sidewall of the first groove 26 to amorphize the substrate 21 of the implantation region and forming a barrier region 29 on the sidewall of the first groove 26.

[0086] Furthermore, the dopant ions include at least one of germanium, carbon, or nitrogen. In this embodiment, germanium ions (Ge+) are used as implantation ions. Germanium atoms have a large atomic mass and can disrupt the lattice of the substrate 21 at a relatively low implantation energy, thereby causing the substrate 21 in the implanted region to undergo an amorphous transformation. Moreover, using germanium ions for implantation allows the implanted region to be recrystallized, serving together with the epitaxial structure 30 as the source / drain of the device.

[0087] Reference Figure 5 In this embodiment, dopant ions are implanted at an angle, meaning the ion beam incident direction is tilted at a predetermined angle relative to the sidewall of the first groove 26, and small doses of dopant ions are implanted repeatedly around the axial direction of the first groove 26 towards the bottom of the sidewall of the first groove 26 or towards the corner region between the sidewall and the bottom surface, so as to amorphize the substrate 21 in the lower or lower middle part of the first groove 26, forming a barrier region 29. In this embodiment, the barrier region 29 includes amorphous silicon-germanium.

[0088] For example, the ion beam incident direction is tilted at an angle of 30° to 60° relative to the sidewall of the first groove 26, and four rotational injections are performed, each rotation being approximately 90°, to ensure that each sidewall of the first groove 26 is uniformly bombarded with ions, and that a continuous blocking region 29 is formed on the circumferential surface at the bottom of the first groove 26.

[0089] In this embodiment, a lower implantation energy is used to implant dopant ions, so that the implantation depth of dopant ions is shallow, thereby forming an amorphous barrier region 29 only on the surface of the sidewall of the first groove 26, avoiding damage or amorphization to the deep structure of the substrate 21 below the first groove 26.

[0090] In some embodiments, refer to Figure 6 Step S104 involves further etching the substrate 21 based on the first groove 26, including: etching the substrate 21 exposed at the bottom of the first groove 26, etching to a second depth to form a second groove 27; wherein the first depth is greater than the second depth.

[0091] After the barrier region 29 is formed, a second dry etching process is performed. Using the buffer dielectric layer 25 on the sidewall of the gate structure 22 as a mask, the substrate 21 is etched downward along the first groove 26. The second depth is etched downward along the vertical direction (perpendicular to the substrate 21) to deepen the depth of the first groove 26. The original first groove 26 and the deepened part together constitute the second groove 27. The total depth of the second groove 27 is equal to the sum of the depths of the first depth and the second depth. The depth of the second groove 27 is also the total depth of the stress groove 28 that is finally formed.

[0092] Reference Figure 6 The blocking region 29 is located on the sidewall of the middle region of the sidewall of the second groove 27, while the sidewall of the second groove 27 below the blocking region 29 is made of uniform crystalline silicon material. Thus, along the vertical direction, the upper and lower sidewalls of the groove are made of uniform crystalline silicon material, and the sidewall of the middle region is the ion-implanted blocking region 29, so that a stress groove 28 with a double sigma morphology can be directly formed by subsequent wet etching.

[0093] For example, the second dry etching can be performed using a reactive ion etching process with a fluorine-based gas, and the etching gas can be selected from at least one of sulfur hexafluoride (SF6) and carbon tetrafluoride (CF4).

[0094] For example, the first depth is two-fifths to three-fifths of the total depth of the stress groove 28, the second depth is two-fifths to three-fifths of the total depth of the stress groove 28, and the sum of the two is equal to the total depth of the stress groove 28.

[0095] In this embodiment, the first depth is greater than the second depth. The first depth is approximately three-fifths of the total depth of the stress groove 28, and the second depth is approximately two-fifths of the total depth of the stress groove 28, meaning the ratio of the first depth to the second depth is approximately 3:2. Thus, in the vertical direction, the blocking region 29 occupies the middle area of ​​the groove, and the sidewalls of the groove above the blocking region 29 are at similar heights to the sidewalls of the groove below the blocking region 29. This results in the stress groove 28 formed by subsequent transverse etching not only having a double-sigma morphology, but also having upper and lower sigma morphologies that are more similar.

[0096] In this embodiment, refer to Figure 7 After performing the second dry etching in step S104, the residual photoresist layer 24 and the by-products of dry etching are cleaned and removed.

[0097] For example, a solution containing caros acid can be used for cleaning. The caros acid mixture is prepared by mixing concentrated sulfuric acid (H2SO4) and hydrogen peroxide (H2O2).

[0098] In some embodiments, step S105 involves etching the sidewalls of the first groove 26 and the second groove 27 in the horizontal direction, including wet etching of the sidewalls of the first groove 26 and the second groove 27; wherein the wet etchant used in this step has a high etching selectivity for the substrate 21.

[0099] Reference Figure 7 In this step, the wet etching agent is a solution containing tetramethylammonium hydroxide (TMAH). The tetramethylammonium hydroxide solution has different etching rates for different crystal orientations of the substrate 21. The etching rate for the Si{111} crystal plane is much lower than that for the Si{100} and Si{110} crystal planes. Therefore, it is possible to selectively laterally etch the sidewalls of the first groove 26 and the second groove 27 along a specific crystal orientation.

[0100] Reference Figure 7 The tetramethylammonium hydroxide solution exhibits a high etching rate in the upper sidewall region of the second groove 27 (corresponding to the original first groove 26 sidewall). The tetramethylammonium hydroxide solution can perform lateral etching on the substrate 21 in the upper sidewall region. The upper sidewall region of the second groove 27 is gradually etched along the Si{111} crystal plane direction, forming an upper sigma sharp profile extending to both sides. Similarly, in the lower sidewall region of the second groove 27 (corresponding to the newly exposed substrate 21 surface at the second depth), there is no obstruction region 29. The tetramethylammonium hydroxide solution can also perform lateral etching on the substrate 21 in the lower region. The lower sidewall of the second groove 27 is gradually etched along the Si{111} crystal plane direction, forming a lower sigma sharp profile extending to both sides.

[0101] Reference Figure 7 In the middle sidewall region of the second groove 27, due to the presence of the blocking region 29, the etching rate of the tetramethylammonium hydroxide solution is very low. During the wet etching process, the middle sidewall region of the second groove 27 is protected by the blocking region 29, and the lateral etching is suppressed, thus maintaining the original vertical morphology.

[0102] In this embodiment, a stress groove 28 with a double sigma profile is finally formed by two dry etching processes, one ion implantation to form the barrier region 29, and one wet etching process. In the vertical direction, the stress groove 28 has two sigma horns located above and below the barrier region 29.

[0103] The stress groove 28 of the double sigma profile formed in this embodiment can exert compressive stress on the channel region together by the upper and lower sharp corners after the subsequent filling of stress material, which can form a stress superposition effect. The cumulative stress generated in the channel region is 1.6 to 1.8 times that of the single sigma structure, which can significantly improve the carrier mobility of the PMOS device.

[0104] In some embodiments, after step S105, the method for fabricating the semiconductor structure further performs the following step: S106: epitaxially forming an epitaxial structure 30 in a stress groove 28, the epitaxial structure 30 having a double sigma profile.

[0105] In this embodiment, refer to Figure 8 An epitaxial structure 30 is formed within the stress trench 28 using a selective epitaxial growth process. The material of the epitaxial structure 30 may include germanium silicon, boron-doped germanium silicon, or other semiconductor materials capable of applying compressive stress to the channel region. Exemplarily, the epitaxial structure 30 includes a germanium silicon epitaxial layer. In this embodiment, the top surface of the epitaxial structure 30 is slightly higher than the original surface of the substrate 21 to facilitate the subsequent formation of a metal silicide layer.

[0106] Since epitaxial growth is performed within the stress groove 28 of a double-sigma profile, the resulting epitaxial structure 30 also possesses a double-sigma profile. The epitaxial structure 30 includes a first spur 33 corresponding to the upper sigma spur and a second spur 34 corresponding to the lower sigma spur. The double-sigma profile epitaxial structure 30 simultaneously applies compressive stress to the channel region through the first spur 33 and the second spur 34, creating a stress superposition effect. This enhances the overall stress acting on the channel region, resulting in a cumulative stress in the channel region that is 1.6 to 1.8 times that of a single-sigma structure, significantly improving the carrier mobility of the PMOS device.

[0107] In some embodiments, the epitaxial structure 30 may include multiple stress sublayers, and the germanium element composition concentration and boron element doping concentration of each stress sublayer can be independently adjusted according to stress requirements and electrical performance requirements to further optimize stress conduction efficiency and channel carrier mobility.

[0108] In some embodiments, refer to Figure 6 , Figure 7 As shown, the barrier region 29 formed by tilted implantation of doped ions was originally an amorphous implantation region 29b. During the epitaxial formation of the epitaxial structure 30 in the stress groove 28, refer to Figure 8As shown, the amorphized implanted region 29b is recrystallized into the crystallized implanted region 29a.

[0109] It is understandable that during the epitaxial growth process to form the epitaxial structure 30, since selective epitaxial growth is usually carried out at higher temperatures (e.g., 600°C to 800°C), the barrier region 29 formed on the sidewall of the groove recrystallizes under high temperature conditions, and the lattice arrangement is restored from a disordered state to an ordered single crystal state with the same lattice as the substrate 21, thus transforming from an amorphous implantation region 29b to a crystallized implantation region 29a.

[0110] In this way, after the barrier region 29 is recrystallized, a continuous single-crystal lattice arrangement is formed between it, the epitaxial structure 30, and the substrate 21, eliminating the interface states and defects that may be introduced by the amorphous implantation region 29b, and ensuring the electrical performance and reliability of the device. At the same time, the barrier region 29 acts as an etching barrier in the wet etching stage and crystallizes in the epitaxial growth stage, thus eliminating the barrier region 29 without the need for additional removal steps, which simplifies the process complexity.

[0111] In some embodiments, the dopant ions implanted in the barrier region 29 are germanium ions. In this way, on the one hand, after the barrier region 29 is recrystallized into the crystallization implantation region 29a, the crystallization implantation region 29a is also made of germanium silicon, and the crystallization implantation region 29a can work together with the epitaxial structure 30 in the stress trench 28 as the source and / or drain of the PMOS device; on the other hand, the concentration of germanium component in the crystallization implantation region 29a is higher than that of the surrounding substrate 21, forming a smoother lattice constant transition between the epitaxial structure 30 and the substrate 21, which is beneficial to reducing abrupt changes in interface stress.

[0112] In this embodiment, refer to Figure 9 After forming the epitaxial structure 30, all the buffer dielectric layer 25 is removed, exposing the sidewalls of the gate structure 22 and the surface of the substrate 21. For example, the buffer dielectric layer 25 can be removed by cleaning with a hot phosphoric acid solution or by etching with a dry etching process, providing a clean process surface for subsequent processes.

[0113] In some embodiments, after removing all of the buffer dielectric layer 25, a step of self-aligned formation of a metal silicide layer can be performed, as shown in the accompanying drawings of this embodiment. A full-length metal layer can be deposited to cover the surface of the epitaxial structure 30, and the semiconductor structure can be thermally treated to cause the portion of the metal layer in contact with the epitaxial structure 30 to react and form a metal silicide layer, thereby reducing contact resistance. Subsequently, the metal layer that did not react with the epitaxial structure 30 is etched away.

[0114] In some other embodiments, the structure formed on the substrate 21 in step S101 is not a gate structure 22, but a dummy gate structure for placement. In this embodiment, after removing the remaining buffer dielectric layer 25, the dummy gate structure is etched away, and the gate structure 22 is formed in the original position of the dummy gate structure.

[0115] According to an exemplary embodiment, this application provides a semiconductor structure, referring to... Figure 9 The semiconductor structure includes a substrate 21, a gate structure 22, and at least one epitaxial structure 30. In this embodiment, the semiconductor structure may include a PMOS device, the gate structure 22 is the gate structure 22 of the PMOS device, and the at least one epitaxial structure 30 may be the source and / or drain of the PMOS device.

[0116] Reference Figure 9 The gate structure 22 is disposed on the substrate 21. The gate structure 22 may include a gate dielectric layer 221 and a gate conductive layer 222 stacked on the substrate 21. For example, the material of the gate dielectric layer 221 may include silicon oxide; the gate conductive layer 222 may be made of a low-resistance metal material such as tungsten (W), aluminum (Al), or copper (Cu).

[0117] In some other embodiments, a high-k dielectric layer is further disposed between the gate dielectric layer 221 and the gate conductive layer 222, wherein the material of the high-k dielectric layer may include hafnium oxide (HfO2) or hafnium silicon oxide (HfSiO2). x ), hafnium zirconium oxide (HfZrO) x Materials with high dielectric constants, such as alumina (AlO).

[0118] Furthermore, the gate structure 22 is covered by an insulating layer, which may be covered with a single layer or multiple layers of insulating layers. The material of each insulating layer may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, a first insulating layer 231 and a second insulating layer 232 are sequentially covered on the gate structure 22. The first insulating layer 231 is made of silicon nitride, and the second insulating layer 232 is made of silicon oxide.

[0119] In this embodiment, a plurality of gate structures 22 may be disposed at intervals on the substrate 21.

[0120] The epitaxial structure 30 is disposed in the substrate 21 on at least one side of the gate structure 22. The epitaxial structure 30 has a double sigma profile. In this embodiment, a double sigma profile epitaxial structure 30 can be disposed on each side of the gate structure 22.

[0121] A two-sigma profile refers to a cross-sectional view of the epitaxial structure 30 along the length (horizontal direction) of the channel, in which two sigma-shaped sharp corners pointing towards the channel region are provided on the sidewall of the epitaxial structure 30 near the channel region. The epitaxial structure 30 includes a first stress structure and a second stress structure disposed below the first stress structure. The first stress structure includes first sharp corners 33 extending horizontally to both sides, and the second stress structure includes second sharp corners 34 extending horizontally to both sides. One sidewall of the epitaxial structure 30 has first sharp corners 33 and second sharp corners 34 disposed at intervals, which together superimpose stress on the channel region below the gate structure 22.

[0122] In this embodiment, the epitaxial structure 30 of the dual sigma profile applies compressive stress to the channel region simultaneously through the first sharp corner 33 and the second sharp corner 34, forming a stress superposition effect, thereby enhancing the overall stress acting on the channel region. The cumulative stress generated in the channel region is 1.6 to 1.8 times that of the single sigma profile, which can significantly improve the carrier mobility of the PMOS device.

[0123] In some embodiments, refer to Figure 9 Along the horizontal direction, the maximum horizontal width of the first stress structure is the same as the maximum horizontal width of the second stress structure, and the horizontal widths of the first sharp corner 33 and the second sharp corner 34 are the same. In this way, the stresses applied to the channel region by the first sharp corner 33 of the first stress structure and the second sharp corner 34 of the second stress structure are superimposed, avoiding stress concentration or offset caused by the width difference.

[0124] In some embodiments, refer to Figure 9 Along a direction perpendicular to the substrate 21, the height of the first stress structure is greater than the height of the second stress structure. Furthermore, the height ratio of the first stress structure to the second stress structure is 3:2.

[0125] Furthermore, the first sharp corner 33 of the first stress structure occupies two-fifths of the height of the upper part of the epitaxial structure 30, and the second sharp corner 34 of the second stress structure occupies two-fifths of the height of the lower part of the epitaxial structure 30. The bisigma morphology of the epitaxial structure 30 is clear, and the size of the first sharp corner 33 is basically the same as that of the second dimension. The first sharp corner 33 and the second sharp corner 34 simultaneously apply compressive stress to the channel region to maximize the stress superposition effect.

[0126] In some embodiments, refer to Figure 9 The semiconductor structure also includes a crystallization implantation region 29a, located between a first sharp corner 33 and a second sharp corner 34 along a direction perpendicular to the substrate 21. In this embodiment, along the vertical direction, the crystallization implantation region 29a is located in the region between the first sharp corner 33 and the second sharp corner 34, which is the region corresponding to the middle of the epitaxial structure 30, and the double sigma morphology of the epitaxial structure 30 is clear.

[0127] In some embodiments, refer to Figure 9 The dopant ions in the crystallization implantation region 29a include at least one of germanium, carbon, or nitrogen.

[0128] In some embodiments, refer to Figure 9 The doped ions in the crystallization implantation region 29a include germanium, and the material of the crystallization implantation region 29a is the same as that of the epitaxial structure 30. Thus, the crystallization implantation region 29a is also made of germanium-silicon. On the one hand, the crystallization implantation region 29a can work together with the epitaxial structure 30 in the stress trench 28 as the source and / or drain of the PMOS device. On the other hand, the concentration of germanium in the crystallization implantation region 29a is higher than that of the surrounding substrate 21, forming a smoother lattice constant transition between the epitaxial structure 30 and the substrate 21, which is beneficial to reducing abrupt changes in interface stress.

[0129] In some embodiments, the two sigma trenches formed simultaneously can be grown sequentially within the trenches using a synchronous epitaxial process, comprising three germanium-silicon layers: a first stress layer, a second stress layer, and a third stress layer. Each of the first, second, and third stress layers has the same germanium concentration at corresponding positions in the upper and lower sigma trenches (i.e., the concentration within the same film layer is consistent), but different germanium concentrations can be set between layers (e.g., between the first stress layer and the second and third stress layers) to achieve a gradient distributed design.

[0130] For example, the first stress layer can be set to a relatively low germanium concentration to serve as a buffer layer; the second and third stress layers can be set to relatively high germanium concentrations to serve as main stress providing layers. The first stress layer is in direct contact with the substrate 21, which can effectively match the lattice constant of the substrate 21 and release the interfacial stress caused by the lattice mismatch between germanium silicon and the silicon substrate, thereby suppressing the nucleation and extension of dislocations during epitaxial growth.

[0131] The semiconductor structure and its fabrication method of this application have the following unexpected effects: A first groove 26 is formed by etching the substrate 21; ion implantation is performed into the sidewalls of the first groove 26 to form a barrier region 29; based on the first groove 26, the substrate 21 is further etched to form a second groove 27; using the barrier region 29 as a barrier, the sidewalls of the first groove 26 and the second groove 27 are etched horizontally, increasing the width of the first groove 26 above the barrier region 29 and the width of the second groove 27 below the barrier region 29, forming a stress groove 28 with a double-sigma morphology. The stress groove 28 includes two pairs of sharp corners, pointing towards… The gate structures 22 on both sides, in the subsequent epitaxial process, can exert stress on the channel region below the gate structure 22 through the two sharp corners, thereby increasing the stress applied to the channel region. Compared with the traditional single-sigma structure, the sharp corners of the double-sigma structure formed in this application have a compact shape, which can increase the stress without increasing or even reducing the lateral size and overall volume of the double-sigma structure. This is beneficial for further miniaturization of device feature size and meets the requirements of high-density integration. At the same time, the shape of the double-sigma sharp corners helps to suppress the generation of dislocations during the epitaxial growth process of the stress layer, thereby avoiding leakage and reliability degradation caused by dislocations.

[0132] The semiconductor structure fabrication method of this application has a simple process flow, without repeated steps of depositing, etching, and removing the dielectric, thus avoiding the introduction of particulate contamination and organic residues, thereby preventing poor contact or leakage, greatly improving the process window and mass production yield, and exhibiting high reproducibility. This application forms a first groove 26 on the substrate 21 of at least one side of the gate structure 22 by etching, and then implants ions into the sidewalls of the first groove 26 to form a barrier region 29. The etching selectivity ratio between the barrier region 29 and the substrate 21 is controlled by ion implantation, thereby forming a double-sharp sigma stress trench 28 through a single wet etching process. The upper and lower sigma trenches are formed simultaneously, completely avoiding the problem of damage or passivation of the tip morphology of the upper sigma trench.

[0133] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0134] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided on which a gate structure is formed; The substrate at least one side of the gate structure is etched to form a first groove in the substrate; Ion implantation is performed into the sidewall of the first groove to form a barrier region on the sidewall of the first groove, wherein the top surface of the barrier region is lower than the top surface of the substrate; Based on the first groove, the substrate is etched further to form a second groove; Using the blocking area as a barrier, the sidewalls of the first groove and the second groove are etched in the horizontal direction to increase the width of the first groove above the blocking area and the width of the second groove below the blocking area, thereby forming a stress groove.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Before etching the substrate on at least one side of the gate structure, the method further includes forming a buffer dielectric layer covering the gate structure and the exposed surface of the substrate.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The substrate for etching at least one side of the gate structure includes: Remove the buffer dielectric layer on the substrate on at least one side of the gate structure to expose the substrate located on at least one side of the gate structure; The exposed substrate is etched to form the first groove at a first depth, the ratio of the first depth to the stress groove depth being (2~3):

5.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The step of continuing to etch the substrate based on the first groove includes: The substrate exposed by etching the bottom surface of the first groove is then etched to a second depth to form the second groove; Wherein, the first depth is greater than the second depth.

5. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The ion implantation into the sidewall of the first groove includes: Doped ions are implanted at an angle into the sidewall of the first groove to amorphize the substrate in the implantation region, thereby forming the barrier region in the sidewall of the first groove.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, The doped ions include at least one of germanium, carbon, or nitrogen.

7. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The horizontal etching of the sidewalls of the first and second grooves includes: The sidewalls of the first and second grooves are wet-etched; wherein the wet etchant used has a high etching selectivity to the substrate.

8. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The manufacturing method further includes: An epitaxial structure is formed in the stress groove, the epitaxial structure having a double sigma profile.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The barrier region is an amorphized implantation region. During the epitaxial formation of the epitaxial structure in the stress groove, the barrier region recrystallizes into a crystallized implantation region.

10. A semiconductor structure, characterized in that, include: Substrate; A gate structure is disposed on the substrate; An epitaxial structure is disposed in the substrate on at least one side of the gate structure. The epitaxial structure has a double sigma profile. The epitaxial structure includes a first stress structure and a second stress structure disposed below the first stress structure. The first stress structure includes a first sharp corner extending to both sides in a horizontal direction, and the second stress structure includes a second sharp corner extending to both sides in a horizontal direction.

11. The semiconductor structure according to claim 10, characterized in that, Along the horizontal direction, the maximum horizontal width of the first stress structure is the same as the maximum horizontal width of the second stress structure, and the horizontal width of the first sharp corner is the same as that of the second sharp corner.

12. The semiconductor structure according to claim 11, characterized in that, Along a direction perpendicular to the substrate, the height of the first stress structure is greater than the height of the second stress structure.

13. The semiconductor structure according to claim 10, characterized in that, Also includes: The crystallization implantation region is located between the first sharp corner and the second sharp corner in a direction perpendicular to the substrate.

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