Semiconductor structure and method of fabricating the same

Abstract

The application relates to a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure comprises the following steps: firstly forming a first sigma groove, forming a protective layer on the inner wall of the first sigma groove, and etching a second sigma groove below the first sigma groove. In the process of forming the second sigma groove, the existing appearance of the first sigma groove is not damaged or changed, a groove with a double-sigma profile is formed, the formed epitaxial structure has a clear double-sigma profile and has two pairs of sigma sharp corners, the stress can be provided for the channel region below the gate structure, and the carrier mobility of the channel region is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] As integrated circuits evolve to smaller nodes, the feature size of metal-oxide-semiconductor field-effect transistors (MOSFETs) continues to shrink, and the power supply voltage decreases accordingly, leading to a decrease in drive current. Simply scaling down the size of MOSFET devices proportionally is no longer sufficient to meet the performance requirements of MOSFETs. To maintain or improve circuit performance, the industry has introduced strain engineering techniques to enhance the mobility of carriers in the channel region, thereby increasing drive current and switching speed.

[0003] Patent 201310113296.3 provides a method for fabricating a PMOS transistor and an NMOS transistor. This method increases the volume of stress material in the source and drain regions by forming double sigma trenches, while the tip of the lower sigma trench is further from the channel to avoid channel damage, thus achieving a balance between stress intensity and device reliability. However, to protect the morphology of the upper sigma trench, this approach requires repeated filling, etching, and removal of the dielectric, significantly increasing process complexity and cost. It also easily introduces particulate contamination, leading to epitaxial voids and high dislocation density, and potentially even leakage. Secondly, the lower sigma trench is far from the channel, limiting the stress exerted on the channel by its tip. Repeated cleaning and etching processes can damage or passivate the tip of the upper sigma trench, negating the stress gain resulting from the increased volume. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problems in the existing technology.

[0005] To achieve the above objectives, this application provides a method for fabricating a semiconductor structure, comprising the following steps:

[0006] A substrate is provided on which a gate structure is formed;

[0007] The substrate at least one side of the gate structure is etched to form a first groove in the substrate;

[0008] The first groove is etched horizontally to increase its width, forming a first sigma groove;

[0009] A protective layer is formed, which at least covers the sidewalls of the first groove;

[0010] The substrate below the first sigma trench is etched to form a second sigma trench below the first sigma trench.

[0011] In one embodiment, etching the first groove horizontally to form a first sigma groove includes:

[0012] Using a first etchant, the sidewalls of the first sigma trench are wet-etched to expose the substrate, thus forming the first sigma trench.

[0013] In one embodiment, forming the protective layer includes:

[0014] A first epitaxial layer is grown on the surface of the wall of the first sigma groove as the protective layer.

[0015] In one embodiment, etching the substrate below the first sigma trench to form a second sigma trench below the first sigma trench includes:

[0016] The protective layer on the bottom surface of the first sigma trench is etched away to expose the substrate;

[0017] The substrate exposed at the bottom of the first sigma trench is formed by wet etching using a second etchant.

[0018] In one embodiment, the second etchant has a high etch selectivity for the protective layer.

[0019] In one embodiment, the depth of the second sigma groove is greater than the depth of the first sigma groove;

[0020] Along the horizontal direction, the first sigma groove includes a first sharp angle extending to both sides, and the second sigma groove includes a second sharp angle extending to both sides, the horizontal dimension of the second sharp angle being greater than the horizontal dimension of the first sharp angle.

[0021] In one embodiment, prior to etching the substrate on at least one side of the gate structure, the method further includes forming a buffer dielectric layer covering the gate structure and the exposed surface of the substrate.

[0022] In one embodiment, etching the substrate on at least one side of the gate structure includes:

[0023] Remove the buffer dielectric layer on the substrate on at least one side of the gate structure to expose the substrate located on at least one side of the gate structure;

[0024] The exposed substrate is etched to form the first groove.

[0025] In one embodiment, the manufacturing method further includes:

[0026] Stress sublayers are epitaxially grown in the first sigma groove and the second sigma groove, forming a first stress structure in the first sigma groove and a second stress structure in the second sigma groove.

[0027] In one embodiment, the epitaxial growth of stress sublayers in the first sigma groove and the second sigma groove includes:

[0028] An epitaxial first stress sublayer is grown to cover the inner wall of the second sigma trench and the surface of the protective layer;

[0029] A second stress sublayer is epitaxially grown to cover the first stress sublayer;

[0030] A third stress sublayer is epitaxially grown to cover the second stress sublayer and fill the first sigma groove and the second sigma groove.

[0031] The protective layer, the first stress sublayer, the second stress sublayer, and the third stress sublayer in the first sigma groove form the first stress structure;

[0032] The first stress sublayer, the second stress sublayer, and the third stress sublayer in the second sigma groove form the second stress structure.

[0033] Secondly, this application provides a semiconductor structure, comprising:

[0034] Substrate;

[0035] A gate structure is disposed on the substrate;

[0036] An epitaxial structure is disposed in the substrate on at least one side of the gate structure. The epitaxial structure includes a first stress structure and a second stress structure disposed sequentially from the top surface of the substrate downwards. Along the horizontal direction, the first stress structure includes two first sharp corners extending to both sides, and the second stress structure includes two second sharp corners extending to both sides. The horizontal dimension of the second sharp corner is greater than the horizontal dimension of the first sharp corner.

[0037] In one embodiment, the two first sharp corners of the first stress structure point towards the gate structures on both sides, and the two second sharp corners of the second stress structure point towards the gate structures on both sides.

[0038] The first stress structure and the second stress structure apply the same stress to the gate structure.

[0039] In one embodiment, the height of the first stress structure is less than the height of the second stress structure along the thickness direction of the substrate.

[0040] In one embodiment, along a cross section perpendicular to the substrate, the first stress structure includes a protective layer, a first stress sublayer, a second stress sublayer, and a third stress sublayer disposed sequentially from the outside to the inside.

[0041] The second stress structure includes a first stress sublayer, a second stress sublayer, and a third stress sublayer arranged sequentially from the outside to the inside.

[0042] The semiconductor structure and its fabrication method of this application have the following unexpected effects: by first forming a first sigma trench, forming a protective layer on the inner wall of the first sigma trench, and then etching a second sigma trench below the first sigma trench, the existing morphology of the first sigma trench is not damaged or changed during the formation of the second sigma trench, thereby forming a trench with a double sigma profile. This results in an epitaxial structure with a clear double sigma profile and two pairs of sigma sharp corners, which can provide stress to the channel region below the gate structure, thereby improving the carrier mobility of the channel region. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a process flow diagram of a method for fabricating a semiconductor structure provided in one embodiment;

[0045] Figure 2 This is a schematic diagram of the structure after the buffer medium layer is formed, as provided in one embodiment;

[0046] Figure 3 This is a schematic diagram of the structure after a patterned photoresist layer has been formed, as provided in one embodiment.

[0047] Figure 4 This is a schematic diagram of the structure after the first groove is formed, provided in one embodiment;

[0048] Figure 5 This is a schematic diagram of the structure after a first sigma groove is formed by etching a first groove along the horizontal direction in one embodiment;

[0049] Figure 6 This is a schematic diagram of the structure after a protective layer is formed on the wall of the first sigma groove, as provided in one embodiment.

[0050] Figure 7This is a schematic diagram of the structure after removing the protective layer on the bottom surface of the first sigma groove in one embodiment;

[0051] Figure 8 This is a schematic diagram of the structure after the formation of the second sigma groove in one embodiment;

[0052] Figure 9 This is a schematic diagram of the structure after the epitaxial structure is formed, as provided in one embodiment;

[0053] Figure 10 This is a schematic diagram of the structure after removing the buffer medium layer in one embodiment.

[0054] Figure 11 This is a schematic diagram of the structure after the formation of a metal silicide layer in one embodiment.

[0055] Explanation of reference numerals in the attached figures:

[0056] 21. Substrate; 22. Gate structure; 221. Gate dielectric layer; 222. Gate conductive layer; 231. First insulating layer; 232. Second insulating layer; 24. Photoresist layer; 25. Buffer dielectric layer; 26a. First trench; 26. First sigma trench; 27. Second sigma trench; 29. ​​Protective layer;

[0057] 30. Epitaxial structure; 301. First stress sublayer; 302. Second stress sublayer; 303. Third stress sublayer; 31. First stress structure; 32. Second stress structure; 33. First sharp corner; 34. Second sharp corner; 41. Metal silicide layer. Detailed Implementation

[0058] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0060] Among the relevant solutions, embedded germanium-silicon source-drain technology still has many shortcomings. In particular, the stress increase of the germanium-silicon epitaxial layer on the channel has approached its limit. How to further enhance the stress applied to the channel to meet the higher requirements of the next generation of high-performance devices for carrier mobility is a technical problem that urgently needs to be solved in this field.

[0061] According to an exemplary embodiment, this embodiment provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the method for fabricating a semiconductor structure includes the following steps:

[0062] Step S101: Provide a substrate 21, on which a gate structure 22 is formed.

[0063] Step S102: Etch at least one side of the substrate 21 of the gate structure 22 to form a first groove 26a in the substrate 21.

[0064] Step S103: Etch the first groove 26a along the horizontal direction to increase the width of the first groove 26a, forming a first sigma groove 26. In this embodiment, a first wet etching is performed to etch the first groove 26a along the horizontal direction to form the first sigma groove 26.

[0065] Step S104: Form a protective layer 29, which at least covers the sidewall of the first groove 26a.

[0066] In this embodiment, an epitaxial process can be used to form a protective layer 29 on the sidewall of the first groove 26a. The protective layer 29 has a high etching selectivity relative to the substrate 21.

[0067] Step S105: Etch the substrate 21 below the first sigma trench 26 to form a second sigma trench 27 below the first sigma trench 26.

[0068] In this embodiment, the sidewall of the first groove 26a is protected by a protective layer 29, and a second wet etching is performed to etch the substrate 21 below the first groove 26a, forming a second sigma groove 27 that communicates with it below the first sigma groove 26.

[0069] The semiconductor structure fabrication method of this embodiment first forms a first sigma trench 26, forms a protective layer 29 on the inner wall of the first sigma trench 26, and then etches a second sigma trench 27 below the first sigma trench 26. Thus, the existing morphology of the first sigma trench 26 is not damaged or changed during the formation of the second sigma trench 27, thereby forming a trench with a double sigma profile. This results in the epitaxial structure 30 having a clear double sigma profile with two pairs of upper and lower sigma sharp corners, which can provide stress to the channel region below the gate structure 22, thereby improving the carrier mobility of the channel region.

[0070] Below, based on the appendix Figures 2-11 The method for fabricating the semiconductor structure in this embodiment will be described in detail.

[0071] In step S101, refer to Figure 2The substrate 21 can be a semiconductor substrate, and the material of the semiconductor substrate can include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other III / V or II / VI semiconductor materials. Alternatively, for example, the semiconductor substrate can be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator. In this embodiment, the substrate 21 is a silicon substrate.

[0072] Reference Figure 2 The gate structure 22 is disposed on the substrate 21. The gate structure 22 may include a gate dielectric layer 221 and a gate conductive layer 222 stacked on the substrate 21. For example, the material of the gate dielectric layer 221 may include silicon oxide; the gate conductive layer 222 may be made of a low-resistance metal material such as tungsten (W), aluminum (Al), or copper (Cu).

[0073] In some other embodiments, a high-k dielectric layer (not shown) is further disposed between the gate dielectric layer 221 and the gate conductive layer 222. The material of the high-k dielectric layer may include hafnium oxide (HfO2) or hafnium silicon oxide (HfSiO2). x ), hafnium zirconium oxide (HfZrO) x Materials with high dielectric constants, such as alumina (AlO).

[0074] Furthermore, the gate structure 22 is covered by an insulating layer, which may be covered with a single layer or multiple layers of insulating layers. The material of each insulating layer may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0075] In this embodiment, refer to Figure 2 A first insulating layer 231 and a second insulating layer 232 are sequentially covered on the gate structure 22. The first insulating layer 231 is made of silicon nitride, and the second insulating layer 232 is made of silicon oxide.

[0076] In this embodiment, a plurality of gate structures 22 may be disposed on the substrate 21 at intervals, and the substrate 21 between two adjacent gate structures 22 is exposed.

[0077] In some embodiments, before etching the substrate 21 on at least one side of the gate structure 22, step S101-1 is performed: forming a buffer dielectric layer 25 to cover the exposed surfaces of the gate structure 22 and the substrate 21.

[0078] In this embodiment, refer to Figure 2A buffer dielectric layer 25 is deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The buffer dielectric layer 25 covers the insulating layer on the surface of the gate structure 22 and the exposed surface of the substrate 21.

[0079] The material of the buffer dielectric layer 25 has a high etch selectivity relative to the second insulating layer 232 on the surface of the gate structure 22; for example, the material of the buffer dielectric layer 25 may include silicon nitride.

[0080] To improve control accuracy and ensure that the horizontal width of the formed stress groove meets design expectations, this embodiment deposits a thicker buffer medium layer 25 compared to the scheme of forming single-sigma topography trenches. Generally, the thickness of the buffer medium layer 25 formed in the single-sigma topography trench is d0. Therefore, the thickness of the buffer medium layer 25 formed in this embodiment is 1.3 times d0 to 1.8 times d0. For example, it can be 1.3 times d0, 1.4 times d0, 1.5 times d0, 1.6 times d0, 1.7 times d0, or 1.8 times d0.

[0081] In step S102, refer to Figure 3 The substrate 21 on at least one side of the gate structure 22 is etched away, forming a first groove 26a on at least one side of the gate structure 22. In this embodiment, both sides of the gate structure 22 are etched to form a first groove 26a on each side of the gate structure 22.

[0082] For example, a dry etching process can be used to etch the substrate 21 to form the first groove 26a.

[0083] In some embodiments, step S102 etching the substrate 21 on at least one side of the gate structure 22 includes steps S1021-S1022.

[0084] Step S1021: Remove the buffer dielectric layer 25 on at least one side of the substrate 21 of the gate structure 22 to expose the substrate 21 located on at least one side of the gate structure 22.

[0085] Reference Figure 3 First, a photoresist material is coated to cover the buffer dielectric layer 25, forming a photoresist layer 24. The photoresist layer 24 is then patterned and developed to expose the areas that need to be etched to form stress grooves. Then, referring to… Figure 4 The patterned buffer dielectric layer 25 is etched using an anisotropic etching process. The buffer dielectric layer 25 located on the substrate 21 between the gate structures 22 and the buffer dielectric layer 25 on the top surface of the gate are also etched. Due to the anisotropic etching process, the buffer dielectric layer 25 on the sidewall of the gate structure 22 is retained.

[0086] Step S1022: Etch the exposed substrate 21 to form the first groove 26a.

[0087] In this embodiment, refer to Figure 4 Using the buffer dielectric layer 25 retained on the sidewalls of the gate structure 22 as a self-aligned hard mask, a first dry etching is performed on the exposed substrate 21. By controlling the etching time and process parameters, the substrate 21 is etched vertically to a first depth to form a first groove 26a. The first groove 26a has a sidewall profile that is substantially perpendicular to the surface of the substrate 21.

[0088] For example, a reactive ion etching process containing fluorine-based gases can be used, and the etching gas can be selected from at least one of sulfur hexafluoride (SF6) and carbon tetrafluoride (CF4).

[0089] The first depth is determined based on the total depth of the stress groove to be formed. For example, the first depth is one-fifth to two-fifths of the total depth of the stress groove, i.e., the ratio of the first depth to the total depth of the stress groove is (1~2):5. In this embodiment, the first depth is approximately two-fifths of the total depth of the stress groove.

[0090] Reference Figure 5 Before etching the first groove 26a in the horizontal direction in step S103, residual photoresist layer 24 and byproducts of dry etching are removed by cleaning. For example, a solution containing caros acid can be used for cleaning. The caros acid mixture is prepared from concentrated sulfuric acid (H2SO4) and hydrogen peroxide (H2O2).

[0091] In step S103, refer to Figure 5 The first groove 26a is etched in the horizontal direction to form a first sigma groove 26, including: using a first etchant to wet etch the sidewall of the first sigma groove 26 to expose the substrate 21, thereby forming the first sigma groove 26.

[0092] The first etchant can be an etchant containing tetramethylammonium hydroxide (TMAH) solution. The tetramethylammonium hydroxide solution has different etching rates for different crystal orientations of the substrate 21. The etching rate of the Si{111} crystal plane is much lower than that of the Si{100} and Si{110} crystal planes. Therefore, it can selectively laterally etch the sidewalls of the first groove 26a along a specific crystal orientation, increase the width of the first groove 26a, and form a first sigma groove 26.

[0093] In some embodiments, step S104 forming a protective layer 29 includes: epitaxially growing a first epitaxial layer on the surface of the wall of the first sigma trench 26 as the protective layer 29.

[0094] In this embodiment, refer to Figure 6 The substrate 21 is a silicon substrate, and the material of the first epitaxial layer is germanium silicon. A selective epitaxial growth process is used so that the first epitaxial layer grows only on the surface of the substrate 21 exposed by the first sigma trench 26.

[0095] In this embodiment, the molar percentage of germanium in the first epitaxial layer is between 20% and 30%, for example, approximately 20%, 25%, 28%, or 30%. This allows the first epitaxial layer to have an extremely high etching selectivity relative to the substrate 21 during the subsequent second wet etching process, thereby effectively protecting the substrate 21 on the sidewalls of the first sigma trench 26 from etching damage, thus ensuring that the outline of the first sigma trench 26 is clear and complete.

[0096] The thickness of the first epitaxial layer should not be too thick, so as not to occupy too much internal space of the first sigma trench 26 and affect the filling of subsequent stress materials; at the same time, it should not be too thin, so as to ensure that it is not completely consumed or broken down during subsequent dry etching and wet etching processes.

[0097] For example, refer to Figure 9 As shown, the thickness of the first epitaxial layer can be 10% to 30% of the preset thickness of the first stress sublayer 301 formed in the second sigma trench 27 in the subsequent epitaxial growth process. For example, the thickness of the first epitaxial layer can be about 10%, 15%, 20%, 25% or 30% of the preset thickness of the first stress sublayer 301 formed in the second sigma trench 27.

[0098] In other embodiments, the protective layer 29 can also be formed by deposition, and the protective layer 29 can be removed by etching after the second sigma groove 27 is formed by subsequent etching.

[0099] In some embodiments, step S105 etches the substrate 21 below the first sigma trench 26 and forms a second sigma trench 27 below the first sigma trench 26, including steps S1051-S1052.

[0100] Step S1051: Etch away the protective layer 29 on the bottom surface of the first sigma trench 26 to expose the substrate 21.

[0101] In this embodiment, refer to Figure 7 The protective layer 29 is etched using an anisotropic dry etching process. The etching stops at the surface of the substrate 21 by utilizing the etching selectivity between the first epitaxial layer and the substrate 21.

[0102] Due to the anisotropic nature of the etching process, the plasma mainly bombards along a direction perpendicular to the surface of the substrate 21, removing the first epitaxial layer located on the bottom surface of the first sigma trench 26. The first epitaxial layer located on the sidewall of the first sigma trench 26 is less bombarded due to its larger tilt angle and is thus preserved intact.

[0103] In step S1052, a second etchant is used to wet-etch the substrate 21 exposed at the bottom surface of the first sigma trench 26 to form the second sigma trench 27. The second etchant has a high etch selectivity for the protective layer 29.

[0104] In this embodiment, refer to Figure 8 The substrate 21 exposed by the first sigma trench 26 is wet-etched using a second etchant to form a second sigma trench 27. The first sigma trench 26 and the second sigma trench 27 are connected to form a stress trench with a double sigma profile.

[0105] For example, the second etchant can be an etchant containing a tetramethylammonium hydroxide (TMAH) solution.

[0106] Reference Figure 8 During this wet etching process, due to the high etching selectivity of the second etchant for the first epitaxial layer, the etching rate of the first epitaxial layer is much lower than the etching rate of the substrate 21. Therefore, the second etchant only acts on the substrate 21 exposed at the bottom surface of the first sigma trench 26. Furthermore, the etching rate of the second etchant on the Si{111} crystal plane is much lower than the etching rate on the Si{100} and Si{110} crystal planes. The second etchant selectively etches downwards and outwards along the Si{100} and Si{110} planes of the substrate 21. The lower etching rate of the Si{111} plane hinders the etching by the second etchant, thereby forming the inclined sidewalls and sharp corners of the second sigma trench 27.

[0107] During the second wet etching process, the sidewalls and sharp corners of the first sigma groove 26 are completely covered and protected by the first epitaxial layer, and are basically not eroded, thus protecting the sigma morphology of the first sigma groove 26.

[0108] It should be noted that the second sigma trench 27 formed in this application is larger in volume than the first sigma trench 26, which is achieved by adjusting the etching conditions. In this embodiment, since there is no film layer constraint in the lateral direction, the lateral etching depth and longitudinal etching depth of the second sigma trench 27 can be controlled by adjusting the duration of wet etching with the second etchant, thereby adjusting the target volume of the second sigma trench 27 according to stress requirements.

[0109] It is understandable that the first sigma trench 26 has boundary constraints on both sides of the gate and ion implantation regions, resulting in a very small adjustable range for its size and a limited volume, which in turn limits the stress applied to the channel region by the first sigma trench 26. In contrast, the second sigma trench 27 does not have boundary constraints on both sides of the gate and ion implantation regions, and its adjustable range for size is larger than that of the first sigma trench 26. Therefore, this application sets the volume of the second sigma trench 27 to be larger, thereby improving the situation of insufficient stress in the first sigma trench 26.

[0110] In some embodiments, refer to Figure 8 The depth of the second sigma groove 27 is greater than the depth of the first sigma groove 26. In this embodiment, the depth ratio of the first sigma groove 26 to the second sigma groove 27 is 2:3.

[0111] Along the horizontal direction (parallel to the substrate 21), the first sigma trench 26 includes first sharp corners 33 extending to both sides, and the second sigma trench 27 includes second sharp corners 34 extending to both sides. The horizontal dimension of the second sharp corners 34 is greater than the horizontal dimension of the first sharp corners 33. The first sigma trench 26 has two first sharp corners 33 extending horizontally toward the gate structures 22 on both sides, and the horizontal extension dimension of the first sharp corners 33 is a first length. The second sigma trench 27 has two second sharp corners 34 extending horizontally toward the gate structures 22 on both sides, and the horizontal extension dimension of the second sharp corners 34 is a second length. The second length is greater than the first length.

[0112] In this way, the first sigma trench 26 is relatively shallow, the first spur 33 has a smaller horizontal dimension, and the first spur 33 is closer to the channel region directly below the gate structure 22. The second sigma trench 27 is deeper, the second spur 34 has a larger horizontal dimension, and the second spur 34 is farther away from the channel region. By making the second sigma trench 27, which is farther away from the channel, larger, the stress of the stress structure in the second sigma trench 27 on the channel region can be increased, and the stress superposition of the stress structure in the first sigma trench 26 and the second sigma trench 27 can be increased, thereby improving the carrier mobility of the channel region.

[0113] In some embodiments, the method for fabricating a semiconductor structure further includes step S106 after step S105: epitaxially growing stress sublayers in a first sigma trench 26 and a second sigma trench 27, forming a first stress structure 31 in the first sigma trench 26, and forming a second stress structure 32 in the second sigma trench 27.

[0114] In this embodiment, refer to Figure 9A stress sublayer is epitaxially grown in the first sigma trench 26 and the second sigma trench 27 using a selective epitaxial growth process to form a first stress structure 31 and a second stress structure 32. The materials of the first stress structure 31 and the second stress structure 32 may include germanium-silicon, boron-doped germanium-silicon, or other semiconductor materials capable of applying compressive stress to the channel region. Exemplarily, the first stress structure 31 and the second stress structure 32 include a germanium-silicon epitaxial layer.

[0115] Since epitaxial growth is performed within trenches with a double-sigma profile, the resulting epitaxial structure 30 also has a double-sigma profile. The epitaxial structure 30 includes a first stress structure 31 located in the first sigma trench 26 and a second stress structure 32 located in the second sigma trench 27. The first stress structure 31 and the second stress structure 32 simultaneously apply compressive stress to the channel region, forming a stress superposition effect, thereby enhancing the overall stress acting on the channel region. The cumulative stress generated in the channel region is twice that of the single-sigma structure, which can significantly improve the carrier mobility of the PMOS device.

[0116] In some embodiments, stress sublayers are epitaxially grown in the first sigma groove 26 and the second sigma groove 27, including:

[0117] Step S1061: Epitaxially grow the first stress sublayer 301 to cover the inner wall of the second sigma groove 27 and the surface of the protective layer 29.

[0118] Reference Figure 9 The first epitaxial growth process is performed, and the first stress sublayer 301 is grown simultaneously in the first sigma groove 26 and the second sigma groove 27.

[0119] In the second sigma trench 27, the first stress sublayer 301 grows directly on the surface of the exposed substrate 21; in the first sigma trench 26, the first stress sublayer 301 grows on the surface of the previously formed protective layer 29 (first epitaxial layer). However, under limited reaction chamber space and gas flow, the epitaxial reaction rate in the first sigma trench 26 tends to saturate / slow down due to surface coverage, while nucleation growth on the exposed silicon surface of the second sigma trench 27 is faster, and the growth of the first stress sublayer 301 in the first sigma trench 26 is relatively lagging. This results in the first stress sublayer 301 in the second sigma trench 27 reaching a preset thickness, while the thickness of the first stress sublayer 301 in the first sigma trench 26 is thinner than that in the second sigma trench 27. This provides a larger process window for the subsequent second stress sublayer 302 and third stress sublayer 303, ensuring the structural integrity of the formed first stress structure 31 and second stress structure 32 without incomplete filling defects.

[0120] Step S1062: Epitaxially grow the second stress sublayer 302 to cover the first stress sublayer 301.

[0121] Reference Figure 9 A second epitaxial growth process is then performed to grow a second stress sublayer 302 on the surface of the first stress sublayer 301. In this embodiment, the germanium content of the second stress sublayer 302 can be gradient-adjusted according to stress design requirements, for example, lower or higher than the germanium content of the first stress sublayer 301, to achieve a better stress distribution.

[0122] Step S1063: Epitaxially grow the third stress sublayer 303, covering the second stress sublayer 302, and filling the first sigma groove 26 and the second sigma groove 27.

[0123] Reference Figure 9 A third epitaxial growth process is then performed to grow a third stress sublayer 303 on the surface of the second stress sublayer 302. Epitaxial growth continues until the third stress sublayer 303 completely fills the remaining space of the first sigma trench 26 and the second sigma trench 27. In this embodiment, the top surface of the third stress sublayer 303 is slightly higher than the original surface of the substrate 21 to facilitate the subsequent formation of the metal silicide layer 41.

[0124] Thus, the protective layer 29, the first stress sublayer 301, the second stress sublayer 302, and the third stress sublayer 303 in the first sigma trench 26 form the first stress structure 31; the first stress sublayer 301, the second stress sublayer 302, and the third stress sublayer 303 in the second sigma trench 27 form the second stress structure 32. The first stress structure 31 and the second stress structure 32 together serve as the source and / or drain of the device.

[0125] It is understandable that after the first stress sublayer 301 is grown, the protective layer 29 in the first sigma trench 26 and the first stress sublayer 301 together serve as the bottom germanium-silicon layer of the first stress structure 31. Although the thickness of the first stress sublayer 301 in the first sigma trench 26 is less than the thickness of the first stress sublayer 301 in the second sigma trench 27, the thickness of the bottom germanium-silicon layer (outermost layer in the figure) in the first sigma trench 26 is greater than that in the second sigma trench 27 because the protective layer 29 (first epitaxial layer) is pre-existing in the first sigma trench 26. The bottom germanium-silicon layer (the outermost layer in the figure) in the sigma trench is the main structure for applying stress. The bottom germanium-silicon layer for applying stress in the first sigma trench 26 is thicker, which can compensate for the differences in volume and apex depth between the first sigma trench 26 and the second sigma trench 27. This ensures that after the second stress sublayer 302 and the third stress sublayer 303 are filled, the stress applied to the channel region by the first stress structure 31 and the second stress structure 32 tends to be consistent, thus improving the stress cancellation problem caused by volume mismatch in the stress structure of the double sigma morphology.

[0126] For example, the thickness of the protective layer 29 is approximately 10% to 30% of the thickness of the first stress sublayer 301 in the second sigma groove 27.

[0127] In some embodiments, refer to Figure 9 The germanium content, doping concentration, and thickness of the first stress sublayer 301, the second stress sublayer 302, and the third stress sublayer 303 can be adjusted. For example, the first stress sublayer 301, which is closer to the channel region, can use a higher germanium content to provide greater short-range stress, while the third stress sublayer 303, which fills the center of the trench, can use a lower germanium content.

[0128] In some embodiments, the material of the protective layer 29 is the same as that of the first stress sublayer 301, that is, the germanium content and doping concentration of the protective layer 29 and the first stress sublayer 301 are the same. The protective layer 29 and the first stress sublayer 301 in the first sigma trench 26 together serve as a structure for applying short-range stress to the channel.

[0129] This can be understood as follows: the epitaxial structure 30 formed in this embodiment includes three germanium-silicon layers: outer, middle, and inner. The formation step of the outermost germanium-silicon layer of the first stress structure 31 is divided into two sub-steps. First, a first epitaxial layer is formed as a protective layer 29. After the second sigma trench 27 is formed, the protective layer 29 is not removed. The first stress sub-layer 301 formed epitaxially serves as the second part of the outermost germanium-silicon layer of the first stress structure 31. In other words, this embodiment forms the outermost bottom germanium-silicon layer of the first stress structure 31 in two steps. The first part of the bottom germanium-silicon layer of the first stress structure 31 formed in the first step serves as a protective layer 29, which is used to protect the first sigma trench 26 from damage during the formation of the second sigma trench 27, thereby protecting the sigma morphology of the first sigma trench 26.

[0130] In this embodiment, the protective layer 29 is made of germanium-silicon material that is the same as or similar to the first stress sublayer 301. During the formation of the second sigma trench 27, the protective layer 29 is used to protect the complete morphology of the first sigma trench 26. After the formation of the second sigma trench 27, there is no need to remove the protective layer 29. The first stress sublayer 301 can be directly epitaxially grown. The protective layer 29 participates in the subsequent stress construction as part of the bottom sublayer of the first stress structure 31, saving a removal process. The stress of the protective layer 29 itself is used to enhance the overall stress of the first stress structure 31 on the channel.

[0131] In other embodiments, the epitaxial structure 30 may include a single-component germanium-silicon layer, or a two-layer, four-layer, or other germanium-silicon layer.

[0132] In this embodiment, after forming the epitaxial structure 30, ion implantation of the source and / or drain can be performed to reduce the ohmic contact of the source and / or drain.

[0133] In this embodiment, after forming the epitaxial structure 30, refer to Figure 11 Alternatively, the entire buffer dielectric layer 25 can be removed, exposing the sidewalls of the gate structure 22 and the surface of the substrate 21. For example, the buffer dielectric layer 25 can be removed by cleaning with a hot phosphoric acid solution or by etching with a dry etching process. This provides a clean process surface for subsequent processes.

[0134] Reference Figure 11 After removing all the buffer dielectric layer 25, a self-aligned metal silicide layer 41 can be formed. A full-length metal layer can be deposited to cover the surface of the third stress sublayer 303, and the semiconductor structure can be thermally treated to allow the portion of the metal layer in contact with the third stress sublayer 303 to react and form the metal silicide layer 41, thereby reducing contact resistance. Afterwards, the metal layer that did not react with the third stress sublayer 303 is etched away.

[0135] In some other embodiments, the polysilicon dummy gate layer formed on the substrate 21 in step S101 is not the gate structure 22, but a placeholder polysilicon dummy gate layer. In this embodiment, after removing the remaining buffer dielectric layer 25, the polysilicon dummy gate layer is etched away, and the gate structure 22 is formed in the original position of the polysilicon dummy gate layer.

[0136] According to an exemplary embodiment, this embodiment provides a semiconductor structure, with reference to... Figure 10 , Figure 11 As shown, the semiconductor structure includes a substrate 21, a gate structure 22, and an epitaxial structure 30. In this embodiment, the semiconductor structure may include a PMOS device, the gate structure 22 is the gate structure 22 of the PMOS device, and at least one epitaxial structure 30 may be the source and / or drain of the PMOS device.

[0137] A gate structure 22 is disposed on a substrate 21. The gate structure 22 may include a gate dielectric layer 221 and a gate conductive layer 222 stacked on the substrate 21. For example, the material of the gate dielectric layer 221 may include silicon oxide; the gate conductive layer 222 may be made of a low-resistance metal material such as tungsten (W), aluminum (Al), or copper (Cu).

[0138] In some other embodiments, a high-k dielectric layer is further disposed between the gate dielectric layer 221 and the gate conductive layer 222, wherein the material of the high-k dielectric layer may include hafnium oxide (HfO2) or hafnium silicon oxide (HfSiO2). x ), hafnium zirconium oxide (HfZrO) x Materials with high dielectric constants, such as alumina (AlO).

[0139] Furthermore, the gate structure 22 is covered by an insulating layer, which may be covered with a single layer or multiple layers of insulating layers. The material of each insulating layer may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, a first insulating layer 231 and a second insulating layer 232 are sequentially covered on the gate structure 22. The first insulating layer 231 is made of silicon nitride, and the second insulating layer 232 is made of silicon oxide.

[0140] In this embodiment, a plurality of gate structures 22 may be disposed at intervals on the substrate 21.

[0141] The epitaxial structure 30 is disposed in the substrate 21 on at least one side of the gate structure 22. The epitaxial structure 30 has a double sigma profile. In this embodiment, a double sigma profile epitaxial structure 30 can be disposed on each side of the gate structure 22.

[0142] The double sigma profile refers to the fact that, in a cross-sectional view of the extension structure 30 along the length direction (horizontal direction) of the channel, the sidewall of the extension structure 30 near the channel region has two sigma-shaped sharp corners pointing towards the channel region.

[0143] Reference Figure 10 , Figure 11 As shown, the epitaxial structure 30 includes a first stress structure 31 and a second stress structure 32 sequentially disposed from the top surface of the substrate 21 downwards. In the horizontal direction, the first stress structure 31 includes two first sharp corners 33 extending to both sides, and the second stress structure 32 includes two second sharp corners 34 extending to both sides. The horizontal dimension of the second sharp corners 34 is greater than the horizontal dimension of the first sharp corners 33. One sidewall of the epitaxial structure 30 has upper and lower spaced first sharp corners 33 and second sharp corners 34, which together superimpose stress onto the channel region below the gate structure 22.

[0144] In this embodiment, the semiconductor structure, the epitaxial structure 30 includes a first stress structure 31 located in the first sigma trench 26 and a second stress structure 32 located in the second sigma trench 27. The first stress structure 31 and the second stress structure 32 simultaneously apply compressive stress to the channel region, forming a stress superposition effect, thereby enhancing the overall stress acting on the channel region. The cumulative stress generated in the channel region is twice that of the single sigma structure, which can significantly improve the carrier mobility of the PMOS device.

[0145] In some embodiments, refer to Figure 10 , Figure 11 As shown, along the thickness direction of the substrate 21, the height of the first stress structure 31 is less than the height of the second stress structure 32. In this embodiment, the depth ratio of the first sigma trench 26 to the second sigma trench 27 is 2:3.

[0146] In this way, the first sigma trench 26 is relatively shallow, the first spur 33 has a smaller horizontal dimension, and the first spur 33 is closer to the channel region directly below the gate structure 22. The second sigma trench 27 is deeper, the second spur 34 has a larger horizontal dimension, and the second spur 34 is farther away from the channel region. By making the second sigma trench 27, which is farther away from the channel, larger, the stress of the stress structure in the second sigma trench 27 on the channel region can be increased, and the stress superposition of the stress structure in the first sigma trench 26 and the second sigma trench 27 can be increased, thereby improving the carrier mobility of the channel region.

[0147] In some embodiments, refer to Figure 10 , Figure 11 As shown, the two first sharp corners 33 of the first stress structure 31 point towards the gate structures 22 on both sides, that is, towards the channel, and the two second sharp corners 34 of the second stress structure 32 point towards the gate structures 22 on both sides; the first stress structure 31 and the second stress structure 32 apply the same stress to the gate structure 22.

[0148] It is understood that the statement in this application that "the first stress structure 31 and the second stress structure 32 apply the same stress to the gate structure 22" means that the stress nature and direction of the stress generated by the two on the channel are completely consistent, and their stress intensity remains highly similar within the process tolerance range, that is, "basically the same".

[0149] In some embodiments, refer to Figure 10 , Figure 11 As shown, along a cross section perpendicular to the substrate 21, the first stress structure 31 includes a protective layer 29, a first stress sublayer 301, a second stress sublayer 302, and a third stress sublayer 303 arranged sequentially from the outside to the inside; the second stress structure 32 includes a first stress sublayer 301, a second stress sublayer 302, and a third stress sublayer 303 arranged sequentially from the outside to the inside.

[0150] In some embodiments, the material of the protective layer 29 is the same as that of the first stress sublayer 301, that is, the germanium content and doping concentration of the protective layer 29 and the first stress sublayer 301 are the same. The protective layer 29 and the first stress sublayer 301 in the first sigma trench 26 together serve as a structure for applying short-range stress to the channel.

[0151] For example, the thickness of the protective layer 29 is approximately 10% to 30% of the thickness of the first stress sublayer 301 in the second sigma trench 27. The thickness of the first stress sublayer 301 in the first sigma trench 26 is greater than the thickness of the first stress sublayer 301 in the second sigma trench 27. The protective layer 29 and the first stress sublayer 301 in the first sigma trench 26 together serve as the bottom germanium-silicon layer that primarily applies stress to the channel in the first stress structure 31, and the total thickness of the protective layer 29 and the first stress sublayer 301 in the first sigma trench 26 is greater than the thickness of the first stress sublayer 301 in the second sigma trench 27.

[0152] In this way, the volume of the first stress structure 31 is smaller than that of the second stress volume, but the thickness of the film layer on which the first stress structure 31 mainly applies stress is thicker than that of the film layer on which the second stress structure 32 mainly applies stress. This thickness difference compensates for the stress attenuation caused by the larger horizontal dimension of the second sharp corner 34 of the second stress volume, so that the stress on the channel by the first stress structure 31 and the second stress structure 32 tends to be consistent, and finally achieves a stress superposition effect twice that of the traditional single sigma topography structure.

[0153] In some embodiments, refer to Figure 10 , Figure 11 As shown, parameters such as germanium content, doping concentration, and thickness in the first stress sublayer 301, second stress sublayer 302, and third stress sublayer 303 can be adjusted. For example, the first stress sublayer 301, which is closer to the channel region, can use a higher germanium content to provide greater short-range stress, while the third stress sublayer 303, which fills the center of the trench, can use a lower germanium content.

[0154] In other embodiments, the epitaxial structure 30 may also include a single-layer, two-layer, or four-layer stress sublayer, and the materials of each stress sublayer may be the same or different.

[0155] The semiconductor structure and its fabrication method of this application have the following unexpected effects: by first forming a first sigma trench 26, forming a protective layer 29 on the inner wall of the first sigma trench 26, and then etching a second sigma trench 27 below the first sigma trench 26, the existing morphology of the first sigma trench 26 is not damaged or changed during the formation of the second sigma trench 27, thereby forming a trench with a double sigma profile, so that the epitaxial structure 30 has a clear double sigma profile with two sigma sharp corners, which can provide stress to the channel region below the gate structure 22, thereby improving the carrier mobility of the channel region.

[0156] The semiconductor structure fabrication method of this application has a simple process flow, without repeated steps of depositing, etching, and removing dielectric materials, thus avoiding the introduction of particulate contamination and organic residues, thereby preventing poor contact or leakage, and greatly improving the process window and mass production yield. This application utilizes a protective layer 29 formed by epitaxial growth as a shielding layer for the first sigma trench 26, using the protective layer 29 to protect the morphology of the first sigma trench 26. The protective layer 29 can then be used to form the first stress structure 31, avoiding repeated cleaning and etching of the first sigma trench 26, preventing the sharp corners of the first sigma trench 26 from being blunted or damaged, and maximizing the preservation of the stress exerted on the channel by the sharp corners of the first stress structure 31.

[0157] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0158] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided on which a gate structure is formed; The substrate at least one side of the gate structure is etched to form a first groove in the substrate; The first groove is etched horizontally to increase its width, forming a first sigma groove; A protective layer is formed, which at least covers the sidewalls of the first groove; The substrate below the first sigma trench is etched to form a second sigma trench below the first sigma trench.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The etching of the first groove along the horizontal direction to form a first sigma groove includes: Using a first etchant, the sidewalls of the first sigma trench are wet-etched to expose the substrate, thus forming the first sigma trench.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The formation of the protective layer includes: A first epitaxial layer is grown on the surface of the wall of the first sigma groove as the protective layer.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The etching of the substrate below the first sigma trench, and the formation of a second sigma trench below the first sigma trench, includes: The protective layer on the bottom surface of the first sigma trench is etched away to expose the substrate; The substrate exposed at the bottom of the first sigma trench is formed by wet etching using a second etchant.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The second etchant has a high etch selectivity for the protective layer.

6. The method for fabricating a semiconductor structure according to any one of claims 1-5, characterized in that, The depth of the second sigma groove is greater than the depth of the first sigma groove; Along the horizontal direction, the first sigma groove includes a first sharp angle extending to both sides, and the second sigma groove includes a second sharp angle extending to both sides, the horizontal dimension of the second sharp angle being greater than the horizontal dimension of the first sharp angle.

7. The method for fabricating a semiconductor structure according to any one of claims 1-5, characterized in that, Before etching the substrate on at least one side of the gate structure, the method further includes forming a buffer dielectric layer covering the gate structure and the exposed surface of the substrate.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The substrate for etching at least one side of the gate structure includes: Remove the buffer dielectric layer on the substrate on at least one side of the gate structure to expose the substrate located on at least one side of the gate structure; The exposed substrate is etched to form the first groove.

9. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The manufacturing method further includes: Stress sublayers are epitaxially grown in the first sigma groove and the second sigma groove, forming a first stress structure in the first sigma groove and a second stress structure in the second sigma groove.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The epitaxial growth of stress sublayers in the first sigma groove and the second sigma groove includes: An epitaxial first stress sublayer is grown to cover the inner wall of the second sigma trench and the surface of the protective layer; A second stress sublayer is epitaxially grown to cover the first stress sublayer; A third stress sublayer is epitaxially grown to cover the second stress sublayer and fill the first sigma groove and the second sigma groove. The protective layer, the first stress sublayer, the second stress sublayer, and the third stress sublayer in the first sigma groove form the first stress structure; The first stress sublayer, the second stress sublayer, and the third stress sublayer in the second sigma groove form the second stress structure.

11. A semiconductor structure, characterized in that, include: Substrate; A gate structure is disposed on the substrate; An epitaxial structure is disposed in the substrate on at least one side of the gate structure. The epitaxial structure includes a first stress structure and a second stress structure disposed sequentially from the top surface of the substrate downwards. Along the horizontal direction, the first stress structure includes two first sharp corners extending to both sides, and the second stress structure includes two second sharp corners extending to both sides. The horizontal dimension of the second sharp corner is greater than the horizontal dimension of the first sharp corner.

12. The semiconductor structure according to claim 11, characterized in that, The two first sharp corners of the first stress structure point towards the gate structures on both sides, and the two second sharp corners of the second stress structure point towards the gate structures on both sides. The first stress structure and the second stress structure apply the same stress to the gate structure.

13. The semiconductor structure according to claim 11, characterized in that, Along the thickness direction of the substrate, the height of the first stress structure is less than the height of the second stress structure.

14. The semiconductor structure according to claim 11, characterized in that, Along a cross section perpendicular to the substrate, the first stress structure includes a protective layer, a first stress sublayer, a second stress sublayer, and a third stress sublayer arranged sequentially from the outside to the inside. The second stress structure includes a first stress sublayer, a second stress sublayer, and a third stress sublayer arranged sequentially from the outside to the inside.

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