Semiconductor device and method for manufacturing semiconductor device

Abstract

Embodiments of the present invention relate to a semiconductor device and a method for manufacturing a semiconductor device. The semiconductor device of the embodiment includes a semiconductor layer, a first insulating film disposed on the semiconductor layer, a first electrode disposed on the first insulating film, a second electrode disposed on the semiconductor layer, a third electrode disposed on the semiconductor layer, and a nitride film disposed on the semiconductor layer on the second electrode side between the first electrode and the second electrode. The nitride film on the first electrode side includes a stepped portion. The nitride film and the first insulating film are arranged in the stacking direction of the semiconductor layer and the first electrode. The nitride film includes a portion directly in contact with the semiconductor layer, and in the stacking direction of the semiconductor layer and the first electrode, the stepped portion of the nitride film includes a portion physically separated from the first insulating film.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2025-046473 (filed on March 21, 2025). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0004] Semiconductor devices such as transistors and diodes are used in circuits such as switching power supplies and inverters. These semiconductor devices require high voltage withstand capability and low on-resistance. Summary of the Invention

[0005] The semiconductor device of the embodiment includes a semiconductor layer, a first insulating film disposed on the semiconductor layer, a first electrode disposed on the first insulating film, a second electrode disposed on the semiconductor layer, a third electrode disposed on the semiconductor layer, and a nitride film disposed on the semiconductor layer on the second electrode side between the first electrode and the second electrode. The nitride film on the first electrode side includes a stepped portion. The nitride film and the first insulating film are arranged in the stacking direction of the semiconductor layer and the first electrode. The nitride film includes a portion directly in contact with the semiconductor layer, and in the stacking direction of the semiconductor layer and the first electrode, the stepped portion of the nitride film includes a portion physically separated from the first insulating film.

[0006] The semiconductor device of the embodiment includes: a semiconductor layer; a first insulating film disposed on the semiconductor layer; a first electrode disposed on the first insulating film; a second electrode disposed on the semiconductor layer; a third electrode disposed on the semiconductor layer; and a nitride film disposed on the semiconductor layer on the second electrode side between the first electrode and the second electrode; the nitride film and the first insulating film are arranged in the stacking direction of the semiconductor layer and the first electrode, the nitride film includes a portion directly in contact with the semiconductor layer, and in the stacking direction of the semiconductor layer and the first electrode, the first electrode side of the nitride film has a portion overlapping the first insulating film on the third electrode side, the length of the overlapping portion in the arrangement direction of the first electrode and the third electrode is greater than 0% and less than 5% of the distance from the end face of the third electrode side of the first electrode to the end face of the first electrode side of the third electrode in the arrangement direction of the first electrode and the third electrode.

[0007] A method for manufacturing a semiconductor device according to an embodiment includes: a step of forming a first insulating film on a semiconductor layer; a step of forming a second insulating film on the first insulating film; a step of forming a first opening in the first insulating film and the second insulating film; a step of forming a nitride film on the semiconductor layer and the second insulating film exposed in the first opening; a step of annealing the nitride film; a step of patterning the annealed nitride film and removing a portion of the nitride film on the second insulating film; a step of at least partially removing the second insulating film to expose a portion of the first insulating film; a step of forming a first electrode on the first insulating film; a step of forming a second opening in the first insulating film and a third opening in the nitride film; and a step of forming a second electrode in the second opening and a third electrode in the third opening.

[0008] According to this embodiment, a highly reliable semiconductor device and a method for manufacturing a highly reliable semiconductor device can be provided. Attached Figure Description

[0009] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment.

[0010] Figure 2 This is a top view schematic diagram of the semiconductor device according to the embodiment.

[0011] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment.

[0012] Figure 4 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment.

[0013] Figure 5 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment.

[0014] Figure 6 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment.

[0015] Figure 7 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment.

[0016] Figure 8 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment.

[0017] Figure 9 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment.

[0018] Figure 10 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment.

[0019] Figure 11This is a schematic diagram related to the manufacturing method of the semiconductor device in the embodiment.

[0020] Figure 12 This is a schematic diagram related to the manufacturing method of the semiconductor device in the embodiment.

[0021] Figure 13 This is a schematic diagram related to the manufacturing method of the semiconductor device in the embodiment.

[0022] Figure 14 This is a schematic diagram related to the manufacturing method of the semiconductor device in the embodiment.

[0023] Figure 15 This is a schematic diagram related to the manufacturing method of the semiconductor device in the embodiment.

[0024] Figure 16 This is a schematic diagram related to the manufacturing method of the semiconductor device in the embodiment.

[0025] Figure 17 This is a schematic diagram related to the manufacturing method of the semiconductor device in the embodiment.

[0026] Figure 18 This is a schematic diagram related to the manufacturing method of the semiconductor device in the embodiment.

[0027] Figure 19 This is a schematic diagram related to the manufacturing method of the semiconductor device in the embodiment.

[0028] Figure 20 This is a schematic diagram related to the manufacturing method of the semiconductor device in the embodiment.

[0029] Figure 21 This is a schematic diagram related to the manufacturing method of the semiconductor device in the embodiment.

[0030] Figure 22 This is a schematic diagram related to the manufacturing method of the semiconductor device in the embodiment.

[0031] Figure 23 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment.

[0032] Explanation of reference numerals in the attached figures

[0033] 1: Semiconductor layer

[0034] 1A: Substrate

[0035] 1B: Channel layer

[0036] 1C: Barrier layer

[0037] 1D: Buffer layer

[0038] 2: First insulating film (gate insulating film)

[0039] 3: First electrode (gate electrode)

[0040] 3A: First electrode pad (gate electrode pad)

[0041] 4: Second electrode (source electrode)

[0042] 4A: Second electrode pad (source electrode pad)

[0043] 5: Third electrode (drain electrode)

[0044] 5A: Third electrode pad (drain electrode pad)

[0045] 6: Nitride film

[0046] 6a: Crystal phase

[0047] 6b: Amorphous phase

[0048] 7: Third insulating film (first interlayer insulating film)

[0049] 8: Second insulating film (buffer film)

[0050] 9: First field plate electrode (source FP electrode)

[0051] 10: Second field plate electrode (drain FP electrode)

[0052] 11: Second interlayer insulating film

[0053] 100: Semiconductor devices

[0054] 101: Semiconductor Devices

[0055] 102: Semiconductor Devices

[0056] 103: Semiconductor Devices

[0057] 104: Semiconductor Devices

[0058] 105: Semiconductor Devices

[0059] 106: Semiconductor Devices

[0060] 107: Semiconductor Devices

[0061] 200: Semiconductor devices Detailed Implementation

[0062] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same reference numerals, and in some cases, the description of a component that has already been described will be omitted.

[0063] In this specification, "nitride semiconductor layer" includes "GaN-based semiconductor". "GaN-based semiconductor" is a general term for semiconductors containing gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and intermediates thereof.

[0064] In this specification, "undoped" means an impurity concentration of 2 × 10⁻⁶. 16 cm -3 the following.

[0065] In this specification, to indicate the positional relationship of components, the upper direction of the figures is described as "upper," and the lower direction of the figures is described as "lower." In this specification, the concepts of "upper" and "lower" are not necessarily terms indicating a relationship with the direction of gravity.

[0066] The physical properties listed in the instruction manual are values ​​in an atmospheric environment at 25°C. The physical properties described in semiconductor devices are also related to the manufacturing method of the semiconductor device.

[0067] (First Implementation)

[0068] The first embodiment relates to a semiconductor device and a method for manufacturing a semiconductor device. The semiconductor device of the first embodiment includes a semiconductor element comprising a semiconductor layer and a wiring layer located on the semiconductor element. The following description will use a GaN-based semiconductor device as an example, but the semiconductor element may also be a lateral transistor other than a GaN-based one.

[0069] Figure 1 This is a cross-sectional schematic diagram of the semiconductor device 100 according to the first embodiment. Figure 2 The diagram shows a top view of the semiconductor device 100. Figure 1 It shows Figure 2 A cross-sectional view along line A-A'. The semiconductor device 100 is, for example, a HEMT (High Eflectron Mobility Transistor) using GaN-based semiconductors. The semiconductor device 100 has a component region that operates as a transistor and a non-component region that does not operate as a transistor.

[0070] Figure 1The semiconductor device 100 comprises a semiconductor layer 1, a first insulating film 2 disposed on the semiconductor layer 1, a first electrode 3 disposed on the first insulating film 2, a second electrode 4 disposed on the semiconductor layer 1, a third electrode 5 disposed on the semiconductor layer 1, a nitride film 6 disposed on the semiconductor layer 1, a second insulating film 8 disposed on the semiconductor layer 1, a third insulating film 7, a first field plate electrode 9, a second field plate electrode 10 and a fourth insulating film 11.

[0071] The semiconductor layer 1, for example, has a substrate 1A, a channel layer 1B (a first nitride semiconductor layer), and a barrier layer 1C (a second nitride semiconductor layer) stacked in sequence. The semiconductor layer 1 comprises an element region and an element isolation region. From Figure 2 the upper side and the lower side, the element isolation region is provided toward the substrate 1A direction on the surface of the barrier layer 1C of the semiconductor layer 1. A region where no element isolation region is provided is the element region.

[0072] The substrate 1A is formed of silicon (Si), for example. In addition to silicon, sapphire (Al2O3) and silicon carbide (SiC) can also be used, for example.

[0073] Preferably, a buffer layer is provided between the substrate 1A and the channel layer 1B. The buffer layer has a function of relieving lattice mismatch between the substrate 1A and the channel layer 1B. The buffer layer is made of, for example, aluminum gallium nitride (Al W Ga 1-W N (0 < W ≤ 1)) multilayer structure.

[0074] The channel layer 1B is provided on the substrate 1A or on the buffer layer. The channel layer 1B is also referred to as an electron transport layer. The channel layer 1B is, for example, undoped aluminum gallium nitride (Al X Ga 1-X N (0 ≤ X < 1)). More specifically, the channel layer 1B is, for example, undoped gallium nitride (GaN). The thickness of the channel layer 1B is, for example, 0.1 [μm] or more and 10 [μm] or less. In the embodiment, for components including the channel layer 1B, thickness refers to the length (height) of each component in the third direction (Z direction), which is the stacking direction of the channel layer 1B and the barrier layer 1C.

[0075] The barrier layer 1C is provided on the channel layer 1B. The barrier layer 1C is also referred to as an electron supply layer. The band gap of the barrier layer 1C is larger than that of the channel layer 1B. The barrier layer 1C is, for example, undoped aluminum gallium nitride (Al Y Ga 1-Y N (0 < Y ≤ 1, X < Y)). More specifically, the barrier layer 1C is, for example, undoped Al 0.25 Ga 0.75 N. The thickness of the barrier layer 1C is, for example, 2 [nm] or more and 100 [nm] or less.

[0076] The channel layer 1B and the barrier layer 1C form a heterojunction interface. A two-dimensional electron gas (2DEG) is formed at the heterojunction interface, which becomes the charge carrier of the semiconductor device 100.

[0077] The device isolation region is a high-resistivity region formed by ion implantation. The high-resistivity region will be described in the second embodiment. The device isolation region is formed, for example, at least into the interior of the channel layer 1B. Nitrogen, argon, etc., can be used as ions for device isolation. Furthermore, the dose accompanying ion implantation is, for example, about 1 × 10⁻⁶. 14 [ions / cm 2 The acceleration energy for ion implantation is, for example, between approximately 100 keV and 200 keV. The region where the component isolation region is formed (the boundary between the component isolation region and the component region) can be confirmed by cross-sectional observation using a transmission electron microscope (TEM) or similar means.

[0078] A gate insulating film (hereinafter referred to as gate insulating film 2) serving as a first insulating film 2 can be disposed between the first electrode 3 and the barrier layer 1C, thus configuring the semiconductor device 100 as a MIS (Metal Insulator Semiconductor) type HEMT. The gate insulating film 2 is disposed between the second electrode 4 and the third electrode 5. The gate insulating film 2 is, for example, an oxide or an oxide nitride. The gate insulating film 2 is, for example, silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide, silicon oxynitride, or aluminum oxynitride. The gate insulating film 2 is a dense insulating film. The gate insulating film 2 is a denser insulating film than the second insulating film 8.

[0079] The density of the gate insulating film 2 is preferably, for example, 2 g / cm³. 3 Above and 3.16 g / cm³ 3 The thickness of the gate insulating film 2 is, for example, 10 nm or more and 100 nm or less. Regarding the gate insulating film 2, the thickness is preferably 10 nm or more and 300 nm or less, more preferably 100 nm or more and 300 nm or less, and more preferably 100 nm or more and 200 nm or less.

[0080] The end of the gate insulating film 2 on the third electrode 5 side is not directly connected to the third electrode 5. Preferably, the end of the gate insulating film 2 on the third electrode 5 side is directly connected to the side of the gate electrode 3 side of the stepped portion of the nitride film 6.

[0081] The surface of the gate insulating film 2 on the side opposite to the semiconductor layer 1 is preferably not in direct contact with the nitride film 6.

[0082] The first electrode (gate electrode) 3 is an electrode having a plurality of fingers extending in a first direction (X direction). The comb-shaped fingers of the gate electrode 3 extend along the first direction and are arranged along a second direction (Y direction). The gate electrode 3 is an electrode disposed on a first insulating film (gate insulating film) 2 disposed above the channel layer 1B and the barrier layer 1C. The gate electrode 3 is electrically connected to the channel layer 1B and the barrier layer 1C. The gate electrode 3 may, for example, be in direct contact with the first insulating film 2. The gate electrode 3 is disposed between the second electrode 4 and the third electrode 5. The gate electrode 3 is connected to a first electrode pad (gate electrode pad) 3A. On the side of the gate electrode 3 opposite to the semiconductor layer 1, it may also have the shape of a plate electrode to mitigate electric field concentration. The gate electrode 3 and the semiconductor layer 1 are stacked in the Z direction.

[0083] Gate electrode 3 is, for example, titanium nitride (TiN).

[0084] Regarding the field plate electrode portion of the gate electrode 3, preferably, in addition to Al, it also includes one or more selected from the group consisting of Cu, Si and Ti.

[0085] The second electrode 4 is a source electrode having a plurality of fingers extending in a first direction. The comb-shaped fingers of the source electrode 4 extend along the first direction and are arranged along a second direction (Y direction). For example, the fingers of the source electrode 4 are held between the fingers of the gate electrode 3. The source electrode 4 is disposed on the semiconductor layer 1, and more specifically, on the channel layer 1B and the barrier layer 1C. The source electrode 4 is electrically connected to the channel layer 1B and the barrier layer 1C. For example, the source electrode 4 or the first field plate electrode 9 is connected to the second electrode pad (source electrode pad) 4A. When the first field plate electrode 9 is connected to the second electrode pad 4A, for example, the source electrode 4 has a shape with only finger portions. The source electrode 4 and the gate electrode 3 are arranged in the X direction.

[0086] The source electrode 4 is, for example, a metal electrode. The source electrode 4 is primarily aluminum, and may be an aluminum film containing 50 wt% or more aluminum, an aluminum alloy film containing 50 wt% or more aluminum, or a laminated film of titanium (Ti) and aluminum (Al). An ohmic contact is preferably established between the source electrode 4 and the barrier layer 1C.

[0087] The semiconductor device 100 preferably includes a first field plate electrode 9. By providing the field plate electrode, the concentration of the electric field towards the electrode can be mitigated. The first field plate electrode 9 is a source field plate electrode (hereinafter referred to as the source FP electrode) connected to the source electrode 4. The source FP electrode 9 is located on top of the source electrode 4 such that the source electrode 4 is located in the middle or approximately in the middle, and such that it covers the source electrode 4 and the gate electrode 3 sandwiching the source electrode 4.

[0088] The source FP electrode 9 is an Al-based conductor. The source FP electrode 9 contains 80 wt% or more Al, preferably 90 wt% or more Al, more preferably 95 wt% or more Al, and even more preferably 99 wt% or more Al.

[0089] Alternatively, a source field plate electrode (not shown) can be provided between the gate electrode 3 and the drain electrode 5. The source field plate electrode (not shown) is electrically connected to the source electrode 4 to mitigate electric field concentration.

[0090] The third electrode 5 is a drain electrode having multiple fingers extending in a first direction (X direction). The comb-shaped fingers of the drain electrode 5 extend along the first direction and are arranged along a second direction (Y direction). The fingers of the drain electrode 5 are in the opposite direction to the fingers of the source electrode 4; that is, the source electrode 4 and drain electrode 5 are arranged facing each other. The drain electrode 5 is disposed above the channel layer 1B and the barrier layer 1C. The drain electrode 5 is electrically connected to the channel layer 1B and the barrier layer 1C. The drain electrode 5 is, for example, connected to the barrier layer 1C. For example, the drain electrode 5 or the second field plate electrode 10 (drain FP electrode) is connected to the third electrode pad (drain electrode pad) 5A. When the drain FP electrode 10 is connected to the third electrode pad 5A, the drain electrode 5 may have a shape with only finger portions. The drain electrode 5 and the gate electrode 3 are arranged in the X direction.

[0091] The drain electrode 5 has a portion that forms an eave with a T-shaped cross-section.

[0092] The drain electrode 5 is, for example, a metal electrode. The drain electrode 5 is, for example, primarily aluminum, and is an aluminum film containing 50% or more aluminum, an aluminum alloy film containing 50% or more aluminum, or a laminated film of titanium (Ti) and aluminum (Al). An ohmic contact is preferably formed between the drain electrode 5 and the barrier layer 1C.

[0093] The distance between the source electrode 4 and the drain electrode 5 is, for example, 5 [μm] or more and 30 [μm] or less.

[0094] In addition, the source electrode 4 and the drain electrode 5 can also be configured to be directly connected to the channel layer 1B.

[0095] The semiconductor device 100 preferably includes a second field plate electrode 10. By providing a field plate electrode, the electric field concentration at the electrode can be mitigated. The second field plate electrode 10 is a drain field plate electrode (hereinafter referred to as the drain FP electrode) connected to the drain electrode 5. The drain FP electrode 10 is preferably disposed on the drain electrode 5.

[0096] The drain FP electrode 10 is an Al-based conductor. The drain FP electrode 10 contains 80 wt% or more Al, preferably 90 wt% or more Al, more preferably 95 wt% or more Al, and even more preferably 99 wt% or more Al.

[0097] A nitride film 6 is disposed on the semiconductor layer 1 on the drain electrode 5 side, between the gate electrode 3 and the drain electrode 5. The nitride film 6 is directly connected to the semiconductor layer 1. Preferably, the nitride film 6 is directly connected to the drain electrode 5. Additionally, the nitride film 6 is disposed between the semiconductor layer 1 and the third insulating film 7. The nitride film 6 has a stepped portion on the gate electrode 3 side. The nitride film 6 is a nitride film containing Al or Al and Ga. For example, the nitride film 6 is Al. Z Ga 1-Z N(0 <Z≤1)。

[0098] Figure 1 The stepped portion of the nitride film 6 in the schematic diagram extends in the stacking direction of the semiconductor layer 1 and the gate electrode 3, preferably along the side surface shape of the drain electrode 5 side of the gate insulating film 2 (preferably, the stepped portion of the nitride film 6 is directly connected to the side surface of the drain electrode 5 side of the gate insulating film 2 and extends along the side surface of the drain electrode 5 side of the gate insulating film 2). For example, the portion of the nitride film 6 along the side surface of the drain electrode 5 side of the gate insulating film 2 includes one or more selected from the group consisting of a portion extending in the stacking direction of the semiconductor layer 1 and the gate electrode 3, a portion inclined relative to the stacking direction of the semiconductor layer 1 and the gate electrode 3, and a portion bent relative to the stacking direction of the semiconductor layer 1 and the gate electrode 3. This inclined shape and the bent shape are also included in the shape of the nitride film 6 having a stepped portion.

[0099] The stepped portion of the nitride film 6 is the portion where the surface of the nitride film 6 on the semiconductor layer 1 side is positioned higher than the surface in contact with the semiconductor layer 1 (the surface of the nitride film 6 on the semiconductor layer 1 side is offset in the direction opposite to the semiconductor layer 1). Figure 1 The structure with clearly defined steps is disclosed, but the stepped portion can also make the position of the semiconductor layer 1 side of the nitride film 6 rise like a slope.

[0100] The height of the step in the stepped portion of the nitride film 6 (the distance between the upper surface of the gate insulating film 2 (the surface facing the side opposite to the semiconductor layer 1) and the surface of the stepped portion of the nitride film 6, which is separated from and opposite the upper surface of the gate insulating film 2, in the stacking direction of the semiconductor layer 1 and the gate electrode 3) is preferably more than 1 and less than 5 times the thickness of the gate insulating film 2, more preferably more than 1 and less than 3 times the thickness of the gate insulating film 2, and even more preferably more than 1 and less than 2 times the thickness of the gate insulating film 2. If the step in the stepped portion of the nitride film 6 is small, the gate insulating film 2 is easily damaged. If the step in the stepped portion of the nitride film 6 is too high, it is not preferable for reasons such as requiring significant changes to the design of the semiconductor device 100.

[0101] The nitride film 6 includes a portion directly in contact with the semiconductor layer 1. In the stacking direction of the semiconductor layer 1 and the gate electrode 3, the stepped portion of the nitride film 6 includes a portion separated from the gate insulating film 2. More specifically, in the stacking direction of the semiconductor layer 1 and the gate electrode 3, it includes a portion where the surface of the gate insulating film 2 facing the nitride film 6 is separated from the surface of the stepped portion of the nitride film 6 facing the gate insulating film 2. Even more specifically, in the stacking direction of the semiconductor layer 1 and the gate electrode 3, the entire surface of the gate insulating film 2 facing the nitride film 6 is separated from the entire surface of the stepped portion of the nitride film 6 facing the gate insulating film 2.

[0102] Figure 3 A schematic diagram of semiconductor device 101 is shown in the figure. Figure 4 A schematic diagram of semiconductor device 102 is shown in the figure. Figure 3 and Figure 4 The diagram is related to Figure 1 Cross-sectional view at the same location. Semiconductor devices 101 and 102 are variations of semiconductor device 100. In the stacking direction of the semiconductor layer 1 and the gate electrode 3 of semiconductor devices 101 and 102, the nitride film 6 has a portion X1 (not shown) overlapping the gate insulating film 2 towards the drain electrode 5 side on the gate electrode 3 side, and preferably has any overlapping portion X1 and a portion X2 (not shown) located closer to the gate electrode 3 side than the overlapping portion X1 and separated from the gate insulating film 6.

[0103] like Figure 3 and Figure 4As shown in the schematic diagram, in the stacking direction of the semiconductor layer 1 and the gate electrode 3, the nitride film 6 can be separated from most of the upper surface of the gate insulating film 2 (the side facing the opposite side to the semiconductor layer 1), or it can be directly connected to a portion of the drain electrode 5 side of the upper surface of the gate insulating film 2 (the side facing the opposite side to the semiconductor layer 1). The overlapping portion X1 and the separated portion X2 are preferably directly adjacent. In the schematic diagram of the semiconductor device 101, the overlapping portion X1 of the nitride film 6 extends in the stacking direction of the semiconductor layer 1 and the gate electrode 3, while the portion of the nitride film 6 along the gate insulating film 2 in the semiconductor device 102 is inclined relative to the stacking direction of the semiconductor layer 1 and the gate electrode 3.

[0104] Regarding the gate electrode 3 side of the nitride film 6, the portion X1 that overlaps on the gate insulating film 2 towards the drain electrode 5 side is the portion where the surface of the gate insulating film 2 opposite to the semiconductor layer 1 side is directly in contact with the nitride film 6. The portion where the gate insulating film 2 is directly in contact with the nitride film 6 is located on the drain electrode 5 side of the gate insulating film 2. Figure 3 Semiconductor device 101 and Figure 4 The semiconductor device 102 includes an attached portion X1 and an arbitrarily separated portion X2 in place of the stepped portion, except... Figure 3 and Figure 4 Apart from the explanation, the explanation of the stepped part is sometimes equivalent to the explanation of the attached part X1 and the arbitrarily separated part X2.

[0105] The portion X1 that overlaps on the gate insulating film 2 on the side of the gate electrode 3 towards the drain electrode 5 of the nitride film 6 is preferably directly connected to (connected to) the nitride film 6 along the side of the gate insulating film 2.

[0106] The length of the connected portion X1 in the arrangement direction of the gate electrode 3 and the drain electrode 5 is preferably greater than 0% of the distance L2 from the end face of the drain electrode 5 side of the gate electrode (bottom) 3 to the end face of the gate electrode 3 side of the drain electrode (bottom) 5 and less than 5% of the distance L2, more preferably greater than 0% of the distance L2 and less than 4% of the distance L2, and even more preferably greater than 0% of the distance L2 and less than 3% of the distance L2.

[0107] The length of the overlap portion X1 in the arrangement direction of the gate electrode 3 and the drain electrode 5 is preferably shorter than the length of the portion of the nitride film 6 directly connected to the semiconductor layer 1 in the arrangement direction of the gate electrode 3 and the drain electrode 5. The length of the overlap portion X1 in the arrangement direction of the gate electrode 3 and the drain electrode 5 is preferably 0% or more and 50% or less, more preferably 0% or more and 30% or less, and even more preferably 0% or more and 20% or less.

[0108] The average distance between the nitride film 6 and the gate insulating film 2 of the separated portion X2 in the stacking direction of the semiconductor layer 1 and the gate electrode 3 is preferably 0.5 times or more and 5 times or less the thickness of the gate insulating film 2, more preferably 1 times or more and 3 times or less the thickness of the gate insulating film 2, and even more preferably 1 times or more and 2 times or less the thickness of the gate insulating film 2.

[0109] In semiconductor devices 101 and 102, which include the attached portion X1, the portion of the nitride film 6 along the side of the drain electrode 5 side of the gate insulating film 2 also includes one or more selected from the group consisting of a portion extending in the stacking direction of the semiconductor layer 1 and the gate electrode 3, a portion inclined relative to the stacking direction of the semiconductor layer 1 and the gate electrode 3, and a portion bent relative to the stacking direction of the semiconductor layer 1 and the gate electrode 3.

[0110] The distance L0 from the position closest to the gate electrode 3 (starting point) of the portion where the gate insulating film 2 and the nitride film 6 are directly in contact, to the end face (end point) of the drain electrode 5 side of the gate electrode (bottom) 3, is preferably more than 90% of the distance L2 from the end face of the drain electrode 5 side of the gate electrode (bottom) 3 to the end face of the gate electrode 3 side of the drain electrode (bottom) 5.

[0111] The stepped portion of the nitride film 6 is located on the gate electrode 3 side, covering a portion of the gate insulating film 2. The nitride film 6 and the gate insulating film 2 are arranged in the stacking direction of the semiconductor layer 1 and the gate electrode 3. The portion physically separated from the gate insulating film 2 in the stacking direction of the semiconductor layer 1 and the gate electrode 3 is preferably the stepped portion of the nitride film 6.

[0112] In the stacking direction of the semiconductor layer 1 and the gate electrode 3, the nitride film 6 and the gate insulating film 2 are preferably not directly connected. In the stacking direction of the semiconductor layer 1 and the gate electrode 3, an insulating film is preferably disposed between the nitride film 6 and the gate insulating film 2. In the stacking direction of the semiconductor layer 1 and the gate electrode 3, a conductive layer is preferably absent between the nitride film 6 and the gate insulating film 2. In the stacking direction of the semiconductor layer 1 and the gate electrode 3, the insulating film present between the nitride film 6 and the gate insulating film 2 is preferably a film with a lower density than the gate insulating film 2. In the stacking direction of the semiconductor layer 1 and the gate electrode 3, an insulating film with a lower density than the gate insulating film 2, such as a second insulating film 8 and / or a third insulating film 7, is preferably disposed between the nitride film 6 and the gate insulating film 2.

[0113] The stepped portion of the nitride film 6 includes at least a portion extending from the semiconductor layer 1 side in the opposite direction to the semiconductor layer 1. Preferably, the stepped portion of the nitride film 6 includes a portion extending from the portion extending in the opposite direction from the semiconductor layer 1 side toward the gate electrode 3 side.

[0114] The nitride film 6 is preferably directly connected to the semiconductor layer 1 and the drain electrode 5. The nitride film 6 is preferably directly adjacent to the drain electrode 5 in the arrangement direction of the gate electrode 3 and the drain electrode 5. The end face of the nitride film 6 on the drain electrode 5 side is preferably directly connected to the drain electrode 5.

[0115] The portion of the nitride film 6 that is directly in contact with the semiconductor layer 1 is located between the gate insulating film 2 and the drain electrode 5 in the arrangement direction of the gate electrode 3 and the drain electrode 5. Preferably, the gate electrode 3 side of the portion of the nitride film 6 that is directly in contact with the semiconductor layer 1 is directly adjacent to the gate insulating film 2. Preferably, the drain electrode 5 side of the portion of the nitride film 6 that is directly in contact with the semiconductor layer 1 is directly adjacent to the drain electrode 5.

[0116] The side of the nitride film 6 opposite to the semiconductor layer 1 and the gate insulating film 2 are preferably not in direct contact.

[0117] Preferably, the end face of the nitride film 6 on the gate electrode 3 side is not directly connected to the gate insulating film 2, nor is it directly connected to the gate electrode 3.

[0118] The side of the nitride film 6 facing the semiconductor layer 1 is preferably not in contact with the gate insulating film 2.

[0119] The nitride film 6 and the gate insulating film 2 are preferably adjacent to each other in the arrangement direction of the gate electrode 3 and the drain electrode 5, and not adjacent to each other in the stacking direction of the semiconductor layer 1 and the gate electrode 3.

[0120] The portion of the gate insulating film 2 that is directly in contact with the nitride film 6 preferably does not exist between the nitride film 6 and the semiconductor layer 1 in the stacking direction of the gate electrode 3 and the semiconductor layer 1.

[0121] The side of the nitride film 6 opposite to the semiconductor layer 1 and the gate insulating film 2 are preferably not in direct contact.

[0122] The side of the semiconductor layer 1 of the stepped portion of the nitride film 6 facing the gate electrode 3 is preferably in direct contact with the gate insulating film 2.

[0123] The structure of the nitride film 6 and the gate insulating film 2 is obtained by employing a manufacturing method that reduces damage to the gate insulating film 2. Details regarding the manufacturing method of the semiconductor device 100 are provided below.

[0124] The nitride film 6 comprises both a highly crystalline crystalline phase and a less crystalline amorphous phase on the side in contact with the semiconductor layer 1. The stepped portion of the nitride film 6 contains an amorphous phase. The amorphous phase may contain a crystalline phase. The crystalline phase contains crystals containing Al or Al and Ga nitrides. The amorphous phase contains amorphous material containing Al or Al and Ga nitrides.

[0125] The height of the stepped portion of the nitride film 6 is the sum of the thickness of the gate insulating film 2, the thickness of the second insulating film 8, and the thickness of the nitride film 6, and varies depending on their thicknesses.

[0126] Through the highly crystalline portion of the nitride film 6 on the side in contact with the semiconductor layer 1, the thickness of the semiconductor layer 1 near the drain electrode 5 becomes substantially locally thicker, resulting in a higher carrier density. This higher carrier density is preferred to improve the reduction of on-resistance and prevent collapse.

[0127] The thickness of the nitride film 6 (the thickness along the portion of the semiconductor layer 1) is preferably 1 nm or more and 10 nm or less.

[0128] The length L1 of the nitride film 6 from the surface in contact with the drain electrode 5 to the end face on the gate electrode 3 side is preferably 1% or more and 20% or less of the distance L2 from the end face on the drain electrode 5 side of the gate electrode (bottom) 3 to the end face on the gate electrode 3 side of the drain electrode (bottom) 5. More preferably, it is 3% or more and 15% or less of the distance L2. More preferably, it is 5% or more and 10% or less of the distance L2.

[0129] From the viewpoint of increasing carrier density, the length L3 of the surface of the nitride film 6 in contact with the semiconductor layer 1 in the arrangement direction of the gate electrode 3 and the drain electrode 5 is preferably 0.1 [μm] or more and 10 [μm] or less, more preferably 0.3 [μm] or more and 7 [μm] or less, and even more preferably 0.5 [μm] or more and 5 [μm] or less.

[0130] The length L4 of the stepped portion of the nitride film 6 in the arrangement direction of the gate electrode 3 and the drain electrode 5 is preferably 0.1 μm or more and 5 μm or less, more preferably 0.3 μm or more and 3 μm or less, and even more preferably 0.5 μm or more and 1.5 μm or less.

[0131] The length L4 of the stepped portion of the nitride film 6 in the arrangement direction of the gate electrode 3 and the drain electrode 5 is preferably 1% or more and 300% or less of the length L3 of the surface of the nitride film 6 in contact with the semiconductor layer 1 in the arrangement direction of the gate electrode 3 and the drain electrode 5, more preferably 10% or more and 200% or less of the length L3, and even more preferably 20% or more and 100% or less of the length L3.

[0132] The length L4 of the stepped portion of the nitride film 6 in the arrangement direction of the gate electrode 3 and the drain electrode 5 is preferably 1% or more and 90% or less of the length L1 of the nitride film 6 from the surface in contact with the drain electrode 5 to the end face on the gate electrode 3 side, more preferably 5% or more and 70% or less of the length L1, and even more preferably 10% or more and 50% or less of the length L1.

[0133] The third insulating film 7 is an interlayer insulating film (hereinafter referred to as the first interlayer insulating film 7). The third insulating film 7 is disposed between the gate insulating film 2 and the fourth insulating film 11. The first interlayer insulating film 7 is disposed on the nitride film 6 and also between the nitride film 6 and the fourth insulating film 11. The first interlayer insulating film 7 partially covers the gate electrode 3, the source electrode 4, and the drain electrode 5. The first interlayer insulating film 7 is, for example, an oxide or a nitride. The first interlayer insulating film 7 is, for example, silicon oxide (SiO2), silicon nitride (SiN), or a high-k material. Hafnium oxide (HfO2) is an example of a high-k material.

[0134] The first interlayer insulating film 7 is shown as a single layer in the attached figure, but it can also be a multi-layer insulating film.

[0135] The first interlayer insulating film 7 is preferably sandwiched between the gate electrode 3 and the nitride film 6 (the stepped portion of the nitride film 6 and the portion on the side opposite to the semiconductor layer 1) in the arrangement direction of the gate electrode 3 and the drain electrode 5.

[0136] The first interlayer insulating film 7 is a low-density insulating film. The first interlayer insulating film 7 has a lower density than the gate insulating film 2. Furthermore, the thickness of the first interlayer insulating film 7 is thicker than that of the gate insulating film 2, for example, 20 nm or more and 500 nm or less. Figure 1 In the semiconductor device 100, the first interlayer insulating film 7 has steps formed by the stepped portion of the nitride film 6. The steps of the first interlayer insulating film 7 can be planarized by CMP (chemical mechanical polishing).

[0137] A second insulating film (buffer film) 8 is disposed between the gate insulating film 2 and the nitride film 6. The buffer film 8 is, for example, an oxide or oxynitride. The gate insulating film 2 is, for example, silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide, silicon oxynitride, or aluminum oxynitride. The buffer film 8 is a low-density insulating film.

[0138] The side of the buffer film 8 facing the semiconductor layer 1 is preferably in direct contact with the gate insulating film 2. The side of the buffer film 8 opposite to the semiconductor layer 1 side is preferably in direct contact with the side of the stepped portion of the nitride film 6 facing the semiconductor layer 1 side.

[0139] Part or all of the buffer membrane 8 can also be replaced by the first interlayer insulating membrane 7.

[0140] The density of the buffer membrane 8 is preferably, for example, 2 g / cm³. 3 ] and above 3 [g / cm 3 The following is the density of buffer membrane 8 [g / m³]. 3Preferably, the thickness of the gate insulating film 2 is 95% or less, more preferably 90% or less. Furthermore, the thickness of the buffer film 8 is thicker than that of the gate insulating film 2, for example, 20 nm or more and 100 nm or less.

[0141] The end face of the buffer film 8 on the gate electrode 3 side is preferably located closer to the drain electrode 5 side than the end face of the nitride film 6 on the gate electrode 3 side.

[0142] The buffer film 8 is an insulating film that may deteriorate during the PDA (Post Deposition Anneal) process after the nitride film 6 is formed. Therefore, the area of ​​the buffer film 8 disposed on the gate insulating film 2 is preferably 0% to 20% of the area of ​​the gate insulating film 2 from the end on the gate electrode 3 side to the end on the drain electrode 5 side.

[0143] The fourth insulating film 11 is an interlayer insulating film (hereinafter referred to as the second interlayer insulating film 11). The second interlayer insulating film 11 is disposed on top of the first interlayer insulating film 7. The first interlayer insulating film 7 is located between the second interlayer insulating film 11 and the gate insulating film 2. The second interlayer insulating film 11 partially covers the source electrode 4 and the drain electrode 5. The second interlayer insulating film 11 is, for example, an oxide or a nitride. The second interlayer insulating film 11 is, for example, silicon oxide (SiO2), silicon nitride (SiN), or a high-k material. Hafnium oxide (HfO2) is an example of a high-k material. The thickness of the second interlayer insulating film 11 is thicker than that of the gate insulating film 2, for example, 50 nm or more and 2000 nm or less.

[0144] Next, refer to Figures 5 to 9 A cross-sectional schematic diagram of the semiconductor device 100 is used to illustrate a variation of the semiconductor device 100.

[0145] Figure 5 The semiconductor device 103 is with Figure 1 A sectional view at the same location. Figure 5 The semiconductor device 103 illustrates the crystalline phase 6a and amorphous phase 6b of the nitride film 6 separately, unlike the semiconductor device 100. In some cases, the boundary between the crystalline phase 6a and the amorphous phase 6b is not clearly defined, such as... Figure 5 As shown in the schematic diagram, the nitride film 6 on the semiconductor layer 1 side is a crystalline phase 6a. The portion of the nitride film 6 growing from the semiconductor layer 1 is the crystalline phase 6a, while the portion growing outside the semiconductor layer 1 is the amorphous phase 6b. The amorphous phase 6b may locally contain crystals such as AlN.

[0146] Figure 6 Semiconductor device 104 is with Figure 1 A sectional view at the same location. Figure 6The semiconductor device 104 has a first interlayer insulating film 7 disposed in a portion between the nitride film 6 and the gate insulating film 2, which differs from the semiconductor device 100. In some cases, the buffer film 8 under the nitride film 6 may be removed during the manufacturing process. In such cases, such as... Figure 6 As shown in the schematic diagram of the semiconductor device 104, a first interlayer insulating film 7 is provided on the side of the gate electrode 3 between the nitride film 6 and the gate insulating film 2.

[0147] Figure 7 The semiconductor device 105 is with Figure 1 A sectional view at the same location. Figure 7 The semiconductor device 105 has a first interlayer insulating film 7 integrally disposed between the nitride film 6 and the gate insulating film 2. The stepped portion of the nitride film 6 along the gate insulating film 2 is inclined relative to the stacking direction of the semiconductor layer 1 and the gate electrode 3, unlike the semiconductor device 100. Regarding the buffer film 8, in some cases, the buffer film 8 under the nitride film 6 may be removed due to manufacturing processes. In this case, such as... Figure 7 As shown in the schematic diagram of the semiconductor device 105, a first interlayer insulating film 7 is provided in the entire gap between the nitride film 6 and the gate insulating film 2.

[0148] Figure 8 Semiconductor device 106 is related to Figure 1 A sectional view at the same location. Figure 8 The semiconductor device 106 differs from the semiconductor device 100 in that the stepped portion of the nitride film 6 is located between the source FP electrode 9 and the drain FP electrode 10. The length of the stepped portion of the nitride film 6 and the length of the portion of the nitride film 6 that is in contact with the semiconductor layer 1 can be... Figure 8 The shape and position of the nitride film 6 can be changed in a way that is not applicable to any other example. Factors such as carrier density can be considered, and the shape and position of the nitride film 6 can be altered according to the required specifications.

[0149] Figure 9 Semiconductor device 107 is related to Figure 1 A sectional view at the same location. Figure 9 The semiconductor device 107 differs from the semiconductor device 100 in that the stepped portion of the nitride film 6 is positioned close to the gate electrode 3. The shape and position of the nitride film 6 can be varied according to required specifications, taking into account factors such as carrier density. Furthermore, when a source FP electrode (not shown) is provided between the gate electrode 3 and the drain electrode 5, this source FP electrode is preferably not directly connected to the nitride film 6.

[0150] Next, the manufacturing method of the semiconductor device 100 will be described. Figure 10 A flowchart illustrating a method for manufacturing the semiconductor device 100 is shown below. (Refer to...) Figures 11 to 22The schematic diagram in the middle relates to the manufacturing method of the semiconductor device 100, and explains the manufacturing method of the semiconductor device 100.

[0151] The manufacturing method of the semiconductor device 100 includes: a step of forming a first insulating film 2 on a semiconductor layer 1 (S01); a step of forming a second insulating film 8 on the first insulating film 2 (S02); a step of forming a first opening V1 on the first insulating film 2 and the second insulating film 8 (S03); a step of forming a nitride film 6 on the semiconductor layer 1 exposed at the first opening V1 and on the second insulating film 8 (S04); a step of annealing the nitride film 6 (S05); and a step of further processing the annealed nitride film 6. The process includes: patterning and removing a portion of the nitride film 6 on the second insulating film 8 (S06); removing at least partially the second insulating film 8 to expose a portion of the first insulating film (S07); forming a first electrode 3 on the first insulating film (S08); forming a second opening V2 on the first insulating film 2 and a third opening V3 on the nitride film 6 (S09); and forming a second electrode 4 on the second opening V2 and a third electrode 5 on the third opening V3 (S10).

[0152] Reference Figure 11 The schematic diagram illustrates the process of forming a first insulating film (gate insulating film) 2 on the semiconductor layer 1 (S01) and the process of forming a second insulating film (buffer film) 8 on the first insulating film (gate insulating film) 2 (S02). By providing the gate insulating film 2 on the semiconductor layer 1, a component 110 is obtained having the gate insulating film 2 on the semiconductor layer 1 and the buffer film 8 on the gate insulating film 2. The buffer film 8 is preferably provided on the entire surface of the gate insulating film 2, and more preferably on the entire surface of the gate insulating film 2 in the element region.

[0153] A dense gate insulating film 2 is formed on the semiconductor layer 1, for example, by LP-CVD (Low-Pressure Chemical Vapor Deposition).

[0154] A low-density buffer film 8 is formed on the gate insulating film 2, for example, by PE-CVD (Plasma-Enhanced Chemical Vapor Deposition).

[0155] Reference Figure 12 The schematic diagram illustrates the process (S03) in which the first opening V1 is formed in the first insulating film (gate insulating film) 2 and the second insulating film (buffer film) 8. Figure 11The component 110, in which the drain electrode 5 of the semiconductor layer 1 and the nitride film 6 in contact with the semiconductor layer 1 are to be disposed, forms a first opening V1 in the gate insulating film 2 and the buffer film 8, thereby obtaining Figure 12 Component 111. The opening area of ​​the first opening V1 varies mainly according to the area of ​​the nitride film 6 in contact with the semiconductor layer 1.

[0156] Reference Figure 13 The schematic diagram illustrates the process (S04) of forming a nitride film 6 on the semiconductor layer 1 exposed at the first opening V1 and on the second insulating film (buffer film) 8. Figure 12 A nitride film 6 is formed on the portion of component 111 that opens at the first opening V1 and on the buffer film 8 disposed on the surface closest to the semiconductor layer 1, thereby obtaining... Figure 12 Component 112. The nitride film 6 is disposed on the cross section of the first opening V1 of the gate insulating film 2, but not on the main surface of the gate insulating film 2, i.e., on the surface along the semiconductor layer 1.

[0157] Since the semiconductor layer 1 includes a portion on which the gate insulating film 2 and the buffer film 8 are stacked, the nitride film 6 disposed on the stack of the gate insulating film 2 and the buffer film 8 and the nitride film 6 disposed on the semiconductor layer 1 are stepped, thus forming a stepped portion. If the nitride film 6 is formed before the gate insulating film 2 is formed, the stepped portion of the nitride film 6 will not be formed.

[0158] If a nitride film 6 is formed directly above the gate insulating film 2, a stepped portion will be formed. If this process is adopted, in the stacking direction of the semiconductor layer 1 and the gate electrode 3 of the semiconductor device 100, the stepped portion of the nitride film 6 is directly connected to the gate insulating film 2 as a whole, and in the stacking direction of the semiconductor layer 1 and the gate electrode 3, the stepped portion of the nitride film 6 does not include a portion separated from the gate insulating film 2.

[0159] Reference Figure 14 The schematic diagram illustrates the process of annealing the nitride film 6 (S05) and the process of patterning the annealed nitride film 6 to remove a portion of the nitride film 6 from the second insulating film (buffer film) 8 (S06). Figure 13 The component 112 is annealed. During annealing, preferably, at least the gate insulating film 2 in the element region is covered by the buffer film 8 and the nitride film 6, and the gate insulating film 2 in the element region is not exposed. If the gate insulating film 2 is exposed during annealing, it may sometimes deteriorate due to annealing damage. By covering the gate insulating film 2 with the buffer film 8 and the nitride film 6 during annealing, annealing can be performed while suppressing the deterioration of the gate insulating film 2.

[0160] Annealing increases the crystallinity of the nitride film 6 and improves its film quality. It is preferable to increase the carrier density using a nitride film 6 with high film quality. Annealing is performed, for example, at 900°C for 30 minutes in a nitrogen atmosphere.

[0161] In the arrangement direction of the gate electrode 3 and the drain electrode 5, the gate insulating film 2, which is provided in the range from the side (starting point) of the gate electrode 3 toward the source electrode 4 to a distance of at least 0.5 [μm] (preferably 1 [μm], more preferably 1.5 [μm]) (end point), is preferably covered by a buffer film 8 during annealing. The gate insulating film 2, which is provided in the range from the side (starting point) of the gate electrode 3 toward the source electrode 4 to at least 50% (preferably 65%, more preferably 80%) of the distance L5 between the gate electrode 3 and the source electrode 4 (end point), is preferably covered by a buffer film 8 during annealing. The gate insulating film 2, which is provided in the range from the side (starting point) of the gate electrode 3 to the end face (end point) of the source electrode 4, is preferably covered by a buffer film 8 during annealing. By removing most of the buffer film 8 covering the gate insulating film 2 in a subsequent process, it is possible to prevent the insulating film from deteriorating due to annealing and thus reducing its function as a gate insulating film.

[0162] The gate insulating film 2, disposed in the arrangement direction of the gate electrode 3 and the drain electrode 5, is preferably covered by the buffer film 8 during annealing, extending at least 5 μm (preferably 10 μm, more preferably 15 μm) from the side of the gate electrode 3 (starting point) toward the drain electrode 5. The gate insulating film 2, disposed in the arrangement direction of the gate electrode 3 (starting point) toward the drain electrode 5, extends at least 50% (preferably 65%, more preferably 80%) of the distance L2 between the gate electrode 3 and the drain electrode 5 (end point). For the interval from the side of the gate electrode 3 (starting point) to the position (end point) where the lower end of the drain electrode 5 side of the nitride film 6 directly contacts the semiconductor layer 1 (end point), which is the distance (end point) from the end face (starting point) of the buffer film 8 from the drain electrode 5 side of the gate electrode 3 towards the drain electrode 5 to L2-L3, the gate insulating film 2 disposed in this interval is preferably covered by the buffer film 8 during annealing. By removing most of the buffer film 8 covering the gate insulating film 2 in a subsequent process, it is possible to prevent the insulating film from deteriorating due to annealing and thus reducing its function as a gate insulating film.

[0163] After annealing, the nitride film 6 is patterned (patterning is formed), and a portion of the nitride film 6 on the buffer film 8 is removed to obtain... Figure 14Component 113. During patterning, the nitride film 6 in the portion where the drain electrode 5 will be formed is removed, leaving the nitride film 6 outside the area where the drain electrode 5 will be formed, and the nitride film 6 in the area where the gate electrode 3 and source electrode 4 will be formed is removed. When patterning the nitride film 6, it is preferable to leave a portion of the nitride film 6 that is directly in contact with the semiconductor layer 1 and a portion of the stepped portion. If the stepped portion is completely removed, the nitride film 6 in the portion directly in contact with the semiconductor layer 1 can also be easily removed. Therefore, before and after the patterning of the nitride film 6, at least in the element region, the semiconductor layer 1 between the gate electrode 3 and the drain electrode 5 is preferably covered by the gate insulating film 2 (more specifically, the gate insulating film 2 is such that during annealing, the end face of the gate insulating film 2 on the side of the subsequent drain electrode 5 is covered by the nitride film 6, the entire surface of the gate insulating film 2 on the side of the semiconductor layer 1 is directly in contact with the semiconductor layer 1, and the entire surface of the gate insulating film 2 on the side opposite to the semiconductor layer 1 is covered by the buffer film 8) and the nitride film 6.

[0164] If annealing is performed after patterning the nitride film 6, the gate insulating film 2 is prone to deterioration, thus weakening the effect of the buffer film 8. Therefore, it is preferable to pattern the nitride film 6 after annealing.

[0165] Reference Figure 15 The schematic diagram illustrates the process (S07) of at least partially removing the buffer film 8 to expose a portion of the first insulating film (gate insulating film) 2. In order to remove... Figure 14 The buffer film 8 of component 113 is subjected to wet etching, for example. The buffer film 8 is selectively removed due to the density difference between the low-density buffer film 8 and the dense gate insulating film 2. Then, the desired result is obtained. Figure 15 Component 114. Depending on the etching solution and other conditions, the buffer film 8 of the stepped portion may also dissolve, therefore, depending on the progress of etching, the following can be obtained: Figure 1 Semiconductor device 100 Figure 6 Semiconductor device 105 or Figure 7 Semiconductor device 106.

[0166] Furthermore, in the accompanying drawings, except for the stepped portion, the buffer film 8 is completely removed. However, as long as it is not layered, a portion of the buffer film 8 may remain on the gate insulating film 2 in an island-like pattern. In this specification, the buffer film 8 remaining in an island-like pattern will not be considered.

[0167] In the process (S06) of patterning the annealed nitride film 6 to remove a portion of the nitride film 6 from the second insulating film (buffer film) 8, if a portion of the gate insulating film 2 is removed, the gate insulating film 2 is also easily dissolved when the buffer film 8 is removed. Therefore, from this viewpoint, it is preferable to have a nitride film 6 with a residual stepped portion.

[0168] Next, the first interlayer insulating film 7 is formed, resulting in... Figure 16 Component 115. Then, a fourth opening V4 for forming the gate electrode 3 is formed, resulting in... Figure 17 Component 116.

[0169] Reference Figure 18 The schematic diagram illustrates the process (S08) of forming the first electrode (gate electrode) 3 on the first insulating film (gate insulating film) 2. The gate electrode 3 is formed on the gate insulating film 2, which was previously covered by the buffer film 8 during annealing, resulting in... Figure 18 Component 117. When forming the gate electrode 3, an interlayer insulating film can be formed after forming the electrode layer, the opening can be formed again, and the field plate electrode portion can be formed. If annealing is performed when forming the gate electrode 3, it is preferable to provide a first interlayer insulating film 7 on the gate insulating film 2.

[0170] Reference Figure 19 The schematic diagram illustrates the process (S09) of forming a second opening V2 in the first insulating film (gate insulating film 2) 2 and a third opening V3 in the nitride film 6. Figure 18 A second opening V2 for the source electrode 4 and a third opening V3 for the drain electrode 5 are formed on component 117, resulting in... Figure 19 Component 118. A second opening V2 and a third opening V3 are also provided in the first interlayer insulating film 7.

[0171] Reference Figure 20 The schematic diagram illustrates the process (S10) of forming the second electrode (source electrode) 4 at the second opening V2 and the third electrode (drain electrode) 5 at the third opening V3. Figure 19 Electrodes are formed at the second opening V2 and the third opening V3 of component 118, thereby forming the active electrode 4 and the drain electrode 5. Figure 20 Component 119. When annealing is performed during the formation of the source electrode 4 and the drain electrode 5, it is preferable to provide a first interlayer insulating film 7 on the gate insulating film 2. Then, a second interlayer insulating film 11, a source FP electrode 9, and a drain FP electrode 10 are formed to obtain the semiconductor device 100.

[0172] Furthermore, in the process (S03) of forming the first opening V1 on the first insulating film (gate insulating film) 2 and the second insulating film (buffer film) 8, depending on the processing conditions of the gate insulating film 2 and the buffer film 8, in some cases the surface of the gate insulating film 2 on the side where the drain electrode 5 will be formed will... Figure 21 The schematic diagram shows component 120 exposed as such. If in Figure 21 If a nitride film 6 is formed on component 120, then a solution can be obtained. Figure 22 The schematic diagram shows component 121, which allows the nitride film 6 to be deposited on the gate insulating film 2 on the drain electrode 5 side. Figure 3 Semiconductor devices like semiconductor device 101 or Figure 4 Semiconductor device 102.

[0173] In obtaining Figure 3 Semiconductor device 101 or Figure 4 In the case of the semiconductor device 102, during the annealing process (S05) of the nitride film 6, a portion of the gate insulating film 2 on the side where the nitride film 6 is directly in contact with the semiconductor layer 1 is not covered by the buffer film 8. However, the proportion of the portion of the gate insulating film 2 not covered by the buffer film 8 during the annealing process (S05) of the nitride film 6 is less than 5% of the area of ​​the side of the gate insulating film 2 opposite to the semiconductor layer 1, preferably less than 4% of the area of ​​the side of the gate insulating film 2 opposite to the semiconductor layer 1, and more preferably less than 3% of the area of ​​the side of the gate insulating film 2 opposite to the semiconductor layer 1. Therefore, the degraded portion is sufficiently separated from the gate electrode 3. In other words, the entire gate insulating film 2 in the region forming the gate electrode 3 is covered by the buffer film 8. Even if a part of the gate insulating film 2 is not covered by the buffer film 8, the annealing process (S03) is a method to obtain a semiconductor device with high reliability.

[0174] By employing the manufacturing method described herein, damage generated on the gate insulating film 2 can be reduced, achieving a balance between reliability and high carrier density. Due to the manufacturing method, a stepped portion is formed on the nitride film 6.

[0175] (Second Implementation)

[0176] The second embodiment relates to a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device of the second embodiment is a variation of the semiconductor device 100 of the first embodiment. Descriptions of the semiconductor device 200 of the second embodiment that are identical to those of the semiconductor device 100 of the first embodiment are omitted. Furthermore, the descriptions in the second embodiment can be applied to the first embodiment.

[0177] Figure 23 The diagram shows a schematic of a semiconductor device 200 according to the second embodiment. The semiconductor device 200 has a trench-type gate electrode 3, and a buffer layer 1D is provided between the substrate 1A and the channel layer 1B in the semiconductor layer 1. Otherwise, it is the same as the semiconductor device 100.

[0178] In the first embodiment, no nitride film 6 is provided between the gate insulating film 2, which is also disposed within the trench, and the semiconductor layer 1. In this respect, the first embodiment is the same as the second embodiment, as the gate insulating film 2 has been degraded and its degradation is suppressed, which can improve the carrier density. From the viewpoint of improving the carrier density of the normally cut-off GaN HEMT with trench-type gate electrode 3, the structure of the embodiment is preferred.

[0179] Secondly, the manufacturing method of semiconductor device 200 is the same as that of semiconductor device 100 except that an additional trench forming step is added before forming the gate insulating film 2. By adopting the manufacturing method of this embodiment, damage to the gate insulating film can be reduced and the carrier density can be increased.

[0180] In the instruction manual, some elements are represented by element symbols.

[0181] The technical solution for the implementation method is described below.

[0182] Technical Solution 1

[0183] A semiconductor device, wherein:

[0184] Semiconductor layer;

[0185] A first insulating film is disposed on the semiconductor layer;

[0186] The first electrode is disposed on the first insulating film;

[0187] The second electrode is disposed on the semiconductor layer;

[0188] A third electrode is disposed on the semiconductor layer; and

[0189] A nitride film is disposed on the semiconductor layer on the second electrode side between the first electrode and the second electrode;

[0190] The nitride film includes a stepped portion on the first electrode side.

[0191] The nitride film and the first insulating film are arranged in the stacking direction of the semiconductor layer and the first electrode.

[0192] The nitride film includes a portion that is directly in contact with the semiconductor layer.

[0193] In the stacking direction of the semiconductor layer and the first electrode, the stepped portion of the nitride film includes a portion that is physically separated from the first insulating film.

[0194] Technical Solution 2

[0195] A semiconductor device, wherein:

[0196] Semiconductor layer;

[0197] A first insulating film is disposed on the semiconductor layer;

[0198] The first electrode is disposed on the first insulating film;

[0199] The second electrode is disposed on the semiconductor layer;

[0200] A third electrode is disposed on the semiconductor layer; and

[0201] A nitride film is disposed on the semiconductor layer on the second electrode side between the first electrode and the second electrode;

[0202] The nitride film and the first insulating film are arranged in the stacking direction of the semiconductor layer and the first electrode.

[0203] The nitride film includes a portion that is directly in contact with the semiconductor layer.

[0204] In the stacking direction of the semiconductor layer and the first electrode, the first electrode side of the nitride film has a portion that overlaps onto the first insulating film on the third electrode side.

[0205] The length of the overlaid portion in the arrangement direction of the first electrode and the third electrode is greater than 0% and less than 5% of the distance from the end face of the third electrode side of the first electrode to the end face of the first electrode side of the third electrode in the arrangement direction of the first electrode and the third electrode.

[0206] Technical Solution 3

[0207] The semiconductor device according to technical solution 1 or 2, wherein,

[0208] In the stacking direction of the semiconductor layer and the first electrode, the stepped portion of the nitride film is physically separated from the first insulating film.

[0209] Technical Solution 4

[0210] The semiconductor device according to any one of technical solutions 1 to 3, wherein,

[0211] In the stacking direction of the semiconductor layer and the first electrode, there is a portion of the first insulating film whose surface facing the nitride film is separated from the surface of the stepped portion of the nitride film facing the first insulating film.

[0212] Technical Solution 5

[0213] The semiconductor device according to any one of technical solutions 1 to 4, wherein,

[0214] The height of the step in the stepped portion of the nitride film is more than 1 and less than 5 times the thickness of the first insulating film.

[0215] Technical Solution 6

[0216] The semiconductor device according to any one of technical solutions 1 to 5, wherein,

[0217] The nitride film is a nitride film containing Al or Al and Ga.

[0218] Technical Solution 7

[0219] The semiconductor device according to any one of technical solutions 1 to 6, wherein,

[0220] The stepped portion contains an amorphous phase.

[0221] Technical Solution 8

[0222] The semiconductor device according to any one of technical solutions 1 to 7, wherein,

[0223] The nitride film is directly connected to the semiconductor layer and the third electrode.

[0224] Technical Solution 9

[0225] The semiconductor device according to any one of technical solutions 1 to 8, wherein,

[0226] The portion of the nitride film that is directly in contact with the semiconductor layer is located between the first insulating film and the third electrode in the arrangement direction of the first electrode and the third electrode.

[0227] Technical Solution 10

[0228] The semiconductor device according to any one of technical solutions 1 to 9, wherein,

[0229] The side of the nitride film opposite to the semiconductor layer side is not directly in contact with the first insulating film.

[0230] Technical Solution 11

[0231] The semiconductor device according to any one of technical solutions 1 to 10, wherein,

[0232] The end face of the nitride film on the first electrode side is not in direct contact with the first insulating film.

[0233] The end face of the nitride film on the first electrode side is not directly connected to the first electrode.

[0234] Technical Solution 12

[0235] The semiconductor device according to any one of technical solutions 1 to 11, wherein,

[0236] The end face of the nitride film on the third electrode side is directly connected to the third electrode.

[0237] Technical Solution 13

[0238] The semiconductor device according to any one of technical solutions 1 to 12, wherein,

[0239] The side of the nitride film facing the semiconductor layer is not in contact with the first insulating film.

[0240] Technical Solution 14

[0241] The semiconductor device according to any one of technical solutions 1 to 13, wherein,

[0242] In the stacking direction of the semiconductor layer and the first electrode, an insulating film with a lower density than the first insulating film is disposed between the nitride film and the first insulating film.

[0243] Technical Solution 15

[0244] The semiconductor device according to any one of technical solutions 1 to 14, wherein,

[0245] The first electrode is a trench electrode.

[0246] Technical Solution 16

[0247] According to the semiconductor device described in technical solution 2, wherein,

[0248] The nitride film also includes a portion located further to the first electrode than the portion attached to it, and the first insulating film is separated from the nitride film.

[0249] Technical Solution 17

[0250] The semiconductor device according to any one of technical solutions 1 to 16 is characterized in that,

[0251] The nitride film runs along the side of the first insulating film on the third electrode side.

[0252] The portion of the nitride film along the side of the third electrode side of the first insulating film includes one or more selected from the group consisting of a portion extending in the stacking direction of the semiconductor layer and the first electrode, a portion inclined relative to the stacking direction of the semiconductor layer and the first electrode, and a portion bent relative to the stacking direction of the semiconductor layer and the first electrode.

[0253] Technical Solution 18

[0254] A method for manufacturing a semiconductor device, characterized by comprising:

[0255] The process of forming a first insulating film on a semiconductor layer;

[0256] The process of forming a second insulating film on the first insulating film;

[0257] The process of forming a first opening on the first insulating film and the second insulating film;

[0258] The process of forming a nitride film on the semiconductor layer exposed at the first opening and on the second insulating film;

[0259] The process of annealing the nitride film;

[0260] The process of patterning the annealed nitride film and removing a portion of the nitride film from the second insulating film;

[0261] The process of removing at least a portion of the second insulating film to expose a portion of the first insulating film;

[0262] The process of forming a first electrode on the first insulating film;

[0263] The steps of forming a second opening in the first insulating film and forming a third opening in the nitride film; and

[0264] The process of forming a second electrode in the second opening and forming a third electrode in the third opening.

[0265] Technical Solution 19

[0266] According to the semiconductor device manufacturing method described in technical solution 18, wherein,

[0267] The first insulating film is denser than the second insulating film.

[0268] The second insulating film is removed by wet etching.

[0269] Technical Solution 20

[0270] The method for manufacturing a semiconductor device according to technical solution 18 or 19, wherein,

[0271] The first insulating film is covered by the second insulating film during the annealing process, or, during the annealing process, a portion of the first insulating film on the side where the nitride film is directly in contact with the semiconductor layer is not covered by the second insulating film.

[0272] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment can be replaced or modified with the constituent elements of other embodiments. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device, characterized in that, have: Semiconductor layer; A first insulating film is disposed on the semiconductor layer; The first electrode is disposed on the first insulating film; The second electrode is disposed on the semiconductor layer; The third electrode is disposed on the semiconductor layer; as well as A nitride film is disposed on the semiconductor layer on the second electrode side between the first electrode and the second electrode; The nitride film includes a stepped portion on the first electrode side. The nitride film and the first insulating film are arranged in the stacking direction of the semiconductor layer and the first electrode. The nitride film includes a portion that is directly in contact with the semiconductor layer. In the stacking direction of the semiconductor layer and the first electrode, the stepped portion of the nitride film includes a portion that is physically separated from the first insulating film.

2. A semiconductor device, characterized in that, have: Semiconductor layer; A first insulating film is disposed on the semiconductor layer; The first electrode is disposed on the first insulating film; The second electrode is disposed on the semiconductor layer; The third electrode is disposed on the semiconductor layer; as well as A nitride film is disposed on the semiconductor layer on the second electrode side between the first electrode and the second electrode; The nitride film and the first insulating film are arranged in the stacking direction of the semiconductor layer and the first electrode. The nitride film includes a portion that is directly in contact with the semiconductor layer. In the stacking direction of the semiconductor layer and the first electrode, the first electrode side of the nitride film has a portion that overlaps onto the first insulating film on the third electrode side. The length of the overlaid portion in the arrangement direction of the first electrode and the third electrode is greater than 0% and less than 5% of the distance from the end face of the first electrode on the third electrode side to the end face of the third electrode on the first electrode side in the arrangement direction of the first electrode and the third electrode.

3. The semiconductor device according to claim 1, characterized in that, In the stacking direction of the semiconductor layer and the first electrode, the stepped portion of the nitride film is physically separated from the first insulating film.

4. The semiconductor device according to claim 1 or 2, characterized in that, In the stacking direction of the semiconductor layer and the first electrode, there is a portion of the first insulating film whose surface facing the nitride film is separated from the surface of the stepped portion of the nitride film facing the first insulating film.

5. The semiconductor device according to claim 1 or 2, characterized in that, The height of the step in the stepped portion of the nitride film is more than 1 and less than 5 times the thickness of the first insulating film.

6. The semiconductor device according to claim 1 or 2, characterized in that, The nitride film is a nitride film containing Al or Al and Ga.

7. The semiconductor device according to claim 1 or 2, characterized in that, The stepped portion contains an amorphous phase.

8. The semiconductor device according to claim 1 or 2, characterized in that, The nitride film is directly connected to the semiconductor layer and the third electrode.

9. The semiconductor device according to claim 1 or 2, characterized in that, The portion of the nitride film that is directly in contact with the semiconductor layer is located between the first insulating film and the third electrode in the arrangement direction of the first electrode and the third electrode.

10. The semiconductor device according to claim 1 or 2, characterized in that, The side of the nitride film opposite to the semiconductor layer side is not in direct contact with the first insulating film.

11. The semiconductor device according to claim 1 or 2, characterized in that, The end face of the nitride film on the first electrode side is not in direct contact with the first insulating film. The end face of the nitride film on the first electrode side is not directly connected to the first electrode.

12. The semiconductor device according to claim 1 or 2, characterized in that, The end face of the nitride film on the third electrode side is directly connected to the third electrode.

13. The semiconductor device according to claim 1, characterized in that, The side of the nitride film facing the semiconductor layer is not in contact with the first insulating film.

14. The semiconductor device according to claim 1, characterized in that, In the stacking direction of the semiconductor layer and the first electrode, an insulating film with a lower density than the first insulating film is disposed between the nitride film and the first insulating film.

15. The semiconductor device according to claim 1, characterized in that, The first electrode is a trench electrode.

16. The semiconductor device according to claim 2, characterized in that, The nitride film also includes a portion located further to the first electrode than the portion attached to it, and the first insulating film is separated from the nitride film.

17. The semiconductor device according to claim 1 or 2, characterized in that, The nitride film runs along the side of the first insulating film on the third electrode side. The portion of the nitride film along the side of the third electrode side of the first insulating film includes one or more selected from the group consisting of a portion extending in the stacking direction of the semiconductor layer and the first electrode, a portion inclined relative to the stacking direction of the semiconductor layer and the first electrode, and a portion bent relative to the stacking direction of the semiconductor layer and the first electrode.

18. A method for manufacturing a semiconductor device, characterized in that, have: The process of forming a first insulating film on a semiconductor layer; The process of forming a second insulating film on the first insulating film; The process of forming a first opening in the first insulating film and the second insulating film; The process of forming a nitride film on the semiconductor layer exposed at the first opening and on the second insulating film; The process of annealing the nitride film; The process of patterning the annealed nitride film and removing a portion of the nitride film from the second insulating film; The process of removing at least a portion of the second insulating film to expose a portion of the first insulating film; The process of forming a first electrode on the first insulating film; The process of forming a second opening in the first insulating film and forming a third opening in the nitride film; as well as The process of forming a second electrode in the second opening and forming a third electrode in the third opening.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that, The first insulating film is denser than the second insulating film. The second insulating film is removed by wet etching.

20. The method of manufacturing a semiconductor device according to claim 18 or 19, characterized in that, The first insulating film is covered by the second insulating film during the annealing process, or, during the annealing process, a portion of the first insulating film on the side where the nitride film is directly in contact with the semiconductor layer is not covered by the second insulating film.

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