Semiconductor die

Abstract

A semiconductor die includes a heteroepitaxial structure including a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a two-dimensional charge carrier gas at or near an interface between the first semiconductor layer and the second semiconductor layer; a first current-driven HEMT in a first region of the semiconductor die, the first current-driven HEMT having a p-type gate region recessed into the second semiconductor layer such that the two-dimensional charge carrier gas is blocked underneath the p-type gate region; a diode device in a second region of the semiconductor die, the diode device configured to inject charge into the p-type gate region under forward bias; and a pull-down device in a third region of the semiconductor die, the pull-down device electrically connected between the p-type gate region and a source of the first current-driven HEMT. The two-dimensional charge carrier gas extends uninterrupted from the first region to the second region and from the second region to the third region.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor dies, and more specifically to semiconductor dies having current-driven transistors, charge-injected diode devices, and pull-down devices. Background Technology

[0002] A normally-off GaN-based transistor, referred to herein as a gate-injected transistor (GIT) high electron mobility transistor (HEMT), utilizes hole injection from the p-GaN region into the AlGaN / GaN heterojunction—which simultaneously increases the electron density in the channel—to achieve a significant increase in drain current through conductivity modulation. Unlike voltage-driven power MOSFETs, the gate of a GIT HEMT actually exhibits diode-like characteristics (i.e., current-driven). GIT HEMTs provide stable gate performance through a self-clamping mechanism. However, GIT HEMTs require a small current injection into the gate to enable conductivity modulation, which can have drawbacks under certain conditions. For example, increasing the gate width and switching frequency requires a larger gate current. Improving the voltage slew rate (i.e., increasing...) This may require a packaging design that does not expose the gate, making gate current control more difficult. Increased saturation current (ID) SAT It also requires a relatively large gate current.

[0003] Therefore, an improved gate current drive technology for GIT HEMT is needed. Summary of the Invention

[0004] According to an embodiment of a semiconductor die, the semiconductor die includes: a heteroepitaxial structure comprising a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a two-dimensional charge carrier gas at or near the interface between the first and second semiconductor layers; a first current-driven HEMT (high electron mobility transistor) located in a first region of the semiconductor die, the first current-driven HEMT having a p-type gate region recessed into the second semiconductor layer such that the two-dimensional charge carrier gas is blocked below the p-type gate region; a diode device located in a second region of the semiconductor die, the diode device being configured to inject charge into the p-type gate region under forward bias; and a pull-down device located in a third region of the semiconductor die, the pull-down device being electrically connected between the source and the p-type gate region of the first current-driven HEMT, wherein the two-dimensional charge carrier gas extends uninterruptedly from the first region to the second region and from the second region to the third region.

[0005] According to another embodiment of the semiconductor die, the semiconductor die includes: a first gate terminal; a source terminal; a drain terminal; a heteroepitaxial structure including a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a two-dimensional charge carrier gas at or near the interface between the first semiconductor layer and the second semiconductor layer; a first current-driven HEMT (high electron mobility transistor) located in a first region of the semiconductor die, the first current-driven HEMT having a p-type gate region recessed into the second semiconductor layer, such that the two-dimensional charge carrier gas is blocked below the p-type gate region; a diode device located in a second region of the semiconductor die, the diode device electrically connecting the first gate terminal to the p-type gate region; and a pull-down device located in a third region of the semiconductor die, the pull-down device being electrically connected between the source and the p-type gate region of the first current-driven HEMT, wherein the two-dimensional charge carrier gas extends uninterruptedly from the first region to the second region and from the second region to the third region.

[0006] Those skilled in the art will recognize the additional features and advantages after reading the following detailed description and viewing the accompanying drawings. Attached Figure Description

[0007] The elements in the accompanying drawings are not necessarily proportional to each other. Similar reference numerals indicate corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Embodiments are depicted in the accompanying drawings and described in detail below.

[0008] Figures 1 to 5 Schematic diagrams of semiconductor dies for monolithic integrated diode devices, including current-driven HEMTs and those driving the gates of current-driven HEMTs, are shown according to various embodiments.

[0009] Figure 6 A cross-sectional view of a portion of a semiconductor die according to another embodiment is shown.

[0010] Figure 7 and Figure 8 A corresponding cross-sectional view of a diode device monolithically integrated in a semiconductor die according to another embodiment is shown.

[0011] Figures 9 to 11 Cross-sectional views of pull-down devices monolithically integrated in a semiconductor die are shown according to various embodiments. Detailed Implementation

[0012] The embodiments described herein provide monolithic integration of a diode device and a current-driven HEMT (High Electron Mobility Transistor) on the same semiconductor chip for driving the gate of the current-driven HEMT, which has a recessed p-type gate region that blocks the two-dimensional charge carrier gas below the p-type gate region. The diode device enables a lower threshold voltage, thereby requiring a smaller gate current to drive the current-driven HEMT without affecting the saturation current, thus enabling new applications of devices based on the GIT HEMT concept. The current-driven HEMT can also be driven without any reduction in gate current, thereby increasing the saturation current, which is beneficial for applications requiring increased saturation current, such as AC line voltage drop in PFC (Power Factor Correction) stages. Pull-down devices for the current-driven HEMT can also be monolithically integrated with the current-driven HEMT and the diode device on the same semiconductor die.

[0013] The following describes an embodiment of a semiconductor die, including a current-driven HEMT and a diode device that drives the gate of the current-driven HEMT, with reference to the accompanying drawings.

[0014] Figure 1 A schematic diagram of an embodiment of a semiconductor die 100 is shown. The semiconductor die 100 includes a current-driven HEMT M1 and a diode device 102 that drives the gate G1 of the current-driven HEMT M1. The diode device 102 may be a pn diode, a Schottky diode, a combined pn-Schottky (MPS) structure, a gate-controlled diode with its gate and source shorted together, or any other type of device having diode characteristics (i.e., belonging to, associated with, or used as a diode). The semiconductor die 100 may also include a pull-down device 104 electrically connected between the gate G1 and the source S1 of the current-driven HEMT M1.

[0015] The gate G1 of the current-driven HEMT M1 includes a recessed p-type region ( Figure 1 (Not shown in the schematic diagram), which blocks the two-dimensional charge carrier gas below the p-type gate region ( Figure 1 (Not shown in the schematic diagram), where a two-dimensional charge carrier gas forms the conductive channel of the current-driven HEMT M1. The p-type region of the gate G1 of the current-driven HEMT actually has diode-like characteristics (i.e., current-driven). Therefore, the current-driven HEMT M1 is a normally-off GIT device.

[0016] In the case of an n-channel device, the two-dimensional charge carrier gas is a two-dimensional electron gas. In the case of a p-channel device, the two-dimensional charge carrier gas is a two-dimensional hole gas. In either case, the pull-down device 104 electrically connected between the gate G1 and the source S1 of the current-driven HEMT M1 is any type of device capable of pulling down the gate G1, thereby ensuring that the current-driven HEMT M1 remains off when the pull-down device 104 is in the active / on state.

[0017] Under forward bias, diode device 102 injects charge into the p-type region of the gate G1 of the current-driven HEMT M1. When the p-type gate region of the current-driven HEMT M1 is turned on / forward biased, the charge (holes) stored in the p-type gate region are released and recombined into the gate G1 to turn on the gate current I of the current-driven HEMT M1. GS Make a contribution. The threshold voltage of a current-driven HEMT M1 is the saturation current (ID). SAT The key parameters of the current-driven HEMT M1 include the threshold voltage, which determines the conduction current (If) generated between the source S1 and drain D1. DS The stronger the threshold voltage, the better. Typically, threshold voltage regulation is achieved by adjusting the thickness of the AlGaN barrier via a regeneration design.

[0018] The diode device 102 described herein enables a reduction in the threshold voltage, thereby reducing the gate current I required for a current-driven HEMT M1. GS This does not significantly affect the forward voltage of the gate diode, which is part of the gate G1 of the current-driven HEMT M1. Simulation results show that adjusting the gate overdrive of the current-driven HEMT M1 via diode device 102 maintains a constant drain current I. DS This will cause the gate current I GS This reduces the current by a factor of 10. Alternatively, a current-driven HEMT M1 can be driven without any reduction in gate current, thereby increasing the saturation current.

[0019] The diode portion of the gate G1 of the current-driven HEMT M1 is composed of Figure 1 The middle is marked as "V" F The diode is indicated by "". The gate-to-source capacitance of the current-driven HEMT M1 is... Figure 1 The middle is marked as "C" GS The capacitor is indicated by "". The gate-to-drain capacitance of the current-driven HEMTM1 is composed of... Figure 1 The middle is marked as "C" GD The capacitor is indicated by "". The drain-to-source capacitance of the current-driven HEMT M1 is composed of... Figure 1 The middle is marked as "C"DS The capacitor is represented by "".

[0020] The semiconductor die 100 also includes a gate terminal "G" for controlling the gate G1 of the current-driven HEMT M1, a source terminal "S" electrically connected to the source S1 of the current-driven HEMT M1, and a drain terminal "D" electrically connected to the drain D1 of the current-driven HEMT M1. Terminals G, S, and D enable external points to make electrical contact with the semiconductor die 100 for providing signal, power, and / or ground connections to the semiconductor die 100. That is, terminals G, S, and D, as part of the semiconductor die 100, can make electrical contact with components outside the semiconductor die 100 and provide corresponding signal / power / ground connections to corresponding nodes within the semiconductor die 100. The terminals G, S, and D of the semiconductor die 100 can be implemented as pins, leads, buses, connectors, disks, etc.

[0021] Figure 2 A schematic diagram of a semiconductor die 100 according to another embodiment is shown. Figure 2 In this embodiment, diode device 102 is implemented as diode 200. The anode 202 of diode 200 is electrically connected to the gate terminal G of semiconductor die 100. The cathode 204 of diode is electrically connected to the gate G1 of current-driven HEMT M1.

[0022] Figure 3 A schematic diagram of a semiconductor die 100 according to another embodiment is shown. Figure 3 In this embodiment, diode device 102 is implemented as a gate-controlled diode 300. A gate-controlled diode is a transistor structure in which the gate 302 and source 304 are shorted together. The gate 302 and source 304 of the gate-controlled diode 300 are electrically connected to the gate terminal G of the semiconductor die 100. The drain 306 of the gate-controlled diode 300 is electrically connected to the gate G1 of the current-driven HEMT M1.

[0023] Figure 4 A schematic diagram of a semiconductor die 100 according to another embodiment is shown. Figure 4 The implementation shown is similar to Figure 2 The implementation method is shown in the figure. Figure 4 In this configuration, the pull-down device 104 is implemented as a second current-driven HEMT M2 with a gate G2, the second current-driven HEMT M2 having a recessed p-type gate region (in... Figure 4(Not shown in the schematic diagram), which blocks the two-dimensional charge carrier gas below the p-type gate region of the second (pull-down) current-driven HEMT M2. The source S2 of the pull-down current-driven HEMT M2 is electrically connected to the source of the main (power) current-driven HEMT M1. The drain D2 of the pull-down current-driven HEMT M2 is electrically connected to the gate G1 of the main current-driven HEMT M1, for example at the intermediate node 400 between the diode device 102 and the gate G1 of the main current-driven HEMT M1.

[0024] Similarly, in Figure 4 In this embodiment, the gates G1 and G2 of the current-driven HEMT M1 and the current-driven HEMT M2 are electrically connected to different electrically isolated gate terminals G_1 and G_2 of the semiconductor chip 100. According to this embodiment, the main current-driven HEMT M1 is controlled via the first gate terminal G_1 of the semiconductor die 100, and the pull-down current-driven HEMT M2 is controlled via the second gate terminal G_2 of the semiconductor die 100. The second gate terminal G_2 of the semiconductor die 100 is electrically isolated from the first gate terminal G_1 of the semiconductor die 100.

[0025] Figure 5 A schematic diagram of a semiconductor die 100 according to another embodiment is shown. Figure 5 The implementation shown is similar to Figure 4 The implementation method is shown in the figure. Figure 5 middle, Figure 3 The gate-controlled diode 300 shown is not Figure 2 The diode 200 shown is used as diode device 102.

[0026] Figure 6 A cross-sectional view of a portion of a semiconductor die 100 according to another embodiment is shown. Figure 6 In this embodiment, the semiconductor die 100 includes a heteroepitaxial structure 600, which includes a first semiconductor layer 602 and a second semiconductor layer 604 on the first semiconductor layer 602. The first semiconductor layer 602 and the second semiconductor layer 604 have different bandgap energies, and a two-dimensional charge carrier gas 606 exists at or near the interface between the first semiconductor layer 602 and the second semiconductor layer 604. As previously described, the two-dimensional charge carrier gas 606 is a two-dimensional electron gas in the case of an n-channel device and a two-dimensional hole gas in the case of a p-channel device.

[0027] In one embodiment, the first semiconductor layer 602 is a GaN layer, and the second semiconductor layer 604 is an AlGaN layer. However, other heteroepitaxial material systems can also be used. For example, the heteroepitaxial structure 600 may include InP, InN, InAlN, InGaN, GaN with an AlN spacer, GaAs, AlGaAs, etc. In each case, the junction between the first semiconductor layer 602 and the second semiconductor layer 604, which are materials with different band gaps, generates a two-dimensional charge carrier gas 606, which forms the channel of the main current driven HEMT M1 (and the pull-down current driven HEMTM2) rather than through a doped region. One or more transition layers 608 may be formed below the first semiconductor layer 602, for example, one or more nucleation layers on a substrate 610 such as silicon, silicon carbide, sapphire, etc.

[0028] A main current driven HEMT M1 is formed in a first region 612 of the semiconductor die 100. The main current driven HEMT M1 includes a p-type gate region 614 recessed into a second semiconductor layer 604, such that the two-dimensional charge carrier gas 606 is blocked below the p-type gate region 614, as... Figure 6 The rightmost break in the dashed line representing the two-dimensional charge carrier gas 606 is indicated in the diagram. The recessed p-type gate region 614 of the main current driven HEMT M1 can have a T-shaped profile. A thinner portion of the p-type gate region 614 is formed on the upper surface of the second semiconductor layer 604 (e.g., AlGaN), and a thicker portion of the p-type gate region 614 is placed in a recess 616 formed in the upper surface of the second semiconductor layer 604. The thinner remaining portion 618 of the second semiconductor layer 604 at the bottom of the recess 616 separates the p-type gate region 614 (e.g., p-GaN, p-AlGaN, etc.) of the main current driven HEMT M1 from the underlying first semiconductor layer 602.

[0029] A diode device 102 is formed in the second region 620 of the semiconductor die 100. Under forward bias, the diode device 102 injects charge into the p-type gate region 614 of the main current driven HEMT M1. The diode device 102... Figure 6 The middle is realized as Figure 2 and Figure 4 The diode 200 shown has its anode 202 electrically connected to the first gate terminal G_1 of the main current driven HEMT M1 of the semiconductor die 100, and its cathode 204 electrically connected to the p-type gate region 614 of the main current driven HEMT M1. However, the diode device 102 can be any type of device with diode characteristics. For example, the diode device 102 can be implemented as follows: Figure 3 and Figure 5 The gate-controlled diode 300 shown in the figure: a HEMT device is formed in the second region 620 of the semiconductor die 100, but the source and gate of the HEMT device are shorted together and electrically connected to the first gate terminal G_1 of the control main current driven HEMT M1 of the semiconductor die 100.

[0030] The pull-down device 104 is formed in the third region 622 of the semiconductor die 100. The pull-down device 104 is... Figure 6 The middle is realized as follows Figure 4 and Figure 5 The current-driven HEMT M2 shown is electrically connected between the p-type gate region 614 and the source S1 of the main current-driven HEMT M1. The pull-down current-driven HEMT M2 has a recessed p-type gate region 624, which blocks the two-dimensional charge carrier gas 606 below the p-type gate region 624 of the pull-down current-driven HEMT M2, as shown. Figure 6 The dashed line representing the two-dimensional charge carrier gas 606 indicates the break at the far left. The p-type gate region 624 of the pull-down current-driven HEMT M2 can be recessed in the same or similar manner as the p-type gate region 614 of the main current-driven HEMT M1 described above. The source S2 of the pull-down current-driven HEMT M2 and the source S1 of the main current-driven HEMT M1 are electrically connected to each other and electrically connected to the source terminal S of the semiconductor die 100. The drain D2 of the pull-down current-driven HEMT M2 is electrically connected to the p-type gate region 614 of the main current-driven HEMT M1. The sources S1, S2 and drains D1, D2 of the current-driven HEMTs M1 and M2 can be implemented as doped semiconductor regions and / or metal contacts.

[0031] No channel / two-dimensional charge carrier gas isolation is required between diode device 102 and main current driven HEMT M1. That is, diode device 102 and main current driven HEMT M1 can be formed side-by-side in a true monolithic solution without isolation and share a common channel / two-dimensional charge carrier gas 606, for example, as... Figure 6 As shown. This layout avoids unnecessary processing. Furthermore, implementing the pull-down device 104 would be more challenging if isolation were used. Figure 6 The illustrated embodiment does not employ isolation to separate the channel / two-dimensional charge carrier gas 606 between the main current-driven HEMT M1 and the diode device 102. Therefore, in Figure 6In the process, a two-dimensional charge carrier gas 606 extends uninterruptedly from a first region 612 of the semiconductor die 100 to a second region 620 of the semiconductor die 100, and from the second region 620 to a third region 622 of the semiconductor die 100. Figure 6 The only interruption of the two-dimensional charge carrier gas 606 occurs below the p-type gate region 624 of the pull-down current driven HEMT M2 and below the p-type gate region 614 of the main current driven HEMT M1.

[0032] When the main current driven HEMT M1 is turned on in the forward direction, it can preferably have a lower threshold voltage to allow for a higher saturation current, but this increases the risk of false turn-on due to the inherent Miller clamp effect. Pull-down device 104 mitigates such false turn-on. By pulling down the p-type gate region 614 of the main current driven HEMT M1 via pull-down device 104, lower gate driver losses are ensured, and for the same gate current I... GS Able to generate higher IDs SAT At the same time, ensure the safe shutdown of the main current driven HEMT M1.

[0033] Figure 7 A cross-sectional view of a diode device 102 monolithically integrated in a semiconductor die 100 according to an embodiment is shown. Figure 7 In the diode device 102, there are an anode 202 and a cathode 204. The anode 202 is electrically connected to the first gate terminal G_1 of the main current driven HEMT M1 of the semiconductor die 100, and the cathode 204 is electrically connected to the p-type gate region 614 of the main current driven HEMT M1. The anode 202 of the diode device 102 can be implemented by, for example, a p-type GaN or AlGaN region 700, and the cathode 204 of the diode device 102 can be implemented by, for example, an n-type GaN or AlGaN region 702.

[0034] exist Figure 7 In the process, the p-type anode region 700 of the diode device 102 is recessed into the second semiconductor layer 604 of the heteroepitaxial structure 600, thereby blocking the two-dimensional charge carrier gas 606 below the p-type anode region 700, such as... Figure 7The dashed line indicating the break in the two-dimensional charge carrier gas 606 is shown in the diagram. The p-type anode region 700 may have a T-like shape, with a thinner portion of the p-type anode region 700 formed on the upper surface of the second semiconductor layer 604 (e.g., AlGaN), and a thicker portion of the p-type anode region 700 placed in a recess 704 formed in the upper surface of the second semiconductor layer 604. The thinner portion 706 remaining at the bottom of the recess 704 of the second semiconductor layer 604 separates the p-type anode region 700 (e.g., p-GaN, p-AlGaN, etc.) from the underlying first semiconductor layer 602. Figure 7 In the diode device 102, the n-type cathode region 702 is not recessed into the second semiconductor layer 604.

[0035] Figure 8 A cross-sectional view of a diode device 102 monolithically integrated in a semiconductor die 100 according to another embodiment is shown. Figure 8 The implementation shown is similar to Figure 7 The embodiment shown is different in that the p-type anode region 700 of the diode device 102 is formed on the non-recessed portion 800 of the second semiconductor layer 604 of the heteroepitaxial structure 600. According to this embodiment, the two-dimensional charge carrier gas 606 is not blocked below the p-type anode region 700 of the diode device 102. That is, no recess is formed in the upper surface of the second semiconductor layer 604, and both the p-type anode region 700 and the n-type cathode region 702 of the diode device 102 are completely formed on the upper surface of the second semiconductor layer 604.

[0036] Figure 9 A cross-sectional view of a pull-down device 104 monolithically integrated in a semiconductor die 100 according to an embodiment is shown. Figure 9 In the pull-down current driven HEMT M2, the p-type gate region 624 is positioned closer to the source S2 of the pull-down current driven HEMT M2 than the drain D2 of the pull-down current driven HEMT M2.

[0037] Figure 10 A cross-sectional view of a pull-down device 104 monolithically integrated in a semiconductor die 100 according to another embodiment is shown. Figure 10 In the pull-down current driven HEMT M2, the p-type gate region 624 is equidistant from the source S2 and drain D2 of the pull-down current driven HEMT M2.

[0038] Figure 11 A cross-sectional view of a pull-down device 104 monolithically integrated in a semiconductor die 100 according to another embodiment is shown. Figure 11In the pull-down current driven HEMT M2, there are metal source contact 1100, metal drain contact 1102 and p-type region 1104 (e.g. p-GaN, p-AlGaN, etc.). The p-type region 1104 is located on the second semiconductor layer 604 of the heteroepitaxial structure 600, between the metal drain contact 1102 and the p-type gate region 624 of the pull-down current driven HEMT M2.

[0039] Although this disclosure is not limited thereto, the following numbered examples illustrate one or more aspects of this disclosure.

[0040] Example 1. A semiconductor die, comprising: a heteroepitaxial structure including a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a two-dimensional charge carrier gas at or near the interface between the first and second semiconductor layers; a first current-driven HEMT (high electron mobility transistor) located in a first region of the semiconductor die, the first current-driven HEMT having a p-type gate region recessed into the second semiconductor layer such that the two-dimensional charge carrier gas is blocked below the p-type gate region; a diode device located in a second region of the semiconductor die, the diode device being configured to inject charge into the p-type gate region under forward bias; and a pull-down device located in a third region of the semiconductor die, the pull-down device being electrically connected between the source and the p-type gate region of the first current-driven HEMT, wherein the two-dimensional charge carrier gas extends uninterruptedly from the first region to the second region and from the second region to the third region.

[0041] Example 2. According to the semiconductor die of Example 1, wherein the pull-down device includes a second current-driven HEMT having a p-type gate region recessed into a second semiconductor layer, such that a two-dimensional charge carrier gas is blocked below the p-type gate region of the second current-driven HEMT.

[0042] Example 3. According to the semiconductor die of Example 2, wherein the p-type gate region of the second current-driven HEMT is positioned closer to the source of the second current-driven HEMT than the drain of the second current-driven HEMT.

[0043] Example 4. According to the semiconductor die of Example 2, wherein the p-type gate region of the second current-driven HEMT is equidistant from the source and drain of the second current-driven HEMT.

[0044] Example 5. A semiconductor die according to any one of Examples 2 to 4, wherein the second current-driven HEMT further includes: a metal source contact; a metal drain contact; and a p-type region located on the second semiconductor layer, between the p-type gate region and the metal drain contact of the second current-driven HEMT.

[0045] Example 6. A semiconductor die according to any one of Examples 2 to 5, wherein a first current-driven HEMT is controlled via a first gate terminal of the semiconductor die, and a second current-driven HEMT is controlled via a second gate terminal of the semiconductor die that is electrically isolated from the first gate terminal.

[0046] Example 7. A semiconductor die according to any one of Examples 1 to 6, wherein the diode device includes an anode electrically connected to a gate terminal of the semiconductor die and a cathode electrically connected to a p-type gate region of a first current-driven HEMT.

[0047] Example 8. A semiconductor die according to Example 7, wherein the anode includes a p-type region recessed into a second semiconductor layer.

[0048] Example 9. A semiconductor die according to Example 7, wherein the anode includes a p-type region formed on a non-recessed portion of the second semiconductor layer.

[0049] Example 10. A semiconductor die according to any one of Examples 1 to 6, wherein the diode device is a gate-controlled diode having a gate and a source electrically connected to a gate terminal of the semiconductor die and a drain electrically connected to a p-type gate region of a first current-driven HEMT.

[0050] Example 11. A semiconductor die, comprising: a first gate terminal; a source terminal; a drain terminal; a heteroepitaxial structure including a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a two-dimensional charge carrier gas at or near the interface between the first semiconductor layer and the second semiconductor layer; a first current-driven HEMT (high electron mobility transistor) located in a first region of the semiconductor die, the first current-driven HEMT having a p-type gate region recessed into the second semiconductor layer such that the two-dimensional charge carrier gas is blocked below the p-type gate region; a diode device located in a second region of the semiconductor die, the diode device electrically connecting the first gate terminal to the p-type gate region; and a pull-down device located in a third region of the semiconductor die, the pull-down device being electrically connected between the source and the p-type gate region of the first current-driven HEMT, wherein the two-dimensional charge carrier gas extends uninterruptedly from the first region to the second region and from the second region to the third region.

[0051] Example 12. A semiconductor die according to Example 11, wherein the pull-down device includes a second current-driven HEMT having a p-type gate region recessed into a second semiconductor layer, such that a two-dimensional charge carrier gas is blocked below the p-type gate region of the second current-driven HEMT.

[0052] Example 13. A semiconductor die according to Example 12, wherein the p-type gate region of the second current-driven HEMT is positioned closer to the source of the second current-driven HEMT than the drain of the second current-driven HEMT.

[0053] Example 14. A semiconductor die according to Example 12, wherein the p-type gate region of the second current-driven HEMT is equidistant from the source and drain of the second current-driven HEMT.

[0054] Example 15. A semiconductor die according to any one of Examples 12 to 14, wherein the second current-driven HEMT further includes: a metal source contact; a metal drain contact; and a p-type region located on the second semiconductor layer, between the p-type gate region of the second current-driven HEMT and the metal drain contact.

[0055] Example 16. A semiconductor die according to any one of Examples 12 to 15, further comprising: a second gate terminal electrically isolated from the first gate terminal, wherein the first current-driven HEMT is controlled via the first gate terminal and the second current-driven HEMT is controlled via the second gate terminal.

[0056] Example 17. A semiconductor die according to any one of Examples 11 to 16, wherein the diode device includes an anode electrically connected to a first gate terminal and a cathode electrically connected to a p-type gate region of a first current-driven HEMT.

[0057] Example 18. A semiconductor die according to Example 17, wherein the anode includes a p-type region recessed into a second semiconductor layer.

[0058] Example 19. A semiconductor die according to Example 17, wherein the anode includes a p-type region formed on a non-recessed portion of the second semiconductor layer.

[0059] Example 20. A semiconductor die according to any one of Examples 11 to 16, wherein the diode device is a gate-controlled diode having a gate and a source electrically connected to a first gate terminal and a drain electrically connected to a p-type gate region of a first current-driven HEMT.

[0060] For example, terms such as "first" and "second" are used to describe various elements, regions, parts, etc., and are not intended to be limiting. Throughout the specification, similar terms refer to similar elements.

[0061] As used herein, the terms “having,” “containing,” “including,” “comprising,” etc., are open-ended terms indicating the presence of the stated element or feature, but not excluding additional elements or features. The articles “a,” “an,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0062] The expression “and / or” should be interpreted to cover all possible combinations of conjunctions and disjunctions, unless otherwise expressly stated. For example, the expression “A and / or B” should be interpreted to mean A but not B, B but not A, or both A and B. The expression “at least one” should be interpreted in the same manner as “and / or”, unless otherwise expressly stated. For example, the expression “at least one of A and B” should be interpreted to mean A but not B, B but not A, or both A and B.

[0063] It should be understood that the features of the various embodiments described herein can be combined with each other, unless otherwise specifically indicated.

[0064] Although specific embodiments have been described and illustrated herein, those skilled in the art will understand that various alternatives and / or equivalent implementations can be used instead of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.

Claims

1. A semiconductor die, comprising: A heteroepitaxial structure comprising a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a two-dimensional charge carrier gas at or near the interface between the first semiconductor layer and the second semiconductor layer; A first current-driven high electron mobility transistor (HEMT) is located in a first region of the semiconductor die. The first current-driven HEMT has a p-type gate region recessed into the second semiconductor layer, such that the two-dimensional charge carrier gas is blocked below the p-type gate region. A diode device located in a second region of the semiconductor die, the diode device being configured to inject charge into the p-type gate region under forward bias; as well as A pull-down device, located in the third region of the semiconductor die, is electrically connected between the source and the p-type gate region of the first current-driven HEMT. The two-dimensional charge carrier gas extends continuously from the first region to the second region and from the second region to the third region.

2. The semiconductor die according to claim 1, wherein, The pull-down device includes a second current-driven HEMT having a p-type gate region recessed into the second semiconductor layer, such that the two-dimensional charge carrier gas is blocked below the p-type gate region of the second current-driven HEMT.

3. The semiconductor die according to claim 2, wherein, The p-type gate region of the second current-driven HEMT is positioned closer to the source of the second current-driven HEMT than the drain of the second current-driven HEMT.

4. The semiconductor die according to claim 2, wherein, The p-type gate region of the second current-driven HEMT is equidistant from the source and drain of the second current-driven HEMT.

5. The semiconductor die according to claim 2, wherein, The second current-driven HEMT also includes: Metal source electrode contact; Metal drain contact; and The p-type region is located on the second semiconductor layer, between the p-type gate region of the second current-driven HEMT and the metal drain contact.

6. The semiconductor die according to claim 2, wherein, The first current-driven HEMT is controlled via a first gate terminal of the semiconductor die, and the second current-driven HEMT is controlled via a second gate terminal of the semiconductor die that is electrically isolated from the first gate terminal.

7. The semiconductor die according to claim 1, wherein, The diode device includes an anode electrically connected to the gate terminal of the semiconductor die and a cathode electrically connected to the p-type gate region of the first current-driven HEMT.

8. The semiconductor die according to claim 7, wherein, The anode includes a p-type region recessed into the second semiconductor layer.

9. The semiconductor die according to claim 7, wherein, The anode includes a p-type region formed on a non-recessed portion of the second semiconductor layer.

10. The semiconductor die according to claim 1, wherein, The diode device is a gate-controlled diode, which has a gate and a source electrically connected to the gate terminal of the semiconductor die, and a drain electrically connected to the p-type gate region of the first current-driven HEMT.

11. A semiconductor die, comprising: First gate terminal; source terminal; Leaking extremes; A heteroepitaxial structure comprising a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a two-dimensional charge carrier gas at or near the interface between the first semiconductor layer and the second semiconductor layer; A first current-driven high electron mobility transistor (HEMT) is located in a first region of the semiconductor die. The first current-driven HEMT has a p-type gate region recessed into the second semiconductor layer, such that the two-dimensional charge carrier gas is blocked below the p-type gate region. A diode device located in the second region of the semiconductor die, the diode device electrically connecting the first gate terminal to the p-type gate region; as well as A pull-down device, located in the third region of the semiconductor die, is electrically connected between the source and the p-type gate region of the first current-driven HEMT. The two-dimensional charge carrier gas extends continuously from the first region to the second region and from the second region to the third region.

12. The semiconductor die according to claim 11, wherein, The pull-down device includes a second current-driven HEMT having a p-type gate region recessed into the second semiconductor layer, such that the two-dimensional charge carrier gas is blocked below the p-type gate region of the second current-driven HEMT.

13. The semiconductor die according to claim 12, wherein, The p-type gate region of the second current-driven HEMT is positioned closer to the source of the second current-driven HEMT than the drain of the second current-driven HEMT.

14. The semiconductor die according to claim 12, wherein, The p-type gate region of the second current-driven HEMT is equidistant from the source and drain of the second current-driven HEMT.

15. The semiconductor die according to claim 12, wherein, The second current-driven HEMT also includes: Metal source electrode contact; Metal drain contact; and The p-type region is located on the second semiconductor layer, between the p-type gate region of the second current-driven HEMT and the metal drain contact.

16. The semiconductor die according to claim 12, further comprising: The second gate terminal is electrically isolated from the first gate terminal. The first current-driven HEMT is controlled via the first gate terminal, and the second current-driven HEMT is controlled via the second gate terminal.

17. The semiconductor die according to claim 11, wherein, The diode device includes an anode electrically connected to the first gate terminal and a cathode electrically connected to the p-type gate region of the first current-driven HEMT.

18. The semiconductor die according to claim 17, wherein, The anode includes a p-type region recessed into the second semiconductor layer.

19. The semiconductor die according to claim 17, wherein, The anode includes a p-type region formed on a non-recessed portion of the second semiconductor layer.

20. The semiconductor die according to claim 11, wherein, The diode device is a gate-controlled diode, which has a gate and a source electrically connected to the first gate terminal and a drain electrically connected to the p-type gate region of the first current-driven HEMT.

Images