Semiconductor device

Abstract

One embodiment provides a semiconductor device having a high breakdown voltage and high reliability. According to one embodiment, a semiconductor device includes: first, second, and third semiconductor regions stacked in order, each region containing impurities of a first, second, and first conduction type, respectively; a first conductor surrounded by and spaced apart from the first semiconductor region; a first insulating portion containing a first insulator disposed in contact with each of a bottom surface and side surfaces near a bottom of the first conductor; a second insulating portion including a gap region disposed on a side surface of the first conductor on which the first insulator is not disposed; a second conductor disposed above the first conductor and spaced apart from the first conductor and the second semiconductor region; and a second insulator disposed in contact with each of the second semiconductor region and the second conductor.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2025-047412, filed on March 21, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to semiconductor devices. Background Technology

[0004] Semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) are used in applications such as power conversion. These semiconductor devices require high breakdown voltage and high reliability. Summary of the Invention

[0005] One embodiment provides a semiconductor device with high breakdown voltage and high reliability.

[0006] Typically, according to one embodiment, a semiconductor device includes: a first semiconductor region containing a first impurity having a first conductivity type; a second semiconductor region disposed on the first semiconductor region and containing a second impurity having a second conductivity type different from the first conductivity type; a third semiconductor region disposed on the second semiconductor region and containing a third impurity having the first conductivity type; a first conductor surrounded by and spaced apart from the first semiconductor region; a first insulating portion disposed between the first semiconductor region and the first conductor, contacting each of a bottom surface and a side surface near the bottom of the first conductor, wherein the first insulating portion includes a first insulator; a second insulating portion disposed on the side surface of the first conductor between the first semiconductor region and the first conductor where the first insulator is not disposed, wherein the second insulating portion includes a gap region; a second conductor disposed above the first conductor and spaced apart from the first conductor and the second semiconductor region; and a second insulator disposed between the second semiconductor region and the second conductor, contacting each of the second semiconductor region and the second conductor. Attached Figure Description

[0007] Figure 1 This is a plan view illustrating an example of a planar layout of a semiconductor device according to the first embodiment.

[0008] Figure 2 This is a plan view illustrating an example of a planar layout of a semiconductor device according to the first embodiment.

[0009] Figure 3 It is along Figure 2The cross-sectional view taken by line III-III shows an example of the cross-sectional structure of the semiconductor device according to the first embodiment.

[0010] Figure 4 It is along Figure 2 The cross-sectional view taken by line IV-IV shows an example of the cross-sectional structure of a semiconductor device according to the first embodiment.

[0011] Figure 5 This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device according to the first embodiment.

[0012] Figure 6 This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device according to the first embodiment.

[0013] Figure 7 This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device according to the first embodiment.

[0014] Figure 8 This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device according to the first embodiment.

[0015] Figure 9 This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device according to the first embodiment.

[0016] Figure 10 This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device according to the first embodiment.

[0017] Figure 11 This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device according to the first embodiment.

[0018] Figure 12 This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device according to the first embodiment.

[0019] Figure 13 This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device according to the first embodiment.

[0020] Figure 14 This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device according to the first embodiment.

[0021] Figure 15 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor device according to the second embodiment.

[0022] Figure 16 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor device according to the third embodiment.

[0023] Figure 17This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor device according to the fourth embodiment.

[0024] Figure 18 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor device according to the fifth embodiment. Detailed Implementation

[0025] In the following description, embodiments will be described with reference to the accompanying drawings. Components having substantially the same function and structure are indicated by the same reference numerals in the description.

[0026] In the following description, the statement that the first element is “connected” to the second element includes cases where the first element is indirectly connected to the second element through an intermediate element that is always or selectively conductive, or cases where the first element is directly connected to the second element without an intermediate element.

[0027] In the accompanying drawings referenced in the following description, an XYZ orthogonal coordinate system is used. The Z direction is also called the "upward direction," and the opposite direction of the Z direction is called the "downward direction." Furthermore, in the plan views, shading lines are appropriately added to enhance the visibility of the drawings. The shading added in the plan views is not necessarily related to the material or properties of the part being shaded.

[0028] 1. First Embodiment

[0029] 1.1 Planar Structure

[0030] Figure 1 and Figure 2 Each is a plan view showing an example of a planar layout of a semiconductor device according to the first embodiment. Figure 1 A planar layout showing the appearance of the semiconductor device 100 is presented. Figure 2 The planar layout of the internal structure of the semiconductor device 100 is shown. (Example) Figure 1 and Figure 2 As shown, the semiconductor device 100 includes conductors 10, 20, 32, and 33, an insulator 25, and contacts C1 and C2. Figure 2 In this text, the insulator is partially omitted. Furthermore, in... Figure 2 In the diagram, the locations of conductors 32 and 33 are shown as areas enclosed by dashed lines.

[0031] Semiconductor device 100 is a transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). Semiconductor device 100 connects or isolates the drain and source terminals according to the voltage applied to the gate terminal. An explanation of the case where semiconductor device 100 is an n-channel MOSFET will be given below. Figure 1As described, conductors 32 and 33 are exposed on the upper surface of semiconductor device 100 and are spaced apart from each other. Conductor 32 is configured to extend in the XY plane. Conductor 32 serves as an electrode intervening in the connection between semiconductor device 100 and an external device, and also serves as a source pad. Conductor 33 includes a first portion 33a and a second portion 33b. The first portion 33a of conductor 33 extends in the XY plane. The first portion 33a of conductor 33 serves as an intermediate electrode for the connection between semiconductor device 100 and an external device, and also serves as a gate pad. The second portion 33b of conductor 33 is configured to surround conductor 32 in a square ring shape in plan view, and contacts the first portion 33a at its end. The second portion 33b of conductor 33 serves as an interconnect connecting the first portion 33a to components disposed within semiconductor device 100. The portions of the upper surface of semiconductor device 100 where conductors 32 and 33 are not disposed are covered by insulator 25. Insulator 25 comprises, for example, silicon oxide (SiO).

[0032] like Figure 2 As shown, each of the plurality of conductors 10 extends in the Y direction and is arranged side by side in the X direction. Figure 2 In the example shown, multiple conductors 10 are arranged in two rows in the Y direction. Each conductor 10 serves as a field plate electrode. The multiple conductors 10 contain, for example, aluminum (Al), molybdenum (Mo), or polycrystalline silicon.

[0033] At the ends of the plurality of conductors 10 in the Y direction, which overlap in the Z direction, a plurality of contacts C1 are provided. Each contact C1 extends in the Z direction and electrically connects the associated conductor 10 to the conductor 32.

[0034] Multiple conductors 20 are disposed above multiple conductors 10 and below conductor 33. Each of the multiple conductors 20 extends in the Y direction and is arranged side by side in the X direction so as to overlap with the associated conductor 10 in the Z direction. Figure 2 In the example shown, multiple conductors 20 are arranged in two rows in the Y direction, similar to multiple conductors 10. Conductors 10 and 20, located at overlapping positions in the Z direction, are spaced apart from each other and electrically isolated. Each conductor 20 serves as a gate electrode. The multiple conductors 20 contain, for example, aluminum, molybdenum, or polycrystalline silicon.

[0035] At the ends of the multiple conductors 20 in the Y direction that overlap in the Z direction, multiple contacts C2 are provided. Each contact C2 extends in the Z direction and electrically connects the associated conductor 20 to the conductor 33.

[0036] 1.2 Cross-sectional structure

[0037] Figure 3 It is along Figure 2The cross-sectional view taken by line III-III shows an example of the cross-sectional structure of the semiconductor device according to the first embodiment. Figure 4 It is along Figure 2 The cross-sectional view taken along line IV-IV shows an example of the cross-sectional structure of a semiconductor device according to the first embodiment. Figure 3 and Figure 4 As shown, the semiconductor device 100 also includes a semiconductor 1, insulating portions 11, 12, and 13, an insulator 21, and a conductor 31. The semiconductor 1 contains, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or gallium arsenide (GaAs) as the semiconductor material. When the semiconductor 1 contains silicon as the semiconductor material, n-type impurities such as arsenic (As), phosphorus (P), or antimony (Sb) can be used. For example, boron (B) or indium (In) can be used as p-type impurities.

[0038] Conductor 31 is exposed on the lower surface of semiconductor device 100. Conductor 31 serves as a drain pad. It should be noted that conductor 31 does not need to be fully exposed on the lower surface of semiconductor device 100; for example, a portion of conductor 31 may be covered with an insulator not described.

[0039] A semiconductor 1 is disposed above conductor 31. Semiconductor 1 is, for example, a silicon substrate. Semiconductor 1 includes semiconductor regions 2, 3, 4, 5, and 6, which are classified based on the conductivity type and amount of impurities contained therein. More specifically, semiconductor region 2 is disposed at its contact with conductor 31. Semiconductor region 2 is in which n-type impurities are present at a high concentration (n... + The doped region. The concentration of n-type impurities in semiconductor region 2 is more than ten times higher than the concentration of n-type impurities in semiconductor region 3, which will be described later, and is, for example, 1.0 × 10⁻⁶. 17 cm -3Or larger. Semiconductor region 2 is electrically connected to conductor 31. Semiconductor region 2 serves as a region connected to the drain terminal. Above semiconductor region 2, semiconductor region 3 is disposed. Semiconductor region 3 is a region in which n-type impurities are doped at a low concentration (n-). Semiconductor region 3 serves as a drift layer. Above semiconductor region 3, semiconductor region 4 is disposed. Semiconductor region 4 is a region in which p-type impurities are doped (p). Semiconductor region 4 is disposed at a position sandwiched by multiple conductors 20 in the X direction. Semiconductor region 4 serves as a region in which a channel (inversion layer) is formed. The boundary between semiconductor regions 3 and 4 corresponds to a pn junction. Above semiconductor region 4, semiconductor regions 5 and 6 are selectively disposed. Semiconductor region 5 is a region in which p-type impurities are doped at a high concentration (p+). For example, in semiconductor region 4, the portion on which semiconductor region 5 is disposed is configured to be thinner in the Z direction than the portion on which semiconductor region 6 is disposed. Semiconductor region 5 is disposed at a position sandwiched in the middle by semiconductor region 4 in the X direction. Semiconductor region 5 is not adjacent to the trench structure TRC, which will be described later. Semiconductor region 5 is used as the region to be connected to the gate terminal. Semiconductor region 6 is at a high concentration (n) + The region is doped with n-type impurities. The lower surface of semiconductor region 6 is configured to be, for example, higher than the upper surface of semiconductor region 5. Semiconductor region 6 is configured to sandwich the trench structure TRC, which will be described later, in the X direction. Semiconductor region 6 serves as the region to be connected to the source terminal. It should be noted that the structures of semiconductor regions 5 and 6 described above are merely examples. The structures of semiconductor regions 5 and 6 can be appropriately designed as long as semiconductor region 5 is used as the region that contacts semiconductor region 4 and is connected to the gate terminal, and semiconductor region 6 is used as the region that is connected to the source terminal.

[0040] Note that the boundary between semiconductor regions 2 and 3 is conveniently defined based on the concentration gradient of n-type impurities. In fact, the concentration of n-type impurities decreases continuously from semiconductor region 2 to semiconductor region 3. Therefore, semiconductor regions 2 and 3 can be considered as a single semiconductor region doped with n-type impurities. Similarly, the boundary between semiconductor regions 4 and 5 is conveniently defined based on the concentration gradient of p-type impurities. In fact, the concentration of p-type impurities increases continuously from semiconductor region 4 to semiconductor region 5. Therefore, semiconductor regions 4 and 5 can be considered as a single semiconductor region doped with p-type impurities.

[0041] An insulator 25 is disposed above a portion of semiconductor 1. Conductors 32 and 33 are disposed above semiconductor 1 and insulator 25. Figure 4 As shown, conductor 32 is in contact with semiconductor region 5 in the Z direction at a position above semiconductor region 5, and in contact with semiconductor region 6 in the X direction.

[0042] like Figure 3and Figure 4 As shown, semiconductor 1 includes multiple trench structures TRC. Each of the multiple trench structures TRC is configured to extend in the Y direction and be formed by hollowing out semiconductor 1 in the Z direction. The bottom of each trench structure TRC reaches semiconductor region 2 of semiconductor 1. Conductors 10 and 20 are respectively disposed in each trench structure TRC.

[0043] like Figure 3 As shown, in each trench structure TRC, conductor 10 includes a first portion 10a extending in both the Y and Z directions, and a second portion 10b disposed above the first portion 10a and extending in the Z direction. The second portion 10b contacts the first portion 10a at its bottom. The bottom of the first portion 10a is located at a depth corresponding to the semiconductor region 2. The second portion 10b is located in the region where conductor 20 is not disposed above the second portion 10b, and is aligned with conductor 20 in the Y direction. Conductor 20 is disposed above the first portion 10a of conductor 10 and extends in the Y direction. Figure 4 As shown, conductor 20 is disposed at a depth corresponding to semiconductor region 4. For example, the upper surface of the second portion 10b of conductor 10 and the upper surface of conductor 20 are disposed at the same height in the Z direction. Contact C1 contacts the upper surface of the second portion 10b of conductor 10. Conductor 10 is connected to conductor 32 via contact C1. Contact C2 contacts the upper surface of conductor 20. Conductor 20 is connected to conductor 33 via contact C2. Contacts C1 and C2 are approximately the same length in the Z direction.

[0044] The insulating portion 11 is provided such that it covers the bottom surface and sides of the conductor 10 near its bottom. The insulating portion 11 comprises, for example, an insulator such as silicon oxide. The upper surface of the insulating portion 11 is located below the boundary between the semiconductor regions 2 and 3. The insulating portion 11 isolates the conductor 10 and the semiconductor region 2. Furthermore, the insulating portion 11 supports the structure of the conductor 10.

[0045] An insulating portion 12 is disposed above the insulating portion 11 in such a way that it covers the side surface of the conductor 10 and the upper surface of the first portion 10a of the conductor 10. The insulating portion 12 is a gap region. The insulating portion 12 is, for example, an air gap. The insulating portion 12 contains, for example, air or a gas composed of a substance used in the manufacturing process of the semiconductor device 100. The insulating portion 12 isolates the conductor 10 from the semiconductor regions 2 and 3.

[0046] An insulating portion 13 is provided above the first portion of conductor 10 and above the insulating portion 12. The insulating portion 13 comprises, for example, an insulator such as silicon oxide. The insulating portion 13 isolates the conductors 10 and 20. Furthermore, the insulating portion 13 supports the structure of conductor 20.

[0047] A conductor 20 is disposed above the insulating portion 13. For example... Figure 4 As shown, insulator 21 is disposed at a position sandwiched in the X direction between conductor 20 and semiconductor 1 (especially semiconductor region 4). Insulator 21 comprises, for example, silicon oxide.

[0048] An insulator 25 is disposed above the conductor 20. The insulator 25 covers the upper surface of the conductor 20.

[0049] 1.3 Operation

[0050] Semiconductor device 100 is electrically connected or isolated between conductors 31 and 32 depending on the magnitude of the voltage applied to conductor 33. The state in which conductors 31 and 32 are electrically connected is called the "on state," and the state in which conductors 31 and 32 are isolated is called the "off state." Semiconductor device 100 has a threshold voltage, and when a voltage equal to or greater than the threshold voltage is applied to conductor 33, which serves as a gate pad, semiconductor device 100 transitions from the off state to the on state. Reference will be made below to... Figure 4 The operation of semiconductor device 100 is explained continuously.

[0051] With a first voltage applied to conductor 31 and a second voltage lower than the first voltage applied to conductor 32, when a voltage equal to or higher than the threshold voltage is applied to conductor 33, a channel (inversion layer) is formed in the semiconductor region 4 adjacent to conductor 20 via insulator 21. When electrons move through this channel, current flows from conductor 31 to conductor 32. Therefore, semiconductor device 100 enters the ON state.

[0052] Subsequently, when the voltage applied to conductor 33 becomes less than the threshold voltage, current flow is blocked because a channel is not formed in semiconductor region 4. Therefore, semiconductor device 100 enters an off state. When semiconductor device 100 switches from an on state to an off state, a depletion layer extends from the pn junction at the boundary between semiconductor regions 3 and 4 toward semiconductor region 3. Simultaneously, due to the capacitive coupling between conductor 10 and semiconductor region 3, the depletion layer also extends from the boundary contacting the insulating portions 11 to 13 in semiconductor region 3 toward semiconductor region 3. Since conductor 10 is disposed in the trench structure TRC, depletion of semiconductor region 3 is promoted, thereby increasing the breakdown voltage of semiconductor device 100. Furthermore, since the concentration of n-type impurities in semiconductor region 3 can increase with the increase of the breakdown voltage of semiconductor device 100, the on-resistance of semiconductor device 100 in the on state can be reduced.

[0053] 1.4 Manufacturing Process

[0054] 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 are cross-sectional views, each illustrating an example of a manufacturing process for a semiconductor device according to the first embodiment. Figure 5 , 6 1, 7, 8, 9, 10, 11, 12, 13, and 14 correspond to Figure 4 The cross-sectional region shown. In the following text, reference will be made to... Figure 5 , 6 7, 8, 9, 10, 11, 12, 13 and 14 appropriately explain the manufacturing process of semiconductor device 100.

[0055] First, semiconductor 1, including semiconductor regions 2 and 3, is formed. For example, by using n + An epitaxial layer corresponding to semiconductor region 3 is grown on a semiconductor substrate. This epitaxial layer corresponds to semiconductor region 2 and is highly doped with n-type impurities to form semiconductor 1. Subsequently, a trench T corresponding to a trench structure TRC is formed. More specifically, a mask with openings is formed in the region corresponding to the trench structure TRC. Then, reactive ion etching (RIE) or similar processes are performed using this mask to form the trench T. The bottom of the trench T reaches semiconductor region 2. Subsequently, for example, by performing thermal annealing and oxidizing the surface of semiconductor 1, insulating portions 11 are formed along the inner walls of the trench T and along the upper surface of semiconductor 1, such as... Figure 5 As shown. The insulating portion 11, formed by thermal oxidation of semiconductor 1, contains silicon oxide as the insulator. It should be noted that the method for forming the insulating portion 11 is not limited to the method described above. For example, the insulator can be deposited along the inner wall of the trench T.

[0056] Next, a conductor 10 is formed within the trench T. The lower end of the conductor 10 is disposed within the semiconductor region 2. After the conductor 10 is embedded within the trench T, a conductor 10 having a first portion 10a and a second portion 10b is formed by selectively etching back the upper surface of the conductor 10. Thereafter, as... Figure 6 As shown, an etch-back process is selectively performed on the upper part of the insulating portion 11 on the sidewall of the trench T to partially remove the insulating portion 11. At this time, the etch-back process is performed such that the insulating portion 11 remains on the sidewall near the bottom of the conductor 10. Through this etch-back process, the upper surface of the insulating portion 11 is disposed inside the semiconductor region 2.

[0057] Next, as Figure 7As shown, the sacrificial member 14 and the insulating portion 13 are sequentially embedded into the trench T. The sacrificial member 14 is disposed in the portion corresponding to the insulating portion 12. The sacrificial member 14 contains a material capable of selectively etching the semiconductor 1 and the insulating portions 11 and 13. The sacrificial member 14 contains, for example, silicon nitride (SiN). The sacrificial member 14 is disposed in such a way that it fills the trench T and is partially removed by an etch-back process. Subsequently, the insulating portion 13 is embedded over the sacrificial member 14.

[0058] Next, after removing the insulating portion 13 through an etch-back process, semiconductor 1 is annealed again. For example... Figure 8 As shown, insulator 21 is formed along the inner wall of trench T and the upper surface of semiconductor 1. Insulator 21, formed by thermal oxidation of semiconductor 1, comprises silicon oxide. It should be noted that the method for forming insulator 21 is not limited to the method described above. For example, the insulator may be deposited along the inner wall of trench T.

[0059] Next, conductor 20 is formed within trench T. The upper surface of conductor 20 is positioned, for example, in a manner aligned with the height of the upper surface of the second portion 10b of conductor 10. Thereafter, as... Figure 9 As shown, an etch-back process is selectively performed on the upper part of the insulator 21 on the sidewall of the trench T to partially remove the insulator 21. At this time, the insulator 21 disposed between the conductor 20 and the semiconductor 1 is retained and not removed.

[0060] Next, as Figure 10 As shown, the sacrificial member 14 is selectively removed via wet etching through trench T. More specifically, the sacrificial member 14 is removed via the region where the second portion 10b of the conductor 10 is disposed, wherein the sacrificial member 14 is exposed on the upper surface within the trench T. For example, in the case where the sacrificial member 14 comprises silicon nitride and the insulating portions 11 and 13 comprise silicon oxide, the sacrificial member 14 can be selectively removed by wet etching with phosphoric acid. The region where the sacrificial member 14 is removed becomes a gap region, forming the insulating portion 12.

[0061] Next, as Figure 11 As shown, the insulator 25 is embedded in the trench T, thereby completing the trench structure TRC. At this time, in the region near the second portion 10b of the conductor 10, the portion of the upper surface of the insulating portion 12 exposed in the trench T is filled with the insulator 25, and the gap region included in the insulating portion 12 is sealed. Subsequently, the insulator 25 is partially removed by an etch-back process.

[0062] Next, in the region sandwiched by multiple trench structures (TRCs) in the X direction, p-type and n-type impurities are sequentially doped into the exposed semiconductor 1 to form semiconductor regions 4 and 6. For example, doping with p-type and n-type impurities is performed by ion implantation. Subsequently, as... Figure 12 As shown, a trench TC is formed in the semiconductor regions 4 and 6 of semiconductor 1. The trench TC passes through semiconductor region 6 of semiconductor 1 in the Z direction and its bottom reaches semiconductor region 4. Thereafter, although not shown, a structure corresponding to contacts C1 and C2 is formed.

[0063] Next, p-type impurities are doped into semiconductor 1 via trench TC to form semiconductor region 5. Subsequently, as... Figure 13 As shown, conductor 32 is formed by filling groove TC. Conductor 32 is connected to conductor 10 via contact C1. Subsequently, although not shown, conductor 33 is formed. Conductor 33 is connected to conductor 20 via contact C2.

[0064] Finally, as Figure 14 As shown, the lower part of the semiconductor region 2 is removed by, for example, back-grinding or chemical mechanical polishing (CMP), and then a conductor 31 is disposed at the bottom of the semiconductor device 100 to contact the semiconductor region 2. Although not shown, an insulator may also be disposed to cover a portion of the lower surface of the conductor 31.

[0065] Through the steps described above, semiconductor device 100 is formed. It should be noted that the manufacturing process described above is merely an example and is not limited thereto. For example, other processes may be inserted between manufacturing steps, and some steps may be omitted or combined. Furthermore, each manufacturing step may be interchanged to the extent possible.

[0066] 1.5 Effect

[0067] The semiconductor device 100 according to the first embodiment has high breakdown voltage and high reliability. This effect obtained from the semiconductor device 100 will be explained below.

[0068] When the semiconductor device 100 switches from an on state to an off state, the depletion layer extends toward the semiconductor region 3. At this time, the electric field strength at the boundary between the semiconductor region 3 and the insulating portions 11 and 12 surrounding the conductor 10 increases. If the thickness of the insulating portions 11 and 12 around the conductor 10 in the X direction (hereinafter referred to as film thickness) is too thin, the electric field strength at the boundary exceeds the critical electric field of the semiconductor region 3, and breakdown occurs, thus there is a possibility that the breakdown voltage of the semiconductor device 100 may decrease. On the other hand, if the film thickness of the insulating portions 11 and 12 around the conductor 10 is too thick, the extension of the depletion layer into the semiconductor region 3 is suppressed due to the small capacitive coupling between the conductor 10 and the semiconductor region 3, thus there is a possibility that the breakdown voltage of the semiconductor device 100 may decrease. Therefore, it is desirable to design the film thickness of the insulating portions 11 and 12 to be an optimal thickness that is neither too thick nor too thin.

[0069] The semiconductor device 100 according to the first embodiment has an insulating portion 12 between the conductor 10 and the semiconductor region 3. The insulating portion 12 contains air, and the dielectric constant of air is lower than that of silicon oxide, silicon nitride, etc., which are commonly used as insulators. Therefore, by forming the insulating portion 12, compared with structures using silicon oxide, silicon nitride, etc., the thickness of the layer in the X direction can be reduced, while suppressing breakdown. Furthermore, by reducing the thickness of the insulating portion 12, the number of conductors 20 per unit area can be increased, thereby reducing the on-resistance of the semiconductor device 100.

[0070] On the other hand, by setting gap regions as insulating parts, the structure may become unstable. For example, if all insulating parts surrounding the conductor 10 are formed by gap regions, since a structure cannot be provided to support the conductor 10 from below, the conductor 10 may detach from the insulator 25 and fall off due to impacts, etc. Therefore, the reliability of the semiconductor device 100 may decrease due to the change in the structure of the semiconductor device 100. Furthermore, in the manufacturing process of the trench structure TRC in which all insulating parts are formed by gap regions, similar to the first embodiment, the trench structure TRC is formed by removing the sacrificial members corresponding to the gap regions by etching, etc. However, if the sacrificial members are not completely removed in the etching process and are partially retained at the bottom of the trench structure, since the electric field is concentrated at the part where the sacrificial members are retained and breakdown occurs, there is a possibility that the breakdown voltage of the semiconductor device 100 may decrease.

[0071] The semiconductor device 100 according to the first embodiment has an insulating portion 11 provided at the bottom of the trench structure TRC to cover the side and bottom surface near the bottom of the conductor 10. With this configuration, the structure of the conductor 10 is supported and the position of the conductor 10 is fixed. Therefore, the reliability of the semiconductor device 100 is improved because the mechanical strength of the trench structure TRC is increased and its impact resistance is improved.

[0072] Furthermore, the semiconductor device 100 according to the first embodiment has a structure in which the bottom of the trench structure TRC reaches a semiconductor region 2 with a high concentration of n-type impurities, and an insulating portion 11 is disposed inside the semiconductor region 2. Because of the high concentration of n-type impurities in the semiconductor region 2, the depletion layer is unlikely to extend into the semiconductor region 2 when the semiconductor device 100 switches from an on-state to an off-state. Therefore, compared to the portion disposed in the semiconductor region 3, the electric field generated along with the extension of the depletion layer is smaller in the portion of the insulating portion surrounding the conductor 10 disposed near the semiconductor region 2. Therefore, even if the insulating portion 11 disposed in the semiconductor region 2 contains an insulator (e.g., silicon oxide) with a dielectric constant higher than that of air, the electric field concentration in the insulating portion 11 is unlikely to occur, and breakdown is suppressed, thus allowing the insulating portion 11 to be thin. Therefore, the insulating portion 11 can be provided with a film thickness similar to that of the insulating portion 12 disposed in the semiconductor region 3. With this configuration, the total thickness of the insulating portion can be reduced while maintaining a sufficiently high breakdown voltage. Furthermore, in the manufacturing process of semiconductor device 100, even when the sacrificial material 14 is partially retained at the bottom of the trench structure TRC during the etching of the sacrificial material 14, the impact on the reduction of the breakdown voltage of semiconductor device 100 is minimal because the concentration of the electric field in the portion where the sacrificial material 14 is partially retained is unlikely to occur. Therefore, the stability of the manufacturing process of trench structure TRC is improved.

[0073] Furthermore, the semiconductor device 100 according to the first embodiment has a structure in which the bottom of the trench structure TRC reaches a semiconductor region 2 with a high concentration of n-type impurities. Because a higher concentration of n-type impurities results in a shorter carrier lifetime in the semiconductor region 2, the reverse recovery charge during the reverse recovery operation of the body diode structurally present in the semiconductor device 100 can be reduced. Therefore, power consumption in the circuit where the body diode of the semiconductor device 100 operates can be reduced.

[0074] 2. Second Embodiment

[0075] Next, a semiconductor device according to a second embodiment will be described. In the following text, explanations of structures and manufacturing processes equivalent to those in the first embodiment will be omitted, and explanations will primarily focus on configurations different from those in the first embodiment.

[0076] 2.1 Structure

[0077] Figure 15 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor device according to the second embodiment. Figure 15 Corresponding to the first embodiment Figure 4 The portion shown. (As shown) Figure 15 As shown, in the semiconductor device 200 according to the second embodiment, the bottom of the trench structure TRC is in contact with the conductor 31. In other words, the conductor 31 is configured to contact the bottom of the semiconductor region 2 and the bottom of the insulating portion 11 in the trench structure TRC.

[0078] 2.2 Manufacturing Process

[0079] The manufacturing process of the semiconductor device 200 according to the second embodiment will be explained. The semiconductor device 200 according to the second embodiment is manufactured using a process similar to that of the semiconductor device 100 according to the first embodiment. Figure 13 The steps shown are similar to those described. Subsequently, before setting conductor 31, the lower surface of semiconductor region 2 is partially removed using, for example, CMP, thereby exposing the insulating portion 11 in the trench structure TRC. At this time, the insulating portion 11 can also be partially removed simultaneously with the removal of semiconductor region 2, provided that the insulating portion 12 in the trench structure TRC is not exposed. Afterward, conductor 31 is set to contact semiconductor region 2 and insulating portion 11. It should be noted that, although not shown, an insulator covering a portion of the lower surface of conductor 31 may also be provided.

[0080] 2.3 Effects

[0081] In the semiconductor device 200 according to the second embodiment, the distance between the conductor 31, which serves as the drain pad, and the conductor 32, which serves as the source pad, is shortened compared to the semiconductor device 100. Therefore, the on-resistance of the semiconductor device 200 can be reduced. Furthermore, since the trench structure TRC has a structure that fixes the conductor 10 through the insulating portion 11, its mechanical strength is increased. Therefore, damage to the trench structure TRC is suppressed during the step of removing the lower surface of the semiconductor region 2 in the manufacturing process of the semiconductor device 200.

[0082] 3. Third embodiment

[0083] Next, a semiconductor device according to a third embodiment will be described. In the following text, explanations of structures and manufacturing processes equivalent to those in the first embodiment will be omitted, and explanations will primarily concern configurations that differ from those in the first embodiment.

[0084] 3.1 Structure

[0085] Figure 16 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor device according to the third embodiment. Figure 16 Corresponding to the first embodiment Figure 4 The portion shown. (As shown) Figure 16 As shown, the semiconductor device 300 according to the third embodiment has an insulating portion 13 in the trench structure TRC to cover the upper surface and side surface near the upper part of the conductor 10.

[0086] 3.2 Manufacturing Process

[0087] The manufacturing process of the semiconductor device 300 according to the third embodiment will be explained. The semiconductor device 300 according to the third embodiment is manufactured using a process similar to that of the semiconductor device 100 according to the first embodiment. Figure 6 The steps shown are similar to those in the process. Subsequently, sacrificial material 14 is embedded, and etching is performed to expose the upper surface and sides near the upper portion of conductor 10. Thereafter, insulating portion 13 is embedded in the etched portion. Subsequent steps are similar to those in the manufacturing process of the semiconductor device 100 according to the first embodiment.

[0088] 3.3 Effects

[0089] According to the third embodiment, the semiconductor device 300 has insulating portions 12 and 13 disposed between the conductor 10 and the semiconductor region 3. The dielectric constant of the insulator contained in the insulating portion 13 is higher than the dielectric constant of the air contained in the insulating portion 12. In other words, when the insulating portions 12 and 13 are considered as one insulating portion, the thickness of the insulating portion is common, with the upper portion having a higher dielectric constant and the lower portion having a lower dielectric constant. With such a structure, when capacitive coupling occurs between the conductor 10 and the semiconductor region 3, the electric field strength can be increased because the capacitive coupling at the upper portion is stronger compared to the case where the dielectric constant is uniformly low. Therefore, the breakdown voltage of the semiconductor device 300 can be improved.

[0090] Furthermore, by providing an insulating portion 13 that covers the upper surface and sides near the upper part of the conductor 10, the upper position of the conductor 10 is fixed. With this configuration, within the trench structure TRC, the position of the conductor 10 is fixed in both the downward and upward directions by the insulating portions 11 and 13. Therefore, the mechanical strength of the trench structure TRC is increased, and its shock resistance is improved, thus enhancing the reliability of the semiconductor device 300.

[0091] 4. Fourth Embodiment

[0092] Next, a semiconductor device according to a fourth embodiment will be described. In the following text, explanations of structures and manufacturing processes equivalent to those in the first embodiment will be omitted, and explanations will primarily concern configurations different from those in the first embodiment.

[0093] 4.1 Structure

[0094] Figure 17 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor device according to the fourth embodiment. Figure 17 Corresponding to the first embodiment Figure 4 The portion shown. (As shown) Figure 17 As shown, the semiconductor device 400 according to the fourth embodiment includes a semiconductor region 7 located within the semiconductor region 2. The semiconductor region 7 is in which n-type impurities are present at a higher concentration (nn) than in the semiconductor region 2. ++ The doped region. Semiconductor region 7 is suitably localized within semiconductor region 2, and is configured, for example, as an insulating portion 11 surrounding the trench structure TRC.

[0095] 4.2 Manufacturing Process

[0096] The manufacturing process of the semiconductor device 400 according to the fourth embodiment will be explained. In the semiconductor device 400 according to the fourth embodiment, after forming a trench T corresponding to the trench structure TRC, an n-type impurity is implanted into the semiconductor 1 to form a semiconductor region 7. For example, the n-type impurity is implanted from the front surface of the semiconductor 1 via both the trench and the mesa adjacent to the trench. A portion of the n-type impurity implanted via the trench penetrates into the lower part of the semiconductor region 2 and is subsequently removed during processes such as back-side polishing or CMP. As a result, only the semiconductor region 7 in the mesa is retained. Subsequent steps are similar to those in the manufacturing process of the semiconductor device 100 according to the first embodiment.

[0097] 4.3 Effects

[0098] The semiconductor device 400 according to the fourth embodiment has a semiconductor region 7 inside the semiconductor region 2, and the semiconductor region 7 has a higher concentration of n-type impurities than the surrounding environment. Due to this structure, when the semiconductor device 400 switches from an on state to an off state, the electric field generated due to the extension of the depletion layer is further suppressed around the semiconductor region 7. Therefore, the concentration of the electric field in the insulating portion (e.g., the insulating portion 11 around the semiconductor region 7) is further suppressed, and the occurrence of breakdown is suppressed. Thus, the reliability of the semiconductor device 400 can be improved.

[0099] 5. Fifth Embodiment

[0100] Next, a semiconductor device according to a fifth embodiment will be described. In the following text, explanations of structures and manufacturing processes equivalent to those in the first embodiment will be omitted, and explanations will primarily concern configurations different from those in the first embodiment.

[0101] 5.1 Structure

[0102] Figure 18 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor device according to the fifth embodiment. Figure 18 Corresponding to the first embodiment Figure 4 The portion shown. (As shown) Figure 18 As shown, the semiconductor device 500 according to the fifth embodiment includes a semiconductor region 8 inside a semiconductor region 2. Semiconductor region 8 is a region in which p-type impurities are doped (p). The boundary between semiconductor regions 2 and 8 corresponds to a pn junction. Semiconductor region 8 is suitably locally disposed inside semiconductor region 2 and is, for example, configured as an insulating portion 11 surrounding a trench structure TRC.

[0103] 5.2 Manufacturing Process

[0104] The manufacturing process of the semiconductor device 500 according to the fifth embodiment will be explained. In the semiconductor device 500 according to the fifth embodiment, after forming a trench T corresponding to the trench structure TRC, a p-type impurity is implanted into the semiconductor 1 to form a semiconductor region 7. For example, the p-type impurity is implanted from the front surface of the semiconductor 1 via both the trench and the mesa adjacent to the trench. A portion of the p-type impurity implanted via the trench penetrates into the lower part of the semiconductor region 2 and is subsequently removed during processes such as back-side polishing or CMP. As a result, only the semiconductor region 7 in the mesa is retained. Subsequent steps are similar to those in the manufacturing process of the semiconductor device 100 according to the first embodiment.

[0105] 5.3 Effects

[0106] The semiconductor device 500 according to the fifth embodiment has a semiconductor region 8 containing p-type impurities within the semiconductor region 2. Due to this structure, because an electric field is also generated at the newly formed pn junction at the boundary between the semiconductor regions 2 and 8, and the depletion layer extends, the concentration of the electric field in the insulating portion (e.g., the insulating portion 11 around the semiconductor region 8) is suppressed, and breakdown is prevented. Therefore, the reliability of the semiconductor device 500 can be improved.

[0107] 6. Other

[0108] In the first to fifth embodiments, an explanation of the n-channel MOSFET has been given, wherein the channel is formed in semiconductor region 3, which is doped with n-type impurities. However, a similar structure can also be applied to a p-channel MOSFET. In this case, the conductivity type of the impurities doped into each semiconductor region is opposite to that of the impurities doped in the first to fifth embodiments. That is, p-type impurities are doped into regions corresponding to semiconductor regions 2, 3, 6, and 7, while n-type impurities are doped into regions corresponding to semiconductor regions 4, 5, and 8.

[0109] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. In fact, the novel embodiments described herein can be embodied in various other forms; furthermore, various omissions, substitutions, and changes can be made to the forms of the embodiments described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover these forms or variations that fall within the scope and spirit of the invention.

Claims

1. A semiconductor device, comprising: A first semiconductor region includes a first impurity having a first conductivity type; A second semiconductor region is disposed on the first semiconductor region and contains a second impurity having a second conductivity type different from the first conductivity type; A third semiconductor region is disposed on the second semiconductor region and contains a third impurity having the first conductivity type; A first conductor is surrounded by and spaced apart from the first semiconductor region; A first insulating portion is disposed between the first semiconductor region and the first conductor, and contacts each of the bottom surface and side surface near the bottom of the first conductor, wherein the first insulating portion comprises a first insulator; A second insulating portion is disposed on the side of the first conductor between the first semiconductor region and the first conductor where the first insulator is not disposed, wherein the second insulating portion includes a gap region; A second conductor is disposed above the first conductor and spaced apart from the first conductor and the second semiconductor region; and A second insulator is disposed between the second semiconductor region and the second conductor, and is in contact with each of the second semiconductor region and the second conductor.

2. The semiconductor device according to claim 1, wherein, The first semiconductor region includes a first portion containing the first impurity at a first concentration and a second portion disposed on the first portion containing the first impurity at a second concentration lower than the first concentration. The bottom surface of the first conductor is located below the boundary between the first portion and the second portion of the first semiconductor region.

3. The semiconductor device according to claim 2, wherein, The concentration of the first impurity in the first portion of the first semiconductor region is not less than 1.0 × 10⁻⁶. 17 cm -3 .

4. The semiconductor device according to claim 2, wherein, The first insulating portion is disposed between the first portion of the first semiconductor region and the first conductor, and contacts each of the first portion of the first semiconductor region and the first conductor. The second insulating portion is disposed between the second portion of the first semiconductor region and the first conductor.

5. The semiconductor device according to claim 4, wherein, The upper end of the first insulating portion is located below the boundary between the first portion and the second portion of the first semiconductor region.

6. The semiconductor device according to claim 4, wherein, The first insulating portion and the second insulating portion have substantially equal film thicknesses in the direction from the first conductor toward the first semiconductor region, and The dielectric constant of the second insulating portion is lower than that of the first insulating portion.

7. The semiconductor device of claim 1, further comprising a third insulating portion disposed in contact with the second conductor, the third insulating portion being located above the first conductor and the second insulating portion and below the second conductor. The third insulating portion includes a third insulator that contacts the first conductor to cover the upper surface of the first conductor and is disposed between the first semiconductor region and the first conductor, contacting each of the first semiconductor region and the first conductor at a side near the upper portion of the first conductor.

8. The semiconductor device according to claim 7, wherein, The second insulating portion and the third insulating portion have substantially equal film thicknesses in the direction from the first conductor toward the first semiconductor region, and The dielectric constant of the third insulating portion is higher than that of the second insulating portion.

9. The semiconductor device according to claim 1, further comprising: A third conductor is configured to be positioned below and in contact with the first semiconductor region and the first insulating portion.

10. The semiconductor device according to claim 2, wherein, A fourth semiconductor region is partially included within the first portion of the first semiconductor region, and the fourth semiconductor region contains the first impurity at a third concentration higher than the first concentration.

11. The semiconductor device according to claim 2, wherein, A fifth semiconductor region is partially included within the first portion of the first semiconductor region, and the fifth semiconductor region contains the second impurity.

12. A semiconductor device, comprising: A first semiconductor region includes a first portion and a second portion disposed on the first portion, wherein the first portion contains a first impurity of a first conductivity type at a first concentration, and the second portion contains the first impurity at a second concentration lower than the first concentration; A second semiconductor region is disposed on the first semiconductor region and contains a second impurity having a second conductivity type different from the first conductivity type; A third semiconductor region is disposed on the second semiconductor region and contains a third impurity having the first conductivity type; A first conductor is surrounded by and spaced apart from the first semiconductor region; A first insulating portion is disposed on the bottom surface of the first conductor between the first portion of the first semiconductor region and the first conductor, and contacts each of the first portion of the first semiconductor region and the first conductor, wherein the first insulating portion comprises a first insulator; A second insulating portion is disposed on the side of the first conductor between the second portion of the first semiconductor region and the first conductor, wherein the second insulating portion includes a gap region; A second conductor is disposed above the first conductor and spaced apart from the first conductor and the second semiconductor region; and A second insulator is disposed between the second semiconductor region and the second conductor, and is in contact with both the second semiconductor region and the second conductor.

13. The semiconductor device according to claim 12, wherein, The concentration of the first impurity in the first portion of the first semiconductor region is not less than 1.0 × 10⁻⁶. 17 cm -3 .

14. The semiconductor device according to claim 12, wherein, The upper end of the first insulating portion is located below the boundary between the first portion and the second portion of the first semiconductor region.

15. The semiconductor device according to claim 12, wherein, The first insulating portion and the second insulating portion have substantially equal film thicknesses in the direction from the first conductor toward the first semiconductor region, and The dielectric constant of the second insulating portion is lower than that of the first insulating portion.

16. The semiconductor device of claim 12, further comprising: The third insulating portion is disposed above the first conductor and the second insulating portion and below the second conductor, and is in contact with the second conductor. The third insulating portion includes a third insulator that contacts the first conductor to cover the upper surface of the first conductor and is disposed between the first semiconductor region and the first conductor, contacting each of the first semiconductor region and the first conductor at a side near the upper portion of the first conductor.

17. The semiconductor device according to claim 16, wherein, The second insulating portion and the third insulating portion have substantially equal film thicknesses in the direction from the first conductor toward the first semiconductor region, and The dielectric constant of the third insulating portion is higher than that of the second insulating portion.

18. The semiconductor device of claim 12, further comprising: A third conductor is configured to be positioned below and in contact with the first semiconductor region and the first insulating portion.

19. The semiconductor device according to claim 12, wherein, A fourth semiconductor region is partially included within the first portion of the first semiconductor region, and the fourth semiconductor region contains the first impurity at a third concentration higher than the first concentration.

20. The semiconductor device according to claim 12, wherein, A fifth semiconductor region is partially included within the first portion of the first semiconductor region, and the fifth semiconductor region contains the second impurity.

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