Methods for fabricating vertical semiconductor devices with robust gate regions and edge termination regions and structures

Abstract

The present disclosure relates to methods and structures for fabricating vertical semiconductor devices with robust gate regions and edge termination regions. A vertical fin FET device includes a semiconductor substrate and a drift region over the semiconductor substrate. A first gate region portion is on the drift region. A trench extends through the first gate region portion to the drift region. A fin is within the trench, extending over the first gate region portion. A second gate region portion is on the first gate region portion and surrounds the fin. The first gate region portion and the drift region form a native interface, the second gate region portion and the first gate region portion form a regrown interface, and the fin includes a base portion within the trench and an upper portion coupled to the base portion and extending over the trench.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 774,646, filed March 19, 2025, which is incorporated herein by reference in its entirety. Background Technology

[0003] Vertical power transistors, in which current flows from the top surface of the transistor to the back or bottom surface of the transistor substrate, are typically used to control high current and high voltage because vertical power transistors have a smaller formation area compared to devices in which the current flowing through the transistor (e.g., field-effect transistor (FET)) is lateral.

[0004] Group III nitride materials, specifically gallium nitride (GaN), allow the fabrication of vertical FET-based power transistors with high breakdown voltages (e.g., over 1200V) while significantly reducing the on-resistance (i.e., the device's on-resistance multiplied by the device area) compared to silicon or silicon carbide materials.

[0005] Despite progress in the field of vertical power transistors, there is still a need for improved methods and systems related to vertical power transistors. Attached Figure Description

[0006] Figure 1 This is a partial cross-sectional view illustrating a vertical fin junction FET (JFET) device according to an embodiment of the present description.

[0007] Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 This is a partial cross-sectional view illustrating an example method for manufacturing a vertical fin FET device according to an embodiment of this description.

[0008] Figure 7 This is a Weibull cumulative distribution function (CDF) plot, which shows the failure time probability of a native PN junction device according to this description compared to a regenerated PN junction device.

[0009] Figure 8 This is a graph illustrating the offset of the high electric field localization of the vertical fin JFET device according to this description from the regrowth interface compared to prior art vertical fin JFET devices.

[0010] Figure 9 This is a graph illustrating the drain current / voltage (I / V) characteristics of a vertical fin JFET device according to this description compared to prior art vertical fin JFET devices.

[0011] Figure 10 This is a partial cross-sectional view illustrating a vertical fin JFET device including active and passive fins according to an embodiment of the present description.

[0012] Figure 11 , Figure 12 and Figure 13 This is a partial cross-sectional view illustrating an example method for manufacturing a vertical fin JFET device with active and passive fins according to an embodiment described herein.

[0013] Figure 14 This is a cross-sectional view illustrating a prior art vertical fin JFET device.

[0014] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. These examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "implementation," "example," and "for example" are non-limiting.

[0015] To keep the illustrations simple and clear, the components in the figures may not be drawn to scale, and the same reference numerals in different figures indicate the same components. Additionally, for the sake of brevity, descriptions and details of well-known steps and components have been omitted.

[0016] For clarity of the accompanying drawings, certain regions of the device structure, such as doped or dielectric regions, trenches, or contacts, may be illustrated as having generally straight edges and corners with precise angles. However, those skilled in the art will understand that the edges of such regions may not typically be straight and the corners may not have precise angles due to the diffusion and activation of dopants or the formation of layers.

[0017] Although semiconductor devices are interpreted herein as having certain N-type and certain P-type conductive regions, those skilled in the art will understand that the conductivity type can be reversed, and that, in accordance with this description, any necessary reversal of voltage polarity, transistor type, and / or current direction can also be taken into account.

[0018] Furthermore, the terminology used herein is for the purpose of describing particular examples only and is not intended to limit this disclosure. As used herein, the singular form is intended to also include the plural form unless the context explicitly indicates otherwise.

[0019] As used herein, “current-carrying electrode” refers to a component within a device that carries current through the device, such as the source or drain of a MOS transistor, the emitter or collector of a bipolar transistor, or the cathode or anode of a diode, and “control electrode” refers to a component within a device that controls the current flowing through the device, such as the gate of a MOS transistor or the base of a bipolar transistor.

[0020] The term "master surface," when used in conjunction with a semiconductor region, wafer, or substrate, refers to the surface of the semiconductor region, wafer, or substrate that forms an interface with another material such as a dielectric, insulator, conductor, or polycrystalline semiconductor. The master surface may have a morphology that varies along the x, y, and z directions.

[0021] Furthermore, the structure described herein can be embodied in a cellular base design (where the main area consists of multiple distinct and separate cells or stripes) or a single base design (where the main area is a single area formed by an elongated pattern, generally in the form of a serpentine pattern or a central portion with connecting appendages). However, for ease of understanding, one embodiment of this description will be described as a cellular base design throughout the description. It should be understood that this description encompasses both cellular base designs and single base designs.

[0022] When used in this description, the terms “comprising,” “including,” “having,” and / or “containing” are open-ended terms that specify the presence of the stated features, numbers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or groups thereof.

[0023] The term "or" refers to any one or more items in a list connected by "or". For example, "x or y" refers to any element in the three-element group {(x), (y), (x, y)}. Similarly, "x, y, or z" refers to any element in the seven-element group {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0024] Although the terms “first,” “second,” etc., may be used herein to describe various components, elements, areas, layers, and / or sections, these components, elements, areas, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one component, element, area, layer, and / or section from another component, element, area, layer, and / or section. Therefore, without departing from the teachings of this disclosure, for example, the first component, first element, first area, first layer, and / or first section discussed below may be referred to as a second component, second element, second area, second layer, and / or second section.

[0025] Those skilled in the art will understand that the phrases “during,” “at the same time,” and “when” used herein in relation to circuit operation do not precisely refer to an action occurring immediately after the initiation of the action, but rather to a possible small but reasonable delay, such as a propagation delay, between the responses triggered by the initial action. Additionally, the term “at the same time” means that an action occurs at least for a period of time during the duration of the initiation of the action.

[0026] The terms “about,” “approximately,” or “basically” indicate that the expected value of a component is close to the declared value or position. However, it is well known in the art that there are always some small deviations that prevent the value or position from being exactly the declared value or position.

[0027] Unless otherwise specified, the phrases “above” or “on” as used herein include the orientation, placement, or relationship in which the specified element may be in direct or indirect physical contact.

[0028] Unless otherwise specified, as used herein, the phrase “overlapping with” includes the orientation, placement, or relationship in which the specified elements can at least partially or completely coincide or align on the same or different planes.

[0029] It should be understood that, unless otherwise stated, the terms and phrases used in this document and their variations should be interpreted as open-ended rather than restrictive. As an example of the foregoing: the term “including” should be understood as “including, but not limited to”; and adjectives such as “conventional,” “traditional,” “normal,” “standard,” “known,” and terms with similar meanings should not be interpreted as limiting the described items to a given time period or to items available at a given time. Rather, these terms should be understood to cover conventional, traditional, normal, or standard techniques that may be available and known now or in the future. Furthermore, although items, elements, or components of this disclosure may be described or claimed in the singular, the plural is considered to be within its scope unless a limitation on the singular is explicitly stated. In some cases, the presence of extended words and phrases such as “one or more,” “at least,” “but not limited to,” or other similar phrases should not be interpreted as implying an intention or need for a narrower scope where such extended phrases may not exist.

[0030] It should also be understood that the examples exemplified and described below may have examples lacking any elements not expressly disclosed herein, and / or may be implemented in the absence of any elements not expressly disclosed herein. Detailed Implementation

[0031] Power semiconductor devices, including transistors and diodes, are now widely used in applications such as industrial power supplies, motor drives, consumer electronics, and other systems. A common application of power semiconductor transistors is their use as switches in switch-mode power supplies or motor drives. In such applications, the ability of devices to operate at high voltages (e.g., 650V or 1200V) and withstand transient overvoltage conditions (e.g., line surges or lightning strikes on power lines) is important.

[0032] Furthermore, to reduce the resistance of the switch and minimize parasitic effects that limit switching speed (e.g., capacitance), it is desirable to increase the conductance per unit area. Switching transistors with predominantly vertical current reduce the resistance per unit area. This benefit is further enhanced by arranging the control channel of the transistor in a vertical direction, such as in a trench-channel transistor. The resistance of a transistor has several components, including the resistance of the transistor channel (i.e., the region where the current is directly controlled by the input gate voltage), the resistance of the drift region (i.e., the region designed to maintain the transistor's breakdown voltage), and the resistance of the initial substrate, contacts, metals, package structure, and other components.

[0033] Transistors with vertical current are typically designed to have a drain contact on the bottom surface of the chip and a gate contact and a source contact on the top surface of the chip.

[0034] To maximize switching conductivity (i.e., minimize switching resistance) and provide a uniform transient response for the device, transistors can be fabricated using an array of many small vertical-channel switching devices surrounded by a control gate; this array may be referred to as an array of "all-toggle" transistors. The completed device has all sources connected to a single electrode, a common gate electrode, and a drain electrode.

[0035] This description generally pertains to the field of electronics, and more specifically to semiconductor manufacturing technology. In a particular example, structures and methods are provided for forming vertical fin FET (FinFET) arrays (i.e., FinFET arrays) with improved vertical device performance and reliability. A vertical fin FET includes a gate-drain interface that can withstand the full voltage applied to the device. This gate-drain interface is generally more robust than in other design approaches. However, any impurities, contaminants, or defects present at the gate-drain interface can degrade the performance and operational lifetime of the vertical fin FET device.

[0036] The methods and structures described herein improve the robustness of the gate-drain interface in vertical fin FETs by using fabrication techniques that may include multiple epitaxial growth regions provided in a single epitaxial growth process. In one example, a first portion of the gate region (specifically, the portion that contacts the drain) is formed during the same epitaxial growth process used to create the drift region portion of the drain region, rather than through a separate second epitaxial growth step. This fabrication method enhances the structural and electrical integrity of the gate-drain interface by forming the drain contact portion of the gate region during the same epitaxial growth step used to form the drift region portion of the drain region. Incorporating these regions into a single epitaxial process reduces the heterogeneous interface associated with the regrowth junction and lowers defect densities, such as through-dislocations, point defects, and impurity incorporation that typically occur in separate regrowth steps. Consequently, the gate-drain junction benefits from a more uniform doping distribution, improved crystal alignment, and reduced trap-assisted leakage paths, resulting in higher breakdown voltages. The methods and structures described herein also contribute to increased drain current and more robust edge-termination regions.

[0037] The methods and structures described herein provide improved device performance and reliability by replacing the regrowth junction with a native junction formed within the epitaxially grown semiconductor layer and by increasing the distance between the high-electric-field region and the epitaxial interface region serving as the regrowth interface. The methods and structures described herein offer independent design capabilities for the gate-drain and gate-source interfaces and provide enhanced edge-termination design capabilities through improved handling and control of gate region doping and the ability to epitaxially form adjacent regions of opposite conductivity types. The methods and structures described herein provide improved FET saturation current and reduced on-resistance by eliminating parasitic high threshold voltage channels at the bottom of the vertical fins.

[0038] The methods and structures described herein can be used to provide passive or non-active fins in certain regions of a device. In some examples, passive fins improve the uniformity of lithography, etching, and epitaxial growth processes across the entire device, including edge-terminating regions, thereby improving device performance and lifetime. The methods and structures described herein are applicable to fin-based or trench-based high-voltage vertical-channel devices, including, for example, vertical GaN and SiC power devices. They also support high-efficiency high-frequency power systems up to 10 MHz (e.g., for data center and EVB drivetrain applications). While the examples described herein relate to vertical-fin JFET devices, it should be understood that the described methods and structures can be used with other semiconductor devices, including but not limited to metal-oxide-semiconductor FETs (MOSFETs) and superjunction MOSFETs.

[0039] In one example, a vertical fin FET device includes a semiconductor substrate characterized by a first conductivity type. A drift region is located above the semiconductor substrate and is characterized by the first conductivity type and a first dopant concentration. A first gate region is located on the drift region and is characterized by a second conductivity type and a second dopant concentration opposite to the first conductivity type. A trench extends through the first gate region to the drift region. A fin extends within the trench above the first gate region and is characterized by the first conductivity type and a third dopant concentration. A second gate region is located on the first gate region, surrounds the fin, and is characterized by the second conductivity type and a fourth dopant concentration. In this example, the first gate region and the drift region form a native interface, the second gate region and the first gate region form a regrowth interface, and the fin includes a base portion within the trench and an upper portion coupled to the base portion and extending above the trench.

[0040] In one example, a vertical fin FET device includes: a semiconductor substrate characterized by a first conductivity type; and a drift region above the semiconductor substrate and characterized by the first conductivity type. A first gate region portion is located on the drift region and characterized by a second conductivity type opposite to the first conductivity type. A second gate region portion is located on the first gate region portion and characterized by the second conductivity type. A fin characterized by the first conductivity type is coupled to the drift region and extends through the first gate region portion and the second gate region portion. In this example, the first gate region portion and the drift region form a native PN junction, the second gate region portion and the first gate region portion form a regrown interface, and the fin includes a base portion adjacent to the drift region and an upper portion coupled to the base portion.

[0041] In one example, a method for fabricating a vertical fin FET device includes providing a semiconductor substrate characterized by a first conductivity type. The method includes, in a first epitaxial growth process, forming a drift region over the semiconductor substrate, the drift region being characterized by the first conductivity type and a first dopant concentration, and forming a first gate region portion on the drift region, the first gate region portion being characterized by a second conductivity type and a second dopant concentration opposite to the first conductivity type. The method includes forming a trench extending through the first gate region portion to the drift region. The method includes, in a second epitaxial growth process, forming a fin channel region within the trench and over the first gate region portion, the fin channel region being characterized by the first conductivity type and a third dopant concentration. The method includes forming a recess region in the fin channel region to form a fin. The method includes a third epitaxial growth process forming a second gate region portion on the first gate region portion, the second gate region portion surrounding the fin and being characterized by the second conductivity type and a fourth dopant concentration. In this example, the first epitaxial growth process is an in-situ process that provides the first gate region portion and the drift region as a native interface, the second gate region portion and the first gate region portion form a regrowth interface, and the fin includes a base portion within the trench and an upper portion coupled to the base portion and extending above the trench.

[0042] Other examples are included in this disclosure. Such examples can be seen in the drawings, the claims, and / or the description of this disclosure.

[0043] Figure 14 This is a partial cross-sectional view of a prior art vertical fin field-effect transistor (FET) device 400. The FET device 400 includes an N-type conductive semiconductor substrate 401, an N-type conductive drift region 402, an N-type conductive graded-doped layer 402A, and N-type conductive fins 403 protruding vertically upward from the graded-doped layer 402A. The FET device 400 also includes a regrown P-type conductive gate region 410 that surrounds the fins 403 and has a bottom portion in direct contact with the graded-doped layer 402A. A source metal layer 405 contacts each fin in the fins 403, a gate metal layer 412 contacts the gate region 410, and a drain metal layer 417 contacts a drain region at the bottom surface of the semiconductor substrate 401.

[0044] Previously, to form fin 403, an epitaxial channel layer was formed on the gradient doped layer 402A. A photolithography process was used to pattern the fin 403, and then the exposed portion of the epitaxial channel layer was removed to form a recess region extending into the gradient doped layer 402A. A separate epitaxial regrowth process was then used to provide the gate region 410 within the recess region, which provided the regrowth interface as indicated by arrow 425.

[0045] This method leads to several problems. For example, after the first epitaxial growth process providing the epitaxial channel layer, the etching step (e.g., dry etching) used to form the trench and fin 403 also damages the gradient doped layer 402A of the drift region 402 at the base of the formed trench, as indicated by arrow 426. Furthermore, in combination with the presence of the gradient doped layer 402A, etch depth control can result in the formation of a parasitic high threshold voltage (Vt) at the lower portion of the fin 403 adjacent to the gradient doped layer 402A. This parasitic device can limit the saturated drain current (i.e., current flow restriction) and increase the on-resistance in the FET device 400. Additionally, the gate region 410 formed using a separate second epitaxial growth (i.e., regeneration epitaxial growth) process results in etch damage to the gate-drain interface and makes it susceptible to impurity doping during the epitaxial growth initiation period. This damage and impurities can lead to reduced high-temperature reverse bias (HTRB) reliability. This description addresses these problems, as well as others.

[0046] Figure 1 A partial cross-sectional view of a vertical fin junction field-effect transistor (JFET) device 100 according to an embodiment of the present disclosure is illustrated. As used herein, the terms “FET,” “FinFET,” and “vertical fin FET” are interchangeable. In this example, the vertical fin JFET device 100 may include a semiconductor substrate 101, a buffer layer 1015, a drift region 102 (in some examples, the drift region may include a uniformly doped region on the semiconductor substrate 101), and a plurality of fins 103 projecting upward from the drift region 102. In some examples, each fin of fin 103 may include a heavily doped contact region 104 disposed in an upper portion of each fin and a contact portion 105 disposed on each doped contact region 104, such as a refractory metal, refractory metal compound, or refractory metal alloy layer (e.g., a TiN layer). The contact portion 105 may include, or be referred to as, a source contact portion. The doped contact region 104 or contact portion 105 is an example of a current-carrying electrode (e.g., a first current-carrying electrode).

[0047] In this example, the semiconductor substrate 101, buffer layer 1015, drift region 102, and fin 103 include a first conductivity type (e.g., N-type conductivity). In some examples, drift region 102 includes a uniformly doped region opposite to the gradient doped region and includes a dopant concentration similar to that of fin 103. More specifically, in this example, the vertical fin JFET device 100 does not contain an N-type conductivity gradient doped layer, such as the previously described gradient doped layer 402A.

[0048] In this example, the semiconductor substrate 101, buffer layer 1015, drift region 102, or fin 103 may comprise a group III nitride semiconductor material, such as GaN, with N-type conductivity. As an example, Si, Ge, or other dopant elements known to those skilled in the art may be used to provide N-type conductivity. It should be understood that the semiconductor substrate 101, buffer layer 1015, drift region 102, or fin 103 may comprise other semiconductor materials, including, but not limited to, silicon, silicon carbide, silicon germanium, group III-V materials, or similar materials known to those skilled in the art.

[0049] According to this description, a vertical fin JFET device 100 includes a multi-part gate region 110, which includes more than one gate region portion or gate region layer. That is, the gate region 110 includes a plurality of gate region portions arranged in a vertically stacked configuration. In this example, the gate region 110 may contain a group III nitride semiconductor material, such as GaN, having a second conductivity type (i.e., P-type conductivity) opposite to a first conductivity type (i.e., N-type conductivity). As an example, Mg or other dopant elements known to those skilled in the art may be used to provide P-type conductivity. It should be understood that the gate region 110 may contain other semiconductor materials, including, but not limited to, silicon, silicon carbide, silicon germanium, group III-V materials, or similar materials known to those skilled in the art.

[0050] In this example, gate region 110 includes a gate region portion 110A on drift region 102 and a gate region portion 110B on gate region portion 110A. According to this description, gate region portions 110A and 110B are formed or provided using separate and different epitaxial growth processes. More specifically, gate region portion 110A is provided using the same epitaxial growth process used to form or provide drift region 102. In this example, gate region portion 110A directly contacts drift region 102 to form native interface 1102.

[0051] According to this description, after the drift region 102 is formed, the gate region portion 110A is formed in situ in the same epitaxial reactor without removing the semiconductor substrate 101 from the epitaxial reactor. This may include the same reactor chamber or a separate reactor chamber within a cluster epitaxial reactor having multiple chambers connected under vacuum. By forming the gate region portion 110A in the same epitaxial growth sequence as the drift region 102, the interface between these regions (i.e., the native interface 1102) is significantly improved. Because the semiconductor substrate 101 is not removed from the epitaxial reactor during this process, the interface is protected from surface contamination, native oxide formation, moisture exposure, and other defects that typically occur when the semiconductor substrate is exposed to environmental conditions. In this example, the gate region portion 110B is formed in a later epitaxial growth process, as will be described in more detail later. The gate region portion 110A may be an example of a first gate region portion, and the gate region portion 110B may be an example of a second gate region portion.

[0052] In some examples, gate region portion 110A may have the same or different dopant concentration as gate region portion 110B. In some examples, gate region portion 110A has a lower dopant concentration than gate region portion 110B. More specifically, the PN junction formed between drift region 102 and gate region portion 110A can be customized to modify the peak electric field at the PN junction during operation of the vertical fin JFET device 100 to improve lifetime performance and / or increase breakdown voltage.

[0053] In the vertical fin JFET device 100, a first end 103A of the fin 103 extends downward through the gate region portion 110A and is coupled to the drift region 102. In this example, the first end 103A directly contacts the drift region 102, which is not provided with a gradient dopant layer. In some examples, the first end 103A may be located in a first plane, and the native interface 1102 between the drift region 102 and the gate region portion 110B is on a second plane different from the first plane. In some examples, the first plane may be recessed or below the second plane.

[0054] In some examples, the thickness of the gate region portion 110A may be non-uniform. For example, the thickness of the gate region portion 110A may increase near the fin 103, thereby providing a tapered upper surface 1101 for the gate region portion 110A at a location adjacent to the fin 103. In some examples, the gate region portion 110A includes a first thickness near the fin 103 and a second thickness away from the fin 103, and the first thickness is greater than the second thickness. In some examples, the fin 103 may include a base portion 1031 and an upper portion 1032, and in a cross-sectional view, the base portion 1031 may be wider than the upper portion 1032. In this example, the gate region portion 110B is on the gate region portion 110A and may surround and cover portions of the base portion 1031 and the upper portion 1032 of the fin 103.

[0055] In some examples, the semiconductor substrate 101, buffer layer 1015, drift region 102, gate region portion 110A, fin 103, gate region portion 110B, and doped contact region 104 may include or be referred to as a semiconductor material body 111. In some examples, the gate region portion 110B may define a top side or upper side 118 of the semiconductor material body 111, and the semiconductor substrate 101 may define a bottom side or lower side 119 of the semiconductor material body 111. The semiconductor material body 111 may include or be referred to as a semiconductor workpiece or semiconductor body.

[0056] The vertical fin JFET device 100 also includes a gate contact structure 112 coupled to the gate region 110. In one embodiment, the gate contact structure 112 may include a nickel (Ni) layer disposed on the gate region 110, a first gold (Au) layer disposed on the nickel (Ni) layer, a barrier layer (including, for example, a metal layer (e.g., molybdenum (Mo), titanium (Ti), tantalum (Ta), or similar materials)) disposed on the first gold (Au) layer, and a second gold (Au) layer disposed on the barrier layer. In this example, a drain metal layer 117 is disposed on the bottom side of the semiconductor substrate 101 (i.e., the lower side 119 of the semiconductor material body 111) to form a drain contact. The gate contact structure 112 is an example of a control electrode, and the drain metal layer 117 is an example of a current-carrying electrode (e.g., a second current-carrying electrode). Although not shown, it should be understood that the vertical fin JFET device 100 may also include various dielectric structures and conductive interconnect structures to isolate various elements of the device and provide electrical contact with various elements of the device.

[0057] Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 This is a partial cross-sectional view illustrating an example method for manufacturing a vertical fin FET device according to an embodiment of the present description, which can be used to manufacture a vertical fin JFET device 100.

[0058] refer to Figure 2 A semiconductor substrate 101 may be provided. In some examples, the semiconductor substrate 101 may comprise an N-type (e.g., N+ doped) Group III nitride substrate (e.g., GaN). In one embodiment, the semiconductor substrate 101 is an N+ doped Group III nitride substrate heavily doped with an N-type dopant such as Si or Ge, wherein the dopant concentration is between about 5 × 10⁻⁶. 17 atoms / cm 3 Up to approximately 5×10 19 atoms / cm 3 The resistivity is within the range of [value missing], and less than 0.020 ohm-cm. In some examples, the resistivity of the N+-doped group III nitride substrate may be from about 0.001 ohm-cm to 0.018 ohm-cm, preferably less than 0.016 ohm-cm, and more preferably less than 0.012 ohm-cm. In other examples, the semiconductor substrate 101 may be an engineered substrate, which may include composite, layered, modified, bonded, or heteroepitaxial substrates. This includes engineered GaN substrates, such as GaN on SOI, GaN on silicon, GaN on polysilicon, AlN ceramic cores, or other substrates designed to reduce dislocations caused by lattice / thermal mismatch (i.e., engineered CTE matching to reduce stress).

[0059] Next, a semiconductor substrate 101 can be prepared and placed within an epitaxial reactor for a first epitaxial growth process. In some examples, a metal-organic chemical vapor deposition (MOCVD) process can be used for the first semiconductor epitaxial growth process. Alternatively, hydride vapor phase epitaxy (HVPE) or other processes known to those skilled in the art can be used for the first epitaxial growth process. As used herein, a first epitaxial growth process refers to a series of fabrication steps performed within the same epitaxial reactor without breaking the vacuum or exposing the semiconductor substrate 101 to the surrounding environment. The fabrication steps of the first epitaxial growth process include, but are not limited to, cleaning and semiconductor growth processes.

[0060] In this example, the first epitaxial growth process includes forming a buffer layer 1015 on a semiconductor substrate 101. In some examples, the buffer layer 1015 includes a core with a diameter of approximately 1.0 × 10⁻⁶. 18 atoms / cm 3 The dopant concentration is low and the thickness is approximately 0.5 micrometers. This is achieved by an N-type conductive group III nitride layer (e.g., a GaN layer doped with Si or Ge). In some examples, the buffer layer 1015 serves as a transition layer between the heavily doped semiconductor substrate 101 and the drift region 102.

[0061] The first epitaxial growth process also includes forming a drift region 102 on the buffer layer 1015. In this example, the drift region 102 includes an N-type conductive Group III nitride layer (e.g., a GaN layer doped with Si or Ge) having a first dopant concentration and a thickness depending on the desired breakdown voltage of the JFET device. In one embodiment, the first dopant concentration is approximately uniform across the entire thickness of the drift region 102. That is, the first dopant concentration is not intentionally gradient across its thickness, but may vary due to effects such as autodoping. In some examples, for a device 100 rated at 700V, the drift region 102 may have a thickness between approximately 8.0 × 10⁻⁶. 15 atoms / cm 3 To approximately 5.0 × 10 16 atoms / cm 3 The dopant concentration (i.e., the first dopant concentration) and thickness range from approximately 3 micrometers to 10 micrometers. For device 100 with a rated voltage of 1200V, the drift region 102 may have a thickness between approximately 8.0 × 10⁻⁶. 15 atoms / cm 3 To approximately 5.0 × 10 16 atoms / cm -3 The dopant concentration (i.e., the first dopant concentration) and thickness range from approximately 5 micrometers to 12 micrometers. Drift region 102 may include, or be referred to as, a uniformly doped native region. In some examples, drift region 102 may be epitaxially grown on buffer layer 1015 at a temperature between 950 degrees Celsius and 1200 degrees Celsius. In this example, drift region 102 does not include, or is provided without, an intentionally gradient N-type conductive layer at its top side.

[0062] The first epitaxial growth process also includes directly forming a gate region portion 110A on the drift region 102. The gate region portion 110A includes a Mg-doped P-type conductive group III nitride layer (e.g., a GaN layer), wherein the concentration of the second dopant is between approximately 5.0 × 10⁻⁶. 16 atoms / cm 3 To approximately 5.0 × 10 18 atoms / cm 3The thickness is within the range of 0.3 micrometers to 0.6 micrometers. According to this description, the first dopant concentration of the drift region 102 and the second dopant concentration of the gate region portion 110A can be customized according to desired device specifications to modulate the electric field in the vertical fin JFET device 100 and set the breakdown voltage. More specifically, in the vertical fin JFET device 100, the PN junction formed between the drift region 102 and the gate region portion 110A serves as a high-voltage gate-drain interface. According to this description, the gate-drain interface (i.e., interface 1102) is characterized as a “native” gate-drain interface. A native gate-drain interface can be characterized as the physical location of the transition point from the N-type conductive dopant in the drift region 102 to the P-type conductive dopant in the gate region portion 110A.

[0063] As will be described in more detail later, in this example, gate region portion 110A may include a dopant concentration that is less than that of gate region portion 110B. In some examples, this configuration achieves a reduced peak electric field and better edge termination performance.

[0064] In some examples, the first epitaxial growth process further includes providing a capping layer 1016 on the gate region portion 110A. In some examples, the capping layer 1016 comprises an undoped group III nitride layer (e.g., GaN) and has a thickness ranging from about 0.2 micrometers to about 0.6 micrometers. In some examples, the capping layer 1016 can be used to accommodate any autodoping from dopants within the gate region portion 110A during subsequent processing, or to protect the gate region portion 110A during subsequent process steps. The capping layer 1016 may include, or be referred to as, a sacrificial capping layer. After the capping layer 1016 is formed, the semiconductor substrate 101 can then be removed from the epitaxial reactor. In this example, this completes the first epitaxial growth process. In some embodiments, after the gate region portion 110A is grown and the semiconductor substrate 101 is removed from the epitaxial reactor, the capping layer 1016 is formed using a separate epitaxial regeneration process by a secondary insertion of the semiconductor substrate 101 into the epitaxial growth reactor.

[0065] Figure 3 A partial cross-sectional view of the vertical fin JFET device 100 after further processing is shown. It should be noted that... Figures 3 to 6 In the diagram, the semiconductor substrate 101 and the buffer layer 1015 are not shown for simplification.

[0066] In this example, mask 201 may be disposed over capping layer 1016 and patterned to provide an array of openings including rows and columns corresponding to the positioning of fin 103. In some examples, mask 201 may comprise a hard mask layer of silicon nitride or other materials known to those skilled in the art. In some examples, mask 201 is formed using photoresist. After mask 201 is provided and patterned to provide openings, an etching process may be used to form trench 202 extending downward through capping layer 1016 and gate region portion 110A. In some examples, trench 202 extends partially downward into and within drift region 102. That is, the lower end of trench 202 is positioned below gate region portion 110A (e.g., below interface 1102). In this example, trench 202 defines the location or positioning of fin 103. Trench 202 is an example of a first trench.

[0067] In some examples, the etching process forming trench 202 may include a Cl-based chemical process using reactive ion etching (RIE). In some examples, after trench 202 is formed, a cleaning process is performed using a tetramethylammonium hydroxide (TMAH) solution of about 25% by weight at a temperature of about 85 degrees Celsius for about 30 minutes. In another embodiment, a pre-cleaning process, such as a piranha-like cleaning using H2SO4:H2O at a volume ratio of 2:1, may be performed before cleaning with the TMAH solution. In some examples, the width of trench 202 may be from about 0.3 micrometers to about 0.6 micrometers. In this example, the width of trench 202 determines the width of the base portion 1031 of fin 103. In some examples, the width of trench 202 may be uniform. In other examples, the width may vary depending on specific design, device integration, or edge termination requirements.

[0068] Figure 4 A partial cross-sectional view of a vertical fin JFET device 100 after further processing is illustrated. In this example, mask 201 is removed, and a second epitaxial growth process is used to form an N-type group III nitride fin channel region (e.g., GaN doped with Si or Ge) within trench 202 and over the gate region portion 110A. The second epitaxial growth process provides and fills the trench 202 with a fin channel region 1030, extending upward over the gate region portion 110A. In some examples, the fin channel region 1030 has a thickness between approximately 0.5 micrometers and approximately 0.9 micrometers, measured from the bottom of trench 202. In some examples, the fin channel region 1030 has a thickness of approximately 1.3 × 10⁻⁶. 17 atoms / cm 3 The dopant concentration (i.e., the third dopant concentration). In some examples, the fin channel region 1030 has a generally uniform or non-gradient dopant distribution.

[0069] In this example, the upper surface of the fin channel region 1030 can be substantially flat. In some examples, a second epitaxial growth process can be used to form a reinforcement layer 1040 on the upper surface of the fin channel region 1030. This reinforcement layer can be a heavily doped N-type conductive group III nitride layer (e.g., GaN doped with Si or Ge) and can have a density greater than 1.0 × 10⁻⁶. 19 atoms / cm 3 The dopant concentration. In other examples, ion implantation or other doping techniques known to those skilled in the art may be used to provide the enhancement layer 1040 within the fin channel region 1030. In some examples, a contact layer 1050 may then be provided on the enhancement layer 1040, which may include a titanium nitride (TiN) layer. In one embodiment, the contact layer 1050 may be omitted. In this example, the contact layer 1050 may be used to provide contacts 105 (e.g., source contacts) for the vertical fin JFET device 100.

[0070] Figure 5 A partial cross-sectional view of a vertical fin JFET device 100 after further processing is illustrated. In this example, a patterned hard mask 206 is provided on the contact layer 1050. In some examples, the patterned hard mask 206 may comprise silicon nitride (Si3N4) and may be formed at approximately 300°C with a thickness of approximately 400 nm by PECVD. In some examples, the openings in the patterned hard mask 206 may be formed using a RIE with an F-based chemical composition. In this example, the patterned hard mask 206 may be aligned with trench 202 and configured to provide an array of fins 103 in rows and columns.

[0071] After providing the patterned hard mask 206, an etching process is performed using the patterned hard mask 206 as a mask to form a recess region 208, and further to form a plurality of fins 103, doped contact regions 104, and contact portions 105. In this example, the recess region 208 is etched into the fin channel region 1030 formed by the second epitaxial growth process, and further etched into the gate region portion 110A formed by the first epitaxial growth process. Figure 5 As shown, the recessed region 208 exposes a portion of the gate region 110A. In this example, the recessed region 208 is positioned such that it is directly aligned with the trench 202.

[0072] In some examples, each fin 103 has a minimum width of about 0.2 micrometers and a height ranging from about 0.7 micrometers to 0.8 micrometers, and is spaced apart from each other by a gap of about 2 micrometers, i.e., the fin pitch is about 2.2 μm. To achieve uniform fin height, good controllability of the etching process depth is utilized. The etching process forming the recessed region 208 may include Cl-based chemicals using a RIE process. The recessed region 208 may include, or is also referred to as, a second trench. In one embodiment, the etching process may stop when about 0.2 micrometers of the gate region portion 110A is removed. In this example, the recessed region 208 does not extend through the gate region portion 110A to the drift region 102 (i.e., the gate region portion 110A is laterally interposed between the drift region 102 and the recessed region 208), which preserves the native interface 1102. In one embodiment, after forming the recessed region 208, the trench 202 may be cleaned using the previously described TMAH cleaning process, including pre-cleaning with Piranha.

[0073] like Figure 5 As shown, the gate region portion 110A surrounds and abuts at least a portion of the base portion 1031 of the fin 103. That is, the fin 103 extends upward from an opening in the gate region portion 110A. In this example, the recessed region 208 may provide a non-uniform thickness for the gate region portion 110A. More specifically, the thickness of the gate region portion 110A may increase near the fin 103, thereby providing a tapered upper surface 1101 for the gate region portion 110A.

[0074] like Figure 5 As further shown, the width of fin 103 can be non-uniform, and the base portion 1031 of fin 103 can be wider than the upper portion 1032. According to this description, since the base portion 1031 is wider and more heavily doped at the lower interface with the drift region 102, it is more compatible with... Figure 14 The problems associated with the described parasitic high threshold voltage transistor (where the bottom portion of fin 403 is adjacent to a lighter-doped gradient doped layer 402A) are reduced and the on-resistance is increased.

[0075] It should be understood that after the etching process, the base portion 1031 may have the same... Figure 5Different shapes are shown. Embodiments are described herein with reference to cross-sectional views as schematic illustrations of idealized embodiments (and intermediate structures) of the invention. For clarity, the thicknesses of layers and regions in the figures may be exaggerated. Additionally, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, embodiments of the invention should not be construed as limited to the specific shapes of the regions illustrated herein, but should be understood to include, for example, shape deviations due to manufacturing processes. In the figures, the bottom portion of the fin is shown at a 90-degree angle to the surface of the gate region portion 110A. However, it should be understood that the bottom portion of the fin may have circular or curved features. Therefore, the regions illustrated in the figures are substantially schematic, and their shapes are not intended to illustrate precise shapes of device regions, nor are they intended to limit the scope of the invention.

[0076] Figure 6 A partial cross-sectional view of the vertical fin JFET device 100 after further processing is illustrated. In this example, a third epitaxial growth process is used to form the gate region 110B within the recess region 208, adjacent to the fin 103, and on the gate region 110A. In this example, the gate region 110B includes a p-type III nitride layer (e.g., a Mg-doped GaN layer) grown within the recess region 208 at a temperature of approximately 950 degrees Celsius until it reaches a thickness substantially flush with the bottom of the contact 105. In some examples, the thickness of the gate region 110B is approximately 1,000 nm. Therefore, in some examples, the regrowing is substantially flush with the bottom of the patterned hard mask 206 or the contact 105 (i.e., above the doped contact region 104). The thickness of the gate region 110B can take into account the thickness of the fin 103, the etching of the gate region 110A, and the thickness of the reinforcement layer 1040.

[0077] The gate region portion 110B may have approximately 2 × 10 19 atoms / cm 3 The dopant concentration is set (i.e., the fourth dopant concentration). Subsequently, thermal annealing (e.g., rapid thermal annealing at 850°C for 5 minutes in N2) is performed to activate the Mg dopant atoms having gate region portions 110B and 110A. Mg atoms may be activated in an amount greater than 10% by weight in the p-type GaN layer. In other examples, the Mg dopant in gate region portion 110A may be activated by similar thermal annealing after the first epitaxial growth process. In this example, the doped contact region 104 is formed by a heavily doped N-type enhancement layer 1040 present between the fin 103 and the contact portion 105 to improve the contact resistance between the fin 103 and the contact portion 105.

[0078] According to this description, the third epitaxial growth process provides a gate region portion 110B as a regrowth region. More specifically, the gate region portion 110B includes a regrowth interface 1103 between the gate region portion 110B and the fin 103. The regrowth interface 1103 defines a gate-source PN junction that controls the channel region of the vertical fin JFET device 100. In this example, the gate-source PN junction is formed as a regrowth interface between the gate region portion 110A and the drift region 102, rather than the native interface 1102. Furthermore, the gate region portion 110B and the gate region portion 110A form a regrowth interface 1104, which is located above the native interface 1102. In this example, the separate gate regions 110A and 110B provide beneficial independent adjustments and optimizations for the formation of the gate-source (channel) PN junction and the gate-drift region PN junction.

[0079] According to this description, the dopant concentration of gate layer portion 110A (i.e., the second dopant concentration) is about 25% or less of the dopant concentration of gate layer portion 110B (i.e., the fourth dopant concentration). In some examples, the second dopant concentration may range from about 0.25% to about 25% of the fourth dopant concentration.

[0080] In subsequent manufacturing steps, the patterned hard mask 206 can be removed, and further processing can be performed to complete the vertical fin JFET device 100. This may include, for example, providing a passivation layer, conductive vias, gate contact structure 112, additional conductive interconnect layers, wafer thinning, and drain metal layer 117.

[0081] In one example, the vertical fin JFET device 100 can be configured as an N-channel enhancement-mode device, which operates as follows: In the off state, the gate-source voltage (V... GS The drain-source voltage is typically 0 volts or a slightly negative voltage between -2 volts and -5 volts. Additionally, the drain-source voltage (V...) DSThe voltage is greater than zero (i.e., the drain metal layer 117 is positive relative to the source electrode (e.g., contact 105), which is typically 0 volts or ground). Under these conditions, the gate-channel junction is reverse biased, the channel within fin 103 is depleted, and current does not flow from the drain region (i.e., semiconductor substrate 101 and drift region 102) through the channel (i.e., fin 103) to the source electrode (i.e., contact 105). In other words, when the gate-channel junction is reverse biased, the leakage current remains low. Furthermore, in the off state, the gate-drain junction can become deeply reverse biased, and the junction supports the main portion of the high electric field. More specifically, the peak electric field is located near the gate-drain junction. According to this description, by using the native gate region portion 110A in combination with the regrowth gate region portion 110B, the device architecture repositions the regrowth interface away from the region where the peak electric field occurs. Instead, a primary high-field PN junction is established between the drift region 102 and the native gate region portion 110A, ensuring the formation of this critical junction without exposure to regrowth-related contamination or defects. Therefore, the gate-drain junction exhibits a significantly reduced defect density compared to prior art designs that rely on the regrowth interface. This enhances device robustness, breakdown reliability, and long-term operational lifetime.

[0082] To switch the vertical fin JFET device 100 to the on state, a positive gate-source voltage (e.g., 2 volts to 5 volts) is applied to forward bias the gate-channel junction and form a low-resistance channel, allowing current to flow from the drain electrode through fin 103 to the source electrode. Typically, forward biasing the gate-channel junction is sufficient to modulate the depletion layer, but it is not usually driven for reconduction. Furthermore, a positive voltage can be maintained on the drain electrode, and the source electrode can be held at 0 volts or ground.

[0083] Figure 7 This is a Weibull cumulative distribution function (Weibull CDF) plot, which shows the relationship between a regenerated PN junction and high-temperature reverse bias (HTRB) conditions (e.g., Figure 14 The failure time probability of a native PN junction (e.g., a PN junction formed by the gate region 110A and the drift region 102 in a vertical fin JFET device 100) compared to a regrowth PN junction between the gate region 410 and the graded doped layer 402A in a vertical fin JFET device 400, according to the present description. Data lines 701 with filled triangles represent data of the native PN junction, and data lines 702 with unfilled triangles represent data of the regrowth PN junction. Figure 7As shown, the native gate-drain PN junction provides a 10-fold improvement in HTRB lifetime performance compared to a regrowth PN junction. More specifically, the native configuration of the gate-drain PN junction formed by the gate region 110A and the drift region 102 enables the formation of a lower defect junction, which improves the lifetime performance of the vertical fin JFET device 100.

[0084] Figure 8 This is a graph illustrating the positioning offset of the vertical fin JFET device according to this description under high electric field, compared to existing vertical fin JFET devices. Figure 8 The electric field measurement in is along Figure 1 The reference cut line CL of the vertical fin JFET device 100 shown is... Figure 14 The reference cut line CL of the vertical fin JFET device 400 shown is used. In this example, CL is located at a distance from... Figure 1 The center and distance of the left fin 103 Figure 14 It is located at a distance Y (i.e., in the horizontal direction) of approximately 1 micrometer from the center of the left fin 403. Figure 8 The vertical dashed line 801 indicates the location of the regrowth interface in the X direction or its depth from the top surface of the gate region (at a 90-degree angle to the cut line CL). More specifically, the X direction is perpendicular to the top surfaces of gate regions 110 and 410 or in a direction perpendicular to the top surfaces of gate regions 110 and 410. In this example, the regrowth interface (dashed line 801) corresponds to the interface between gate region portions 110B and 110A in the vertical fin JFET device 100 and the interface between gate region 410 and drift regions 402 / 402A in the vertical fin JFET device 400.

[0085] Data line 802 contains the electric field data of the operating vertical-fin JFET device 100, and data line 803 contains the electric field data of the operating vertical-fin JFET device 400. For example... Figure 8 It is evident that the electric field in the vertical fin JFET device 100 is approximately 97% lower near the regrowth interface compared to the electric field in the vertical fin JFET device 400. According to this description, by removing the regrowth interface from the peak electric field location, the reliability of the vertical fin JFET device 100 is improved compared to the reliability of the vertical fin JFET device 400.

[0086] Figure 9 This is a graph illustrating the drain current / voltage (I / V) characteristics of the vertical-fin JFET device according to this description, compared to prior art vertical-fin JFET devices. Figure 9In the diagram, data line 901 represents the I / V data of the vertical-fin JFET device 100, and data line 902 represents the I / V data of the vertical-fin JFET device 400. As previously mentioned, a characteristic of the vertical-fin JFET device 100 is that the base portion 1031 of the fin 103 has a higher doping concentration, wherein the base portion 1031 is connected to or coupled to the drift region 102. Conversely, in the vertical-fin JFET device 400, the base region of the fin 403 has a lower doping concentration due to the gradient doped layer 402A. More specifically, in the vertical-fin JFET device 100, the base portion 1031 has a uniform doping that matches the overall doping of the fin 103, thus avoiding the gradient doping characteristics of prior art devices. Among other things, this feature of the vertical-fin JFET device 100 improves the saturation drain current (Is). DSAT ),like Figure 9 As shown.

[0087] Further determination using deep-level transient spectroscopy (DLTS) revealed that the native gate-drain PN junction described herein possesses improved junction quality compared to the regrown gate-drain PN junction. For example, DLTS data showed that the native PN junction has three (3) electron trap levels compared to the 11 electron trap levels of the regrown PN junction. Furthermore, the cumulative electron trap density of the regrown PN junction is 6.1 × 10⁻⁶. 15 cm -3 In comparison, the cumulative electron trap density of a native PN junction is 2.5 × 10⁻⁶. 14 cm -3 Furthermore, the cumulative electron trapping density of the regenerated PN junction is 1182 cm⁻¹. -1 In comparison, the cumulative electron trapping density of a native PN junction is three (3) cm. -1 Additionally, compared to the regenerated PN junction which has six (6) hole trap levels, the native PN junction has three (3) hole trap levels. Furthermore, the cumulative hole trap density of the regenerated PN junction is 1.6 × 10⁻⁶. 16 cm -3 In comparison, the cumulative hole trap density of a native PN junction is 1.1 × 10⁻⁶. 16 cm -3 Finally, the cumulative hole trap density capture XS of the regenerated PN junction was 105 cm⁻¹. -1 In comparison, the cumulative hole trap density capture XS of the native PN junction is 11 cm⁻¹. -1 This data quantifies the benefits of a native PN junction, as described herein, by providing a native gate-drain junction with lower defects (i.e., a native PN junction provided by drift region 102 and gate region portion 110A).

[0088] Typically, fins used in vertical fin JFET devices are provided in large arrays, comprising patterns or arrays of columns and rows of fins across a semiconductor substrate. It should be understood that the uniformity of both the photolithography and etching processes used to fabricate vertical fin JFET devices can vary significantly between regions with regular fin patterns and regions with sparse fin patterns. This variation can occur at the edges of the fin array. For example, the presence of large sparse regions next to a regular array can lead to differences in exposure dose due to proximity effects, which may cause the resist linewidth to vary between the center and edges of the array, resulting in increased electrical variations in the fin devices near the array edges. Additionally, the presence of large sparse patterned regions next to a regular patterned array can lead to differences in etching rates caused by variations in the amount of etchant consumed in the sparse patterned regions compared to the amount consumed in the regular patterned array. Such differences in etching rates affect fin width and fin height, resulting in increased electrical variations in the fin devices near the array edges.

[0089] Furthermore, it should be understood that the local pattern density in the fin array can affect the uniformity of the regrowth gate region process. Such variations in the growth rate can lead to non-uniform growth height on the fin sidewalls, which will affect the effective channel length of the JFET device and, for fins near the array edges, may result in variations in leakage current and threshold voltage at high voltages. Variations in the growth rate can also affect the uniformity of dopant incorporation in GaN during regrowth, which in turn can lead to variations in the threshold voltage.

[0090] Figure 10 This is a partial cross-sectional view illustrating a vertical fin JFET device 150 including fin 103 and passive fin 303 according to an embodiment of this description. In this example, fin 103 may include, or be referred to as, an active fin. The vertical fin JFET device 150 has some similarities in construction to the vertical fin JFET device 100, and such similarities will not be repeated here. In this regard, only certain differences will be discussed below.

[0091] In this example, the vertical fin JFET device 150 includes passive fins 303, which may be part of a plurality of passive fins 303 positioned in a specific location within the vertical fin JFET device 150. More specifically, the passive fins 303 may be provided as part of one or more arrays of passive fins 303 placed in regions of the semiconductor substrate 101 to address uniformity issues, etc., associated with the previously described photolithography, etching, and gate regrowth processes. Such regions may include, but are not limited to, edge regions of the semiconductor substrate 101 that provide edge-terminating structures.

[0092] According to this description, the passive fin 303 includes an upper portion 1032 similar to fin 103, but does not include a base portion 1031. Instead, the passive fin 303 is adjacent to a portion 1110A of the gate region portion 110A. When the passive fin 303 has N-type conductivity and the gate region portion 110A (which includes portion 1110A) has P-type conductivity, the passive fin 303 is electrically isolated from the drift region 102 and does not provide a channel for current conduction during operation of the vertical fin JFET device 150. That is, the gate region portion 110A is interposed between the passive fin 303 and the drift region 102 such that the gate region portion 110A electrically isolates the passive fin 303 from the drift region 102. In some examples, the contact portion 105 does not contact the passive fin 303, and the passive fin 303 may be characterized as an electrically floating structure.

[0093] Figure 11 , Figure 12 and Figure 13 This is a partial cross-sectional view illustrating an example method for manufacturing a vertical fin JFET device according to an embodiment of the present description, which can be used to manufacture a vertical fin JFET device 150. Figures 11 to 13 The described method and Figures 3 to 5 The methods described have some similarities, and these similarities will not be repeated here. In this regard, only certain differences will be discussed below.

[0094] In this example, it can be provided Figure 2 The semiconductor substrate 101 and associated layers are described in the figure. Figure 11 A partial cross-sectional view of the vertical fin JFET device 150 after further processing is shown. It should be noted that... Figures 11 to 13 In this example, semiconductor substrate 101 and buffer layer 1015 are not shown. Mask 201 may be provided above capping layer 1016 and patterned to provide openings corresponding to the positioning of fin 103, but... Figure 3 Compared to the previous example, the opening in mask 201 is not set at the location where the passive fin 303 will be formed.

[0095] Figure 12A partial cross-sectional view of a vertical fin JFET device 150 after further processing is illustrated. In this example, mask 201 can be removed, and a second epitaxial growth process is used to form an N-type group III nitride fin channel region 1030 (e.g., GaN doped with Si or Ge) within trench 202 and over the gate region portion 110A. The second epitaxial growth process provides and fills the fin channel region 1030 within trench 202 and extends in the direction over the gate region portion 110A. In some examples, the second epitaxial growth process can be used to form a reinforcement layer 1040 at the upper portion of the fin channel region 1030. In some examples, a contact layer 1050 can then be provided on the reinforcement layer 1040, as previously described. In some examples, if the contact layer 1050 is included, the contact layer can be patterned to remove the portion located above the positioning of the passive fin 303, such as... Figure 12 As shown.

[0096] Figure 13 A partial cross-sectional view of the vertical fin JFET device 150 after further processing is illustrated. In this example, a patterned hard mask 206 is provided on the contact layer 1050, as previously described. In this example, the patterned hard mask 206 is alignable with the trench 202 and configured to provide an array of fins 103 in rows and columns. Furthermore, the patterned hard mask 206 can be aligned using alignment keys or other alignment structures to provide an array of passive fins 303 in rows and columns.

[0097] After providing a patterned hard mask 206, an etching process is performed using the patterned hard mask 206 as a mask to form fins 103 having doped contact regions 104 and contact portions 105 (e.g., patterned metal contacts) and passive fins 303 having doped contact regions 104. It should be understood that contact portions 105 may include passive fins 303, but such contact portions 105 are subsequently not electrically connected to source metal contacts. According to this description, passive fins 303 are provided on a portion 1110A of the gate region portion 110A and are electrically isolated from the drift region 102. In some examples, portion 1110A is thicker than those portions of the gate region portion 110A that interface with the gate region portion 110B. That is, portion 1110A has a first thickness 131, and the portion of the gate region portion 110A that forms a generally horizontal interface with the gate region portion 110B in a cross-sectional view has a second thickness 132 less than the first thickness. This feature provides beneficial electrical isolation between the passive fin 303 and the drift region 102. Then, as previously discussed... Figure 6 The vertical fin JFET device 150 is processed as described to provide... Figure 10 The example shown.

[0098] In summary, the passive fin 303 can be used in selected regions of the vertical fin JFET device 150 to address uniformity issues associated with the previously described photolithography, etching, and gate regrowth processes. Such regions may include, but are not limited to, the edge regions of the semiconductor substrate 101 that provide edge-terminating structures.

[0099] Based on all the foregoing, those skilled in the art will recognize that, in this example, the semiconductor device includes a vertical fin FET comprising a gate region, a portion of which contacts a drain region fabricated within a single epitaxial growth process, wherein the single epitaxial growth process includes modifying the peak electric field at the junction of the gate and drain regions during operation, thereby improving lifetime performance or increasing breakdown voltage. In another example, the semiconductor device may also include independent p-side control of the gate-source and gate-drift junctions, thereby selecting the breakdown voltage, channel control, drain current, and edge termination characteristics of the semiconductor device.

[0100] In another example, any crystal damage that occurs during FET fabrication occurs at the interface experiencing relatively low voltage / field during device operation. In yet another example, the semiconductor device may also include one or more passive fins to improve structural uniformity on the semiconductor device, including edge-termination features. In yet another example, the gate region may be divided into a first portion and a second portion to facilitate the fabrication of one or more passive fins, at least one of which includes an N-type fin that is not electrically connected to the N-type drain of the semiconductor device.

[0101] Based on all the foregoing, those skilled in the art will determine that, in one example, the semiconductor device includes a vertical fin FET having a fin channel semiconductor region formed by a second semiconductor epitaxial growth applied to a patterned first semiconductor epitaxial growth including a drift region.

[0102] Based on all the foregoing, those skilled in the art will determine that, in one example, the semiconductor device includes a vertical fin FET having a gate semiconductor region partially formed by a third selective region semiconductor epitaxial growth applied to a combination of a patterned second semiconductor epitaxial growth including a fin channel region and a patterned first epitaxial growth including the gate semiconductor region. In another example, the semiconductor device may also include one or more non-active fins to improve structural uniformity on the semiconductor device including edge-terminating regions.

[0103] In another example, one or more non-active fins improve the morphological uniformity of the third selective region epitaxial growth process and help control the layer thickness in portions of the fabrication edge termination region of the semiconductor device.

[0104] In summary, structures and methods for semiconductor devices, including vertical fin FET devices with improved gate-drain interfaces, have been described. More specifically, a first portion of the gate region (specifically, the portion contacting the drain) is formed during the same epitaxial growth process used to create the drift region portion of the drain region, rather than through a separate second epitaxial growth step. In this example, a second portion of the gate region is formed on the first portion in a later step of fabrication. The fabrication method enhances the structural and electrical integrity of the gate-drain interface by forming the drain contact portion of the gate region during the same epitaxial growth step used to form the drift region portion of the drain region. Integrating these regions into a single epitaxial process reduces the heterojunction associated with the regrowth junction and lowers defect densities, such as through-dislocations, point defects, and impurity incorporation that typically occur in separate regrowth steps. Consequently, the gate-drain junction benefits from a more uniform doping distribution, improved crystal alignment, and reduced trap-assisted leakage paths, resulting in higher breakdown voltages. The methods and structures described herein also contribute to increased drain current and more robust edge-termination regions compared to prior art designs.

[0105] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not by way of limitation. Similarly, various illustrations may depict exemplary architectures or other configurations of this disclosure in order to aid in understanding the features and functionality that may be included in this disclosure. This disclosure is not limited to the exemplary architectures or configurations illustrated, but may be implemented using various alternative architectures and configurations. Additionally, although this disclosure has been described above with reference to various exemplary embodiments and specific implementations, it should be understood that the various features and functionalities described in one or more individual embodiments are not limited in their applicability to the specific embodiments in which they are described. Rather, they may be applied individually or in some combination to one or more embodiments of this disclosure, whether or not such embodiments are described, and whether or not such features are presented as part of the described embodiments. Therefore, the breadth and scope of this disclosure should not be limited to any of the exemplary embodiments described above.

[0106] It should be understood that, for clarity, the above description has referenced various functional units and processors to describe embodiments of the invention. However, it will be apparent that any suitable distribution of functionality among different functional units, processors, or domains may be used without departing from the invention. For example, functionality exemplified as being performed by a separate processor or controller may be performed by the same processor or controller. Therefore, references to specific functional units are to be regarded only as references to suitable components used to provide the described functionality, and not as indications of a strict logical or physical structure or organization.

[0107] It should also be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes will be made by those skilled in the art based thereon, and such modifications or changes will be included within the spirit and scope of this application and within the scope of the appended claims.

Claims

1. A vertical fin FET device, the vertical fin FET device comprising: A semiconductor substrate, wherein the semiconductor substrate is characterized by a first conductivity type; A drift region, the drift region being above the semiconductor substrate and characterized by the first conductivity type and the first dopant concentration; A first gate region portion, which is located in the drift region and is characterized by a second conductivity type and a second dopant concentration that are opposite to the first conductivity type; A trench that extends through a portion of the first gate region to the drift region; A fin, which extends over the first gate region portion within the trench and is characterized by the first conductivity type and the third dopant concentration; and The second gate region portion, which is on the first gate region portion, surrounds the fin and is characterized by the second conductivity type and the fourth dopant concentration; in: The first gate region and the drift region form a native interface; The second gate region and the first gate region form a regrowth interface; and The fin includes a base portion within the groove and an upper portion coupled to the base portion and extending above the groove.

2. The vertical fin FET device according to claim 1, wherein: The first dopant concentration is a uniform dopant concentration; and The concentration of the second dopant is less than the concentration of the fourth dopant.

3. The vertical fin FET device according to claim 1, wherein: The base portion of the fin is wider than the upper portion; and The semiconductor substrate includes an engineered GaN substrate.

4. The vertical fin FET device according to claim 1, wherein: The first gate region includes a first thickness close to the fin and a second thickness away from the fin; and The first thickness is greater than the second thickness.

5. The vertical fin FET device according to claim 1, wherein: The semiconductor substrate, the drift region, the first gate region portion, the fin, and the second gate region portion comprise a group III nitride semiconductor material.

6. The vertical fin FET device according to claim 1, wherein: The drift region does not contain a gradient dopant layer of the first conductivity type interposed between the drift region and the first gate region portion.

7. The vertical fin FET device according to claim 1, further comprising: A passive fin is located on the first gate region portion, wherein the first gate region portion electrically isolates the passive fin from the drift region.

8. The vertical fin FET device according to claim 7, wherein: The passive fin is an electrically levitated structure.

9. The vertical fin FET device according to claim 1, wherein: The base portion of the fin includes a first end coupled to the drift region; The first end is located within the first plane; and The native interface is located in a second plane that is different from the first plane.

10. The vertical fin FET device according to claim 1, wherein: The first gate region portion includes a tapered upper surface at a location adjacent to the fin.

11. A vertical fin FET device, the vertical fin FET device comprising: A semiconductor substrate, wherein the semiconductor substrate is characterized by a first conductivity type; A drift region, the drift region being above the semiconductor substrate and characterized by the first conductivity type; A first gate region portion, which is located on the drift region and is characterized by a second conductivity type opposite to the first conductivity type; The second gate region portion is on the first gate region portion and is characterized by the second conductivity type; and A fin, characterized by the first conductivity type, coupled to the drift region and extending through the first gate region portion and the second gate region portion; in: The first gate region and the drift region form a native PN junction; The second gate region and the first gate region form a regrowth interface; and The fin includes a base portion adjacent to the drift region and an upper portion coupled to the base portion.

12. The vertical fin FET device according to claim 11, wherein: The drift region includes a uniform dopant concentration; and The first gate region has a lower dopant concentration than the second gate region.

13. The vertical fin FET device of claim 11, further comprising: A trench extending through the first gate region portion, wherein the base portion of the fin is located within the trench.

14. The vertical fin FET device according to claim 11, wherein: The semiconductor substrate, the drift region, the first gate region portion, the fin, and the second gate region portion comprise a group III nitride semiconductor material.

15. The vertical fin FET device of claim 11, further comprising: A passive fin is located on a first gate region portion, wherein the first gate region portion is inserted between the passive fin and the drift region such that the first gate region portion electrically isolates the passive fin from the drift region.

16. A method for manufacturing a vertical fin FET device, the method comprising: A semiconductor substrate is provided, the semiconductor substrate being characterized by a first conductivity type; In the first epitaxial growth process: A drift region is formed above the semiconductor substrate, the drift region being characterized by the first conductivity type and the first dopant concentration; as well as A first gate region portion is formed on the drift region, the first gate region portion being characterized by a second conductivity type and a second dopant concentration that are opposite to the first conductivity type; A trench is formed, the trench extending through a portion of the first gate region to reach the drift region; In the second epitaxial growth process, a fin channel region is formed in the trench and above the first gate region portion, the fin channel region being characterized by the first conductivity type and the third dopant concentration; A groove region is formed in the fin channel region to form a fin; and In the third epitaxial growth process, a second gate region is formed on the first gate region, the second gate region surrounding the fin, and is characterized by the second conductivity type and the fourth dopant concentration; in: The first epitaxial growth process is an in-situ process, wherein the in-situ process provides the first gate region portion and the drift region as a native interface; The second gate region and the first gate region form a regrowth interface; and The fin includes a base portion within the groove and an upper portion coupled to the base portion and extending above the groove.

17. The method of claim 16, wherein: Forming the drift region includes providing the first dopant concentration as a uniform dopant concentration; and Forming the groove region includes: Align the recessed area with the groove; and The base portion is provided to be wider than the upper portion of the fin.

18. The method of claim 16, wherein: Providing the recessed region includes providing a first gate region portion having a first thickness close to the fin and a second thickness distant from the fin; and The first thickness is greater than the second thickness.

19. The method of claim 16, wherein: Forming the fin includes providing a passive fin on the first gate region portion; and The first gate region portion electrically isolates the passive fin from the drift region.

20. The method of claim 16, wherein: The semiconductor substrate, the drift region, the first gate region portion, the fin, and the second gate region portion comprise a group III nitride semiconductor material.

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