Semiconductor device

Abstract

A semiconductor device includes an active pattern located on a substrate, a first channel structure and a second channel structure spaced apart from each other over the active pattern, a gate electrode located on the first channel structure and the second channel structure, and a separation structure provided between the first channel structure and the second channel structure. Each of the first channel structure and the second channel structure includes a plurality of semiconductor patterns. An upper surface of the separation structure has a height higher than a height of an upper surface of an uppermost semiconductor pattern among the plurality of semiconductor patterns. The gate electrode provided between the plurality of semiconductor patterns is in contact with the separation structure.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to semiconductor devices including pillar structures. Background Technology

[0002] Semiconductor devices can include integrated circuits containing metal-oxide-semiconductor field-effect transistors (MOS-FETs). To meet the growing demand for semiconductor devices with smaller pattern sizes and simplified design rules, the size of MOS-FETs has been reduced. However, this reduction in MOS-FET size can lead to a degradation in the operating characteristics of semiconductor devices. The goal is to overcome the technical hurdles associated with semiconductor device miniaturization and to provide high-performance semiconductor devices. Summary of the Invention

[0003] This disclosure relates to a semiconductor device having improved electrical and reliability characteristics.

[0004] Typically, according to some aspects, a semiconductor device may include: an active pattern located on a substrate; a first channel structure and a second channel structure spaced apart from each other on the active pattern; a gate electrode located on the first channel structure and the second channel structure; and a separator structure disposed between the first channel structure and the second channel structure, wherein each of the first channel structure and the second channel structure includes a plurality of semiconductor patterns, wherein the height of the upper surface of the separator structure is greater than the height of the uppermost semiconductor pattern among the plurality of semiconductor patterns, and wherein the gate electrode disposed between the plurality of semiconductor patterns is in contact with the separator structure.

[0005] Typically, according to some aspects, a semiconductor device may include: a substrate including an active pattern; a device isolation layer defining the active pattern; a first channel structure and a second channel structure spaced apart from each other on the active pattern; a gate electrode located on the first channel structure and the second channel structure; a gate insulating layer disposed between the gate electrode and the first channel structure and between the gate electrode and the second channel structure; and a partition structure disposed between the first channel structure and the second channel structure, wherein each of the first channel structure and the second channel structure includes a plurality of semiconductor patterns having four surfaces, the height of the upper surface of the partition structure is greater than the height of the uppermost semiconductor pattern among the plurality of semiconductor patterns, the gate insulating layer surrounds the four surfaces of each of the plurality of semiconductor patterns, and a portion of the side surface of the partition structure is exposed from the gate insulating layer.

[0006] Typically, according to some aspects, a semiconductor device may include: a substrate including a first active pattern and a second active pattern defined by a device isolation layer; a first channel structure and a second channel structure, the first channel structure being located on the first active pattern and the second channel structure being located on the second active pattern; a source / drain pattern connected to the first channel structure and the second channel structure; a first gate electrode and a second gate electrode, the first gate electrode being located on the first channel structure and the second gate electrode being located on the second channel structure; and a gate insulating layer disposed between the first gate electrode and the first channel structure and the second gate electrode. Between the first gate electrode and the second channel structure; and a partition structure disposed between the first channel structure and the second channel structure, wherein each of the first channel structure and the second channel structure includes a plurality of semiconductor patterns having four surfaces, the gate insulating layer surrounds the four surfaces of each of the plurality of semiconductor patterns, the upper surface of the partition structure is higher than the upper surface of the uppermost of the plurality of semiconductor patterns, and from a horizontal viewpoint, a portion of the side surface of the partition structure contacts the gate insulating layer, and the remainder of the side surface of the partition structure contacts the first gate electrode and the second gate electrode.

[0007] Typically, according to some aspects, a method of manufacturing a semiconductor device may include: forming a first channel structure and a second channel structure comprising a plurality of semiconductor patterns on a substrate; forming a gate insulating layer on the semiconductor patterns; forming a partition structure comprising a core structure between the first channel structure and the second channel structure; and forming a gate electrode on the gate insulating layer, wherein forming the plurality of semiconductor patterns includes forming a first semiconductor layer and a second semiconductor layer alternately stacked on the substrate, wherein forming the gate insulating layer includes forming a gate insulating layer surrounding four surfaces of the semiconductor patterns, and forming the partition structure includes forming a photoresist pattern covering the plurality of semiconductor patterns on the substrate, etching the photoresist pattern to form a hole, filling the hole with an insulating material, and etching the upper portion of the insulating material.

[0008] Typically, depending on some aspects, etching the upper portion of the insulating material may include performing the etching process such that the height of the upper surface of the insulating material remains above the height of the uppermost semiconductor pattern disposed among the plurality of semiconductor patterns.

[0009] Typically, depending on some aspects, forming the separation structure may further include etching the upper portion of the insulating material to form a core structure, removing the photoresist pattern, and forming a cladding structure around the core structure.

[0010] Typically, depending on some aspects, forming the gate electrode may include forming the gate electrode until the height of the upper surface of the gate electrode is equal to the height of the upper surface of the separator structure.

[0011] Typically, depending on some aspects, a method of manufacturing a semiconductor device may also include forming a source / drain pattern connected to the first channel structure and the second channel structure prior to forming the separation structure. Attached Figure Description

[0012] Figure 1 This is a top view showing an example of a semiconductor device.

[0013] Figure 2A It is along Figure 1 Example cross-section diagram taken from line AA′.

[0014] Figure 2B It is along Figure 1 Example cross-sectional view of line BB′.

[0015] Figure 2C It is along Figure 1 Example cross-sectional view of line CC′.

[0016] Figure 2D It is along Figure 1Example cross-sectional view of line DD′.

[0017] Figure 3 It is shown Figure 2A An enlarged example of a portion of the "CU".

[0018] Figure 4 It is shown Figure 2A An enlarged example of a portion of the "CU".

[0019] Figure 5 It is along Figure 1 Example cross-section diagram taken from line AA′.

[0020] Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 16C and Figure 16D This is a cross-sectional view illustrating an example of a process for manufacturing semiconductor devices. Detailed Implementation

[0021] Example embodiments will now be described more fully with reference to the accompanying drawings, in which example embodiments are illustrated.

[0022] Figure 1 This is a top view showing an example of a semiconductor device. Figure 2A It is along Figure 1 Example cross-section diagram taken from line AA′. Figure 2B It is along Figure 1 Example cross-sectional view of line BB′. Figure 2C It is along Figure 1 Example cross-sectional view of line CC′. Figure 2D It is along Figure 1 Example cross-sectional view of line DD′.

[0023] refer to Figures 1 to 2D The semiconductor device may include a substrate 10. The substrate 10 may be in the form of a plate extending along a plane defined by a first direction D1 and a second direction D2.

[0024] In this specification, the first direction D1 is defined as a direction parallel to the upper surface of the substrate 10. The second direction D2 is defined as a direction parallel to the upper surface of the substrate 10 and perpendicular to the first direction D1. The third direction D3 is defined as a direction perpendicular to the upper surface of the substrate 10.

[0025] The substrate 10 may be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor substrate may include, for example, silicon (Si), germanium (Gi), silicon-germanium (SiGe), GaP, or GaAs.

[0026] Logic transistors constituting a logic circuit can be disposed on a substrate 10. The substrate 10 may include a first active pattern AP1 and a second active pattern AP2. Each of the first active pattern AP1 and the second active pattern AP2 may extend in a second direction D2. The first active pattern AP1 and the second active pattern AP2 may be arranged sequentially in a first direction D1. The first active pattern AP1 and the second active pattern AP2 may be spaced apart from each other in the first direction D1. The first active pattern AP1 and the second active pattern AP2 may be the upper portion of the substrate 10 protruding in a third direction D3.

[0027] A device isolation layer 12 may be disposed in the substrate 10. The device isolation layer 12 may be disposed in a first direction D1. The device isolation layer 12 may be disposed between a first active pattern AP1 and a second active pattern AP2. That is, the device isolation layer 12 may define the first active pattern AP1 and the second active pattern AP2. The device isolation layer 12 may include an insulating material. For example, the device isolation layer 12 may include silicon oxide.

[0028] A first insulating layer IL1 can be provided covering the isolation layer 12 of the device. A second insulating layer IL2 can be provided covering the upper surface of the first active pattern AP1 and the upper surface of the second active pattern AP2. The first insulating layer IL1 and the second insulating layer IL2 may include, for example, an insulating material.

[0029] A first channel structure CH1 can be disposed on the third-direction D3, overlapping with the first active pattern AP1. A second channel structure CH2 can be disposed on the third-direction D3, overlapping with the second active pattern AP2.

[0030] Channel structures CH1 and CH2, which overlap with active patterns AP1 and AP2 in the third direction D3, can be arranged in the second direction D2. For example, as Figure 2C As shown, the first channel structure CH1, which overlaps with the first active pattern AP1 in the third direction D3, can be spaced apart from each other in the second direction D2.

[0031] Each first channel structure CH1 may include a first semiconductor pattern SP1 disposed on a third-direction D3. The first semiconductor pattern SP1 may be spaced apart on the third-direction D3. Each second channel structure CH2 may include a second semiconductor pattern SP2 disposed on a third-direction D3. The second semiconductor pattern SP2 may be spaced apart on the third-direction D3. The number of semiconductor patterns SP1 and SP2 in each channel structure CH1 and CH2 is not limited to the number in the example shown.

[0032] In some embodiments, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include silicon (Si). For example, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include crystalline silicon.

[0033] A partition structure 25 can be provided between the first channel structure CH1 and the second channel structure CH2, and between the first gate electrode GE1 and the second gate electrode GE2. The partition structure 25 can extend in the second direction D2. Multiple partition structures 25 can be provided along the second direction D2. The height of the upper surface of the partition structure 25 can be higher than the height of the uppermost semiconductor patterns SP1t and SP2t. Therefore, the first gate electrode GE1 and the second gate electrode GE2 can be separated from each other. The height of the lower surface of the partition structure 25 can be lower than the height of the upper surface of the first active pattern AP1 and the upper surface of the second active pattern AP2.

[0034] The separator structure 25 may include a core structure 22 and a cladding structure 26 surrounding the core structure 22. The height of the upper surface 22t of the core structure 22 may be higher than the height of the upper surfaces of the uppermost semiconductor patterns SP1t and SP2t.

[0035] The core structure 22 and cladding structure 26 may include insulating materials. The core structure 22 and cladding structure 26 may include the same or different materials. For example, the core structure 22 and cladding structure 26 may include at least one of silicon oxide, silicon nitride, or silicon carbonitride. A description of the separator structure 25 will follow... Figure 3 A more detailed description is provided below.

[0036] The first source / drain pattern SD1 can be set on the first active pattern AP1. The second source / drain pattern SD2 can be set on the second active pattern AP2. The first source / drain pattern SD1 can overlap with the first active pattern AP1 on the third-direction D3. The second source / drain pattern SD2 can overlap with the second active pattern AP2 on the third-direction D3. For example... Figure 1 As shown, the partition structure 25 can be spaced apart from the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0037] A first source / drain pattern SD1 can be disposed between adjacent first channel structures CH1 along the second direction D2. A second source / drain pattern SD2 can be disposed between adjacent second channel structures CH2 along the second direction D2. The first source / drain pattern SD1 can be connected to a first semiconductor pattern SP1 of the first channel structure CH1. The second source / drain pattern SD2 can be connected to a second semiconductor pattern SP2 of the second channel structure CH2.

[0038] Each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be an epitaxial pattern formed by a selective epitaxial growth process. Each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can include, for example, silicon (Si) or silicon germanium (SiGe).

[0039] Each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may include impurities. The first source / drain pattern SD1 and the second source / drain pattern SD2 may be doped to have the same conductivity type. As an example, the conductivity type of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be P-type. As an example, the conductivity type of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be N-type.

[0040] In some embodiments, the first source / drain pattern SD1 and the second source / drain pattern SD2 can be doped to have different conductivity types from each other. The first source / drain pattern SD1 can be doped to have a first conductivity type, while the second source / drain pattern SD2 can be doped to have a second conductivity type different from the first conductivity type. For example, the first conductivity type can be P-type, and the second conductivity type can be N-type. For example, the first conductivity type can be N-type, and the second conductivity type can be P-type.

[0041] The first gate electrode GE1 can be configured to overlap with the first active pattern AP1 on the third direction D3. The first gate electrode GE1 can also overlap with the first channel structure CH1 on the third direction D3. The second gate electrode GE2 can be configured to overlap with the second active pattern AP2 on the third direction D3. The second gate electrode GE2 can also overlap with the second channel structure CH2 on the third direction D3.

[0042] The first gate electrode GE1 can be disposed between first source / drain patterns SD1 that are adjacent to each other along the second direction D2. The second gate electrode GE2 can be disposed between second source / drain patterns SD2 that are adjacent to each other along the second direction D2. The first gate electrode GE1 and the second gate electrode GE2, as well as the first semiconductor pattern SP1 and the second semiconductor pattern SP2, can constitute a three-dimensional field-effect transistor (e.g., MBCFET or GAAFET).

[0043] A gate insulating layer GI can be disposed on a first gate electrode GE1 and a second gate electrode GE2. The gate insulating layer GI can separate the first gate electrode GE1 from the first semiconductor pattern SP1 and the second gate electrode GE2 from the second semiconductor pattern SP2. Based on a line extending in the third direction D3, one end of the gate insulating layer GI can be aligned with one end of the first gate electrode GE1 and the second gate electrode GE2. The gate insulating layer GI can include an insulating material. As an example, the gate insulating layer GI can include silicon oxide, silicon oxynitride, and / or a high dielectric constant material. In this document, a high dielectric constant material can be a material with a dielectric constant higher than that of silicon oxide.

[0044] The gate spacer GS can be disposed on the two sidewalls of the gate electrodes GE1 and GE2. The gate spacer GS may include an insulating material.

[0045] A gate cover pattern GP can be configured. The gate cover pattern GP can be configured on the first gate electrode GE1 and the second gate electrode GE2. The gate cover pattern GP can cover the first gate electrode GE1 and the second gate electrode GE2. The gate cover pattern GP can include an insulating material. As an example, the gate cover pattern GP can include silicon nitride.

[0046] Interlayer insulating layer 13 can be disposed on device isolation layer 12. Interlayer insulating layer 13 can cover the first source / drain pattern SD1 and the second source / drain pattern SD2. For example... Figure 2D As shown, multiple separating structures 25 can be disposed in the interlayer insulating layer 13 along the second direction D2. The interlayer insulating layer 13 may include an insulating material. As an example, the interlayer insulating layer 13 may include silicon oxide.

[0047] Active contacts 41 can be provided. Multiple active contacts 41 can be provided on the first direction D1. The active contacts 41 can penetrate the gate cover pattern GP and the interlayer insulating layer 13 to connect to the first source / drain pattern SD1 or the second source / drain pattern SD2. The active contacts 41 can include conductive materials. For example, the active contacts 41 can include metallic materials.

[0048] A gate contact 45 can be provided. The gate contact 45 can be connected to the gate electrodes GE1 and GE2 via a gate overlay pattern GP. The gate contact 45 may include a conductive material. For example, the gate contact 45 may include a metallic material.

[0049] Figure 3 It is shown Figure 2A An enlarged example of a portion of the "CU".

[0050] refer to Figure 2A and Figure 3 A portion of the side surface of the separator structure 25 may be exposed from the gate insulating layer GI. Specifically, a portion of the side surface of the cladding structure 26 may be exposed from the gate insulating layer GI.

[0051] From a vertical perspective, the first gate electrode GE1 disposed between multiple first semiconductor patterns SP1 and the second gate electrode GE2 disposed between multiple second semiconductor patterns SP2 can contact the separator structure 25. The first gate electrode GE1 can be closer to the separator structure 25 than the side surface SP1s of the first semiconductor pattern SP1, which is the side surface of the first semiconductor pattern SP1 that is closest to the separator structure 25. The second gate electrode GE2 can be closer to the separator structure 25 than the side surface SP2s of the second semiconductor pattern SP2, which is the side surface of the second semiconductor pattern SP2 that is closest to the separator structure 25.

[0052] The gate insulating layer GI may surround the four surfaces of the first semiconductor pattern SP1. The gate insulating layer GI may surround the four surfaces of the second semiconductor pattern SP2. The portions of the gate insulating layer GI surrounding the semiconductor patterns SP1 and SP2 may contact the separator structure 25.

[0053] From a vertical perspective, the portion of the gate insulating layer GI that contacts the separator structure 25 can overlap with the gate electrodes GE1 and GE2. From a horizontal perspective, a portion of the side surface of the separator structure 25 can contact the gate insulating layer GI, while the remaining portion of the side surface of the separator structure 25 can contact the gate electrodes GE1 and GE2.

[0054] From a horizontal perspective, the cladding structure 26 can be disposed between the gate insulating layer GI and the core structure 22, as well as between the gate electrodes GE1 and GE2 and the core structure 22.

[0055] The core structure 22 may include a first portion P1 and a second portion P2 located on the first portion P1. The second portion P2 may have a shape that protrudes from the cladding structure 26. That is, the second portion P2 may be located further away from the substrate 10 than the first portion P1. The height P2h of the second portion P2 may be 10% to 45% of the height 22h of the core structure 22. As an example, the height P2h of the second portion P2 may be 5 nm to 40 nm.

[0056] The core structure 22 may have a first width W1 in the first direction D1. The first width W1 may be increased in a third direction D3 away from the substrate 10. The cladding structure 26 may have a second width W2 in the first direction D1. The second width W2 may be decreased in a third direction D3 away from the substrate 10. The second width W2 may be smaller than the first width W1. As an example, the first width W1 may be from 10 nm to 40 nm. As an example, the second width W2 may be from 2 nm to 10 nm.

[0057] The height of the upper surface 22t of the core structure 22 can be higher than the height of the upper surface 26t of the cladding structure 26. The height of the upper surface GIt of the gate insulating layer GI surrounding the uppermost semiconductor patterns SP1t and SP2t can be the same as the height of the upper surface 26t of the cladding structure 26. In some embodiments, the upper surface GIt of the gate insulating layer GI surrounding the uppermost semiconductor patterns SP1t and SP2t can be the same as the upper surface 26t of the cladding structure 26.

[0058] Figure 4 It is shown Figure 2A An enlarged example of a portion of the "CU".

[0059] refer to Figure 4 The partition structure 25 may include multiple recessed regions IND. Specifically, the side surface 26S of the cladding structure 26 may have multiple recessed regions IND. The shape of the recessed regions IND is not limited to the shape shown.

[0060] The first gate electrode GE1 and the second gate electrode GE2 can fill each recessed region IND. As an example, the width INDW of each recessed region IND can be from 2 nm to 10 nm.

[0061] Since the partition structure 25 includes the recessed region IND, the area occupied by the first gate electrode GE1 and the second gate electrode GE2 can be increased, thereby further improving the channel controllability of the first gate electrode GE1 and the second gate electrode GE2.

[0062] Figure 5 It is along Figure 1 Example cross-section diagram taken from line AA′.

[0063] refer to Figure 5 The semiconductor device may include a first separator structure 25a and a second separator structure 25b. The first separator structure 25a may include a first core structure 22a and a first cladding structure 26a surrounding the first core structure 22a. The second separator structure 25b may include a second core structure 22b and a second cladding structure 26b surrounding the second core structure 22b.

[0064] The height 25aH of the first partition structure 25a can be greater than the height 25bH of the second partition structure 25b. The height 25bH of the second partition structure 25b can be determined later. Figure 14A The etching process described in the text is used for adjustment.

[0065] The first separator 25a may contact the gate cover pattern GP. The second separator 25b may be spaced apart from the gate cover pattern GP. The height of the upper surface of the gate insulating layer GI surrounding the uppermost semiconductor patterns SP1t and SP2t may be the same as the height of the upper surface of the second separator 25b. In some embodiments, the upper surface of the gate insulating layer GI surrounding the uppermost semiconductor patterns SP1t and SP2t may be the same as the upper surface of the second separator 25b.

[0066] Because the second separator structure 25b is spaced apart from the gate cover pattern GP, ​​the first gate electrode GE1 and the second gate electrode GE2 located in a portion of the semiconductor device can be connected to each other. In other words, because the heights of the first separator structure 25a and the second separator structure 25b are different, the connection and design freedom of the gate electrodes can be improved.

[0067] Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 16C and Figure 16D This is a cross-sectional view illustrating an example of a process for manufacturing semiconductor devices. Specifically, Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A and Figure 16A It is along Figure 1 The cross-sectional view taken by line AA′ in the diagram. Figure 8B , Figure 9B , Figure 12B , Figure 13B , Figure 14B and Figure 16B It is along Figure 1 The cross-sectional view taken from line BB′. Figure 6B , Figure 7B , Figure 8C , Figure 9C , Figure 10B , Figure 11B , Figure 12C , Figure 13C , Figure 14C , Figure 15B and Figure 16C It is along Figure 1 The cross-sectional view taken by line CC′. Figure 7C , Figure 8D , Figure 9D , Figure 10C , Figure 13D , Figure 14D and Figure 16D It is along Figure 1 The cross-sectional view of the line DD′.

[0068] refer to Figure 6A and Figure 6B A substrate 10 can be provided. A first active pattern AP1, a second active pattern AP2, a first semiconductor layer 82, and a second semiconductor layer 83 can be formed on the substrate 10.

[0069] Forming the first active pattern AP1, the second active pattern AP2, the first semiconductor layer 82, and the second semiconductor layer 83 may include forming a preliminary semiconductor layer on the substrate 10, forming a mask pattern on the preliminary semiconductor layer, and patterning the preliminary semiconductor layer and the substrate 10 using the mask pattern.

[0070] The substrate 10 can be patterned to form a first active pattern AP1 and a second active pattern AP2. A preliminary semiconductor layer can be patterned to form a first semiconductor layer 82 and a second semiconductor layer 83. The first semiconductor layer 82 and the second semiconductor layer 83 can be stacked alternately on the substrate 10.

[0071] Each of the first semiconductor layer 82 and the second semiconductor layer 83 may include a semiconductor material. The first semiconductor layer 82 and the second semiconductor layer 83 may include different materials. As an example, the first semiconductor layer 82 may include silicon germanium (SiGe), while the second semiconductor layer 83 may include silicon (Si).

[0072] Subsequently, a device isolation layer 12 can be formed between the first active pattern AP1 and the second active pattern AP2. A first insulating layer IL1 can be formed on the device isolation layer 12, the first semiconductor layer 82, and the second semiconductor layer 83.

[0073] refer to Figures 7A to 7C A dummy layer POL can be formed on the first active pattern AP1, the second active pattern AP2, and the device isolation layer 12. The dummy layer POL can extend in the second direction D2. The dummy layer POL can include, for example, polysilicon.

[0074] Then, a hard mask layer HM can be formed on the dummy layer POL. The hard mask layer HM can extend in the second direction D2.

[0075] refer to Figures 8A to 8D Patterning processes can be performed on the dummy layer POL and the hard mask layer HM. As a result of performing the patterning process, a dummy pattern POLP and a first hard mask pattern HMP1 can be formed from the dummy layer POL and the hard mask layer HM, respectively. A portion of the first semiconductor layer 82 and the second semiconductor layer 83 on the first active pattern AP1 and the second active pattern AP2 can be removed.

[0076] A first source / drain pattern SD1 and a second source / drain pattern SD2 can be formed in the region where the first semiconductor layer 82 and the second semiconductor layer 83 have been removed. Forming the first source / drain pattern SD1 and the second source / drain pattern SD2 may include performing an epitaxial growth process using active patterns AP1 and AP2 as seed layers.

[0077] refer to Figures 9A to 9DThe first hard mask pattern HMP1 can be removed. An interlayer insulating layer 13 can be formed on the first active pattern AP1, the second active pattern AP2, and the device isolation layer 12. The interlayer insulating layer 13 can cover the first source / drain pattern SD1 and the second source / drain pattern SD2. The interlayer insulating layer 13 can be formed between dummy patterns POLP. The dummy patterns POLP can then be removed. At this time, a portion of the first insulating layer IL1 exposed from the interlayer insulating layer 13 can be removed.

[0078] refer to Figures 10A to 10C The first insulating layer IL1 covering the first semiconductor layer 82 and the second semiconductor layer 83 can be removed. Then the first semiconductor layer 82 can be selectively removed.

[0079] The etching process that selectively removes the first semiconductor layer 82 can remove only the first semiconductor layer 82 while retaining the second semiconductor layer 83. The etching process for removing the first semiconductor layer 82 can, for example, have a higher etching rate for silicon-germanium. Due to the etching process, a first channel structure CH1 including first semiconductor patterns SP1 and SP1t and a second channel structure CH2 including second semiconductor patterns SP2 and SP2t can be formed from the second semiconductor layer 83. The first channel structure CH1 and the second channel structure CH2 can be spaced apart from each other in the first direction D1.

[0080] Subsequently, gate spacers GS can be formed on the uppermost semiconductor patterns SP1t and SP2t. A second insulating layer IL2 can be formed on the device isolation layer 12. The second insulating layer IL2 can cover the upper surface of the first active pattern AP1 and the upper surface of the second active pattern AP2. A gate insulating layer GI can be formed on the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The gate insulating layer GI can be formed to surround the four surfaces of each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2.

[0081] refer to Figure 11A and Figure 11B An internal gap filling layer GF can be formed on a first semiconductor pattern SP1 and a second semiconductor pattern SP2 that are adjacent to each other along a third direction D3. Forming the internal gap filling layer GF may include, for example, forming the internal gap filling layer GF on the device isolation layer 12 and patterning a portion of the internal gap filling layer GF.

[0082] refer to Figures 12A to 12C A photoresist pattern PR and a second hard mask pattern HMP2 can be formed on the device isolation layer 12. The second hard mask pattern HMP2 can be formed on the photoresist pattern PR.

[0083] Then, an etching process can be performed on the photoresist pattern PR and the second hard mask pattern HMP2. As a result of performing the etching process, multiple holes H can be formed. The holes H can extend on the third direction D3. The etching process can be performed, for example, until the upper surface of the second insulating layer IL2 is exposed.

[0084] refer to Figures 13A to 13D The second hard mask pattern HMP2 can then be removed. The preliminary core structure 22L can then fill the aperture H in a self-aligned manner. In this specification, the preliminary core structure 22L filling the aperture H can be represented in the same way as the insulating material filling the aperture H. The preliminary core structure 22L can fill between the interlayer insulating layers 13 and cover the upper surface of the photoresist pattern PR.

[0085] The preliminary core structure 22L may include, for example, an insulating material. As an example, the preliminary core structure 22L may include at least one of silicon oxide, silicon nitride, or silicon carbonitride.

[0086] refer to Figures 14A to 14D An etching process can be performed on the preliminary core structure 22L. Due to the etching process, the upper part of the preliminary core structure 22L, including the portion of the upper surface covering the photoresist pattern PR, can be removed.

[0087] At this point, the height of the upper surface of the preliminary core structure 22L can be adjusted by an etching process. For example, the upper part of the preliminary core structure 22L can be etched until the height of the upper surface of the preliminary core structure 22L is equal to or higher than the height of the uppermost semiconductor patterns SP1t and SP2t. Since the height of the upper surface of the preliminary core structure 22L is adjusted by this etching process, the heights of the first gate electrode GE1 and the second gate electrode GE2 can be adjusted. As a result of performing the etching process, the core structure 22 can be formed from the preliminary core structure 22L. Since the core structure 22 is formed after the semiconductor patterns SP1 and SP2 and the gate insulating layer GI are formed, damage to the semiconductor patterns SP1 and SP2 can be prevented.

[0088] refer to Figure 15A and Figure 15B The photoresist pattern PR can be removed. Then, a cladding structure 26 can be formed around the core structure 22 in a self-aligned manner. Forming the cladding structure 26 may include forming the cladding on the device isolation layer 12 and performing a patterning process on the cladding.

[0089] As a result of the patterning process, the remaining portion of the cladding can be removed, except for the portion formed between the first channel structure CH1 and the second channel structure CH2. The height of the upper surface of the cladding structure 26 can be the same as the height of the upper surface of the gate insulating layer GI surrounding the uppermost semiconductor patterns SP1t and SP2t.

[0090] With the formation of the cladding structure 26, a separation structure 25 comprising the core structure 22 and the cladding structure 26 can be formed. Subsequently, the internal gap-filling layer GF can be removed.

[0091] refer to Figures 16A to 16D A planarization process can be performed on the interlayer insulating layer 13. Then, a first gate electrode GE1 and a second gate electrode GE2 can be formed on the gate insulating layer GI. As an example, the first gate electrode GE1 can be formed on a first semiconductor pattern SP1. The second gate electrode GE2 can be formed on a second semiconductor pattern SP2. Forming the first gate electrode GE1 and the second gate electrode GE2 can include forming the first gate electrode GE1 and the second gate electrode GE2 until the height of the upper surface of the first gate electrode GE1 and the upper surface of the second gate electrode GE2 is equal to the height of the upper surface of the separator structure 25. That is, since the heights of the first gate electrode GE1 and the second gate electrode GE2 are formed to be equal to the height of the separator structure 25, a step difference between the two components can be prevented. A gate overlay pattern GP covering the first gate electrode GE1 and the second gate electrode GE2 can be formed.

[0092] Then, refer to again Figures 2A to 2D A semiconductor device can be completed by forming a gate contact 45 that penetrates the gate cover pattern GP and an active contact 41 that penetrates the interlayer insulating layer 13.

[0093] The semiconductor device may include a separator structure located between multiple semiconductor patterns, which separates gate electrodes positioned at a height higher than the semiconductor patterns. In this case, a portion of the side surface of the separator structure is exposed from the gate insulating layer to contact the gate electrode. Because the gate electrode is positioned closer to the separator structure than the side surface of the semiconductor patterns, the area provided for the gate electrode can be increased. Therefore, the controllability of the semiconductor pattern of the gate electrode can be further improved.

[0094] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope that may be claimed, but rather as descriptions of features characteristic of particular embodiments of a particular invention. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, in some cases, one or more features from a combination may be removed from that combination, and the combination may refer to a sub-combination or a variation of a sub-combination.

[0095] While embodiments have been described above, those skilled in the art will understand that various modifications and variations can be made without departing from the spirit and scope of this disclosure as defined in the appended claims. Therefore, the exemplary embodiments should be considered illustrative rather than restrictive in all respects, and the spirit and scope of this disclosure are indicated by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: An active pattern, wherein the active pattern is located on a substrate; A first channel structure and a second channel structure are spaced apart from each other on the active pattern. A gate electrode, wherein the gate electrode is located on the first channel structure and the second channel structure; as well as A partition structure is provided, located between the first channel structure and the second channel structure. The first channel structure includes multiple first semiconductor patterns, and the second channel structure includes multiple second semiconductor patterns. Wherein, the upper surface of the separating structure is higher than the upper surface of the uppermost semiconductor pattern among the plurality of first semiconductor patterns and the plurality of second semiconductor patterns, and The gate electrode contacts the partition structure.

2. The semiconductor device according to claim 1, wherein, The separating structure includes at least one of silicon oxide, silicon nitride, or silicon carbonitride.

3. The semiconductor device according to claim 1, wherein, The partition structure includes a core structure and a cladding structure surrounding the core structure, and The upper surface of the core structure is higher than the upper surface of the cladding structure.

4. The semiconductor device according to claim 3, wherein: The core structure has a first width in a first direction parallel to the upper surface of the substrate. The cladding structure has a second width in the first direction, and The second width is smaller than the first width.

5. The semiconductor device according to claim 4, wherein, The first width is in the range of 10 nm to 40 nm, and the second width is in the range of 2 nm to 10 nm.

6. The semiconductor device according to claim 3, wherein, The core structure includes a first part and a second part located on the first part. The second portion protrudes from the cladding structure, and The height of the second part is 10% to 45% of the height of the core structure.

7. The semiconductor device according to claim 6, wherein, The height of the second part is 5 nm to 40 nm.

8. The semiconductor device of claim 1, further comprising a source / drain pattern connected to the first channel structure and the second channel structure, and in, The separation structure is spaced apart from the source / drain pattern.

9. A semiconductor device, the semiconductor device comprising: Substrate, the substrate comprising an active pattern; A device isolation layer that defines the active pattern; A first channel structure and a second channel structure are spaced apart from each other on the active pattern. A gate electrode, wherein the gate electrode is located on the first channel structure and the second channel structure; A gate insulating layer, the gate insulating layer being located between the gate electrode and the first channel structure and between the gate electrode and the second channel structure; and A partition structure is provided, located between the first channel structure and the second channel structure. The first channel structure includes multiple first semiconductor patterns, each having four surfaces, and the second channel structure includes multiple second semiconductor patterns, each having four surfaces. Wherein, the upper surface of the separating structure is higher than the upper surface of the uppermost semiconductor pattern among the plurality of first semiconductor patterns and the plurality of second semiconductor patterns. Wherein, the gate insulating layer surrounds the four surfaces of each of the plurality of first semiconductor patterns and the plurality of second semiconductor patterns, and A portion of the side surface of the partition structure is exposed from the gate insulating layer.

10. The semiconductor device according to claim 9, wherein, A portion of the gate insulating layer contacts the separator structure, and Wherein, the portion of the gate insulating layer that contacts the separation structure overlaps with the gate electrode from a vertical viewing angle.

11. The semiconductor device according to claim 9, wherein, The partition structure includes multiple recessed areas, and The gate electrode is disposed at each of the plurality of recessed regions.

12. The semiconductor device according to claim 11, wherein, The width of each of the plurality of recessed regions is 2 nm to 10 nm.

13. The semiconductor device according to claim 9, wherein, The partition structure includes a core structure and a cladding structure surrounding the core structure, and In a horizontal view, the cladding structure is located between the gate insulating layer and the core structure, and between the gate electrode and the core structure.

14. The semiconductor device according to claim 13, wherein, The upper surface of the gate insulating layer surrounding the uppermost semiconductor pattern is the same as the upper surface of the cladding structure.

15. A semiconductor device, the semiconductor device comprising: The substrate includes a first active pattern and a second active pattern, the first active pattern and the second active pattern being defined by a device isolation layer; A first channel structure and a second channel structure, wherein the first channel structure is located on the first active pattern and the second channel structure is located on the second active pattern; Source / drain pattern, wherein the source / drain pattern is connected to the first channel structure and the second channel structure; A first gate electrode and a second gate electrode, wherein the first gate electrode is located on the first channel structure and the second gate electrode is located on the second channel structure; A gate insulating layer, the gate insulating layer being located between the first gate electrode and the first channel structure and between the second gate electrode and the second channel structure; and A partition structure is provided, located between the first channel structure and the second channel structure. The first channel structure includes multiple first semiconductor patterns, each having four surfaces, and the second channel structure includes multiple second semiconductor patterns, each having four surfaces. The gate insulating layer surrounds the four surfaces of each of the plurality of first semiconductor patterns and the plurality of second semiconductor patterns. Wherein, the upper surface of the separating structure is higher than the upper surface of the uppermost semiconductor pattern among the plurality of first semiconductor patterns and the plurality of second semiconductor patterns, and From a horizontal perspective, a portion of the side surface of the partition structure contacts the gate insulating layer, and the remaining portion of the side surface of the partition structure contacts the first gate electrode and the second gate electrode.

16. The semiconductor device according to claim 15, wherein, The partition structure includes a first partition structure and a second partition structure spaced apart from each other, and The height of the first partition structure is greater than the height of the second partition structure.

17. The semiconductor device of claim 16, further comprising a gate overlay pattern covering the first gate electrode and the second gate electrode. in, The first separator structure contacts the gate cover pattern, and The second separating structure is spaced apart from the gate cover pattern.

18. The semiconductor device according to claim 16, wherein, The upper surface of the gate insulating layer surrounding the uppermost semiconductor pattern is the same as the upper surface of the second separator structure.

19. The semiconductor device according to claim 15, wherein, The first gate electrode and the second gate electrode are closer to the separating structure than the side surfaces of the plurality of first semiconductor patterns and the side surfaces of the plurality of second semiconductor patterns.

20. The semiconductor device according to claim 15, wherein, One end of the gate insulating layer is aligned with one end of the first gate electrode and one end of the second gate electrode relative to a line extending in the vertical direction.

Images