Inverters, memory devices, and electronic devices

Abstract

Inverters, memory devices, and electronic devices are provided. An inverter includes a first field effect transistor including a first channel layer, first and second source / drain electrodes disposed on opposite sides of the first channel layer, a first gate electrode facing the first channel layer, and a first gate insulating layer between the first channel layer and the first gate electrode, and a second field effect transistor including a second channel layer, third and fourth source / drain electrodes disposed on opposite sides of the second channel layer, a second gate electrode facing the second channel layer, and a second gate insulating layer between the second channel layer and the second gate electrode. The first channel layer includes a p-type oxide semiconductor based on tellurium oxide, and the second channel layer includes an n-type oxide semiconductor based on indium oxide.

Description

Technical Field

[0001] The exemplary embodiments of this disclosure relate to inverters including oxide semiconductors, memory devices including inverters, and / or electronic devices including memory devices, and more specifically, to inverters including n-type oxide semiconductors and p-type oxide semiconductors, memory devices including inverters, and / or electronic devices including memory devices. Background Technology

[0002] Oxide-semiconductor (OSB) transistors using metal oxides as the semiconductor channel layer offer various advantages, including transparency, relatively low-temperature processability, relatively high electron field-effect mobility, and relatively low leakage current. However, in the case of typical OSBs, the valence band maximum (VBM) is composed of the 2p orbitals of oxygen ions and is located very deep from the vacuum level due to the characteristics of the electronic structure, thus the hole field-effect mobility can be relatively low. Furthermore, p-type doping can be difficult in typical OSBs. Therefore, the application of OSB transistors may be limited in devices using relatively high-performance p-type semiconductor materials, such as static random-access memory (SRAM). Summary of the Invention

[0003] Some example implementations provide inverters that include n-type oxide semiconductors and p-type oxide semiconductors.

[0004] In addition, some example implementations provide memory devices including n-type oxide semiconductors and p-type oxide semiconductors.

[0005] In addition, some example implementations provide electronic devices that include memory devices.

[0006] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practicing the exemplary embodiments presented in this disclosure.

[0007] According to an exemplary embodiment of this disclosure, an inverter includes: a first field-effect transistor including a first channel layer, a first source / drain electrode and a second source / drain electrode spaced apart from each other on the opposite side of the first channel layer, a first gate electrode facing the first channel layer, and a first gate insulating layer between the first channel layer and the first gate electrode; and a second field-effect transistor including a second channel layer, a third source / drain electrode and a fourth source / drain electrode spaced apart from each other on the opposite side of the second channel layer, a second gate electrode facing the second channel layer, and a second gate insulating layer between the second channel layer and the second gate electrode, wherein the second source / drain electrode and the third source / drain electrode are electrically connected to each other, the first channel layer includes a p-type oxide semiconductor based on tellurium oxide, and the second channel layer includes an n-type oxide semiconductor based on indium oxide.

[0008] For example, p-type oxide semiconductors may include telluride oxides doped with at least one element selected from selenium (Se), germanium (Ge), and sulfur (S).

[0009] For example, p-type oxide semiconductors may include Te a X b O, wherein X may include at least one of selenium (Se), germanium (Ge) and sulfur (S), a≥0.7 and b≤0.3.

[0010] For example, p-type oxide semiconductors may include In a Te b O c , where a+b=1, a≤0.5, and b≥0.5.

[0011] For example, In a Te b O c The value of c in the equation can be less than the stoichiometric value.

[0012] For example, In a Te b O c The oxygen vacancy concentration in the medium can be from about 5% to about 80%.

[0013] For example, an n-type oxide semiconductor may include indium oxide doped with at least one element selected from gallium (Ga), zinc (Zn), tin (Sn), and tungsten (W).

[0014] For example, n-type oxide semiconductors may include In a Ga b Zn c O, where a=b=c.

[0015] In one embodiment, the inverter may further include a substrate, wherein a first channel layer, a first source / drain electrode and a second source / drain electrode may be on the substrate, a first gate insulating layer may be on the first channel layer, and a first gate electrode may be on the first gate insulating layer.

[0016] The second gate electrode can be on the substrate, the second gate insulating layer can be on the substrate and cover the second gate electrode, and the second channel layer, the third source / drain electrode and the fourth source / drain electrode can be on the second gate insulating layer.

[0017] The upper surface of the second source / drain electrode may include an exposed upper surface of the second source / drain electrode, which is partially exposed between the first gate insulating layer and the second gate insulating layer, and the third source / drain electrode may extend over the exposed upper surface of the second source / drain electrode.

[0018] In an example embodiment, the inverter may further include a substrate, wherein a first gate electrode may be on the substrate, a first gate insulating layer may be on the substrate and cover the first gate electrode, and a first channel layer, a first source / drain electrode, and a second source / drain electrode may be on the first gate insulating layer.

[0019] The second channel layer, the third source / drain electrode, and the fourth source / drain electrode can be on the substrate, the second gate insulating layer can be on the second channel layer, and the second gate electrode can be on the second gate insulating layer.

[0020] The upper surface of the third source / drain electrode may include an exposed upper surface of the third source / drain electrode, which is partially exposed between the first gate insulating layer and the second gate insulating layer, and the second source / drain electrode may extend over the exposed upper surface of the third source / drain electrode.

[0021] The first gate insulating layer and the second gate insulating layer can form a single common gate insulating layer, and the first gate electrode and the second gate electrode can form a single common gate electrode.

[0022] In an example embodiment, the inverter may further include a substrate, wherein a first channel layer, a first source / drain electrode, and a second source / drain electrode may be on the substrate, a single common gate insulating layer may be on the first channel layer, a single common gate electrode may be buried in the single common gate insulating layer, a second channel layer, a third source / drain electrode, and a fourth source / drain electrode may be on the single common gate insulating layer, and the third source / drain electrode may extend along the sidewall of the single common gate insulating layer to the surface of the second source / drain electrode.

[0023] In another example embodiment, the inverter may further include a substrate, wherein a second channel layer, a third source / drain electrode, and a fourth source / drain electrode may be on the substrate, a single common gate insulating layer may be on the second channel layer, a single common gate electrode may be buried in the single common gate insulating layer, a first channel layer, a first source / drain electrode, and a second source / drain electrode may be on the single common gate insulating layer, and the second source / drain electrode may extend along the sidewall of the single common gate insulating layer to the surface of the third source / drain electrode.

[0024] According to an exemplary embodiment of this disclosure, a memory device includes: a first inverter and a second inverter, cyclically connected in series to form a ring oscillator; a first access transistor configured to enable or block access to the first inverter; and a second access transistor configured to enable or block access to the second inverter, wherein the first inverter includes a first pull-up transistor and a first pull-down transistor, the second inverter includes a second pull-up transistor and a second pull-down transistor, each of the first pull-up transistor and the second pull-up transistor includes a first channel layer, the first channel layer including a p-type oxide semiconductor based on tellurium oxide, and each of the first access transistor, the second access transistor, the first pull-down transistor and the second pull-down transistor includes a second channel layer, the second channel layer including an n-type oxide semiconductor based on indium oxide.

[0025] For example, p-type oxide semiconductors may include Te a X b O or In c Te d O e X may include at least one of selenium (Se), germanium (Ge), and sulfur (S), in Te a X b In O, a≥0.7 and b≤0.3, c+d=1, c≤0.5, d≥0.5, and e can be less than the stoichiometric value, and the n-type oxide semiconductor can include indium oxide doped with at least one element selected from gallium (Ga), zinc (Zn), tin (Sn), and tungsten (W).

[0026] According to an exemplary embodiment of this disclosure, an electronic device includes a main memory, an auxiliary storage device, a central processing unit (CPU), and an input / output device. The CPU includes a cache memory, an arithmetic logic unit, and a control unit. The cache memory includes: a first inverter and a second inverter, cyclically connected in series to form a ring oscillator; a first access transistor configured to enable or block access to the first inverter; and a second access transistor configured to enable or block access to the second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, and the second inverter includes a second pull-up transistor and a second pull-down transistor. Each of the first pull-up transistor and the second pull-up transistor includes a first channel layer comprising a p-type oxide semiconductor based on tellurium oxide. Furthermore, each of the first access transistor, the second access transistor, the first pull-down transistor, and the second pull-down transistor includes a second channel layer comprising an n-type oxide semiconductor based on indium oxide. Attached Figure Description

[0027] The above and other aspects, features and / or advantages of certain exemplary embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 A circuit diagram of an inverter according to an example embodiment is shown schematically;

[0029] Figure 2 This is a graph illustrating an example of the current-voltage characteristics of a p-type field-effect transistor;

[0030] Figure 3 This is a graph illustrating an example of the current-voltage characteristics of an n-type field-effect transistor;

[0031] Figure 4A This is a graph showing an example of the density of states (DOS) for energy of indium telluride oxide with a composition of Te:In=3:1;

[0032] Figure 4B This is a graph showing an example of the DOS for energy of indium telluride oxide with a composition of Te:In=1:3;

[0033] Figure 5A This is a graph showing an example of the DOS for energy when the composition is Te:In=1:1 and the oxygen content is 20% lower than the stoichiometric value;

[0034] Figure 5B This is a graph showing an example of the DOS for energy when the composition is Te:In=1:1 and the oxygen content is 10% lower than the stoichiometric value;

[0035] Figure 5CThis is a graph showing an example of the DOS for energy when the composition is Te:In=1:1 and the oxygen content has a stoichiometric value.

[0036] Figure 6 It is shown Figure 1 The diagram shows a cross-sectional view of a schematic structure of an inverter.

[0037] Figure 7 This is a cross-sectional view showing a schematic structure of an inverter according to another exemplary embodiment.

[0038] Figure 8 This is a cross-sectional view showing a schematic structure of an inverter according to another exemplary embodiment.

[0039] Figure 9 This is a cross-sectional view showing a schematic structure of an inverter according to another exemplary embodiment.

[0040] Figure 10 A circuit diagram of a memory device according to an example embodiment is shown schematically;

[0041] Figure 11 It is shown Figure 10 A schematic cross-sectional view of the structure of the first inverter of the shown memory device;

[0042] Figure 12 It is shown Figure 10 A cross-sectional view of a schematic structure of the first inverter and the first access transistor of the shown memory device; and

[0043] Figure 13 This is a conceptual diagram illustrating a device architecture applicable to electronic devices according to an example implementation. Detailed Implementation

[0044] Reference will now be made in detail to exemplary embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always denote the same elements. In this respect, these exemplary embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the exemplary embodiments are described below only by reference to the accompanying drawings to explain various aspects. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “one of…”, “one or more of…”, “any one of…”, “at least one of…”, “at least one of…”, and “selected from at least one of…”, when preceding a list of elements, modify the entire list of elements without modifying any individual elements in that list. For example, expressions such as “at least one of A, B, and C” or “selected from at least one of the group consisting of A, B, and C” can be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C, such as A, B, and C, A and B, B and C, and A and C.

[0045] Although the terms “identical,” “equal,” or “same” are used in the description of the example implementations, it should be understood that some imprecisions may exist. Therefore, when one element is referred to as being identical to another element, it should be understood that the one element is identical to the other element within a desired range of manufacturing or operational tolerances (e.g., ±10%).

[0046] When the terms “about,” “substantially,” or “approximately” are used in conjunction with numerical values ​​in this specification, they mean that the relevant numerical value includes manufacturing or operational tolerances (e.g., ±10%) near the stated numerical value. Furthermore, when the terms “about,” “substantially,” or “approximately” are used in conjunction with geometry, they mean that precision of the geometry is not required, but the shape is within the scope of this disclosure. Moreover, regardless of whether a numerical value or shape is modified with “about” or “substantially,” it should be understood that such numerical values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) near the stated numerical value or shape.

[0047] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion without departing from the teachings of the exemplary embodiments.

[0048] In the following description, an inverter including an oxide semiconductor, a memory device including an inverter, and an electronic device including a memory device are described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same elements, and the dimensions of each element may be exaggerated for clarity and ease of explanation. Furthermore, some of the exemplary embodiments described herein are merely examples, and various modifications can be made to these exemplary embodiments.

[0049] In the following text, the terms “above,” “up,” “below,” or “under” will include not only those that are directly above, below, to the left, or to the right in a contact manner, but also those that are located above, below, to the left, or to the right in a non-contact manner. Unless the context clearly indicates otherwise, the singular form used herein is intended to include the plural form as well. It will be understood that the terms “comprising,” “including,” or “having” as used herein specify the presence of the stated element, but do not exclude the presence or addition of one or more other elements.

[0050] The use of the term "the" and similar indicator words can correspond to both the singular and plural. The operations constituting a method can be performed in any suitable order unless otherwise stated herein or clearly contradicted by the context, and are not necessarily limited to the order stated.

[0051] Furthermore, terms such as “unit” and “module” described in the specification mean a unit that performs at least one function or operation and can be implemented as hardware, software or a combination of hardware and software.

[0052] The connecting lines or connecting components shown in the accompanying drawings are intended to illustrate exemplary functional relationships and / or physical or logical connections between various components. It should be noted that many alternative or additional functional relationships, physical connections, or logical connections may exist in actual devices.

[0053] All illustrative or explanatory terms used in the exemplary embodiments described below are merely for the purpose of describing the technical ideas in detail, and the scope of this disclosure is not limited by the illustrative or explanatory terms unless they are limited by the claims.

[0054] Figure 1 A circuit diagram of an inverter 100 according to an example embodiment is shown schematically. The inverter 100 may be, for example, a complementary metal-oxide-semiconductor (CMOS) inverter. (Refer to...) Figure 1The inverter 100 may include a p-type field-effect transistor 110 and an n-type field-effect transistor 120 connected between a power supply terminal VDD and a ground terminal GND. For example, one source / drain electrode of the p-type field-effect transistor 110 may be electrically connected to the power supply terminal VDD, one source / drain electrode of the n-type field-effect transistor 120 may be electrically connected to the ground terminal GND, and the other source / drain electrodes of the p-type field-effect transistor 110 and the other source / drain electrodes of the n-type field-effect transistor 120 may be electrically connected to each other. The gates of the p-type field-effect transistor 110 and the n-type field-effect transistor 120 may be electrically connected to a common input terminal. Additionally, the mutually connected source / drain electrodes of the p-type field-effect transistor 110 and the n-type field-effect transistor 120 may be electrically connected to a common output terminal.

[0055] The p-type field-effect transistor 110 is a p-type metal-oxide-semiconductor field-effect transistor (PMOS FET) and has a negative threshold voltage below 0 V. The n-type field-effect transistor 120 is an n-type metal-oxide-semiconductor field-effect transistor (NMOS FET) and has a positive threshold voltage above 0 V. Therefore, when a voltage above the positive threshold voltage (e.g., signal "1") is applied to the input terminal, the p-type field-effect transistor 110 can be turned off and the n-type field-effect transistor 120 can be turned on, so the output terminal can be electrically connected to the ground terminal GND. In other words, when signal "1" is input to the input terminal, signal "0" can be output from the output terminal. When a voltage below the negative threshold voltage (e.g., signal "0") is applied to the input terminal, the p-type field-effect transistor 110 can be turned on and the n-type field-effect transistor 120 can be turned off, so the output terminal can be electrically connected to the power supply terminal VDD. In other words, when signal "0" is input to the input terminal, signal "1" can be output from the output terminal.

[0056] According to an example embodiment, each of the p-type field-effect transistor 110 and the n-type field-effect transistor 120 may include an oxide semiconductor material as a channel layer. For example, the channel layer of the p-type field-effect transistor 110 may include a p-type oxide semiconductor material, and the channel layer of the n-type field-effect transistor 120 may include an n-type oxide semiconductor material.

[0057] For example, p-type oxide semiconductor materials may include tellurium oxide (TeO) based materials. x p-type oxide semiconductors can consist solely of tellurium oxide, or they can include tellurium oxide further doped with at least one metallic or nonmetallic element selected from selenium (Se), germanium (Ge), and sulfur (S). For example, p-type oxide semiconductor materials may include Te... a X bO, where X may include at least one of selenium (Se), germanium (Ge), and sulfur (S). In p-type oxide semiconductor materials, tellurium (Te) may be included in a content of about 70 at% or greater, and other metallic or nonmetallic elements may be included in a content of about 30 at% or less, among all elements except oxygen. For example, in Te... a X b In O, a ≥ 0.7 and b ≤ 0.3.

[0058] For example, n-type oxide semiconductor materials may include indium oxide (InOx)-based oxide semiconductors. n-type oxide semiconductor materials may consist only of indium oxide, or may include indium oxide further doped with at least one metal element selected from gallium (Ga), zinc (Zn), tin (Sn), and tungsten (W). For example, n-type oxide semiconductor materials may include In... a Ga b Zn c O. In a Ga b Zn c In O, a, b, and c can be equal to each other. In other words, n-type oxide semiconductor materials can include indium oxide (InOx)-based oxide semiconductors having components in which the proportions of indium (In), gallium (Ga), and zinc (Zn) are substantially equal to each other. For example, in In a Ga b Zn c In O, a=b=c=0.33.

[0059] Compared to other oxide semiconductors, such as those based on tin oxide (SnO), tellurium oxide-based oxide semiconductors can have relatively high hole field-effect mobilities. For example, the hole field-effect mobility of tellurium oxide-based oxide semiconductors can be substantially similar to that of indium oxide-based oxide semiconductors. Therefore, the p-type field-effect transistor 110 can have field-effect mobilities and on / off current ratios substantially similar to those of the n-type field-effect transistor 120. Furthermore, because the p-type field-effect transistor 110 and the n-type field-effect transistor 120 have similar performance, the channels of the p-type field-effect transistor 110 and the n-type field-effect transistor 120 can have substantially the same dimensions.

[0060] Therefore, the inverter 100 according to the example embodiment can have relatively high gain characteristics. In addition, since both the p-type field-effect transistor 110 and the n-type field-effect transistor 120 of the inverter 100 use oxide semiconductor as the channel layer material, leakage current can be reduced, thereby reducing the power consumption of the inverter 100.

[0061] Figure 2 This is a graph illustrating an example of the current-voltage characteristics of a p-type field-effect transistor 110. Figure 3 This is a graph illustrating an example of the current-voltage characteristics of an n-type field-effect transistor 120. Figure 2 The channel layer of the p-type field-effect transistor 110 includes Te a Se b O(a=0.7, b=0.3), and Figure 3 The channel layer of the n-type field-effect transistor 120 includes In a Ga b Zn c O(a, b, c = 0.33). In Figure 2 and Figure 3 In the p-type field-effect transistor 110, the on-state current is approximately 20.1 mA / mm, and in the n-type field-effect transistor 120, the on-state current is approximately 10.9 mA / mm. Furthermore, the mobility of the p-type field-effect transistor 110 is approximately 7.95 cm⁻¹. 2 The mobility of the n-type field-effect transistor 120 is approximately 9.55 cm⁻¹ / Vs. 2 / Vs. Furthermore, the channel layer of the p-type field-effect transistor 110 and the channel layer of the n-type field-effect transistor 120 each have a width of 10 μm. Therefore, when the widths of the channel layers are equal, Te... a Se b The performance of the p-type field-effect transistor 110 with an O (a=0.7, b=0.3) channel layer is substantially similar to or better than that of the n-type field-effect transistor 120.

[0062] In another example, the channel layer of the p-type field-effect transistor 110 is based on tellurium oxide (TeO2). x The oxide semiconductor can include amorphous indium telluride (In) a Te b O c In a Te b O c In this context, a + b = 1, a ≤ 0.5, b ≥ 0.5, and c can be less than the stoichiometric value. Therefore, when the channel layer of the p-type field-effect transistor 110 includes indium telluride (In... a Te b O c In some cases, the channel layer can have a stoichiometric oxygen-deficient component. For example, in a stoichiometric reaction system of In, Te, and O, when a=0.5 and b=0.5, the stoichiometric value of oxygen can be 1.75, therefore c can be less than 1.75. For example, when a=0.25 and b=0.75, the stoichiometric value of oxygen can be 1.875, therefore c can be less than 1.875.

[0063] Figure 4A This is a graph showing an example of the density of states (DOS) for energy of indium tellurium oxide with a composition of Te:In = 3:1. The oxygen content c is 1.875. Figure 4A In the diagram, curve A1 shows the DOS for the entire indium tellurium oxide, curve B1 shows the DOS for oxygen, curve C1 shows the DOS for indium, and curve D1 shows the DOS for tellurium. A region VB1 with relatively low and widespread DOS for indium, tellurium, and oxygen appears at the valence band boundary. Region VB1 indicates that indium tellurium oxide with a Te:In = 3:1 composition exhibits p-type semiconductor characteristics. In this case, tellurium-related shallow states form near the valence band maximum (VBM), thus exhibiting hole-doped p-type semiconductor characteristics.

[0064] Figure 4B This is a graph showing an example of the DOS for energy of indium telluride oxide with a Te:In ratio of 1:3. The oxygen content c is 1.625. Figure 4B In the diagram, curve A2 shows the DOS for the entire indium telluride oxide, curve B2 shows the DOS for oxygen, curve C2 shows the DOS for indium, and curve D2 shows the DOS for tellurium. The region VB2, where the DOS for indium, tellurium, and oxygen are relatively low, appears to be very narrow at the valence band boundary. This indicates that indium telluride oxide with a Te:In = 1:3 composition exhibits almost no p-type semiconductor characteristics.

[0065] Figure 5A This is a graph showing an example of the DOS for energy when the composition is Te:In = 1:1 and the oxygen content is 20% lower than the stoichiometric value. The oxygen deficiency relative to the stoichiometric value is defined as the oxygen vacancy concentration or oxygen loss. Figure 5A This illustrates the case where the oxygen vacancy concentration is 20% and the oxygen content c is 1.4, when the stoichiometry of oxygen is 1.75. Figure 5A In the diagram, curve A3 shows the DOS for the entire indium telluride oxide, curve B3 shows the DOS for oxygen, curve C3 shows the DOS for indium, and curve D3 shows the DOS for tellurium. A region VB3 with low and widespread DOS for tellurium, indium, and oxygen appears at the valence band boundary. Therefore, when the oxygen content is 20% less than the stoichiometric value, indium telluride oxide exhibits p-type semiconductor characteristics.

[0066] Figure 5B This is a graph showing an example of the DOS for energy when the composition is Te:In=1:1 and the oxygen content is 10% lower than the stoichiometric value. Figure 5B This illustrates the case where the oxygen vacancy concentration is 10% and the oxygen content c is 1.575 when the stoichiometry of oxygen is 1.75. Figure 5BIn the diagram, curve A4 shows the DOS for the entire indium telluride oxide, curve B4 shows the DOS for oxygen, curve C4 shows the DOS for indium, and curve D4 shows the DOS for tellurium. A region VB4 with relatively low and widely distributed DOS for tellurium, indium, and oxygen appears at the conduction band boundary. Therefore, when the oxygen content is 10% less than the stoichiometric value, indium telluride oxide exhibits p-type semiconductor characteristics.

[0067] Figure 5C This is a graph showing an example of the DOS for energy when the composition is Te:In = 1:1 and the stoichiometry of oxygen content is 1.75. Figure 5C In the diagram, curve A5 shows the DOS for the entire indium telluride oxide, curve B5 shows the DOS for oxygen, curve C5 shows the DOS for indium, and curve D5 shows the DOS for tellurium. Figure 5C In the DOS of tellurium, indium, and oxygen at the valence band boundary, they hardly exhibit p-type semiconductor characteristics.

[0068] Reference Figures 5A to 5C The channel layer may include indium telluride oxide with a stoichiometric oxygen-deficient component. Furthermore, compared to 10%, a 20% oxygen vacancy concentration exhibits relatively strong p-type semiconductor characteristics. Therefore, as the oxygen vacancy concentration increases, the p-type semiconductor characteristics become more pronounced. For example, the oxygen vacancy concentration can be 5% to 80%, 10% to 70%, or 10% to 60%. As described above, the channel layer of the p-type field-effect transistor 110 may include indium telluride oxide (In... a Te b O c (a + b = 1, a ≤ 0.5, b ≥ 0.5, and c can be less than the stoichiometric value. For example, c < 1.875, c < 1.8, or c < 1.75.)

[0069] Figure 6 It is shown Figure 1 The diagram shows a schematic cross-sectional view of the inverter 100. The p-type field-effect transistor 110 and the n-type field-effect transistor 120 of the inverter 100 can be horizontally adjacent to each other on a single substrate 101. The inverter 100 can be a planar inverter.

[0070] Reference Figure 6The p-type field-effect transistor 110 (or the first field-effect transistor) may include: a first channel layer 111 disposed on a substrate 101; a first source / drain electrode 112 disposed on the substrate 101 and electrically connected to a first side surface of the first channel layer 111; a second source / drain electrode 113 disposed on the substrate 101 and electrically connected to a second side surface of the first channel layer 111 opposite to the first side surface in a horizontal direction (e.g., a first direction) parallel to the upper surface of the substrate 101; a first gate insulating layer 114 configured to cover the first source / drain electrode 112, the first channel layer 111 and the second source / drain electrode 113; and a first gate electrode 115 disposed on the first gate insulating layer 114 facing the first channel layer 111 in a direction perpendicular to the upper surface of the substrate 101 (e.g., a second direction). The first source / drain electrode 112 and the second source / drain electrode 113 may be disposed on the substrate 101 and spaced apart from each other on opposite sides of the first channel layer 111 in a first direction. The first channel layer 111 may be disposed between the first source / drain electrode 112 and the second source / drain electrode 113. The first gate insulating layer 114 may be disposed between the first channel layer 111 and the first gate electrode 115.

[0071] As described above, the first channel layer 111 may comprise a p-type oxide semiconductor material. The first channel layer 111 may comprise, for example, amorphous tellurium oxide (TeO) based material. x The first channel layer 111 may be an oxide semiconductor. In an example, the oxide semiconductor material of the first channel layer 111 may include tellurium oxide doped with at least one metallic or nonmetallic element selected from selenium (Se), germanium (Ge), and sulfur (S). For example, the first channel layer 111 may include Te a X b O, where X may include at least one of selenium (Se), germanium (Ge), and sulfur (S), a ≥ 0.7, b ≤ 0.3. In another example, the first channel layer 111 may include amorphous indium telluride (In... a Te b O c ), where a+b=1, a≤0.5, b≥0.5, and c can be less than the stoichiometric value.

[0072] The n-type field-effect transistor 120 (or the second field-effect transistor) may include a second gate electrode 125 disposed on a substrate 101, a second gate insulating layer 124 disposed on the second gate insulating layer 124 facing the second gate electrode 125 in a second direction, a third source / drain electrode 122 disposed on the second gate insulating layer 124 and electrically connected to a first side surface of the second channel layer 121, and a fourth source / drain electrode 123 disposed on the second gate insulating layer 124 and electrically connected to a second side surface of the second channel layer 121 opposite to the first side surface in a first direction. The third source / drain electrode 122 and the fourth source / drain electrode 123 may be disposed on the second gate insulating layer 124 and spaced apart from each other on opposite sides of the second channel layer 121 in the first direction. The second channel layer 121 may be disposed between the third source / drain electrode 122 and the fourth source / drain electrode 123. The second gate insulating layer 124 may be disposed between the second channel layer 121 and the second gate electrode 125.

[0073] The second gate insulating layer 124 of the n-type field-effect transistor 120 may extend in a first direction to contact the side surface of the second source / drain electrode 113 of the p-type field-effect transistor 110. The upper surface of the second source / drain electrode 113 of the p-type field-effect transistor 110 may be at least partially exposed between the first gate insulating layer 114 of the p-type field-effect transistor 110 and the second gate insulating layer 124 of the n-type field-effect transistor 120. The third source / drain electrode 122 of the n-type field-effect transistor 120 may extend over the exposed upper surface of the second source / drain electrode 113 of the p-type field-effect transistor 110. Therefore, the second source / drain electrode 113 of the p-type field-effect transistor 110 and the third source / drain electrode 122 of the n-type field-effect transistor 120 may be electrically connected to each other.

[0074] exist Figure 6 In the inverter 100 shown, the first source / drain 112 of the p-type field-effect transistor 110 can be electrically connected to the power supply terminal VDD, and the fourth source / drain 123 of the n-type field-effect transistor 120 can be connected to the ground terminal GND. Additionally, the first gate electrode 115 of the p-type field-effect transistor 110 and the second gate electrode 125 of the n-type field-effect transistor 120 can be electrically connected to the input terminal, and the second source / drain electrode 113 of the p-type field-effect transistor 110 and the third source / drain electrode 122 of the n-type field-effect transistor 120 can be electrically connected to the output terminal.

[0075] The second channel layer 121 of the n-type field-effect transistor 120 may include an n-type oxide semiconductor material. The second channel layer 121 may include, for example, an amorphous indium oxide (InO) based material. x The second channel layer 121 may be an oxide semiconductor. In an example, the oxide semiconductor material of the second channel layer 121 may include indium oxide doped with at least one metal element selected from gallium (Ga), zinc (Zn), tin (Sn), and tungsten (W). For example, the second channel layer 121 may include In a Ga b Zn c O (a=b=c).

[0076] Figure 7 This is a cross-sectional view showing a schematic structure of an inverter 100a according to another exemplary embodiment. Although Figure 6 A p-type field-effect transistor 110 with a top-gate structure and an n-type field-effect transistor 120 with a bottom-gate structure are shown, but this disclosure is not limited thereto. For example, Figure 7 The inverter 100a shown may include a p-type field-effect transistor 110 with a bottom gate structure and an n-type field-effect transistor 120 with a top gate structure.

[0077] Reference Figure 7 The p-type field-effect transistor 110 may include a first gate electrode 115 disposed on a substrate 101, a first gate insulating layer 114 disposed on the first gate insulating layer 114 and facing the first gate electrode 115 in a second direction, a first source / drain electrode 112 disposed on the first gate insulating layer 114 and electrically connected to a first side surface of the first channel layer 111, and a second source / drain electrode 113 disposed on the first gate insulating layer 114 and electrically connected to a second side surface of the first channel layer 111 opposite to the first side surface in a first direction. The first source / drain electrode 112 and the second source / drain electrode 113 may be disposed on the first gate insulating layer 114 and spaced apart from each other on opposite sides of the first channel layer 111 in the first direction.

[0078] The n-type field-effect transistor 120 may include: a second channel layer 121 disposed on a substrate 101; a third source / drain electrode 122 disposed on the substrate 101 and electrically connected to a first side surface of the second channel layer 121; a fourth source / drain electrode 123 disposed on the substrate 101 and electrically connected to a second side surface of the second channel layer 121 opposite to the first side surface in a first direction; a second gate insulating layer 124 configured to cover the third source / drain electrode 122, the second channel layer 121, and the fourth source / drain electrode 123; and a second gate electrode 125 disposed on the second gate insulating layer 124 to face the second channel layer 121 in a second direction. The third source / drain electrode 122 and the fourth source / drain electrode 123 may be disposed on the substrate 101 and spaced apart from each other on opposite sides of the second channel layer 121 in the first direction.

[0079] The first gate insulating layer 114 of the p-type field-effect transistor 110 may extend in a first direction to contact the side surface of the third source / drain electrode 122 of the n-type field-effect transistor 120. The upper surface of the third source / drain electrode 122 of the n-type field-effect transistor 120 may be at least partially exposed between the first gate insulating layer 114 of the p-type field-effect transistor 110 and the second gate insulating layer 124 of the n-type field-effect transistor 120. The second source / drain electrode 113 of the p-type field-effect transistor 110 may extend over the exposed upper surface of the third source / drain electrode 122 of the n-type field-effect transistor 120. In this way, the second source / drain electrode 113 of the p-type field-effect transistor 110 and the third source / drain electrode 122 of the n-type field-effect transistor 120 may be electrically connected to each other.

[0080] Figure 8 This is a cross-sectional view showing a schematic structure of an inverter 100b according to another exemplary embodiment. Although referenced... Figure 6 and Figure 7 The structure of p-type field-effect transistor 110 and n-type field-effect transistor 120 disposed in a planar form on substrate 101 is described, but p-type field-effect transistor 110 and n-type field-effect transistor 120 can be disposed in a stacked form. (Refer to...) Figure 8 The inverter 100b may include a p-type field-effect transistor 110 disposed on a substrate 101 and an n-type field-effect transistor 120 stacked on the p-type field-effect transistor 110.

[0081] For example, inverter 100b may include: a first channel layer 111 disposed on substrate 101; a first source / drain electrode 112 disposed on substrate 101 and electrically connected to a first side surface of the first channel layer 111; a second source / drain electrode 113 disposed on substrate 101 and electrically connected to a second side surface of the first channel layer 111 opposite to the first side surface in a first direction; a common gate insulating layer 134 configured to cover the first source / drain electrode 112, the first channel layer 111, and the second source / drain electrode 113; and a common gate insulating layer 134. A third source / drain electrode 122 is disposed within the common gate insulating layer 134 and faces the first channel layer 111 in a second direction; a second channel layer 121 is disposed on the common gate insulating layer 134 and faces the common gate electrode 135 in a second direction; a third source / drain electrode 122 is disposed on the common gate insulating layer 134 and electrically connected to a first side surface of the second channel layer 121; and a fourth source / drain electrode 123 is disposed on the common gate insulating layer 134 and electrically connected to a second side surface of the second channel layer 121 opposite to the first side surface in a first direction.

[0082] The p-type field-effect transistor 110 may include a first channel layer 111, a first source / drain electrode 112, a second source / drain electrode 113, a common gate insulating layer 134, and a common gate electrode 135. The n-type field-effect transistor 120 may include a second channel layer 121, a third source / drain electrode 122, a fourth source / drain electrode 123, a common gate insulating layer 134, and a common gate electrode 135. The common gate insulating layer 134 may be a gate insulating layer shared by the p-type field-effect transistor 110 and the n-type field-effect transistor 120. In other words, the first gate insulating layer of the p-type field-effect transistor 110 and the second gate insulating layer of the n-type field-effect transistor 120 may be formed as or constitute a common gate insulating layer 134. The common gate electrode 135 may be a gate electrode shared by the p-type field-effect transistor 110 and the n-type field-effect transistor 120. In other words, the first gate electrode of the p-type field-effect transistor 110 and the second gate electrode of the n-type field-effect transistor 120 can be formed as or constitute a common gate electrode 135. In this case, the common gate electrode 135 can be electrically connected to the input terminal of the inverter 100b. The common gate insulating layer 134 can be configured to surround the upper surface, lower surface, first side surface, and second side surface of the common gate electrode 135. Therefore, the common gate electrode 135 can be buried in the common gate insulating layer 134.

[0083] The upper surface or sidewall of the second source / drain electrode 113 of the p-type field-effect transistor 110 may be at least partially exposed so as not to be covered by the common gate insulating layer 134. The third source / drain electrode 122 of the n-type field-effect transistor 120 may extend along the sidewall of the common gate insulating layer 134 to the exposed surface of the second source / drain electrode 113 of the p-type field-effect transistor 110. Therefore, the second source / drain electrode 113 of the p-type field-effect transistor 110 and the third source / drain electrode 122 of the n-type field-effect transistor 120 may be electrically connected to each other.

[0084] According to the above-described exemplary embodiment, the p-type field-effect transistor 110 and the n-type field-effect transistor 120 can be formed in a vertically stacked structure, thereby increasing the integration density of the entire circuit, including the inverter 100b. Furthermore, the stacked structure can further reduce leakage current.

[0085] Figure 9 This is a cross-sectional view showing a schematic structure of an inverter 100c according to another exemplary embodiment. Although reference has been made to... Figure 8 The description describes an n-type field-effect transistor 120 stacked on top of a p-type field-effect transistor 110, but this disclosure is not limited thereto. See also... Figure 9 The inverter 100c may include an n-type field-effect transistor 120 disposed on a substrate 101 and a p-type field-effect transistor 110 stacked on the n-type field-effect transistor 120.

[0086] Inverter 100c may include: a second channel layer 121 disposed on substrate 101; a third source / drain electrode 122 disposed on substrate 101 and electrically connected to a first side surface of the second channel layer 121; a fourth source / drain electrode 123 disposed on substrate 101 and electrically connected to a second side surface of the second channel layer 121 opposite to the first side surface in a first direction; a common gate insulating layer 134 configured to cover the third source / drain electrode 122, the second channel layer 121, and the fourth source / drain electrode 123; and a common gate electrode 1 35, disposed within the common gate insulating layer 134 to face the second channel layer 121 in the second direction; a first channel layer 111, disposed on the common gate insulating layer 134 to face the common gate electrode 135 in the second direction; a first source / drain electrode 112, disposed on the common gate insulating layer 134 and electrically connected to a first side surface of the first channel layer 111; and a second source / drain electrode 113, disposed on the common gate insulating layer 134 and electrically connected to a second side surface of the first channel layer 111 opposite to the first side surface in the first direction.

[0087] The upper surface or sidewall of the third source / drain electrode 122 of the n-type field-effect transistor 120 may be at least partially exposed so as not to be covered by the common gate insulating layer 134. The second source / drain electrode 113 of the p-type field-effect transistor 110 may extend along the sidewall of the common gate insulating layer 134 to the exposed surface of the third source / drain electrode 122 of the n-type field-effect transistor 120.

[0088] The inverter according to the embodiments can be applied to semiconductor devices and electronic devices, such as memory devices. Figure 10 A circuit diagram of a memory device 200 according to an example embodiment is shown schematically. Figure 10 The memory device 200 shown may be, for example, static random access memory (SRAM). The memory device 200 may include a plurality of memory cells arranged in a two-dimensional manner. Figure 10 An example of the circuit configuration of the memory cells of the memory device 200 is shown.

[0089] Reference Figure 10 The memory cell of the memory device 200 may include six transistors. For example, the memory cell of the memory device 200 may include a first access transistor XT1, a second access transistor XT2, a first pull-up transistor PUT1, a second pull-up transistor PUT2, a first pull-down transistor PDT1, and a second pull-down transistor PDT2.

[0090] The first pull-up transistor PUT1 and the second pull-up transistor PUT2 can each be a p-type field-effect transistor (e.g., a PMOS FET), and the first access transistor XT1, the second access transistor XT2, the first pull-down transistor PDT1, and the second pull-down transistor PDT2 can each be an n-type field-effect transistor (e.g., an NMOS FET). The first pull-up transistor PUT1 and the first pull-down transistor PDT1 can form a first inverter INV1 and can be used as a storage element. Additionally, the second pull-up transistor PUT2 and the second pull-down transistor PDT2 can form a second inverter INV2 and can be used as a storage element. The first pull-up transistor PUT1 and the second pull-up transistor PUT2 can be electrically connected to the power supply terminal VDD, and the first pull-down transistor PDT1 and the second pull-down transistor PDT2 can be electrically connected to the ground terminal GND.

[0091] The first inverter INV1 and the second inverter INV2 can be connected in series in a loop to form a ring oscillator. For example, the output terminal of the first inverter INV1 can be electrically connected to the input terminal of the second inverter INV2, and the output terminal of the second inverter INV2 can be electrically connected to the input terminal of the first inverter INV1. The signal input to the first inverter INV1 and the second inverter INV2 can be stored in the ring oscillator while circulating through it. Therefore, the first inverter INV1 and the second inverter INV2 can operate together as a storage element.

[0092] The first access transistor XT1 and the second access transistor XT2 can allow access to the first inverter INV1 and the second inverter INV2, which are storage elements, during data read and write operations, and can block access to the first inverter INV1 and the second inverter INV2 during data hold operations. For example, the first access transistor XT1 can be provided to allow or block access to the first inverter INV1, and the second access transistor XT2 can be provided to allow or block access to the second inverter INV2.

[0093] The source of the first access transistor XT1 can be electrically connected to the first bit line BL1, and the drain of the first access transistor XT1 can be electrically connected to the gate electrode of the second pull-up transistor PUT2 and the second pull-down transistor PDT2 through the first node N1. The source of the second access transistor XT2 can be electrically connected to the second bit line BL2, and the drain of the second access transistor XT2 can be electrically connected to the gate electrode of the first pull-up transistor PUT1 and the first pull-down transistor PDT1 through the second node N2. The gates of the first access transistor XT1 and the second access transistor XT2 can be electrically connected to the word line WL.

[0094] According to an example embodiment, the first access transistor XT1, the second access transistor XT2, the first pull-up transistor PUT1, the second pull-up transistor PUT2, the first pull-down transistor PDT1, and the second pull-down transistor PDT2 of the memory device 200 may each include an oxide semiconductor material as a channel layer. For example, the channel layers of the first pull-up transistor PUT1 and the second pull-up transistor PUT2 may each include a p-type oxide semiconductor material, and the channel layers of the first access transistor XT1, the second access transistor XT2, the first pull-down transistor PDT1, and the second pull-down transistor PDT2 may each include an n-type oxide semiconductor material.

[0095] For reference Figure 1As described, p-type oxide semiconductor materials may include tellurium oxide-based oxide semiconductors and may be further doped with at least one metallic or nonmetallic element selected from selenium (Se), germanium (Ge), and sulfur (S). For example, p-type oxide semiconductor materials may include Te. a X b O, where X may include at least one of selenium (Se), germanium (Ge), and sulfur (S), a ≥ 0.7 and b ≤ 0.3. In another example, the p-type oxide semiconductor material may include amorphous indium telluride (In... a Te b O c ), where a+b=1, a≤0.5, b≥0.5, and c can be less than the stoichiometric value. Additionally, n-type oxide semiconductor materials can include those based on indium oxide (InO). x The n-type oxide semiconductor may be further doped with at least one metallic element selected from gallium (Ga), zinc (Zn), tin (Sn), and tungsten (W). For example, n-type oxide semiconductor materials may include In. a Ga b Zn c O (a=b=c). Therefore, the first pull-up transistor PUT1 and the second pull-up transistor PUT2 can each be connected to a reference. Figure 1 The p-type field-effect transistor 110 described is identical, and the first access transistor XT1, the second access transistor XT2, the first pull-down transistor PDT1, and the second pull-down transistor PDT2 can each be referenced. Figure 1 The n-type field-effect transistor 120 described is identical. Additionally, the first inverter INV1 and the second inverter INV2 can each be connected to a reference... Figure 1 The inverter 100 described is the same.

[0096] According to the example implementation, because oxide semiconductor is used as the material for the channel layer, the gain of the first inverter INV1 and the second inverter INV2 can be increased, and the performance of the memory device 200 including the first inverter INV1 and the second inverter INV2 can be improved. For example, noise can be reduced and / or leakage current can be reduced during read operations of the memory device 200, thereby reducing the power consumption of the memory device 200.

[0097] The first inverter INV1 and the second inverter INV2 can have a planar structure, such as Figure 6 The inverter 100 shown or Figure 7 The inverter 100a shown may also have a stacked structure, such as Figure 8 The inverter 100b shown or Figure 9 The inverter 100c shown is shown.

[0098] Figure 11 It is shown Figure 10 A schematic cross-sectional view of the structure of the first inverter INV1 of the memory device 200 shown. (Refer to...) Figure 11 The first pull-up transistor PUT1 and the first pull-down transistor PDT1 of the first inverter INV1 can be provided on a single substrate 201 in a planar structure.

[0099] The first pull-up transistor PUT1 may include: a first channel layer 211 disposed on a substrate 201; a first source / drain electrode 212 disposed on the substrate 201 and electrically connected to a first side surface of the first channel layer 211; a second source / drain electrode 213 disposed on the substrate 201 and electrically connected to a second side surface of the first channel layer 211 opposite to the first side surface in a first direction; a first gate insulating layer 214 configured to cover the first source / drain electrode 212, the first channel layer 211 and the second source / drain electrode 213; and a first gate electrode 215 disposed on the first gate insulating layer 214 to face the first channel layer 211 in a second direction.

[0100] The first pull-down transistor PDT1 may include: a second gate electrode 225 disposed on a substrate 201; a second gate insulating layer 224 disposed on the substrate 201 and the second gate electrode 225; a second channel layer 221 disposed on the second gate insulating layer 224 and facing the second gate electrode 225 in a second direction; a third source / drain electrode 222 disposed on the second gate insulating layer 224 and electrically connected to a first side surface of the second channel layer 221; and a fourth source / drain electrode 223 disposed on the second gate insulating layer 224 and electrically connected to a second side surface of the second channel layer 221 opposite to the first side surface in a first direction.

[0101] The second gate insulating layer 224 of the first pull-down transistor PDT1 may extend in a first direction to contact the side surface of the second source / drain electrode 213 of the first pull-up transistor PUT1. The upper surface of the second source / drain electrode 213 of the first pull-up transistor PUT1 may be at least partially exposed between the first gate insulating layer 214 of the first pull-up transistor PUT1 and the second gate insulating layer 224 of the first pull-down transistor PDT1. The third source / drain electrode 222 of the first pull-down transistor PDT1 may extend over the exposed upper surface of the second source / drain electrode 213 of the first pull-up transistor PUT1. In this way, the second source / drain electrode 213 of the first pull-up transistor PUT1 and the third source / drain electrode 222 of the first pull-down transistor PDT1 may be electrically connected to each other.

[0102] although Figure 11The diagram shows a first pull-up transistor PUT1 with a top-gate structure and a first pull-down transistor PDT1 with a bottom-gate structure, but this disclosure is not limited thereto. For example, a first inverter INV1 may include a first pull-up transistor PUT1 with a bottom-gate structure and a first pull-down transistor PDT1 with a top-gate structure. A second inverter INV2 may also have the same structure as... Figure 11 The first inverter INV1 shown has the same planar structure.

[0103] Figure 12 It is shown Figure 10 A schematic cross-sectional view of the structure of the first inverter INV1 and the first access transistor XT1 of the memory device 200 shown. (Refer to...) Figure 12 The first pull-up transistor PUT1 and the first pull-down transistor PDT1 can be provided in a stacked structure, and the first access transistor XT1 can be provided on the substrate 201 adjacent to the first inverter INV1 in the horizontal direction.

[0104] The first inverter INV1 may include: a first channel layer 211 disposed on a substrate 201; a first source / drain electrode 212 disposed on the substrate 201 and electrically connected to a first side surface of the first channel layer 211; a second source / drain electrode 213 disposed on the substrate 201 and electrically connected to a second side surface of the first channel layer 211 opposite to the first side surface in a first direction; a common gate insulating layer 234 configured to cover the first source / drain electrode 212, the first channel layer 211, and the second source / drain electrode 213; and a common gate electrode. 235, disposed within the common gate insulating layer 234 and facing the first channel layer 211 in a second direction; a second channel layer 221, disposed on the common gate insulating layer 234 and facing the common gate electrode 235 in a second direction; a third source / drain electrode 222, disposed on the common gate insulating layer 234 and electrically connected to a first side surface of the second channel layer 221; and a fourth source / drain electrode 223, disposed on the common gate insulating layer 234 and electrically connected to a second side surface of the second channel layer 221 opposite to the first side surface in a first direction.

[0105] The first pull-up transistor PUT1 may include a first channel layer 211, a first source / drain electrode 212, a second source / drain electrode 213, a common gate insulating layer 234, and a common gate electrode 235. The first pull-down transistor PDT1 may include a second channel layer 221, a third source / drain electrode 222, a fourth source / drain electrode 223, a common gate insulating layer 234, and a common gate electrode 235. Therefore, it can be said that the first pull-down transistor PDT1 is stacked on top of the first pull-up transistor PUT1. The common gate insulating layer 234 may be a gate insulating layer shared by the first pull-up transistor PUT1 and the first pull-down transistor PDT1. The common gate insulating layer 234 may be configured to surround the upper surface, lower surface, first side surface, and second side surface of the common gate electrode 235. Therefore, the common gate electrode 235 may be buried in the common gate insulating layer 234.

[0106] The upper surface or sidewall of the second source / drain electrode 213 of the first pull-up transistor PUT1 can be at least partially exposed so as not to be covered by the common gate insulating layer 234. The third source / drain electrode 222 of the first pull-down transistor PDT1 can extend along the sidewall of the common gate insulating layer 234 to the exposed surface of the second source / drain electrode 213 of the first pull-up transistor PUT1. In this way, the second source / drain electrode 213 of the first pull-up transistor PUT1 and the third source / drain electrode 222 of the first pull-down transistor PDT1 can be electrically connected to each other.

[0107] The first access transistor XT1 may include: a third gate electrode 245 disposed on a substrate 201; a third gate insulating layer 244 configured to cover the substrate 201 and the third gate electrode 245; a third channel layer 241 disposed on the third gate insulating layer 244 and facing the third gate electrode 245 in a second direction; a fifth source / drain electrode 242 disposed on the third gate insulating layer 244 and electrically connected to a first side surface of the third channel layer 241; and a sixth source / drain electrode 243 disposed on the third gate insulating layer 244 and electrically connected to a second side surface of the third channel layer 241 opposite to the first side surface in the first direction. The third channel layer 241 of the first access transistor XT1 may include an n-type oxide semiconductor material. The sixth source / drain electrode 243 of the first access transistor XT1 may extend laterally along the upper surface of the third gate insulating layer 244 to be electrically connected to the second source / drain electrode 213 of the first pull-up transistor PUT1 and the third source / drain electrode 222 of the first pull-down transistor PDT1. In an example implementation, the third source / drain electrode 222 of the first pull-down transistor PDT1 and the sixth source / drain electrode 243 of the first access transistor XT1 can be integrally formed as a single electrode.

[0108] The stacked structure can reduce the size of a single memory cell in the memory device 200 and increase the storage capacity of the memory device 200.

[0109] although Figure 12 The diagram shows a first pull-down transistor PDT1 stacked on top of a first pull-up transistor PUT1, but a first inverter INV1 can be configured such that the first pull-up transistor PUT1 is stacked on top of the first pull-down transistor PDT1. Additionally, a second inverter INV2 and a second access transistor XT2 can have the same characteristics as... Figure 12 The structure shown is the same as the structure shown.

[0110] The aforementioned memory device 200 can be applied to various electronic devices. Figure 13 This is a conceptual diagram schematically illustrating a device architecture applicable to an electronic device 300 according to an example embodiment. (Refer to...) Figure 13The electronic device 300 may include a main memory 310, an auxiliary storage device 320, a central processing unit (CPU) 330, and an input / output device 340. The CPU 330 may include a cache memory 331, an arithmetic logic unit (ALU) 332, and a control unit 333. The cache memory 331 may be SRAM and may include the memory device 200 according to the above-described exemplary embodiment. The main memory 310 may include dynamic random access memory (DRAM). Alternatively, the cache memory 331, main memory 310, and auxiliary storage device 320 may each include the memory device 200 according to the above-described exemplary embodiment. In some cases, the electronic device 300 may be implemented such that computing unit elements and memory unit elements are adjacent to each other on a single chip, without distinguishing between the aforementioned sub-units.

[0111] Any functional blocks shown in the figure and described above can be implemented in processing circuitry, which may be hardware or a hardware / software combination including logic circuitry (such as a processor executing software). For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0112] The above example implementation methods can be summarized as follows.

[0113] (1) An inverter according to an example embodiment may include: a first field-effect transistor including a first channel layer, a first source / drain electrode and a second source / drain electrode spaced apart from each other on the opposite side of the first channel layer, a first gate electrode facing the first channel layer, and a first gate insulating layer between the first channel layer and the first gate electrode; and a second field-effect transistor including a second channel layer, a third source / drain electrode and a fourth source / drain electrode spaced apart from each other on the opposite side of the second channel layer, a second gate electrode facing the second channel layer, and a second gate insulating layer between the second channel layer and the second gate electrode, wherein the second source / drain electrode and the third source / drain electrode are electrically connected to each other, the first channel layer includes a p-type oxide semiconductor based on tellurium oxide, and the second channel layer includes an n-type oxide semiconductor based on indium oxide.

[0114] (2) For example, p-type oxide semiconductors may include telluride oxides doped with at least one element selected from selenium (Se), germanium (Ge) and sulfur (S).

[0115] (3) For example, p-type oxide semiconductors may include Te a X bO, wherein X may include at least one of selenium (Se), germanium (Ge) and sulfur (S), a≥0.7 and b≤0.3.

[0116] (4) For example, p-type oxide semiconductors may include In a Te b O c , where a+b=1, a≤0.5, and b≥0.5.

[0117] (5) For example, In a Te b O c The value of c in the equation can be less than the stoichiometric value.

[0118] (6) For example, In a Te b O c The oxygen vacancy concentration in the medium can be from about 5% to about 80%.

[0119] (7) For example, an n-type oxide semiconductor may include an indium oxide doped with at least one element selected from gallium (Ga), zinc (Zn), tin (Sn) and tungsten (W).

[0120] (8) For example, n-type oxide semiconductors may include In a Ga b Zn c O, where a=b=c.

[0121] (9) In an embodiment, the inverter may further include a substrate, wherein the first channel layer, the first source / drain electrode and the second source / drain electrode may be on the substrate, the first gate insulating layer may be on the first channel layer and the first gate electrode may be on the first gate insulating layer.

[0122] (10) The second gate electrode can be on the substrate, the second gate insulating layer can be on the substrate and cover the second gate electrode, and the second channel layer, the third source / drain electrode and the fourth source / drain electrode can be on the second gate insulating layer.

[0123] (11) The upper surface of the second source / drain electrode may include the exposed upper surface of the second source / drain electrode, the exposed upper surface of the second source / drain electrode being partially exposed between the first gate insulating layer and the second gate insulating layer, and the third source / drain electrode may extend over the exposed upper surface of the second source / drain electrode.

[0124] (12) In other example embodiments, the inverter may further include a substrate, wherein the first gate electrode may be on the substrate, the first gate insulating layer may be on the substrate and cover the first gate electrode, and the first channel layer, the first source / drain electrode and the second source / drain electrode may be on the first gate insulating layer.

[0125] (13) The second channel layer, the third source / drain electrode and the fourth source / drain electrode can be on the substrate, the second gate insulating layer can be on the second channel layer and the second gate electrode can be on the second gate insulating layer.

[0126] (14) The upper surface of the third source / drain electrode may include the exposed upper surface of the third source / drain electrode, which is partially exposed between the first gate insulating layer and the second gate insulating layer, and the second source / drain electrode may extend over the exposed upper surface of the third source / drain electrode.

[0127] (15) The first gate insulating layer and the second gate insulating layer can form a single common gate insulating layer, and the first gate electrode and the second gate electrode can form a single common gate electrode.

[0128] (16) In an example embodiment, the inverter may further include a substrate, wherein the first channel layer, the first source / drain electrode and the second source / drain electrode may be on the substrate, a single common gate insulating layer may be on the first channel layer, a single common gate electrode may be buried in the single common gate insulating layer, the second channel layer, the third source / drain electrode and the fourth source / drain electrode may be on the single common gate insulating layer, and the third source / drain electrode may extend along the sidewall of the single common gate insulating layer to the surface of the second source / drain electrode.

[0129] (17) In other embodiments, the inverter may further include a substrate, wherein the second channel layer, the third source / drain electrode and the fourth source / drain electrode may be on the substrate, a single common gate insulating layer may be on the second channel layer, a single common gate electrode may be buried in the single common gate insulating layer, the first channel layer, the first source / drain electrode and the second source / drain electrode may be on the single common gate insulating layer, and the second source / drain electrode may extend along the sidewall of the single common gate insulating layer to the surface of the third source / drain electrode.

[0130] (18) A memory device according to an example embodiment may include: a first inverter and a second inverter, cyclically connected in series to form a ring oscillator; a first access transistor configured to enable or block access to the first inverter; and a second access transistor configured to enable or block access to the second inverter, wherein the first inverter includes a first pull-up transistor and a first pull-down transistor, the second inverter includes a second pull-up transistor and a second pull-down transistor, each of the first pull-up transistor and the second pull-up transistor includes a first channel layer, the first channel layer including a p-type oxide semiconductor based on tellurium oxide, and each of the first access transistor, the second access transistor, the first pull-down transistor and the second pull-down transistor includes a second channel layer, the second channel layer including an n-type oxide semiconductor based on indium oxide.

[0131] (19) For example, p-type oxide semiconductors may include Te a X b O or In c Te d O e X may include at least one of selenium (Se), germanium (Ge) and sulfur (S), a≥0.7 and b≤0.3, c+d=1, c≤0.5, d≥0.5, and e may be less than the stoichiometric value, and the n-type oxide semiconductor may include indium oxide doped with at least one element selected from gallium (Ga), zinc (Zn), tin (Sn) and tungsten (W).

[0132] (20) An electronic device according to an example embodiment may include a main memory, an auxiliary storage device, a CPU, and an input / output device, wherein the CPU includes a cache memory, an arithmetic logic unit, and a control unit, the cache memory including: a first inverter and a second inverter, cyclically connected in series to form a ring oscillator; a first access transistor configured to enable or block access to the first inverter; and a second access transistor configured to enable or block access to the second inverter, the first inverter including a first pull-up transistor and a first pull-down transistor, the second inverter including a second pull-up transistor and a second pull-down transistor, each of the first pull-up transistor and the second pull-up transistor including a first channel layer, the first channel layer including a p-type oxide semiconductor based on tellurium oxide, and the first access transistor, the second access transistor, the first pull-down transistor, and the second pull-down transistor each including a second channel layer, the second channel layer including an n-type oxide semiconductor based on indium oxide.

[0133] It should be understood that some of the exemplary embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each exemplary embodiment should generally be considered applicable to other similar features or aspects in other exemplary embodiments. Although one or more exemplary embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the claims.

Claims

1. An inverter, comprising: The first field-effect transistor includes a first channel layer, a first source / drain electrode and a second source / drain electrode spaced apart from each other on opposite sides of the first channel layer, a first gate electrode facing the first channel layer, and a first gate insulating layer between the first channel layer and the first gate electrode. as well as The second field-effect transistor includes a second channel layer, a third source / drain electrode and a fourth source / drain electrode spaced apart from each other on the opposite side of the second channel layer, a second gate electrode facing the second channel layer, and a second gate insulating layer between the second channel layer and the second gate electrode. The second source / drain electrode and the third source / drain electrode are electrically connected to each other. The first channel layer comprises a tellurium oxide-based p-type oxide semiconductor, and The second channel layer comprises an indium oxide-based n-type oxide semiconductor.

2. The inverter according to claim 1, wherein, The p-type oxide semiconductor includes telluride doped with at least one element selected from selenium (Se), germanium (Ge), and sulfur (S).

3. The inverter according to claim 1, wherein, The p-type oxide semiconductor includes Te. a X b O, wherein X includes at least one of selenium (Se), germanium (Ge) and sulfur (S), a≥0.7 and b≤0.

3.

4. The inverter according to claim 1, wherein, The p-type oxide semiconductor includes In a Te b O c , where a+b=1, a≤0.5, and b≥0.

5.

5. The inverter according to claim 4, wherein, In a Te b O c The value of c in the equation is less than the stoichiometric value.

6. The inverter according to claim 5, wherein, In a Te b O c The oxygen vacancy concentration in it ranges from 5% to 80%.

7. The inverter according to claim 1, wherein, The n-type oxide semiconductor includes indium oxide doped with at least one element selected from gallium (Ga), zinc (Zn), tin (Sn), and tungsten (W).

8. The inverter according to claim 1, wherein, The n-type oxide semiconductor includes In a Ga b Zn c O, where a=b=c.

9. The inverter of claim 1, further comprising a substrate, wherein... The first channel layer, the first source / drain electrode, and the second source / drain electrode are on the substrate. The first gate insulating layer is on the first channel layer, and The first gate electrode is on the first gate insulating layer.

10. The inverter according to claim 9, wherein The second gate electrode is on the substrate. The second gate insulating layer is on the substrate and covers the second gate electrode, and The second channel layer, the third source / drain electrode, and the fourth source / drain electrode are on the second gate insulating layer.

11. The inverter of claim 10, wherein The upper surface of the second source / drain electrode includes an exposed upper surface of the second source / drain electrode, which is partially exposed between the first gate insulating layer and the second gate insulating layer. The third source / drain electrode extends over the exposed upper surface of the second source / drain electrode.

12. The inverter of claim 1, further comprising a substrate, wherein... The first gate electrode is on the substrate. The first gate insulating layer is on the substrate and covers the first gate electrode, and The first channel layer, the first source / drain electrode, and the second source / drain electrode are on the first gate insulating layer.

13. The inverter according to claim 12, wherein The second channel layer, the third source / drain electrode, and the fourth source / drain electrode are on the substrate. The second gate insulating layer is on the second channel layer, and The second gate electrode is on the second gate insulating layer.

14. The inverter of claim 13, wherein The upper surface of the third source / drain electrode includes an exposed upper surface of the third source / drain electrode, which is partially exposed between the first gate insulating layer and the second gate insulating layer. The second source / drain electrode extends over the exposed upper surface of the third source / drain electrode.

15. The inverter according to claim 1, wherein The first gate insulating layer and the second gate insulating layer constitute a single common gate insulating layer, and The first gate electrode and the second gate electrode constitute a single common gate electrode.

16. The inverter of claim 15, further comprising a substrate, wherein... The first channel layer, the first source / drain electrode, and the second source / drain electrode are on the substrate. The single common gate insulating layer is on the first channel layer. The single common gate electrode is buried in the single common gate insulating layer. The second channel layer, the third source / drain electrode, and the fourth source / drain electrode are located on the single common gate insulating layer, and The third source / drain electrode extends along the sidewall of the single common gate insulating layer to the surface of the second source / drain electrode.

17. The inverter of claim 15, further comprising a substrate, wherein... The second channel layer, the third source / drain electrode, and the fourth source / drain electrode are on the substrate. The single common gate insulating layer is on the second channel layer. The single common gate electrode is buried in the single common gate insulating layer. The first channel layer, the first source / drain electrode, and the second source / drain electrode are located on the single common gate insulating layer, and The second source / drain electrode extends along the sidewall of the single common gate insulating layer to the surface of the third source / drain electrode.

18. A memory device, comprising: The first inverter and the second inverter are connected in series in a loop to form a ring oscillator; The first access transistor is configured to enable or block access to the first inverter; as well as The second access transistor is configured to enable or block access to the second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor. The second inverter includes a second pull-up transistor and a second pull-down transistor. The first pull-up transistor and the second pull-up transistor each include a first channel layer, the first channel layer including a p-type oxide semiconductor based on tellurium oxide, and The first access transistor, the second access transistor, the first pull-down transistor, and the second pull-down transistor each include a second channel layer, the second channel layer including an n-type oxide semiconductor based on indium oxide.

19. The memory device of claim 18, wherein The p-type oxide semiconductor includes Te. a X b O or In c Te d O e X includes at least one of selenium (Se), germanium (Ge), and sulfur (S), a ≥ 0.7, b ≤ 0.3, c + d = 1, c ≤ 0.5, d ≥ 0.5, and e is less than the stoichiometric value. The n-type oxide semiconductor includes indium oxide doped with at least one element selected from gallium (Ga), zinc (Zn), tin (Sn), and tungsten (W).

20. An electronic device, comprising: Main memory; Auxiliary storage device; Central Processing Unit (CPU); as well as Input / output devices The central processing unit includes a cache memory, an arithmetic logic unit, and a control unit. The cache memory includes: The first inverter and the second inverter are connected in series in a loop to form a ring oscillator; A first access transistor is configured to enable or block access to the first inverter; and The second access transistor is configured to enable or block access to the second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor. The second inverter includes a second pull-up transistor and a second pull-down transistor. The first pull-up transistor and the second pull-up transistor each include a first channel layer, the first channel layer including a p-type oxide semiconductor based on tellurium oxide, and The first access transistor, the second access transistor, the first pull-down transistor, and the second pull-down transistor each include a second channel layer, the second channel layer including an n-type oxide semiconductor based on indium oxide.

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