Array substrate, preparation method thereof, display panel and display device

Abstract

The application provides an array substrate and a preparation method thereof, a display panel and a display device. The array substrate comprises a first wiring layer on one side of a substrate; an insulating layer provided on a side of the first wiring layer away from the substrate and having a via hole; a second wiring layer on a side of the insulating layer away from the first wiring layer, the second wiring layer being connected with the first wiring layer through the via hole; and a support column provided on the insulating layer, the support column surrounding at least part of the via hole, and the Young's modulus of the support column being greater than the Young's modulus of the insulating layer. The support column with a greater Young's modulus is arranged around the via hole connected between the first wiring layer and the second wiring layer, thereby supporting the second wiring layer, so that when an external force is impacted, the problem that the second wiring layer is broken in a boundary region of the via hole due to a large difference in deformation between a region where the via hole is located and a surrounding region near the via hole can be effectively avoided.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Organic light-emitting diode (OLED) display technology is considered the most promising next-generation display technology. Compared with liquid crystal display technology, OLED display technology has advantages such as low energy consumption, low cost, self-emissiveness, wide viewing angle, and fast response speed.

[0003] With the development of smart devices, the application of display panels is becoming more and more widespread and diverse, such as folding and rolling. While ensuring flexibility, their impact resistance will deteriorate. When subjected to external impact, the traces in the display panel will break, resulting in failure phenomena such as bright spots and black spots, and thus causing display abnormalities. Summary of the Invention

[0004] To address the aforementioned problems, this invention provides an array substrate and its fabrication method, a display panel, and a display device, thereby preventing trace breakage.

[0005] This application provides an array substrate, comprising:

[0006] Substrate; The first wiring layer is located on one side of the substrate; An insulating layer is disposed on the side of the first wiring layer away from the substrate; the insulating layer has vias, and the orthographic projection of the vias on the substrate at least partially overlaps with the orthographic projection of the first wiring layer on the substrate; The second routing layer is located on the side of the insulating layer away from the first routing layer, and the second routing layer is connected to the first routing layer through vias; A support post is disposed in the insulation layer, the support post surrounds at least part of the through hole, and the Young's modulus of the support post is greater than the Young's modulus of the insulation layer.

[0007] In some embodiments, the orthographic projection of the support pillar on the substrate at least partially overlaps with the orthographic projection of the second wiring layer on the substrate.

[0008] In some embodiments, the support post surrounds the through hole.

[0009] In some embodiments, the distance between the support pillar and the via is 0-1.7 micrometers in the thickness direction perpendicular to the array substrate.

[0010] In some embodiments, the Young's modulus of the support column is 200 GPa-320 GPa.

[0011] In some embodiments, the support column is made of inorganic materials.

[0012] In some embodiments, the material of the support column includes silicon nitride doped with carbon, silicon nitride doped with boron, silicon nitride doped with aluminum, or aluminum oxide.

[0013] In some embodiments, the insulation layer comprises at least two layers, and the support post is disposed in at least one of the layers.

[0014] In some embodiments, along the thickness direction of the array substrate, the insulating layer includes a first insulating layer, a second insulating layer, and a third insulating layer stacked sequentially, and the support pillar is disposed in at least one of the first insulating layer, the second insulating layer, and the third insulating layer.

[0015] In some embodiments, the third insulating layer is provided with a groove, and the support post is located in the groove.

[0016] In some embodiments, the depth of the groove along the thickness direction of the array substrate is less than or equal to the thickness of the third insulating layer.

[0017] In some embodiments, the surface of the insulating layer on the side away from the substrate where the support pillar is disposed is flush with the surface of the support pillar on the side away from the substrate.

[0018] In some embodiments, the first routing layer includes an active layer, and the second routing layer includes a first electrode and a second electrode spaced apart, wherein the first electrode is connected to the active layer through a via, and the second electrode is connected to the active layer through a via.

[0019] In some embodiments, the array substrate further includes a first metal layer and a second metal layer, wherein the first metal layer is located between a first insulating layer and a second insulating layer, the first metal layer includes a gate and a lower electrode, the second metal layer is located between a second insulating layer and a third insulating layer, the second metal layer includes an upper electrode, and the orthogonal projection of the upper electrode on the substrate at least partially overlaps with the orthogonal projection of the lower electrode on the substrate.

[0020] In some embodiments, the system further includes a support block located between the insulating layer and the second wiring layer, and the support block has a through hole connected to a via.

[0021] In some embodiments, the support block is disposed around the via, and the second wiring layer is in direct contact with the support block.

[0022] In some embodiments, the material of the support block is the same as the material of the second wiring layer.

[0023] In some embodiments, the material of the support block includes at least one of molybdenum, aluminum, copper, or titanium.

[0024] This application provides a method for fabricating an array substrate, the steps of which are as follows: Provide a substrate; A first wiring layer is fabricated on one side of the substrate; An insulating layer is formed on the side of the first wiring layer away from the substrate. A via and a support pillar are provided on the insulating layer. The orthographic projection of the via on the substrate at least partially overlaps with the orthographic projection of the first wiring layer on the substrate. The support pillar surrounds at least part of the via, and the Young's modulus of the support pillar is greater than that of the insulating layer. A second wiring layer is formed on the side of the insulating layer away from the substrate, and the second wiring layer is connected to the first wiring layer through vias.

[0025] This application provides a display panel, comprising: an array substrate according to any one of the above-described methods, or an array substrate prepared by the above-described preparation method.

[0026] This application provides a display device, including the display panel described above.

[0027] This application provides support for the second routing layer by providing support pillars with a large Young's modulus around the via connecting the first and second routing layers. This effectively prevents the second routing layer from breaking at the boundary of the via due to the large difference in deformation between the area where the via is located and the surrounding area near the via when subjected to external impact. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of an array substrate provided in an embodiment of the present invention; Figure 2 for Figure 1 A schematic diagram of a cross-sectional structure at point AA in the middle; Figure 3 for Figure 1 Another cross-sectional structural diagram at point AA; Figure 4 for Figure 1 Another cross-sectional structural diagram at point AA; Figure 5 for Figure 1 Another cross-sectional structural diagram at point AA; Figure 6 This is a schematic diagram of another array substrate provided in an embodiment of the present invention; Figure 7 for Figure 6 A schematic diagram of a cross-sectional structure at point AA in the middle; Figure 8 This is a schematic cross-sectional view of an array substrate provided in an embodiment of the present invention; Figure 9 A flowchart illustrating a method for fabricating an array substrate according to an embodiment of the present invention; Figures 10a-10b A schematic diagram of the process structure of a method for fabricating an array substrate according to an embodiment of the present invention; Figures 11a-11c A schematic diagram of the process structure of another method for fabricating an array substrate provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 13 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention; Figure 14 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention.

[0030] Explanation of reference numerals in the attached figures: 1. Display device; 10. Display panel; 100, Substrate; 200, Semiconductor layer; 210, Active layer; 310, First insulating layer; 310a, First initial insulating layer; 320, Second insulating layer; 320a, Second initial insulating layer; 330, Third insulating layer; 330a, Third initial insulating layer; 330b, Third intermediate insulating layer; 400, First metal layer; 410, Gate; 420, Lower electrode; 500, Second metal layer; 510, Upper electrode; 600, Via; 700, Third metal layer; 710, First electrode; 720, Second electrode; 800, Support pillar; 810, Groove; 820, Support block; 910, First planarization layer; 920, Second planarization layer; 1100, First electrode; 1200, Light-emitting functional layer; 1300, Second electrode; 1400, Pixel limiting layer; SPX, sub-pixel; SPX1, first sub-pixel; SPX2, second sub-pixel; SPX3, third sub-pixel; AA, display area; NA, non-display area. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0032] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0033] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0034] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.

[0035] For certain elements, terms such as "above" or "above" are sometimes used when describing the position of an element located in the Z direction, and "below" or "below" are used when describing the position of an element located in the opposite direction. In addition, when using terms such as "above," "above," "below," "below," and "relative" to define the positional relationship between two elements, it can include not only the state in which the two elements are directly connected, but also the state in which the two elements are separated by gaps or other elements.

[0036] Furthermore, the terms "first," "second," etc., are used to describe various elements, components, regions, layers, and / or parts, but these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, and / or part from another element, component, region, layer, and / or part.

[0037] Unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0038] With the development of smart devices, the application of display panels is becoming more and more widespread and diverse, such as folding and rolling. While ensuring flexibility, their impact resistance will deteriorate. When subjected to external impact, the traces in the display panel will break, resulting in failure phenomena such as bright spots and black spots, and thus causing display abnormalities.

[0039] To address the aforementioned technical problems, embodiments of this application provide an array substrate and its fabrication method, a display panel, and a display device.

[0040] The following will combine Figures 1-14 The array substrate, its fabrication method, display panel, and display device provided in the embodiments of this application will be described.

[0041] Combination Figures 1-8 This application provides an array substrate, comprising: a substrate 100; a first wiring layer located on one side of the substrate 100; an insulating layer disposed on the side of the first wiring layer away from the substrate 100; the insulating layer having a via 600, the orthographic projection of the via 600 on the substrate 100 at least partially overlapping the orthographic projection of the first wiring layer on the substrate 100; a second wiring layer located on the side of the insulating layer away from the first wiring layer, the second wiring layer being connected to the first wiring layer through the via 600; and a support pillar 800 disposed on the insulating layer, the support pillar 800 surrounding at least a portion of the via 600, and the Young's modulus of the support pillar 800 being greater than the Young's modulus of the insulating layer.

[0042] This application provides support columns 800 with a large Young's modulus around the via 600 connecting the first and second routing layers, thereby supporting the second routing layer. This effectively prevents the second routing layer from breaking at the boundary of the via 600 due to the large deformation difference between the area where the via 600 is located and the surrounding area near the via 600 when subjected to external impact.

[0043] It is worth noting that, in order to connect the second and first trace layers, a via 600 is provided on the insulating layer. The second trace layer fills the via 600, and the second trace layer located within the via 600 is connected to the first trace layer below. Thus, the area where the via 600 is located consists of the first trace layer superimposed with the second trace layer within the via 600. Compared to a second trace layer simply located on one side of the insulating layer, its overall thickness is relatively small. Therefore, under external impact, the deformation of the second trace layer in the via 600 area and the non-via area is significantly different, causing the second trace layer to be prone to breakage in the boundary area of ​​the via 600, thereby preventing subsequent traces from transmitting signals.

[0044] In some embodiments, substrate 100 may provide support for subsequent structural layers. In some examples, substrate 100 may be a rigid substrate, for example, the material of substrate 100 may be glass. In other examples, substrate 100 may be a flexible substrate, and the material of substrate 100 may include at least one of polyimide (PI), polyethylene terephthalate, polyethylene naphthalate, polyethylene, polyacrylate, polyetherimide, polycarbonate, polyarylate, polyethersulfone, silicon nitride, silicon oxide, and silicon oxynitride.

[0045] In some embodiments, the substrate 100 may include a multilayer stacked structure, for example, a multilayer stacked structure formed by stacking at least one layer of polyimide and at least one layer of silicon oxide.

[0046] In some embodiments, along the thickness direction Z of the array substrate, the thickness of the second trace layer at the via 600 is greater than the thickness of the second trace layer in other regions (regions without via 600), thereby ensuring the stability of the connection between the second trace layer and the first trace layer at the via 600, and thus ensuring stable signal transmission.

[0047] In some embodiments, the orthographic projection of the support pillar 800 on the substrate 100 at least partially overlaps with the orthographic projection of the second trace layer on the substrate 100; thereby the support pillar 800 supports the second trace layer not located in the via 600, so that when the area is subjected to external force impact, the deformation difference between the area and the via 600 area is reduced, thereby effectively preventing the trace from breaking.

[0048] In some embodiments, the support post 800 is arranged around the via 600, thereby effectively ensuring that the via 600 is supported by the support post 800, and further preventing the trace from breaking.

[0049] Furthermore, in the thickness direction Z perpendicular to the array substrate 10, the distance between the support pillar 800 and the via 600 is 0-1.7 micrometers; for example, the distance between the support pillar 800 and the via 600 is 0 micrometers, 0.1 micrometers, 0.25 micrometers, 0.3 micrometers, 0.36 micrometers, 0.4 micrometers, 0.45 micrometers, 0.5 micrometers, 0.58 micrometers, 0.64 micrometers, 0.72 micrometers, 0.85 micrometers, 0.9 micrometers, 1 micrometer, 1.1 micrometers, 1.2 micrometers, 1.35 micrometers, 1.4 micrometers, 1.45 micrometers, 1.5 micrometers, 1.62 micrometers, or 1.7 micrometers. If the distance between the support pillar 800 and the via 600 is too large, although the support pillar 800 can support the second routing layer, the area closer to the via 600 cannot be supported. When subjected to external force impact, the routing will still break in the boundary area, thus preventing subsequent routing from transmitting signals.

[0050] In some embodiments, the Young's modulus of the support column 800 is 200 GPa-320 GPa; for example, the Young's modulus of the support column 800 is 200 GPa, 205 GPa, 210 GPa, 225 GPa, 230 GPa, 235 GPa, 240 GPa, 250 GPa, 255 GPa, 260 GPa, 275 GPa, 280 GPa, 285 GPa, 290 GPa, 300 GPa, 305 GPa, 310 GPa, or 320 GPa, etc.

[0051] In some embodiments, the material of the support column 800 includes inorganic materials, which can, on the one hand, insulate and isolate the second wiring layer, and on the other hand, ensure a tighter connection with the insulating layer, preventing the two films from separating.

[0052] In some specific embodiments, the material of the support column 800 includes carbon-doped silicon nitride, boron-doped silicon nitride, aluminum-doped silicon nitride, or aluminum oxide; wherein, the carbon-doped silicon nitride has a carbon doping atomic percentage content of 1%-3%, for example, 1%, 1.04%, 1.06%, 1.08%, 1.1%, 1.15%, 1.18%, 1.2%, 1.26%, 1.3%, 1.36%, 1 ... 0.4%, 1.43%, 1.5%, 1.7%, 1.85%, 2%, 2.2%, 2.34%, 2.43%, 2.5%, 2.65%, 2.78%, 2.86%, or 3%, etc.; Doping with carbon improves the support capacity of the support pillars 800. However, if the carbon doping content is too high, the film will become brittle and prone to fracture under external impact. Therefore, the carbon doping content needs to be controlled; Boron-doped silicon nitride, its boron doping... The percentage content of boron doping is 0.5%-1%, with boron doping percentages of 0.5%, 0.52%, 0.54%, 0.55%, 0.58%, 0.6%, 0.63%, 0.65%, 0.7%, 0.72%, 0.75%, 0.8%, 0.87%, 0.9%, 0.94%, or 1%, etc. Boron doping improves the support capacity of the support pillar 800. However, excessive boron content may lead to leakage risks. Aluminum-doped silicon nitride... The atomic percentage content of aluminum doping is 0.5%-1%, with specific percentages of 0.5%, 0.52%, 0.54%, 0.55%, 0.58%, 0.6%, 0.63%, 0.65%, 0.7%, 0.72%, 0.75%, 0.8%, 0.87%, 0.9%, 0.94%, or 1%. Aluminum doping enhances the support capacity of the support pillar 800. However, excessive aluminum doping can reduce the reliability of the film layer.

[0053] In some embodiments, the insulating layer includes at least two layers, and the support post 800 is disposed in at least one of the layers; when the insulating layer is a multi-layer structure, the support post 800 can be disposed in any one layer or any multiple layers.

[0054] Combination Figures 2-5 Specifically, along the thickness direction Z of the array substrate 10, the insulating layer includes a first insulating layer 310, a second insulating layer 320, and a third insulating layer 330 stacked sequentially, and a support post 800 is disposed in at least one of the first insulating layer 310, the second insulating layer 320, and the third insulating layer 330. For ease of explanation, the following embodiment will describe the insulating layer formed by the stacking of the first insulating layer 310, the second insulating layer 320, and the third insulating layer 330. Of course, in other embodiments, the insulating layer may include two, four, or five layers, etc., and this application does not specifically limit it.

[0055] For example, such as Figure 2 and Figure 3 As shown, the support column 800 is disposed on the third insulating layer 330, and as... Figure 4 As shown, the support post 800 is disposed on the second insulating layer 320; for example, the support post 800 is disposed on the first insulating layer 310. Of course, in some other embodiments, the support post 800 may also be disposed on the second insulating layer 320 and the third insulating layer 330, or on the first insulating layer 310 and the third insulating layer 330.

[0056] Furthermore, in order to set the support pillar 800, a corresponding groove 810 is provided on any film layer in the insulating layer. The support pillar 800 is located in the groove 810. The groove 810 limits the support pillar 800, preventing the support pillar 800 from being directly placed on the surface of any film layer in the insulating layer, which would cause the surface of the insulating layer away from the substrate 100 to be uneven, especially in the area near the via 600, thereby causing the second wiring layer to break during the formation process.

[0057] In some embodiments, the third insulating layer 330 is provided with a groove 810, and the support post 800 is located in the groove 810.

[0058] like Figure 2 As shown, along the thickness direction Z of the array substrate 10, the depth of the groove 810 is equal to the thickness of the third insulating layer 330, that is, the groove 810 penetrates the third insulating layer 330. Or, as... Figure 3 As shown, along the thickness direction Z of the array substrate 10, the depth of the groove 810 is less than the thickness of the third insulating layer 330, that is, the groove 810 does not penetrate the third insulating layer 330.

[0059] In addition, to further avoid the support pillar 800 from affecting the second wiring layer, the surface of the insulating layer with the support pillar 800 away from the substrate 100 is flush with the surface of the support pillar 800 away from the substrate 100. That is, within the allowable range of process error, the surface of the support pillar 800 away from the substrate 100 is flush with the surface of the insulating layer, thereby ensuring the flatness of the surface in the area near the via 600, which is conducive to the subsequent formation of a more continuous and stable second wiring layer.

[0060] In some specific embodiments, the first wiring layer includes a semiconductor layer 200, the semiconductor layer includes an active layer 210, and the second wiring layer includes a first electrode 710 and a second electrode 720 spaced apart. The first electrode 710 is connected to the active layer 210 through a via 600, and the second electrode 720 is connected to the active layer 210 through a via 600. The first electrode 710 serves as one of the source and drain electrodes, and the second electrode 720 serves as the other of the source and drain electrodes, thereby constituting a partial structure of the transistor in the array substrate.

[0061] In some embodiments, the array substrate 10 further includes a first metal layer 400 and a second metal layer 500, wherein the first metal layer 400 is located between a first insulating layer 310 and a second insulating layer 320, and includes a gate 410 and a lower electrode 420, wherein the orthographic projection of the gate 410 on the substrate 100 partially overlaps with the orthographic projection of the active layer 210 on the substrate 100; the second metal layer 500 is located between a second insulating layer 320 and a third insulating layer 330, and includes an upper electrode 510, the orthographic projection of the upper electrode 510 on the substrate 100 at least partially overlapping with the orthographic projection of the lower electrode 420 on the substrate 100; the upper electrode 510 and the lower electrode 420 constitute a capacitor structure in the array substrate. Furthermore, the array substrate also includes a third metal layer 700, which includes a first electrode 710 and a second electrode 720.

[0062] Transistors and capacitors together constitute a pixel driving circuit, which drives the light-emitting unit to emit light. Examples include 2T1C pixel driving circuits, 7T1C pixel driving circuits, and 8T1C pixel driving circuits in related technologies.

[0063] In addition, the array substrate 10 is provided with a plurality of pixel driving circuits. One pixel driving circuit can drive one light-emitting unit to emit light. Of course, in some other embodiments, one pixel driving circuit can drive multiple light-emitting units of the same color. Each pixel driving circuit includes a plurality of transistors, and support pillars 800 of the above embodiments are provided at the source and drain of each transistor.

[0064] like Figures 1-7 As shown, in some embodiments, the gate 410 is disposed on the side of the active layer 210 away from the substrate 100. Of course, in some other embodiments, the gate 410 is disposed on the side of the active layer 210 facing the substrate 100. In other embodiments, a dual-gate structure is provided, that is, one gate 410 is disposed on the side of the active layer 210 away from the substrate 100, and the other gate 410 is disposed on the side of the active layer 210 facing the substrate 100.

[0065] Combination Figure 1 and Figure 6 In some embodiments, the orthographic projection of the support post 800 onto the substrate 100 is annular, combined with Figures 1-5 The shape of the orthographic projection of the support pillar 800 onto the substrate 100 is symmetrical; of course, in some other embodiments, combined with Figure 6 and Figure 7 The shape of the orthographic projection of the support column 800 onto the substrate 100 is an asymmetrical structure.

[0066] In addition, such as Figure 8As shown, the array substrate also includes a support block 820, which is located between the insulating layer and the second wiring layer. The support block 820 is provided with a through hole, which is connected to a via 600. The second wiring layer is connected to the first wiring layer through the through hole and the via 600.

[0067] In some embodiments, the orthographic projection of the support post 800 on the substrate 100 lies within the orthographic projection of the support block 820 on the substrate 100, thereby further improving the support capability for the area surrounding the via 600.

[0068] In some specific embodiments, the support block 820 is disposed around the via 600, and the second wiring layer is in direct contact with the support block 820.

[0069] Preferably, the material of the support block 820 is the same as the material of the second trace layer, so that the support block 820 can also transmit electrical signals, thereby reducing the impedance of the second trace layer and facilitating signal transmission.

[0070] For example, the material of support block 820 includes at least one of molybdenum, aluminum, copper or titanium.

[0071] Of course, in some other embodiments, when the insulating layer has multiple film layers, the support block 820 can be disposed between any two film layers, or the support block 820 can be located on the side of the insulating layer facing the substrate 100.

[0072] In some other embodiments, the array substrate further includes a fourth metal layer and a fifth metal layer. The specific number of metal layers can be selected according to the actual situation, and this application does not impose a specific limitation. Taking five metal layers as an example, the first wiring layer can be one of semiconductor layer 200, first metal layer 400, second metal layer 500, third metal layer 700, and fourth metal layer, and the second wiring layer can be one of first metal layer 400, second metal layer 500, third metal layer 700, fourth metal layer, and fifth metal layer. This application does not impose any limitations.

[0073] In addition, the array substrate also includes a planarization layer, which is located on the side of the third metal layer 700 away from the substrate 100. The planarization layer includes a first planarization layer 910 and a second planarization layer 920. Of course, in other embodiments, one or three planarization layers may also be provided. By flattening the surface of the array substrate through the planarization layer, it is beneficial to place the light-emitting units on the side of the planarization layer away from the substrate 100, thereby ensuring that the light-emitting units are on the same plane and ensuring the display effect.

[0074] Based on the same inventive concept, embodiments of this application also provide a method for fabricating an array substrate, such as... Figures 9-11c As shown, the steps include: Step S100: Provide a substrate 100; Step S200: Prepare a first wiring layer on one side of the substrate 100; Step S300: An insulating layer is formed on the side of the first wiring layer away from the substrate 100. A via 600 and a support pillar 800 are provided on the insulating layer. The orthographic projection of the via 600 on the substrate 100 at least partially overlaps with the orthographic projection of the first wiring layer on the substrate 100. The support pillar 800 surrounds at least part of the via 600, and the Young's modulus of the support pillar 800 is greater than the Young's modulus of the insulating layer. Step S400: A second wiring layer is formed on the side of the insulating layer away from the substrate 100. The second wiring layer is connected to the first wiring layer through a via 600.

[0075] By providing support pillars 800 with a large Young's modulus around the via 600 connecting the first and second routing layers, the second routing layer is supported. This effectively prevents the second routing layer from breaking at the boundary of the via 600 due to the large difference in deformation between the area where the via 600 is located and the surrounding area near the via 600 when subjected to external impact.

[0076] For ease of understanding, this application embodiment uses a semiconductor layer 200 as the first wiring layer, a third metal layer 700 as the second wiring layer, and three insulating layers as an example for illustration; of course, the first wiring layer can also be other metal layers in the array substrate, the second wiring layer can also be other metal layers in the array substrate, and the insulating layer can also be a single layer or multiple layers, which is not limited in this application.

[0077] Combination Figures 10a-11c Step S200, the step of fabricating a first wiring layer on one side of the substrate 100, includes: fabricating an active layer 210 on one side of the substrate 100; Step S300, the step of forming an insulating layer on the side of the first wiring layer away from the substrate 100, includes: forming a first initial insulating layer 310a on the side of the active layer 210 away from the substrate 100; A gate 410 is formed on the side of the first initial insulating layer 310a away from the substrate 100, and the orthogonal projection of the gate 410 on the substrate 100 overlaps with the orthogonal projection of the active layer 210 on the substrate 100. A second initial insulating layer 320a and a third initial insulating layer 330a are formed on the side of the gate 410 away from the substrate 100; The first initial insulating layer 310a, the second initial insulating layer 320a and the third initial insulating layer 330a are patterned to form an insulating layer having a via 600 and a groove 810, wherein the via 600 penetrates the first initial insulating layer 310a, the second initial insulating layer 320a and the third initial insulating layer 330a, and the groove 810 is located in the third initial insulating layer 330a and surrounds at least part of the via 600; A support column 800 is formed within the groove 810, and the Young's modulus of the support column 800 is greater than that of the insulating layer.

[0078] In some embodiments, the vias 600 and grooves 810 can be formed using the same process during the patterning process of the first initial insulating layer 310a, the second initial insulating layer 320a, and the third initial insulating layer 330a, such as... Figure 10a and Figure 10b As shown, the groove 810 is formed simultaneously during the formation of the via 600. For example, it can be prepared using a half-tone mask.

[0079] Combination Figures 11a-11c In other embodiments, the step of patterning the first initial insulating layer 310a, the second initial insulating layer 320a, and the third initial insulating layer 330a to form the via 600 and the groove 810 includes: The third initial insulating layer 330a is patterned to form a third intermediate insulating layer 330b with grooves 810; A support column 800 is formed within the groove 810, and the Young's modulus of the support column 800 is greater than that of the insulating layer. The third intermediate insulating layer 330b is patterned to form a via 600, which penetrates the first initial insulating layer 310a, the second initial insulating layer 320a and the third initial insulating layer 330a, and the support post 800 surrounds at least part of the via 600.

[0080] Of course, in some other embodiments, the via 600 can be formed first, then the groove 810 can be formed, and the support post 800 can be formed in the groove 810. The specific order in which the via 600 and the groove 810 are formed is not limited.

[0081] In addition, in some other embodiments, the second initial insulating layer 320a may be patterned to form a groove 810, or the first initial insulating layer 310a may be patterned to form a groove 810, and then a support post 800 may be formed in the groove 810.

[0082] In some embodiments, after the step of forming the support post 800 in the groove 810, the surface of the support post 800 away from the substrate 100 is surface treated so that the surface of the support post 800 away from the substrate 100 is flush with the surface of the insulating layer on which the support post 800 is disposed away from the substrate 100, thereby ensuring the flatness of the surface in the area near the via 600, which is beneficial for the subsequent formation of a more continuous and stable second wiring layer.

[0083] Furthermore, the specific structure of the array substrate formed by the method for fabricating the array substrate provided in this application can be referred to the array substrates in the previous embodiments, and therefore will not be repeated here.

[0084] Based on the same inventive concept, this application also provides a display panel 10, such as... Figure 12 and Figure 13 As shown, the display panel 10 may include the array substrate in the above embodiments.

[0085] In some embodiments, the display panel 10 may be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) display panel. The display panel 10 includes a display area AA with display function and a non-display area NA.

[0086] The shape of the display area AA of the display panel 10 can be rectangular, square, circular, oval, or other shapes.

[0087] The display area AA includes a plurality of sub-pixels SPX arranged in the X and Y directions. Each sub-pixel SPX displays a different color. In some embodiments, the plurality of sub-pixels SPX includes a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. For example, the first sub-pixel SPX1 is blue, the second sub-pixel SPX2 is green, and the third sub-pixel SPX3 is red. In some embodiments, in addition to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, the sub-pixels SPX also include sub-pixels SPX that emit white or other colors of light; furthermore, the X and Y directions intersect; in some specific embodiments, the X and Y directions are perpendicular.

[0088] Sub-pixels (SPX) include pixel driving circuits and light-emitting units that emit light of the corresponding color, driven by the pixel driving circuits. First sub-pixel SPX1 includes a first light-emitting unit, second sub-pixel SPX2 includes a second light-emitting unit, and third sub-pixel SPX3 includes a third light-emitting unit. One pixel driving circuit drives at least one light-emitting unit to emit light. For example, display area AA includes a normal display area and a light-transmitting display area. The light-transmitting display area is a display area corresponding to a sensor and has light-transmitting properties, while the normal display area is a display area not corresponding to a sensor. In the normal display area, one pixel driving circuit drives one light-emitting unit to emit light, and in the light-transmitting display area, one pixel driving circuit drives one or more light-emitting units to emit light.

[0089] Combination Figure 13 The light-emitting unit includes a first electrode 1100, a light-emitting functional layer 1200, and a second electrode 1300. The first electrode 1100 can be an anode, and the second electrode 1200 can be a cathode. Alternatively, in some other embodiments, the first electrode 1100 can be a cathode, and the second electrode 1200 can be an anode. The first electrode 1100 of the light-emitting unit can be connected to a pixel driving circuit via a via located on the planarization layer, so that the pixel driving circuit drives the light-emitting unit to emit light.

[0090] The first electrode 1100 may include a multilayer structure, such as a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed, for example, using silver, a metallic material with excellent light reflectivity. Each conductive oxide layer can be formed, for example, from a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide). The second electrode 1300 is formed, for example, from a metallic material such as an alloy of magnesium and silver (MgAg).

[0091] The light-emitting functional layer 1200 includes a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting material layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL stacked along a direction away from the substrate 100 (i.e., the Z direction). The light-emitting functional layer 1200 may include a single light-emitting material layer EML, or a stacked light-emitting structure including multiple light-emitting material layers EML.

[0092] The display panel 10 also includes a pixel limiting layer 1400, which is located on one side of the array substrate and has multiple pixel openings. The light-emitting unit is at least partially located in the corresponding pixel opening. The position of the light-emitting unit is limited by the pixel opening to avoid crosstalk between adjacent sub-pixels SPX.

[0093] In some other embodiments, the display panel 10 may further include at least one film layer such as a touch layer, a polarizer, or a color filter substrate. This film layer may also be bonded to the display panel 10 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0094] In addition, the display panel 10 also includes a cover plate to protect the display panel 10.

[0095] Based on the same inventive concept, this application also provides a display device 1, such as... Figure 14 As shown, the display device 1 may include the display panel 10 in the above embodiments. The display device may be an electronic paper device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, smart bracelet, smartwatch, supercomputer, navigator, wireless device, personal digital assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, clock, calculator, television monitor, computer monitor, car display (e.g., odometer display, etc.), cockpit controller and / or display, camera view display (e.g., display of rearview camera in a vehicle), electronic billboard or sign, projector, and other mobile or fixed terminals.

[0096] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0097] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0098] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, include: Substrate; The first wiring layer is located on one side of the substrate; An insulating layer is disposed on the side of the first wiring layer away from the substrate; The insulating layer is provided with a via, and the orthographic projection of the via on the substrate at least partially overlaps with the orthographic projection of the first wiring layer on the substrate; The second routing layer is located on the side of the insulating layer away from the first routing layer, and the second routing layer is connected to the first routing layer through the via; A support post is disposed in the insulating layer, the support post surrounding at least a portion of the through hole, and the Young's modulus of the support post is greater than the Young's modulus of the insulating layer.

2. The array substrate according to claim 1, characterized in that, The orthographic projection of the support pillar on the substrate at least partially overlaps with the orthographic projection of the second wiring layer on the substrate; Preferably, the support column surrounds the through hole; Preferably, the distance between the support post and the via is 0-1.7 micrometers in the thickness direction perpendicular to the array substrate.

3. The array substrate according to claim 1, characterized in that, The Young's modulus of the support column is 200 GPa-320 GPa; Preferably, the material of the support column includes inorganic materials; Preferably, the material of the support column includes silicon nitride doped with carbon, silicon nitride doped with boron, silicon nitride doped with aluminum, or aluminum oxide.

4. The array substrate according to claim 1, characterized in that, The insulating layer comprises at least two layers, and the support column is disposed in at least one of the layers; Preferably, along the thickness direction of the array substrate, the insulating layer includes a first insulating layer, a second insulating layer, and a third insulating layer stacked sequentially, and the support pillar is disposed in at least one of the first insulating layer, the second insulating layer, and the third insulating layer; Preferably, the third insulating layer is provided with a groove, and the support column is located within the groove; Preferably, along the thickness direction of the array substrate, the depth of the groove is less than or equal to the thickness of the third insulating layer.

5. The array substrate according to claim 4, characterized in that, The insulating layer on the side of the support pillar away from the substrate is flush with the side of the support pillar away from the substrate.

6. The array substrate according to claim 4, characterized in that, The first routing layer includes an active layer, and the second routing layer includes a first electrode and a second electrode spaced apart. The first electrode is connected to the active layer through the via, and the second electrode is connected to the active layer through the via. Preferably, the array substrate further includes a first metal layer and a second metal layer, wherein the first metal layer is located between the first insulating layer and the second insulating layer, the first metal layer includes a gate and a lower electrode, the second metal layer is located between the second insulating layer and the third insulating layer, the second metal layer includes the upper electrode, and the orthographic projection of the upper electrode on the substrate at least partially overlaps with the orthographic projection of the lower electrode on the substrate.

7. The array substrate according to claim 1, characterized in that, Also includes: A support block is located between the insulating layer and the second wiring layer, and the support block is provided with a through hole, which is connected to the via. Preferably, the support block is arranged around the via, and the second wiring layer is in direct contact with the support block; Preferably, the material of the support block is the same as the material of the second wiring layer; Preferably, the material of the support block includes at least one of molybdenum, aluminum, copper, or titanium.

8. A method for fabricating an array substrate, characterized in that, The steps are as follows: Provide a substrate; A first wiring layer is prepared on one side of the substrate; An insulating layer is formed on the side of the first wiring layer away from the substrate. A via and a support pillar are provided on the insulating layer. The orthographic projection of the via on the substrate at least partially overlaps with the orthographic projection of the first wiring layer on the substrate. The support pillar surrounds at least a portion of the via, and the Young's modulus of the support pillar is greater than that of the insulating layer. A second trace layer is formed on the side of the insulating layer away from the substrate, and the second trace layer is connected to the first trace layer through the via.

9. A display panel, characterized in that, include: The array substrate according to any one of claims 1-7, or the array substrate prepared by the preparation method according to claim 8.

10. A display device, characterized in that, Includes the display panel as described in claim 9.

Images