Array substrate and display device

Abstract

The present disclosure relates to the technical field of display, and discloses an array substrate and a display device; the array substrate comprises a substrate, an active layer, a first connecting conductor layer, a blocking layer and an insulating layer group which are sequentially stacked; the first connecting conductor layer comprises a first connecting part and a second connecting part which are arranged at intervals, the first connecting part comprises a first part connected to the active layer, and the second connecting part comprises a second part connected to the active layer; the blocking layer comprises a first blocking part and a second blocking part which are arranged at intervals, the first blocking part is arranged on at least one side of the first part away from the substrate, and covers the sidewall of the first part to extend to one side of the active layer away from the substrate; the second blocking part is arranged on at least one side of the second part away from the substrate, and covers the sidewall of the second part to extend to one side of the active layer away from the substrate; the insulating layer group is arranged on one side of the blocking layer away from the substrate, and the blocking layer of the array substrate can protect the active layer.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to an array substrate and a display device. Background Technology

[0002] Oxide semiconductors are compound semiconductor materials formed by metals and oxygen (e.g., In, Ga, Zn, O). Oxide semiconductors conduct electricity through the electron orbitals formed by metal ions, exhibiting high mobility; furthermore, oxide semiconductor thin-film transistors have attracted widespread attention due to their advantages such as large-area fabrication capabilities.

[0003] However, refer to Figure 1 As shown, oxide semiconductor materials are quite sensitive to water vapor / hydrogen (Water (H2O), H+). After adsorbing water vapor, additional charge carriers e- will be generated, and the charge carrier concentration of active layer 6 will increase. This will lead to a negative bias in the threshold voltage (Vth) of the oxide semiconductor thin film transistor (TFT) device, causing a decrease in the stability of the oxide semiconductor thin film transistor, which will manifest as defects such as uneven sand (mura) and stains on the product.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide an array substrate and a display device.

[0006] According to one aspect of this disclosure, an array substrate is provided, comprising:

[0007] Substrate;

[0008] An active layer is disposed on one side of the substrate.

[0009] A first connecting conductor layer is disposed on the side of the active layer away from the substrate. The first connecting conductor layer includes a first connecting portion and a second connecting portion disposed at intervals. The first connecting portion includes a first part connected to the active layer. The second connecting portion includes a second part connected to the active layer.

[0010] The barrier layer includes a first barrier portion and a second barrier portion disposed at intervals. The first barrier portion is at least disposed on the side of the first portion away from the substrate and covers the sidewall of the first portion to extend to the side of the active layer away from the substrate. The second barrier portion is at least disposed on the side of the second portion away from the substrate and covers the sidewall of the second portion to extend to the side of the active layer away from the substrate.

[0011] An insulating layer group is disposed on the side of the barrier layer opposite to the substrate.

[0012] In one exemplary embodiment of this disclosure, a crack is formed on the insulating layer group, the crack being located on the insulating layer group opposite to the sidewall of the first connecting portion, and / or the crack being located on the insulating layer group opposite to the sidewall of the second connecting portion.

[0013] In one exemplary embodiment of this disclosure, the crack is located on the insulating layer group opposite to the first bottom end, the first bottom end being the end of the sidewall of the first connection portion near the substrate; and / or, the crack is located on the insulating layer group opposite to the second bottom end, the second bottom end being the end of the sidewall of the second connection portion near the substrate.

[0014] In one exemplary embodiment of this disclosure, the first blocking portion extends to the region between the first connecting portion and the second connecting portion, and the second blocking portion extends to the region between the first connecting portion and the second connecting portion.

[0015] In one exemplary embodiment of this disclosure, the barrier layer is made of metal.

[0016] In one exemplary embodiment of this disclosure, the first connecting conductor layer includes at least two stacked metal layers.

[0017] In one exemplary embodiment of this disclosure, the first blocking portion protrudes from the sidewall of the first portion in the extending direction of the sidewall of the first portion, and the second blocking portion protrudes from the sidewall of the second portion in the extending direction of the sidewall of the second portion.

[0018] In an exemplary embodiment of this disclosure, the orthographic projection of the first connecting portion on the substrate is located within the orthographic projection of the first blocking portion on the substrate, so that the first blocking portion covers the sidewall of the first connecting portion; the orthographic projection of the second connecting portion on the substrate is located within the orthographic projection of the second blocking portion on the substrate, so that the second blocking portion covers the sidewall of the second connecting portion.

[0019] In one exemplary embodiment of this disclosure, the first blocking portion extends beyond the minimum dimension of the first connecting portion by more than or equal to 1.0 μm and less than or equal to 2.0 μm; the second blocking portion extends beyond the minimum dimension of the second connecting portion by more than or equal to 1.0 μm and less than or equal to 2.0 μm.

[0020] In one exemplary embodiment of this disclosure, the minimum dimension of the distance between the first blocking portion and the second blocking portion is greater than or equal to 3 μm.

[0021] In one exemplary embodiment of this disclosure, the thickness of the barrier layer is greater than or equal to 10 nm.

[0022] In an exemplary embodiment of this disclosure, the distance between the sidewall of the first connecting portion and its center of mass in a first direction decreases as the height of the sidewall of the first connecting portion in a third direction increases, and the distance between the sidewall of the second connecting portion and its center of mass in the first direction decreases as the height of the sidewall of the second connecting portion in a third direction increases;

[0023] The first direction is parallel to the substrate, and the third direction is perpendicular to the substrate.

[0024] In one exemplary embodiment of this disclosure, the sidewall of the first connecting portion includes a first inclined surface, the angle between the first inclined surface and the substrate being greater than or equal to 30° and less than or equal to 70°; the sidewall of the second connecting portion includes a second inclined surface, the angle between the second inclined surface and the substrate being greater than or equal to 30° and less than or equal to 70°.

[0025] In one exemplary embodiment of this disclosure, the insulating layer group includes:

[0026] A first inorganic insulating layer is disposed on the side of the barrier layer away from the substrate.

[0027] The second inorganic insulating layer is disposed on the side of the first inorganic insulating layer away from the substrate.

[0028] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0029] A gate layer is disposed on one side of the substrate, the gate layer includes a gate and a gate line, the gate line extends along a first sub-direction, the first sub-direction being parallel to the substrate;

[0030] A gate insulating layer group is disposed between the gate layer and the active layer.

[0031] In one exemplary embodiment of this disclosure, the first connection conductor layer further includes a data line extending along a second sub-direction, the second connection portion being a part of the data line, the width of the second connection portion being less than the width of the data line, the second sub-direction being parallel to the substrate, and the second sub-direction intersecting the first sub-direction.

[0032] In an exemplary embodiment of this disclosure, the active layer includes a first conductor portion, a channel portion, and a second conductor portion connected in sequence, wherein the orthographic projection of the edge line of the second connection portion away from the first connection portion on the substrate coincides with the orthographic projection of the edge line of the second conductor portion away from the channel portion on the substrate.

[0033] Alternatively, the orthographic projection of the edge line of the second connection portion away from the first connection portion on the substrate is located on the side of the orthographic projection of the edge line of the second conductor portion away from the channel portion on the substrate closer to the channel portion.

[0034] In an exemplary embodiment of this disclosure, the portion where the orthographic projection of the gate on the substrate and the orthographic projection of the second connection portion on the substrate intersect is a first overlapping portion, and the orthographic projection of the first overlapping portion on the substrate is located within the orthographic projection of the active layer on the substrate.

[0035] The second blocking portion includes an extension portion, the orthographic projection of the extension portion on the substrate does not overlap with the orthographic projection of the gate on the substrate, the orthographic projection of the extension portion on the substrate does not overlap with the orthographic projection of the second connecting portion on the substrate, and the orthographic projection of the extension portion on the substrate overlaps with the orthographic projection of the active layer on the substrate.

[0036] According to another aspect of this disclosure, a display device is provided, comprising:

[0037] The array substrate is any one of the array substrates described above.

[0038] The array substrate disclosed herein can protect the active layer through a barrier layer, preventing moisture from entering the active layer. This avoids the active layer from absorbing moisture and causing additional charge carriers, thus ensuring the normal threshold voltage of the oxide semiconductor thin film transistor and thereby ensuring the stability of the oxide semiconductor thin film transistor. It also avoids defects such as unevenness (mura) and stains on the product.

[0039] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0040] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0041] Figure 1 This is a schematic diagram of the additional charge carriers generated after the active layer of an oxide semiconductor material adsorbs water vapor.

[0042] Figure 2 This is a schematic diagram of an example embodiment of the array substrate disclosed herein.

[0043] Figure 3 This is a schematic diagram of an electron microscope showing a crack formed on the insulating layer of an array substrate in a related technology.

[0044] Figure 4 This is a top view of the first exemplary embodiment of the array substrate disclosed herein.

[0045] Figure 5 This is a top view of a second exemplary embodiment of the array substrate disclosed herein.

[0046] Figure 6 This is a top view of a third exemplary embodiment of the array substrate disclosed herein.

[0047] Figure 7 This is a top view of the fourth exemplary embodiment of the array substrate disclosed herein.

[0048] Figure 8 This is a top view of the fifth exemplary embodiment of the array substrate disclosed herein.

[0049] Figure 9 This is a top view of the sixth exemplary embodiment of the array substrate disclosed herein.

[0050] Figure 10 This is a top view of the sixth exemplary embodiment of the array substrate disclosed herein.

[0051] Figures 11-14 A schematic diagram of the various steps involved in fabricating the barrier layer in the array substrate disclosed herein.

[0052] Figure 15 This is a schematic diagram of another example embodiment of the array substrate disclosed herein.

[0053] Figure 16 This is a schematic diagram of another example embodiment of the array substrate disclosed herein.

[0054] Explanation of reference numerals in the attached figures:

[0055] 1. Substrate;

[0056] 2. Light-blocking layer;

[0057] 3. Buffer layer;

[0058] 4. Gate layer; 41. Gate;

[0059] 5. Gate insulating layer group; 51. First gate insulating layer; 52. Second gate insulating layer;

[0060] 6. Active layer; 61. First conductor section; 62. Channel section; 63. Second conductor section;

[0061] 7. First connecting conductor layer; 7a. Metal layer; 71. First connecting portion; 711. First part; 712. First inclined surface; 72. Second connecting portion; 721. Second part; 722. Second inclined surface;

[0062] 8a. Barrier material layer; 8. Barrier layer; 81. First barrier portion; 82. Second barrier portion; 821. Extension portion;

[0063] 9. Insulation layer group; 91. First inorganic insulation layer; 92. Second inorganic insulation layer; 93. Crack;

[0064] Data, data line; Gate, gate line; PR, photoresist; PRT, photolithography pattern; JD, first overlapping portion;

[0065] X, first direction; X1, first sub-direction; X2, second sub-direction; Z, third direction. Detailed Implementation

[0066] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0067] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0068] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0069] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0070] This disclosure provides an array substrate according to exemplary embodiments, with reference to... Figure 2 , Figures 4-16As shown, the array substrate may include a substrate 1, an active layer 6, a first connecting conductor layer 7, a barrier layer 8, and an insulating layer group 9. The active layer 6 is disposed on one side of the substrate 1 and includes a first conductor portion 61, a channel portion 62, and a second conductor portion 63 connected in sequence. The first connecting conductor layer 7 is disposed on the side of the active layer 6 away from the substrate 1 and includes a first connecting portion 71 and a second connecting portion 72 spaced apart. The first connecting portion 71 includes a first part 711 connected to the first conductor portion 61, and the second connecting portion 72 includes a second part 72. The second part 721 is connected to the second conductor part 63; the barrier layer 8 may include a first barrier part 81 and a second barrier part 82 disposed at intervals. The first barrier part 81 is at least disposed on the side of the first part 711 away from the substrate 1, and covers the sidewall of the first part 711 to extend to the side of the active layer 6 away from the substrate 1; the second barrier part 82 is at least disposed on the side of the second part 721 away from the substrate 1, and covers the sidewall of the second part 721 to extend to the side of the active layer 6 away from the substrate 1; the insulating layer group 9 is disposed on the side of the barrier layer 8 away from the substrate 1.

[0071] The array substrate disclosed herein can protect the active layer 6 through the barrier layer 8, preventing moisture from entering the active layer 6. This avoids the active layer 6 from absorbing moisture and causing additional charge carriers, thus ensuring the normal threshold voltage of the oxide semiconductor thin film transistor and thereby ensuring the stability of the oxide semiconductor thin film transistor. It also avoids defects such as unevenness (mura) and stains on the product.

[0072] In this exemplary embodiment, the material of the substrate 1 may include inorganic materials, such as glass, quartz, or metal. The material of the substrate 1 may also include organic materials, such as resins like polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The substrate 1 may be formed from multiple material layers; for example, the substrate 1 may include multiple substrate layers, and the substrate layers may be made of any of the materials described above. Of course, the substrate 1 may also be a single layer, and may be any of the materials described above.

[0073] Reference Figure 2 As shown, a light-shielding layer 2 can be disposed on one side of the substrate 1. Light incident from the substrate 1 into the active layer 6 will generate photogenerated carriers in the active layer 6, which will have a significant impact on the characteristics of the thin-film transistor and ultimately affect the display quality of the display device. The light-shielding layer 2 can block the light incident from the substrate 1, thereby avoiding the impact on the characteristics of the thin-film transistor and the display quality of the display device. Depending on the type of thin-film transistor or the process conditions, the light-shielding layer 2 can be omitted.

[0074] Reference Figure 2 As shown, a buffer layer 3 can be disposed on the side of the light-shielding layer 2 facing away from the substrate 1. The buffer layer 3 serves to block moisture and impurity ions in the substrate 1 (especially organic materials) and to increase hydrogen ions for the subsequently formed active layer 6. The buffer layer 3 is made of an insulating material to insulate the light-shielding layer 2 from the active layer 6. The buffer layer 3 may include silicon nitride, silicon oxide, or silicon oxynitride. Depending on the type of thin-film transistor or process conditions, the buffer layer 3 may be omitted.

[0075] Reference Figure 2 As shown, a gate layer 4 is disposed on the side of the buffer layer 3 facing away from the substrate 1. The gate layer 4 may include interconnected gates 41 and gate lines. The gate lines extend along a first sub-direction X1. A gate insulating layer group 5 is disposed on the side of the gate layer 4 facing away from the substrate 1. Specifically, the gate insulating layer group 5 may include a first gate insulating layer 51 and a second gate insulating layer 52. The first gate insulating layer 51 is disposed on the side of the gate layer 4 facing away from the substrate 1, and the second gate insulating layer 52 is disposed on the side of the first gate insulating layer 51 facing away from the substrate 1. The material of the first gate insulating layer 51 may be, but is not limited to, silicon nitride, and the material of the second gate insulating layer 52 may be, but is not limited to, silicon oxide.

[0076] Of course, in some other exemplary embodiments of this disclosure, the gate insulating layer group 5 may include only one first gate insulating layer 51, and the gate insulating layer group 5 may include only one second gate insulating layer 52; the gate insulating layer group 5 may also include three insulating layers, that is, a third gate insulating layer is provided on the side of the second gate insulating layer 52 away from the substrate 1, and the material of the third gate insulating layer may be, but is not limited to, silicon nitride, silicon oxynitride, etc.

[0077] Reference Figure 2 As shown, an active layer 6 is provided on the side of the gate insulating layer group 5 facing away from the substrate 1. The active layer 6 may include a first conductor portion 61, a channel portion 62, and a second conductor portion 63 connected in sequence. When the area of ​​the gate 41 is large, the gate 41 can block the channel portion 62, preventing light from entering the channel portion 62 from the substrate 1, thereby avoiding affecting the characteristics of the thin film transistor and ensuring the display quality of the display device. The light-shielding layer 2 can be omitted. When the area of ​​the gate 41 is small, the gate 41 and the light-shielding layer 2 together block the channel portion 62, preventing light from entering the channel portion 62 from the substrate 1, thereby avoiding affecting the characteristics of the thin film transistor and ensuring the display quality of the display device.

[0078] The active layer 6 can be made of metal oxide semiconductor material, which may include any one or more of indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), and rare earth element doped metal oxide (RE-OS), wherein the rare earth element doped metal oxide may include lanthanide doped metal oxide (Ln-OS); the crystallization state of the active layer 6 material may be amorphous, partially crystalline, or polycrystalline.

[0079] Reference Figure 2 As shown, a first connecting conductor layer 7 is provided on the side of the active layer 6 facing away from the substrate 1. The first connecting conductor layer 7 may include a first connecting portion 71 and a second connecting portion 72 disposed at intervals, with a gap between the first connecting portion 71 and the second connecting portion 72, meaning there is no connection between the first connecting portion 71 and the second connecting portion 72. The first connecting portion 71 may include a first part 711, which is connected to the active layer 6. Specifically, the first part 711 is connected to the side of the active layer 6 facing away from the substrate 1, meaning the first part 711 is the portion of the first connecting portion 71 provided on the side of the active layer 6 facing away from the substrate 1. The first part 711 is connected to the first conductor portion 61 of the active layer 6, enabling current to flow between the first part 711 and the first conductor portion 61. The second connection portion 72 may include a second portion 721, which is connected to the active layer 6. Specifically, the second portion 721 is connected to the side of the active layer 6 away from the substrate 1, that is, the second portion 721 is the part of the second connection portion 72 provided on the side of the active layer 6 away from the substrate 1. The second portion 721 is connected to the second conductor portion 63 of the active layer 6, so that current can be conducted between the second portion 721 and the second conductor portion 63.

[0080] A thin-film transistor is formed by a gate 41, an active layer 6, a first connection portion 71, and a second connection portion 72. The first connection portion 71 can be the source, and the second connection portion 72 can be the drain.

[0081] It should be noted that the thin-film transistor described in this specification is a bottom-gate thin-film transistor. In other exemplary embodiments of this disclosure, the thin-film transistor may also be a top-gate or dual-gate type, and its specific structure will not be described in detail here. Moreover, in cases where thin-film transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged, that is, the first connection portion 71 may be the drain and the second connection portion 72 may be the source.

[0082] In this example embodiment, the blocking layer 8 may include a first blocking portion 81 and a second blocking portion 82 that are spaced apart, with a gap between the first blocking portion 81 and the second blocking portion 82, that is, there is no connection between the first blocking portion 81 and the second blocking portion 82.

[0083] The first blocking portion 81 is at least provided on the side of the first portion 711 away from the substrate 1, and covers the sidewall of the first portion 711 to extend to the side of the active layer 6 away from the substrate 1; that is, the first blocking portion 81 extends from the side of the first portion 711 away from the substrate 1 to cover the sidewall of the first portion 711, and extends to the side of the active layer 6 away from the substrate 1.

[0084] The second blocking portion 82 is at least provided on the side of the second portion 721 away from the substrate 1, and covers the sidewall of the second portion 721 to extend to the side of the active layer 6 away from the substrate 1; that is, the first blocking portion 81 extends from the side of the first portion 711 away from the substrate 1 to cover the sidewall of the first portion 711, and extends to the side of the active layer 6 away from the substrate 1.

[0085] An insulating layer group 9 is disposed on the side of the barrier layer 8 facing away from the substrate 1. Cracks 93 are easily generated on the insulating layer group 9. For example, cracks 93 are formed in a part of the insulating layer group 9 and extend to the active layer 6; cracks 93 are not formed in a part of the insulating layer group 9; cracks 93 are formed in almost the entire area of ​​the insulating layer group 9 and extend to the active layer 6; almost no cracks 93 are formed on the insulating layer group 9. Moisture can penetrate into the active layer 6 through the cracks 93 on the insulating layer group 9. After the active layer 6 absorbs moisture, it will generate additional charge carriers, which will cause the threshold voltage (Vth) of the oxide semiconductor thin film transistor (TFT) device to be negatively biased, causing the stability of the oxide semiconductor thin film transistor to decrease, and exhibiting defects such as murmur and stains on the product.

[0086] The barrier layer 8 protects the active layer 6, preventing moisture from entering the active layer 6 through the crack 93 on the insulating layer group 9. This prevents the active layer 6 from absorbing moisture and causing additional charge carriers, ensuring the normal threshold voltage of the oxide semiconductor thin film transistor, thereby ensuring the stability of the oxide semiconductor thin film transistor and avoiding defects such as uneven sand (mura) and stains on the product.

[0087] Reference Figure 3 As shown, Figure 3In this diagram, Gate 41 is the gate electrode, GI is the gate insulating layer group 5, Oxide is the active layer 6, SD is the first interconnect conductor layer 7, and PVX is the insulating layer group 9. The inventors discovered that cracks 93 are more likely to form on the insulating layer group 9 opposite to the sidewalls of the first connection portion 71 and the second connection portion 72. For example, cracks 93 may be located on the insulating layer group 9 opposite to the sidewall of the first connection portion 71, or cracks 93 may be located on the insulating layer group 9 opposite to the sidewall of the second connection portion 72, or a portion of cracks 93 may be located on the insulating layer group 9 opposite to the sidewall of the first connection portion 71, and another portion of cracks 93 may be located on the insulating layer group 9 opposite to the sidewall of the second connection portion 72.

[0088] The inventors further discovered that a large portion of the cracks 93 are located on the insulating layer group 9 opposite to the first bottom end, the first bottom end being the end of the sidewall of the first connecting portion 71 near the substrate 1; and another large portion of the cracks 93 are located on the insulating layer group 9 opposite to the second bottom end, the second bottom end being the end of the sidewall of the second connecting portion 72 near the substrate 1.

[0089] This allows moisture to more easily penetrate the active layer 6 through crack 93. The adsorption of moisture in the active layer 6 generates additional charge carriers, which leads to a negative bias in the threshold voltage (Vth) of the oxide semiconductor thin film transistor (TFT) device. This causes a decrease in the stability of the oxide semiconductor thin film transistor and manifests as defects such as uneven sand inclusions and stains on the product.

[0090] Reference Figure 2 As shown, the first blocking portion 81 is disposed on the side of the first portion 711 away from the substrate 1, and covers the sidewall of the first portion 711 to extend to the side of the active layer 6 away from the substrate 1. This allows the first blocking portion 81 to block the crack 93 on the insulating layer group 9 opposite to the sidewall of the first connecting portion 71, thereby preventing moisture from entering the active layer 6 through the crack 93 on the insulating layer group 9 opposite to the sidewall of the first connecting portion 71. This prevents the active layer 6 from absorbing moisture and causing additional charge carriers, ensuring the normal threshold voltage of the oxide semiconductor thin film transistor, thereby ensuring the stability of the oxide semiconductor thin film transistor and avoiding defects such as uneven sand (mura) and stains on the product.

[0091] Alternatively, the first blocking portion 81 can extend to the area between the first connecting portion 71 and the second connecting portion 72, so that the first blocking portion 81 can block the crack 93 located on the insulating layer group 9 opposite to the first bottom end, thereby preventing water vapor from entering the active layer 6 through the crack 93 located on the insulating layer group 9 opposite to the first bottom end, thereby preventing the active layer 6 from absorbing water vapor and causing additional charge carriers, so as to ensure the normal threshold voltage of the oxide semiconductor thin film transistor, thereby ensuring the stability of the oxide semiconductor thin film transistor and avoiding defects such as uneven sand (mura) and stains on the product.

[0092] The second blocking portion 82 is disposed on the side of the second portion 721 away from the substrate 1 and covers the sidewall of the second portion 721 to extend to the side of the active layer 6 away from the substrate 1. This allows the second blocking portion 82 to block the crack 93 on the insulating layer group 9 opposite to the sidewall of the second connecting portion 72, thereby preventing moisture from entering the active layer 6 through the crack 93 on the insulating layer group 9 opposite to the sidewall of the second connecting portion 72. This prevents the active layer 6 from absorbing moisture and causing additional charge carriers, ensuring the normal threshold voltage of the oxide semiconductor thin film transistor, thereby ensuring the stability of the oxide semiconductor thin film transistor and avoiding defects such as unevenness (mura) and stains on the product.

[0093] Alternatively, the second blocking portion 82 may also extend to the area between the first connecting portion 71 and the second connecting portion 72, so that the second blocking portion 82 can block the crack 93 located on the insulating layer group 9 opposite to the second bottom end, thereby preventing water vapor from entering the active layer 6 through the crack 93 located on the insulating layer group 9 opposite to the second bottom end, thereby preventing the active layer 6 from absorbing water vapor and causing additional charge carriers, so as to ensure the normal threshold voltage of the oxide semiconductor thin film transistor, thereby ensuring the stability of the oxide semiconductor thin film transistor and avoiding defects such as uneven sand (mura) and stains on the product.

[0094] Specifically, refer to Figure 4 As shown, the first blocking portion 81 may only cover a portion of the first portion 711, specifically, the first blocking portion 81 may only cover a portion of the first portion 711 near the channel portion 62. The second blocking portion 82 may also only cover a portion of the second portion 721, specifically, the second blocking portion 82 may only cover a portion of the second portion 721 near the channel portion 62.

[0095] Of course, refer to Figure 5 As shown, the first blocking part 81 can cover the entire first part 711, and the second blocking part 82 can also cover the entire second part 721.

[0096] Reference Figures 4-10As shown, the first blocking portion 81 protrudes beyond the sidewall of the first portion 711 in the extending direction of the sidewall, and the second blocking portion 82 protrudes beyond the sidewall of the second portion 721 in the extending direction of the sidewall. This allows the first blocking portion 81 and the second blocking portion 82 to provide better protection for the active layer 6, further preventing moisture from penetrating the active layer 6 through the crack 93 on the insulating layer group 9. This prevents the active layer 6 from absorbing moisture and generating additional charge carriers, ensuring the normal threshold voltage of the oxide semiconductor thin film transistor, thereby ensuring the stability of the oxide semiconductor thin film transistor and avoiding defects such as unevenness (mura) and stains on the product.

[0097] The barrier layer 8 is made of metal, which is generally a conductive material. For example, the barrier layer 8 can be made of copper, silver, molybdenum, titanium, molybdenum-niobium alloy, molybdenum-titanium alloy, molybdenum-titanium-nickel alloy, etc. If the first barrier portion 81 and the second barrier portion 82 of the barrier layer 8 are connected to each other, the first portion 711 and the second portion 721 of the first connecting conductor layer 7 will be connected through the barrier layer 8, thereby connecting the first connecting portion 71 and the second connecting portion 72 of the first connecting conductor layer 7, which will cause the two electrodes (source and drain) of the oxide semiconductor thin film transistor to connect and cause a short circuit.

[0098] The first blocking portion 81 and the second blocking portion 82 are spaced apart to prevent the first connecting portion 71 and the second connecting portion 72 of the first connecting conductor layer 7 from being connected through the blocking layer 8, thereby preventing the two electrodes (source and drain) of the oxide semiconductor thin film transistor from being connected and causing a short circuit, thus ensuring the performance of the oxide semiconductor thin film transistor.

[0099] The first connecting conductor layer may include at least two stacked metal layers 7a.

[0100] Reference Figure 15 As shown, the first connecting conductor layer 7 may include three stacked metal layers 7a, that is, the first connecting portion 71 may include three stacked metal layers 7a, and the second connecting portion 72 may also include three stacked metal layers 7a.

[0101] For example, the first connecting conductor layer 7 may include stacked MoNb (molybdenum-niobium alloy), Cu and MoNb, or stacked MoTi (molybdenum-titanium alloy), Cu and MoTi, or stacked MoNb, Cu and MTD (molybdenum-titanium-nickel alloy).

[0102] Reference Figure 16As shown, the first connecting conductor layer 7 may include two stacked metal layers 7a, that is, the first connecting portion 71 may include two stacked metal layers 7a, and the second connecting portion 72 may also include two stacked metal layers 7a.

[0103] For example, the first connecting conductor layer 7 may include stacked MoNb and Cu, or stacked MoTi and Cu. When the barrier layer 8 is made of a molybdenum-niobium alloy, a molybdenum-titanium alloy, or a molybdenum-titanium-nickel alloy, it is equivalent to forming the first connecting conductor layer 7 and the barrier layer 8 by two patterning processes, where the three metal layers 7a are stacked.

[0104] Optionally, refer to Figures 6-10 As shown, the orthographic projection of the first connecting portion 71 on the substrate 1 is located within the orthographic projection of the first blocking portion 81 on the substrate 1, that is, the area of ​​the orthographic projection of the first connecting portion 71 on the substrate 1 is larger than the area of ​​the orthographic projection of the first blocking portion 81 on the substrate 1, and the orthographic projection of the first blocking portion 81 on the substrate 1 completely covers the orthographic projection of the first connecting portion 71 on the substrate 1; so that the first blocking portion 81 covers the sidewall of the first connecting portion 71, that is, the first blocking portion 81 not only covers the side of the first connecting portion 71 away from the substrate 1, but also covers the sidewall of the first connecting portion 71; where the active layer 6 is provided, the first blocking portion 81 also extends to the side of the active layer 6 away from the substrate 1, and where the active layer 6 is not provided, the first blocking portion 81 also extends to the side of the gate insulating layer group 5 away from the substrate 1.

[0105] The orthographic projection of the second connecting portion 72 on the substrate 1 is located within the orthographic projection of the second blocking portion 82 on the substrate 1, that is, the area of ​​the orthographic projection of the second connecting portion 72 on the substrate 1 is larger than the area of ​​the orthographic projection of the second blocking portion 82 on the substrate 1, and the orthographic projection of the second blocking portion 82 on the substrate 1 completely covers the orthographic projection of the second connecting portion 72 on the substrate 1; so that the second blocking portion 82 covers the sidewall of the second connecting portion 72, that is, the second blocking portion 82 not only covers the side of the second connecting portion 72 away from the substrate 1, but also covers the sidewall of the second connecting portion 72; where the active layer 6 is provided, the second blocking portion 82 also extends to the side of the active layer 6 away from the substrate 1, and where the active layer 6 is not provided, the second blocking portion 82 also extends to the side of the gate insulating layer group 5 away from the substrate 1.

[0106] This configuration allows almost all cracks 93 on the insulating layer group 9 to be blocked by the first blocking portion 81 and the second blocking portion 82, providing better protection for the active layer 6. It further prevents moisture from penetrating the active layer 6 through the cracks 93 on the insulating layer group 9, thus preventing the active layer 6 from absorbing moisture and generating additional charge carriers. This ensures the normal threshold voltage of the oxide semiconductor thin-film transistor, thereby guaranteeing the stability of the oxide semiconductor thin-film transistor and preventing defects such as murmurs and stains on the product. Moreover, it avoids accidental etching of the first connection portion 71 and the second connection portion 72 during the etching process of forming the first blocking portion 81 and the second blocking portion 82, which could affect the conductivity of the first connection portion 71 and the second connection portion 72. Additionally, increasing the area of ​​the first blocking portion 81 and the second blocking portion 82 can further reduce the resistance of the first connection portion 71 and the second connection portion 72, reducing the power consumption of the array substrate.

[0107] Alternatively, the minimum dimension of the first blocking portion 81 extending beyond the first connecting portion 71 may be greater than or equal to 1.0 μm and less than or equal to 2.0 μm; for example, the minimum dimension of the first blocking portion 81 extending beyond the first connecting portion 71 may be 1.2 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.9 μm, etc.

[0108] If the first blocking portion 81 is too small beyond the minimum size of the first connecting portion 71, moisture will still penetrate the active layer 6 through the crack 93 when the crack 93 is formed on the insulating layer group 9 opposite to the bottom of the sidewall of the first connecting portion 71.

[0109] If the first blocking portion 81 exceeds the minimum size of the first connecting portion 71 by too much, the minimum size of the gap between the first blocking portion 81 and the second blocking portion 82 will be too small, which will easily cause a breakdown between the first blocking portion 81 and the second blocking portion 82, resulting in the failure of the thin film transistor.

[0110] The above-mentioned numerical range not only ensures that water vapor will not penetrate the active layer 6 through the crack 93, but also ensures that there will be no breakdown between the first barrier 81 and the second barrier 82, so as to ensure the performance of the thin film transistor.

[0111] The minimum dimension of the second blocking portion 82 extending beyond the second connecting portion 72 is greater than or equal to 1.0 μm and less than or equal to 2.0 μm; for example, the minimum dimension of the second blocking portion 82 extending beyond the second connecting portion 72 may be 1.2 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.9 μm, etc.

[0112] If the second blocking portion 82 is too small beyond the minimum size of the second connecting portion 72, moisture will still penetrate the active layer 6 through the crack 93 when the crack 93 is formed on the insulating layer group 9 opposite to the bottom of the sidewall of the second connecting portion 72.

[0113] If the second blocking portion 82 exceeds the minimum size of the second connecting portion 72 by too much, the minimum size of the gap between the first blocking portion 81 and the second blocking portion 82 will be too small, which will easily cause breakdown between the first blocking portion 81 and the second blocking portion 82, resulting in the failure of the thin film transistor.

[0114] The above-mentioned numerical range not only ensures that water vapor will not penetrate the active layer 6 through the crack 93, but also ensures that there will be no breakdown between the first barrier 81 and the second barrier 82, so as to ensure the performance of the thin film transistor.

[0115] Alternatively, the minimum size of the distance between the first blocking part 81 and the second blocking part 82 is greater than or equal to 3μm. For example, the minimum size of the distance between the first blocking part 81 and the second blocking part 82 can be 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, etc.

[0116] If the minimum size of the gap between the first blocking part 81 and the second blocking part 82 is too small, it will be easy for the first blocking part 81 and the second blocking part 82 to break down, resulting in the failure of the thin film transistor.

[0117] The above numerical range ensures that water vapor will not penetrate the active layer 6 through crack 93.

[0118] With a fixed size for the active layer 6, the distance between the first blocking part 81 and the second blocking part 82 is mutually constrained by the minimum size by which the first blocking part 81 exceeds the first connecting part 71 and the minimum size by which the second blocking part 82 exceeds the second connecting part 72. The distance between the first blocking part 81 and the second blocking part 82 cannot be too large. If the distance between the first blocking part 81 and the second blocking part 82 is too large, it is easy to cause the minimum size by which the first blocking part 81 exceeds the first connecting part 71 to be too small and / or the minimum size by which the second blocking part 82 exceeds the second connecting part 72 to be too small. When the crack 93 is formed on the insulating layer group 9 opposite to the bottom of the sidewall of the first connecting part 71, water vapor will still enter the active layer 6 through the crack 93 there. When the crack 93 is formed on the insulating layer group 9 opposite to the bottom of the sidewall of the second connecting part 72, water vapor will still enter the active layer 6 through the crack 93 there.

[0119] Alternatively, the thickness of the barrier layer 8 may be greater than or equal to 10 nm. For example, the thickness of the barrier layer 8 may be 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc.

[0120] If the thickness of the barrier layer 8 is too small, it will be difficult for the barrier layer 8 to form a relatively uniform film. Even if the barrier layer 8 is easy to form a hollow structure, the effect of the barrier layer 8 in protecting the active layer 6 cannot be guaranteed.

[0121] The above numerical range can ensure the effectiveness of the barrier layer 8 in protecting the active layer 6.

[0122] Of course, the thickness of the barrier layer 8 should not be too large. If the thickness of the barrier layer 8 is too large, it will not be conducive to the thin and light design of the array substrate, and it will not be conducive to ensuring the bending performance of the flexible array substrate.

[0123] Reference Figure 11 – Figure 14 As shown, the barrier layer 8 can be formed by photolithography. Specifically, refer to... Figure 11 As shown, a barrier material layer 8a is formed on the side of the first connecting conductor layer 7 facing away from the substrate 1; Refer to Figure 12 As shown, photoresist PR is formed on the side of the barrier material layer 8a facing away from the substrate 1; (Refer to...) Figure 13 As shown, the photoresist PR is exposed and developed to form the photolithographic pattern PRT; refer to Figure 14 As shown, the barrier layer 8 is formed by etching the barrier material layer 8a using the photolithographic pattern PRT as a mask; finally, the photolithographic pattern PRT is removed by peeling to form the barrier layer 8. Figure 1 The structure of the barrier layer 8 shown.

[0124] Optionally, refer to Figure 2 As shown, the distance between the sidewall of the first connecting portion 71 and its centroid in the first direction X decreases as the height of the sidewall of the first connecting portion 71 in the third direction Z increases. That is, the first connecting portion 71 has a first surface and a second surface disposed opposite to each other, with the first surface being closer to the substrate 1 than the second surface, and the area of ​​the first surface being smaller than the area of ​​the second surface. This results in the first connecting portion 71 having a structure where the top is smaller than the bottom.

[0125] In some exemplary embodiments of this disclosure, the sidewall of the first connecting portion 71 may include a curved surface; the sidewall of the first connecting portion 71 may include a first wall surface, a second wall surface, and a third wall surface that are smoothly connected in sequence, the first wall surface being closer to the substrate 1 than the third wall surface, the second wall surface being configured as an inclined surface, the first wall surface and the third wall surface being configured as arc surfaces, the first wall surface being configured as a recessed shape, and the third wall surface being configured as a protruding shape; specifically, the portion of the sidewall of the first connecting portion 71 that is close to the substrate 1 may be an arc surface, the middle portion of the sidewall of the first connecting portion 71 may be configured as an inclined surface, and the portion of the sidewall of the first connecting portion 71 that is away from the substrate 1 may be an arc surface.

[0126] In some other exemplary embodiments of this disclosure, the sidewall of the first connecting portion 71 may be configured as an inclined surface. The sidewall of the first connecting portion 71 may consist only of a first wall surface and a third wall surface that are smoothly connected, but the sidewall of the first connecting portion 71 is generally inclined.

[0127] The above structure makes the sidewall of the first connecting part 71 include a first inclined surface 712, and the angle between the first inclined surface 712 and the substrate 1 is greater than or equal to 30° and less than or equal to 70°. For example, the angle between the first inclined surface 712 and the substrate 1 can be 35°, 40°, 45°, 50°, 55°, 60°, 65°, etc.

[0128] If the angle between the first inclined surface 712 and the substrate 1 is too large, making the first inclined surface 712 almost perpendicular to the substrate 1, when the first blocking part 81 covers the first inclined surface 712, it cannot fill the corner formed by the first inclined surface 712 and the active layer 6. That is, a gap is easily formed at the corner formed by the first inclined surface 712 and the active layer 6, and the crack 93 may extend into the gap, causing the first blocking part 81 to fail to play a good protective role.

[0129] If the angle between the first inclined surface 712 and the substrate 1 is too small, it will be difficult to achieve in terms of process.

[0130] The above-mentioned numerical range not only ensures that the first blocking part 81 can fill to the corner formed by the first inclined surface 712 and the active layer 6, thus ensuring the protective effect of the first blocking part 81 on the active layer 6, but also makes it easier to implement in terms of process.

[0131] In addition, it should be noted that the angle between the first inclined surface 712 and the substrate 1 is the angle in general products. In some other products, the angle between the first inclined surface 712 and the substrate 1 can be larger or smaller.

[0132] Optionally, refer to Figure 2 As shown, the distance between the sidewall of the second connecting portion 72 and its centroid in the first direction X decreases as the height of the sidewall of the second connecting portion 72 in the third direction Z increases. That is, the second connecting portion 72 has a third surface and a fourth surface disposed opposite to each other, with the third surface being closer to the substrate 1 than the fourth surface, and the area of ​​the third surface being smaller than the area of ​​the fourth surface. This results in the second connecting portion 72 having a structure where the top is smaller than the bottom.

[0133] In some exemplary embodiments of this disclosure, the sidewall of the second connecting portion 72 may include a curved surface; the sidewall of the second connecting portion 72 may include a fourth wall surface, a fifth wall surface, and a sixth wall surface that are smoothly connected in sequence, the fourth wall surface being closer to the substrate 1 than the sixth wall surface, the fifth wall surface being a slope, and the fourth and sixth wall surfaces being arc surfaces, the fourth wall surface being recessed and the sixth wall surface being protruding; specifically, the portion of the sidewall of the second connecting portion 72 that is close to the substrate 1 may be an arc surface, the middle portion of the sidewall of the second connecting portion 72 may be a slope, and the portion of the sidewall of the second connecting portion 72 that is away from the substrate 1 may be an arc surface.

[0134] In some other exemplary embodiments of this disclosure, the sidewall of the second connecting portion 72 may be configured as an inclined surface, and the sidewall of the second connecting portion 72 may only include a smoothly connected fourth wall surface and a sixth wall surface, but the sidewall of the second connecting portion 72 is generally inclined.

[0135] The above structure makes the sidewall of the second connecting part 72 include a second inclined surface 722, and the angle between the second inclined surface 722 and the substrate 1 is greater than or equal to 30° and less than or equal to 70°. For example, the angle between the second inclined surface 722 and the substrate 1 can be 35°, 40°, 45°, 50°, 55°, 60°, 65°, etc.

[0136] If the angle between the second inclined surface 722 and the substrate 1 is too large, making the second inclined surface 722 almost perpendicular to the substrate 1, when the second blocking part 82 covers the second inclined surface 722, it cannot fill the corner formed by the second inclined surface 722 and the active layer 6. That is, a gap is easily formed at the corner formed by the second inclined surface 722 and the active layer 6, and the crack 93 may extend into the gap, causing the second blocking part 82 to fail to play a good protective role.

[0137] If the angle between the second inclined plane 722 and the substrate 1 is too small, it will be difficult to achieve in terms of process.

[0138] The above-mentioned numerical range not only ensures that the second blocking part 82 can fill to the corner formed by the second inclined surface 722 and the active layer 6, thus ensuring the protective effect of the second blocking part 82 on the active layer 6, but also makes it easier to implement in terms of process.

[0139] In addition, it should be noted that the angle between the second inclined surface 722 and the substrate 1 is the angle in general products. In some other products, the angle between the second inclined surface 722 and the substrate 1 can be larger or smaller.

[0140] It should be noted that the so-called "center of mass," also known as the centroid, is the center of mass of all points on an object or shape, or it can be considered as the point of application of the resultant force of gravity acting on the object or shape. In a homogeneous object, the center of mass coincides with the centroid. For a regular object, its center of mass is located at the geometric center of the object.

[0141] In this disclosure, the first direction X is parallel to the substrate 1, that is, the first direction X is an infinite number of directions parallel to the substrate 1, the first sub-direction X1 is one of the directions of the first direction X, the second sub-direction X2 is also one of the directions of the first direction X, the first sub-direction X1 and the second sub-direction X2 intersect, for example, the first sub-direction X1 and the second sub-direction X2 are perpendicular; the third direction Z is perpendicular to the substrate 1.

[0142] In some exemplary embodiments of this disclosure, the insulating layer group 9 may include a first inorganic insulating layer 91 and a second inorganic insulating layer 92. The first inorganic insulating layer 91 is disposed on the side of the barrier layer 8 facing away from the substrate 1; the second inorganic insulating layer 92 is disposed on the side of the first inorganic insulating layer 91 facing away from the substrate 1. The material of the first inorganic insulating layer 91 may be, but is not limited to, silicon oxide, and the material of the second inorganic insulating layer 92 may be, but is not limited to, silicon nitride. Of course, in some other exemplary embodiments of this disclosure, the materials of the first inorganic insulating layer 91 and the second inorganic insulating layer 92 may be interchanged; the insulating layer group 9 may also include only the first inorganic insulating layer 91, or only the second inorganic insulating layer 92; the insulating layer group 9 may also include three or more inorganic insulating layers.

[0143] The film structure of the array substrate has been described above. The top view structure of the array substrate will be described below.

[0144] Reference Figures 4-10 As shown, the gate 41 can be rectangular, with one side of the gate 41 connected to the gate line, making the gate 41 a rectangular extension protruding along the second sub-direction X2 connected to the gate line. Of course, the gate 41 can also be configured with other structures, which will not be elaborated here.

[0145] The active layer 6 can be configured as a strip extending along the first sub-direction X1; for example, the active layer 6 can be configured as a rectangle extending along the first sub-direction X1. (See reference...) Figure 6 , Figure 8 and Figure 9As shown, a portion of the orthographic projection of the active layer 6 on the substrate 1 may overlap with a portion of the orthographic projection of the gate 41 on the substrate 1. Specifically, the orthographic projections of the channel portion 62 and the second conductor portion 63 of the active layer 6 on the substrate 1 may overlap with the orthographic projection of the gate 41 on the substrate 1. A portion of the orthographic projection of the first conductor portion 61 of the active layer 6 on the substrate 1 may overlap with the orthographic projection of the gate 41 on the substrate 1, while another portion of the orthographic projection of the first conductor portion 61 on the substrate 1 may not overlap with the orthographic projection of the gate 41 on the substrate 1.

[0146] Reference Figure 7 and Figure 10 As shown, the orthogonal projection of the active layer 6 on the substrate 1 can be located within the orthogonal projection of the gate 41 on the substrate 1.

[0147] In some exemplary embodiments of this disclosure, reference is made to Figure 6 and Figure 7 As shown, the first connecting conductor layer 7 may also include a data line Data, which extends along the second sub-direction X2. The second connecting portion 72 may be a part of the data line Data, that is, a part of the data line Data is used as the second connecting portion 72, so that the second connecting portion 72 is directly connected to the data line Data. The width of the second connecting portion 72 is smaller than the width of the data line Data, thereby reducing the overlap area between the second connecting portion 72 and the gate 41 and reducing parasitic capacitance.

[0148] Optionally, refer to Figure 6 and Figure 7 As shown, the orthographic projection of the edge line of the second connecting portion 72 away from the first connecting portion 71 on the substrate 1 can coincide with the orthographic projection of the edge line of the second conductor portion 63 away from the channel portion 62 on the substrate 1. This arrangement reduces the overlap area, thereby reducing parasitic capacitance.

[0149] Optionally, refer to Figures 8-10 As shown, the orthographic projection of the edge line of the second connection portion 72 away from the first connection portion 71 onto the substrate 1 is located on the side of the orthographic projection of the edge line of the second conductor portion 63 away from the channel portion 62 onto the substrate 1 closer to the channel portion 62, thus making the second connection portion 72 protrude beyond the data line Data in the first sub-direction X1. With this configuration, even if there is a misalignment during the formation of the first connection conductor layer, the connection between the second connection portion 72 and the active layer 6 can be guaranteed.

[0150] In some exemplary embodiments of this disclosure, reference is made to Figure 8 and Figure 9As shown in the figure, the first overlapping portion JD is represented by a dashed line; the first overlapping portion JD is the part where the orthographic projection of the gate 41 on the substrate 1 and the orthographic projection of the second connection portion 72 on the substrate 1 intersect. The orthographic projection of the first overlapping portion JD on the substrate 1 is located within the orthographic projection of the active layer 6 on the substrate.

[0151] Alternatively, the edge of the orthographic projection of the first overlapping portion JD on the substrate 1 has a non-zero spacing with the edge of the orthographic projection of the active layer 6 on the substrate, that is, the orthographic projection of the active layer 6 on the substrate covers and is larger than the orthographic projection of the first overlapping portion JD on the substrate 1.

[0152] In this way, the gate insulating layer group 5 and the active layer 6 are present between the gate 41 and the second connection portion 72 in the third direction Z, thereby increasing the vertical distance between the gate 41 and the second connection portion 72 and increasing the electron movement distance. Even if there are impurity particles in the gate insulating layer group 5, the active layer 6 on the upper side of the gate insulating layer group 5 is still an insulating layer, thereby preventing the gate 41 and the second connection portion 72 from short-circuiting. This effectively reduces the incidence of gate and source-drain short-circuit defects (DGS issues) in thin-film transistors and improves the quality of thin-film transistors.

[0153] The second blocking portion 82 may include an extension portion 821, which is a part of the portion of the second blocking portion 82 that extends beyond the second connecting portion 72. Therefore, the orthographic projection of the extension portion 821 on the substrate 1 does not overlap with the orthographic projection of the second connecting portion 72 on the substrate 1.

[0154] The orthographic projection of the extended portion 821 on the substrate 1 does not overlap with the orthographic projection of the gate 41 on the substrate 1, but the orthographic projection of the extended portion 821 on the substrate 1 overlaps with the orthographic projection of the active layer 6 on the substrate 1. The active layer 6 can isolate the extended portion 821 from the gate 41. In the third direction Z, the gate insulating layer group 5 and the active layer 6 are present between the gate 41 and the extended portion 821, thereby increasing the vertical distance between the gate 41 and the extended portion 821 and increasing the electron movement distance. Even if there are impurity particles in the gate insulating layer group 5, the active layer 6 on the upper side of the gate insulating layer group 5 is still an insulating layer, thereby preventing the gate 41 and the extended portion 821 from short-circuiting, thereby preventing the gate 41 and the second connection portion 72 from short-circuiting, effectively reducing the occurrence rate of gate and source-drain short-circuit defects (DGS Issue) of thin film transistors and improving the quality of thin film transistors.

[0155] Based on the same inventive concept, this disclosure provides a display device that may include the array substrate described in any of the above-described embodiments. The specific structure of the array substrate has been described in detail above, and therefore will not be repeated here.

[0156] The display device can be a liquid crystal display panel, an OLED (Organic Light-Emitting Diode) display panel, a QLED (Quantum Dot Light Emitting Diodes) display panel, a micro-LED (micro-Light Emitting Diode) display panel, a mini-LED (mini-Light Emitting Diode) display panel, and so on.

[0157] When the display device can be a liquid crystal display panel, the display device may also include a color filter substrate, and the color filter substrate and the array substrate are bonded together by a frame.

[0158] The specific type of display device is not particularly limited; any type of display device commonly used in the field is acceptable, such as mobile devices like mobile phones, wearable devices like watches, VR devices, etc. Those skilled in the art can make the appropriate selection based on the specific purpose of the display device, which will not be elaborated further here.

[0159] It should be noted that, in addition to the array substrate, the display device also includes other necessary components and parts. Taking the display as an example, these include, for instance, the casing, circuit board, power cord, etc. Those skilled in the art can supplement these components according to the specific usage requirements of the display device, and will not be elaborated here.

[0160] Compared with the prior art, the beneficial effects of the display device provided by the exemplary embodiments of the present invention are the same as the beneficial effects of the array substrate provided by the above exemplary embodiments, and will not be repeated here.

[0161] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An array substrate, characterized in that, include: Substrate; An active layer is disposed on one side of the substrate. A first connecting conductor layer is disposed on the side of the active layer away from the substrate. The first connecting conductor layer includes a first connecting portion and a second connecting portion disposed at intervals. The first connecting portion includes a first part connected to the active layer. The second connecting portion includes a second part connected to the active layer. The barrier layer includes a first barrier portion and a second barrier portion disposed at intervals. The first barrier portion is at least disposed on the side of the first portion away from the substrate and covers the sidewall of the first portion to extend to the side of the active layer away from the substrate. The second barrier portion is at least disposed on the side of the second portion away from the substrate and covers the sidewall of the second portion to extend to the side of the active layer away from the substrate. An insulating layer group is disposed on the side of the barrier layer opposite to the substrate.

2. The array substrate according to claim 1, characterized in that, Cracks are formed on the insulating layer group, the cracks being located on the insulating layer group opposite to the sidewall of the first connecting portion, and / or the cracks being located on the insulating layer group opposite to the sidewall of the second connecting portion.

3. The array substrate according to claim 2, characterized in that, The crack is located on the insulating layer group opposite to the first bottom end, the first bottom end being the end of the sidewall of the first connection portion near the substrate; and / or, the crack is located on the insulating layer group opposite to the second bottom end, the second bottom end being the end of the sidewall of the second connection portion near the substrate.

4. The array substrate according to claim 1, characterized in that, The first blocking portion extends to the region between the first connecting portion and the second connecting portion, and the second blocking portion extends to the region between the first connecting portion and the second connecting portion.

5. The array substrate according to claim 1, characterized in that, The barrier layer is made of metal.

6. The array substrate according to claim 1, characterized in that, The first connecting conductor layer includes at least two stacked metal layers.

7. The array substrate according to claim 1, characterized in that, The first blocking portion protrudes from the sidewall of the first portion in the extending direction of the sidewall of the first portion, and the second blocking portion protrudes from the sidewall of the second portion in the extending direction of the sidewall of the second portion.

8. The array substrate according to claim 1, characterized in that, The orthographic projection of the first connecting portion on the substrate is located within the orthographic projection of the first blocking portion on the substrate, so that the first blocking portion covers the sidewall of the first connecting portion; the orthographic projection of the second connecting portion on the substrate is located within the orthographic projection of the second blocking portion on the substrate, so that the second blocking portion covers the sidewall of the second connecting portion.

9. The array substrate according to claim 1, characterized in that, The first blocking portion extends beyond the minimum dimension of the first connecting portion by more than or equal to 1.0 μm and less than or equal to 2.0 μm; the second blocking portion extends beyond the minimum dimension of the second connecting portion by more than or equal to 1.0 μm and less than or equal to 2.0 μm.

10. The array substrate according to claim 9, characterized in that, The minimum dimension of the distance between the first blocking part and the second blocking part is greater than or equal to 3μm.

11. The array substrate according to claim 1, characterized in that, The thickness of the barrier layer is greater than or equal to 10 nm.

12. The array substrate according to claim 1, characterized in that, The distance between the sidewall of the first connecting part and its center of mass in the first direction decreases as the height of the sidewall of the first connecting part in the third direction increases; the distance between the sidewall of the second connecting part and its center of mass in the first direction decreases as the height of the sidewall of the second connecting part in the third direction increases. The first direction is parallel to the substrate, and the third direction is perpendicular to the substrate.

13. The array substrate according to claim 12, characterized in that, The sidewall of the first connecting portion includes a first inclined surface, and the angle between the first inclined surface and the substrate is greater than or equal to 30° and less than or equal to 70°; the sidewall of the second connecting portion includes a second inclined surface, and the angle between the second inclined surface and the substrate is greater than or equal to 30° and less than or equal to 70°.

14. The array substrate according to claim 1, characterized in that, The insulating layer assembly includes: A first inorganic insulating layer is disposed on the side of the barrier layer away from the substrate. The second inorganic insulating layer is disposed on the side of the first inorganic insulating layer away from the substrate.

15. The array substrate according to claim 1, characterized in that, The array substrate further includes: A gate layer is disposed on one side of the substrate, the gate layer includes a gate and a gate line, the gate line extends along a first sub-direction, the first sub-direction being parallel to the substrate; A gate insulating layer group is disposed between the gate layer and the active layer.

16. The array substrate according to claim 15, characterized in that, The first connecting conductor layer further includes a data line extending along a second sub-direction, the second connecting portion being a part of the data line, the width of the second connecting portion being less than the width of the data line, the second sub-direction being parallel to the substrate, and the second sub-direction intersecting the first sub-direction.

17. The array substrate according to claim 16, characterized in that, The active layer includes a first conductor portion, a channel portion, and a second conductor portion connected in sequence. The orthographic projection of the edge line of the second connection portion away from the first connection portion on the substrate coincides with the orthographic projection of the edge line of the second conductor portion away from the channel portion on the substrate. Alternatively, the orthographic projection of the edge line of the second connection portion away from the first connection portion on the substrate is located on the side of the orthographic projection of the edge line of the second conductor portion away from the channel portion on the substrate closer to the channel portion.

18. The array substrate according to claim 15, characterized in that, The portion where the orthogonal projection of the gate on the substrate and the orthogonal projection of the second connection portion on the substrate intersect is the first overlapping portion, and the orthogonal projection of the first overlapping portion on the substrate is located within the orthogonal projection of the active layer on the substrate. The second blocking portion includes an extension portion, the orthographic projection of the extension portion on the substrate does not overlap with the orthographic projection of the gate on the substrate, the orthographic projection of the extension portion on the substrate does not overlap with the orthographic projection of the second connecting portion on the substrate, and the orthographic projection of the extension portion on the substrate overlaps with the orthographic projection of the active layer on the substrate.

19. A display device, characterized in that, include: The array substrate is the array substrate as described in any one of claims 1 to 18.

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