Display substrate, preparation method thereof, pixel circuit and display device

Abstract

The application provides a display substrate, a preparation method thereof, a pixel circuit and a display device. The display substrate comprises a driving circuit layer, and the pixel circuit in the driving circuit layer comprises a first transistor, a second transistor and a third transistor. The driving circuit layer comprises a first functional film layer and a second functional film layer which are sequentially stacked in a direction away from a substrate. The first functional film layer comprises the first transistor, and the second functional film layer comprises the second transistor and the third transistor. The first electrode of the second transistor is electrically coupled with the control electrode of the first transistor through a first via, and the first electrode of the third transistor is electrically coupled with the first electrode of the first transistor through a second via. The orthographic projection of the first transistor on the substrate at least partially overlaps with the orthographic projection of the second transistor and / or the third transistor on the substrate. The high resolution of the display panel can be realized by stacking the transistors of the pixel circuit in different functional film layers and electrically coupling them through the vias.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display substrate and its preparation method, pixel circuit, and display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely fast response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The purpose of this application is to provide a display substrate and its preparation method, pixel circuit, and display device.

[0004] In a first aspect, this application provides a display substrate, comprising:

[0005] Substrate;

[0006] A driving circuit layer is disposed on the substrate and includes multiple pixel circuits arranged in an array, wherein the pixel circuits include a first transistor, a second transistor and a third transistor;

[0007] The array of multiple sub-pixels is electrically coupled to the multiple pixel circuits in a one-to-one correspondence, and is disposed on the side of the driving circuit layer away from the substrate.

[0008] The driving circuit layer includes a first functional film layer and a second functional film layer sequentially stacked along a direction away from the substrate.

[0009] The first functional film layer includes the first transistor, the second functional film layer includes the second transistor and the third transistor, the first electrode of the second transistor is electrically coupled to the control electrode of the first transistor through a first via, the first electrode of the third transistor is electrically coupled to the first electrode of the first transistor through a second via, and the orthographic projection of the first transistor on the substrate at least partially overlaps with the orthographic projection of the second transistor and / or the third transistor on the substrate.

[0010] In a second aspect, this application provides a pixel circuit applied to a display substrate as described in the first aspect, wherein the pixel circuit includes a driving unit, a first storage capacitor, a light-emitting unit, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, and a fifth switching unit.

[0011] The first switching unit is electrically coupled to the first reset signal terminal and the first terminal of the first storage capacitor;

[0012] The second switching unit is electrically coupled to the data signal terminal and the first terminal of the first storage capacitor;

[0013] The third switching unit is electrically coupled to the light-emitting unit and the second terminal of the first storage capacitor;

[0014] The light-emitting unit is electrically coupled to the first power supply terminal;

[0015] The fourth switching unit is electrically coupled to the second power supply terminal and the driving unit;

[0016] The driving unit is electrically coupled to a first terminal and a second terminal of the first storage capacitor.

[0017] The fifth switching unit is electrically coupled to the initial signal terminal and the second terminal of the first storage capacitor.

[0018] In a third aspect, this application provides a display device including a display substrate as described in the first aspect.

[0019] A fourth aspect of this application provides a method for fabricating a display substrate, comprising:

[0020] Provide a substrate;

[0021] A driving circuit layer is formed on the substrate, the driving circuit layer including a plurality of pixel circuits arranged in an array, the pixel circuit including a first transistor, a second transistor and a third transistor;

[0022] A plurality of sub-pixels are formed in an array on the side of the driving circuit layer away from the substrate, and the plurality of sub-pixels are electrically coupled to the plurality of pixel circuits in a one-to-one correspondence.

[0023] The driving circuit layer includes a first functional film layer and a second functional film layer sequentially stacked along a direction away from the substrate.

[0024] The first functional film layer includes the first transistor, the second functional film layer includes the second transistor and the third transistor, the first electrode of the second transistor is electrically coupled to the control electrode of the first transistor through a first via, the first electrode of the third transistor is electrically coupled to the first electrode of the first transistor through a second via, and the orthographic projection of the first transistor on the substrate at least partially overlaps with the orthographic projection of the second transistor and / or the third transistor on the substrate.

[0025] As can be seen from the above description, this application provides a display substrate, its fabrication method, pixel circuit, and display device. The display substrate includes a driving circuit layer, and the pixel circuit in the driving circuit layer includes a first transistor, a second transistor, and a third transistor. The driving circuit layer includes a first functional film layer and a second functional film layer sequentially stacked along a direction away from the substrate. The first functional film layer includes a first transistor, and the second functional film layer includes a second transistor and a third transistor. The first electrode of the second transistor is electrically coupled to the control electrode of the first transistor through a first via, and the first electrode of the third transistor is electrically coupled to the first electrode of the first transistor through a second via. The orthographic projection of the first transistor on the substrate at least partially overlaps with the orthographic projection of the second transistor and / or the third transistor on the substrate. By stacking multiple transistors of the pixel circuit in different functional film layers and electrically coupling them through vias, a high resolution of the display panel can be achieved. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A schematic diagram of an exemplary display device 100 according to an embodiment of this application is shown.

[0028] Figure 2 An equivalent circuit diagram of a pixel circuit 200 according to an embodiment of this application is shown.

[0029] Figure 3 A timing diagram of each node in a driving method of an exemplary pixel circuit 200 according to an embodiment of this application is shown.

[0030] Figure 4A A schematic diagram of the structure of an exemplary pixel circuit 400 according to an embodiment of this application is shown.

[0031] Figure 4BAn equivalent circuit diagram of an exemplary pixel circuit 420 according to an embodiment of this application is shown.

[0032] Figure 4C A schematic diagram of the structure of an exemplary pixel circuit 440 according to an embodiment of this application is shown.

[0033] Figure 4D An equivalent circuit diagram of an exemplary pixel circuit 460 according to an embodiment of this application is shown.

[0034] Figure 5 Timing diagrams of nodes in a driving method of an exemplary pixel circuit 400 or pixel circuit 420 according to embodiments of this application are shown.

[0035] Figure 6A A schematic diagram of an exemplary display substrate 600 according to an embodiment of this application is shown.

[0036] Figure 6B A schematic diagram of an exemplary display substrate 700 according to an embodiment of this application is shown.

[0037] Figure 7 A schematic flowchart of an exemplary display substrate fabrication method 710 according to an embodiment of this application is shown. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0039] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0040] With the diversification of market demands in the display technology field, the requirements for high resolution of display panels are also increasing. However, in order to improve the display effect, multiple thin-film transistor devices need to be applied in the pixel circuit corresponding to each pixel in the display panel. The increase in the number of thin-film transistor devices and their occupied area also increase, which limits the aperture area of ​​the pixel and thus limits the resolution of the display panel.

[0041] To at least address the aforementioned technical problems, this application provides a display substrate and its fabrication method, a pixel circuit, and a display device. The display substrate includes a driving circuit layer, and the pixel circuit in the driving circuit layer includes a first transistor, a second transistor, and a third transistor. The driving circuit layer includes a first functional film layer and a second functional film layer sequentially stacked along a direction away from the substrate. The first functional film layer includes a first transistor, and the second functional film layer includes a second transistor and a third transistor. The first electrode of the second transistor is electrically coupled to the control electrode of the first transistor through a first via, and the first electrode of the third transistor is electrically coupled to the first electrode of the first transistor through a second via. The orthographic projection of the first transistor on the substrate at least partially overlaps with the orthographic projection of the second transistor and / or the third transistor on the substrate. By stacking multiple transistors of the pixel circuit in different functional film layers and electrically coupling them through vias, a high resolution of the display panel can be achieved.

[0042] Figure 1 A schematic diagram of an exemplary display device 100 according to an embodiment of this application is shown.

[0043] Display device 100 is a product with image display function, such as: monitor, television, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large wall, home appliance, information query equipment (such as business query equipment of e-government, bank, hospital, power and other departments, monitor, etc.).

[0044] like Figure 1 As shown, the display device 100 may include a display substrate 102. The display substrate 102 may include a base substrate (not shown). The display device 100 may also include a driving circuit layer (not shown) disposed on the base substrate. The driving circuit layer may include a plurality of pixel circuits arranged in an array, which are used to control the brightness and grayscale of the pixels. In some embodiments, the pixel circuits may be 2T1C, 3T1C, 4T1C, 5T1C, 6T1C, or 7T1C structures.

[0045] Figure 2A schematic diagram of an equivalent circuit of a pixel circuit 200 according to an embodiment of this application is shown. The pixel circuit 200 may be a 7T1C structure.

[0046] like Figure 2 As shown, the pixel circuit 200 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C. The third transistor T3 may be a driving transistor T3.

[0047] For example, such as Figure 2 As shown, the first transistor T1 is the first reset transistor T1, the second transistor T2 is the threshold compensation transistor T2, the fourth transistor T4 is the data writing transistor T4, the fifth transistor T5 is the second light-emitting control transistor T5, the sixth transistor T6 is the first light-emitting control transistor T6, and the seventh transistor T7 is the second reset transistor T7.

[0048] For example, the first terminal of the first transistor T1 is connected to node N1, which is electrically coupled to the control terminal of the driving transistor T3. The second terminal of the first transistor T1 is electrically coupled to the first initial signal terminal Vinit1, which is electrically coupled to the first reset signal line to receive the reset signal. The control terminal of the first transistor T1 is electrically coupled to the first reset signal terminal Re1, which is electrically coupled to the reset control signal line to receive the reset control signal. The first terminal of the second transistor T2, which is also the threshold compensation transistor, is connected to node N1, which is electrically coupled to the control terminal of the driving transistor T3. The second terminal of the second transistor T2 is connected to the driving transistor... The second terminal of transistor T3 is electrically coupled to the control terminal of the second transistor T2, which is electrically coupled to the first drive signal terminal G1 to receive the compensation control signal. The control terminal of the drive transistor T3 is connected to node N1, and is electrically coupled to the first terminal of the storage capacitor C, the first terminal of the first transistor T1, and the first terminal of the second transistor T2. The first terminal of the fourth transistor T4, which is also the data write transistor, is electrically coupled to the data signal terminal Data to receive the data signal. The second terminal of the fourth transistor T4 is connected to the first terminal of the drive transistor T3, and the control terminal of the fourth transistor T4 is electrically coupled to the second drive signal terminal G2 to receive the scan signal. The first terminal of the fifth transistor T5, which is also the second light-emitting control transistor, is electrically coupled to the first power supply terminal VDD to receive the first power supply signal. The second terminal of the fifth transistor T5 is electrically coupled to the first terminal of the drive transistor T3, and the control terminal of the fifth transistor T5 is electrically coupled to the light-emitting control signal terminal EM to receive the light-emitting control signal. The first terminal of the sixth transistor T6, which is also the first light-emitting control transistor, is electrically coupled to the second terminal of the drive transistor T3. The second terminal of the sixth transistor T6 is electrically coupled to the first terminal of the seventh transistor T7, and the control terminal of the sixth transistor T6 is electrically coupled to the light-emitting control signal terminal EM. The pixel circuit 200 is connected to receive the light emission control signal. The second terminal of the seventh transistor T7 is electrically coupled to the second initial signal terminal Vinit2, i.e., electrically coupled to the second reset signal line to receive the reset signal Vinit. The control terminal of the seventh transistor T7 is electrically coupled to the second reset signal terminal Re2, i.e., electrically coupled to the reset control signal line to receive the reset control signal. The first terminal of the seventh transistor T7 is connected to node N4. The first terminal of the storage capacitor C is connected to node N1 and electrically coupled to the control terminal of the driving transistor T3. The second terminal of the storage capacitor C is electrically coupled to the first power supply terminal VDD, i.e., connected to the first power supply signal line. This pixel circuit 200 can connect to the light emission unit 120, which can be an organic light-emitting diode (OLED). The pixel circuit 200 is used to drive the light emission unit 120 to emit light. The light emission unit 120 can be connected between the second terminal of the sixth transistor T6 and the second power supply terminal VSS, i.e., connected to the second power supply signal line.

[0049] For example, the first power signal line mentioned above refers to the signal line for the output voltage signal VDD, which can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal. The second power signal line mentioned above refers to the signal line for the output voltage signal VSS, which can be connected to a voltage source to output a constant voltage signal, such as a negative voltage signal.

[0050] For example, the scan signal and the compensation control signal can be the same; that is, the control electrode of the data write transistor T4 and the control electrode of the threshold compensation transistor T2 can be electrically coupled to the same signal line to receive the same signal, thereby reducing the number of signal lines. Alternatively, the control electrode of the data write transistor T4 and the control electrode of the threshold compensation transistor T2 can be electrically coupled to different signal lines; that is, the control electrode of the data write transistor T4 can be electrically coupled to the second scan signal line, and the control electrode of the threshold compensation transistor T2 can be electrically coupled to the first scan signal line. The signals transmitted by the first scan signal line and the second scan signal line can be the same or different, thus allowing the control electrodes of the data write transistor T4 and the threshold compensation transistor T2 to be controlled separately, thereby increasing the flexibility of the pixel circuit control.

[0051] For example, the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can receive the same light-emitting control signal. That is, the control terminals of the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can be electrically coupled to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the control terminals of the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can be electrically coupled to different light-emitting control signal lines. In this case, the signals transmitted by the different light-emitting control signal lines can be the same or different.

[0052] For example, the reset control signals input to the second reset transistor T7 and the first reset transistor T1 can be the same. That is, the control terminals of the second reset transistor T7 and the first reset transistor T1 can be electrically coupled to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the control terminals of the second reset transistor T7 and the first reset transistor T1 can be electrically coupled to different reset control signal lines. In this case, the signals on the different reset control signal lines can be the same or different.

[0053] For example, the first transistor T1 and the second transistor T2 can be N-type transistors. For example, the first transistor T1 and the second transistor T2 can be N-type metal-oxide transistors. N-type metal-oxide transistors have smaller leakage current, thus avoiding leakage current through the N1 node during the light-emitting stage. Meanwhile, the driving transistors T3, T4, T5, T6, and T7 can be P-type transistors. For example, the driving transistors T3, T4, T5, T6, and T7 can be P-type low-temperature polysilicon transistors. P-type low-temperature polysilicon transistors have higher carrier mobility, which is beneficial for achieving display panels with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal Vinit1 and the second initial signal terminal Vinit2 can output the same or different voltage signals depending on the actual situation.

[0054] Figure 3 A timing diagram of each node in a driving method of an exemplary pixel circuit 200 according to an embodiment of this application is shown.

[0055] like Figure 3 As shown, G1 represents the timing of the first driving signal terminal G1, G2 represents the timing of the second driving signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the light emission control signal terminal EM, and Data represents the timing of the data signal terminal Data. The driving method of the pixel circuit 200 may include a first reset stage t1, a compensation stage t2, a second reset stage t3, and a light emission stage t4. In the first reset stage t1: the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to node N1. In the compensation stage t2: the first driving signal terminal G1 outputs a high-level signal, the second driving signal terminal G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and at the same time, the data signal terminal Data outputs a driving signal to write a voltage Vdata + Vth (i.e., the sum of voltages Vdata and Vth) to node N1, where Vdata is the voltage of the driving signal and Vth is the threshold voltage of the driving transistor T3. In the second reset phase t3: the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second terminal of the sixth transistor T6. In the light-emitting phase t4: the light-emitting control signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit 120 to emit light under the action of the voltage Vdata+Vth stored in the storage capacitor C.

[0056] It should be noted that, in the embodiments of this application, each pixel circuit can, in addition to being able to... Figure 2 In addition to the 7T1C (i.e., seven transistors and one capacitor) structure shown, other structures including other numbers of transistors are also possible, such as 2T1C, 3T1C, 4T1C, 5T1C, 6T1C or 7T1C structures. This application does not limit the embodiments to this.

[0057] like Figure 3 As shown, during the driving of the pixel circuit 200, both data writing and Vth compensation occur in the compensation phase t2. Simultaneous Vth compensation and data writing can lead to a conflict in time resources. The compensation process requires sufficient time to accurately extract and store the Vth value, while data writing also requires enough time to ensure accurate data transmission and storage. If both occur simultaneously, neither may be able to complete within the limited time, thus affecting the display effect.

[0058] Figure 4A A schematic diagram of the structure of an exemplary pixel circuit 400 according to an embodiment of this application is shown.

[0059] like Figure 4A As shown, in some embodiments, the pixel circuit 400 may include a driving unit 402, a first storage capacitor 404, a light-emitting unit 406, a first switching unit 408, a second switching unit 410, a third switching unit 412, a fourth switching unit 414, and a fifth switching unit 416. The first switching unit 408 is electrically coupled to a first reset signal terminal Vref and a first terminal of the first storage capacitor 404; the second switching unit 410 is electrically coupled to a data signal terminal Data and a first terminal of the first storage capacitor 404; the third switching unit 412 is electrically coupled to the light-emitting unit 406 and a second terminal of the first storage capacitor; the light-emitting unit 406 is electrically coupled to a first power supply terminal VSS; the fourth switching unit 414 is electrically coupled to a second power supply terminal VDD and the driving unit 402; the driving unit 402 is electrically coupled to a first terminal and a second terminal of the first storage capacitor 404; and the fifth switching unit 416 is electrically coupled to an initial signal terminal Vinit and a second terminal of the first storage capacitor 404. The first switching unit 408, the second switching unit 410, the driving unit 402 and the first storage capacitor 404 are respectively connected to node N1, the driving unit 402, the first storage capacitor 404, the third switching unit 412 and the fifth switching unit 416 are respectively connected to node N2, and the third switching unit 412 is also connected to node N3.

[0060] Figure 4B An equivalent circuit diagram of an exemplary pixel circuit 420 according to an embodiment of this application is shown. In some embodiments, pixel circuit 400 may be pixel circuit 420.

[0061] like Figure 4B As shown, in some embodiments, the driving unit 402 may include a first transistor T1, the first switching unit 408 may include a second transistor T2, the third switching unit 412 may include a third transistor T3, the second switching unit 410 may include a fourth transistor T4, the fourth switching unit 414 may include a fifth transistor T5, and the fifth switching unit 416 may include a sixth transistor T6. The first storage capacitor 404 may be a first storage capacitor Cst1.

[0062] The control electrode of the first transistor T1 is electrically coupled to the first electrode of the fourth transistor T4, the first terminal of the first storage capacitor Cst1, and the first electrode of the second transistor T2. The first electrode of the first transistor T1 is electrically coupled to the second terminal of the first storage capacitor Cst1, the first electrode of the third transistor T3, and the first electrode of the sixth transistor T6. The second electrode of the first transistor T1 is electrically coupled to the first electrode of the fifth transistor T5.

[0063] The second terminal of the second transistor T2 is electrically coupled to the first reset signal terminal Vref, and the control terminal of the second transistor T2 is electrically coupled to the first drive signal terminal G1.

[0064] The second electrode of the third transistor T3 is electrically coupled to the light-emitting unit 406, the light-emitting unit 406 is electrically coupled to the first power supply terminal VSS, and the control electrode of the third transistor T3 is electrically coupled to the first light-emitting control signal terminal EM1.

[0065] The second terminal of the fourth transistor T4 is electrically coupled to the data signal terminal Data, and the control terminal of the fourth transistor T4 is electrically coupled to the second drive signal terminal G2.

[0066] The second terminal of the fifth transistor T5 is electrically coupled to the second power supply terminal VDD, and the control terminal of the fifth transistor T5 is electrically coupled to the second light-emitting control signal terminal EM2.

[0067] The second terminal of the sixth transistor T6 is electrically coupled to the initial signal terminal Vinit, and the control terminal of the sixth transistor T6 is electrically coupled to the second reset signal terminal Reset.

[0068] Figure 4C A schematic diagram of the structure of an exemplary pixel circuit 440 according to an embodiment of this application is shown.

[0069] like Figure 4C As shown, in some embodiments, the pixel circuit 440 may include a second storage capacitor 442, the first terminal of the second storage capacitor 442 being electrically coupled to the second power supply terminal VDD, and the second terminal of the second storage capacitor 442 being electrically coupled to the driving unit 402.

[0070] Figure 4DAn equivalent circuit diagram of an exemplary pixel circuit 460 according to an embodiment of this application is shown. In some embodiments, pixel circuit 440 may be pixel circuit 460.

[0071] like Figure 4D As shown, in some embodiments, the first terminal of the second storage capacitor 442 is electrically coupled to the second power supply terminal VDD, and the second terminal of the second storage capacitor 442 is electrically coupled to the first terminal of the first transistor T1. The second storage capacitor 442 may be a second storage capacitor Cst2.

[0072] Figure 5 Timing diagrams of nodes in a driving method of an exemplary pixel circuit 400 or pixel circuit 420 according to embodiments of this application are shown.

[0073] like Figure 5 As shown, G1 represents the timing of the first driving signal terminal G1, G2 represents the timing of the second driving signal terminal G2, Reset represents the timing of the second reset signal terminal Reset, EM1 represents the timing of the first light emission control signal terminal EM1, and EM2 represents the timing of the second light emission control signal terminal EM2. The driving method of pixel circuit 400 or pixel circuit 420 may include an initialization phase t1, a compensation phase t2, a data writing phase t3, and a light emission phase t4. In the initialization phase t1: the first driving signal terminal G1 outputs a high-level signal, the second transistor T2 is turned on, and the first reset signal terminal Vref inputs a reset signal to node N1; the second reset signal terminal Reset outputs a high-level signal, the sixth transistor T6 is turned on, and the initial signal terminal Vinit inputs an initial signal to node N2. During compensation phase t2: The first drive signal terminal G1 outputs a high-level signal, the second light-emitting control signal terminal EM2 outputs a high-level signal, the second transistor T2 and the fifth transistor T5 are turned on, and simultaneously the first reset signal terminal Vref outputs a reset signal to write voltage Vref (the voltage of the reset signal) to node N1. The second power supply terminal VDD outputs a drive signal to write voltage Vref-Vth (the difference between voltages Vref and Vth) to node N2, where Vth is the threshold voltage of the first transistor T1 (the drive transistor). During data writing phase t3: The second drive signal terminal G2 outputs a high-level signal, the fourth transistor T4 is turned on, and the data signal terminal Data outputs a drive signal to write data voltage Vdata (the voltage of the data signal) to node N1. At this time, the voltage change at node N2 is Vdata-Vref, and the voltage at node N2 is Vref-Vth+Vdata-Vref, i.e., Vdata-Vth. During the light-emitting stage t4: the first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM2 output high-level signals, the third transistor T3 and the fifth transistor T5 are turned on, and the first transistor T1 drives the light-emitting unit 406 to emit light under the action of the voltage of the first storage capacitor Cst1.

[0074] It should be noted that the timing of the driving method for pixel circuits 440 or 460 is similar to that of pixel circuits 400 or 420, and will not be repeated here. For the data writing stage t3 of pixel circuits 440 or 460, since a second storage capacitor Cst2 is included in pixel circuits 440 or 460, the voltage change at node N2 is... Where C1 represents the capacitance value of the first storage capacitor Cst1, C2 represents the capacitance value of the second storage capacitor Cst2, and the voltage of node N2 is... Right now It can be seen that, due to the setting of the second storage capacitor Cst2, a portion of the Vref voltage is retained, thus making the voltage of node N2 more sufficient.

[0075] Figure 6A A schematic diagram of an exemplary display substrate 600 according to an embodiment of this application is shown. Pixel circuits 400, 420, 440, and 460 can be applied to the display substrate 600.

[0076] like Figure 6A As shown, in some embodiments, the display substrate 600 may include a substrate 602; a driving circuit layer 604, disposed on the substrate 602, including a plurality of pixel circuits arranged in an array, wherein the pixel circuits may be 400, 420, 440, and 460. The pixel circuits include a first transistor T1, a second transistor T2, and a third transistor T3. The display substrate 600 may also include a plurality of sub-pixels arranged in an array, electrically coupled to the plurality of pixel circuits in a one-to-one correspondence, and disposed on the side of the driving circuit layer 604 away from the substrate 602. The driving circuit layer 604 includes a first functional film layer 6042 and a second functional film layer 6044 sequentially stacked along a direction away from the substrate 602.

[0077] The first functional film layer 6042 includes the first transistor T1, and the second functional film layer 6044 includes the second transistor T2 and the third transistor T3. The first electrode 606 of the second transistor T2 is electrically coupled to the control electrode 608 of the first transistor T1 through a first via, and the first electrode 610 of the third transistor T3 is electrically coupled to the first electrode 612 of the first transistor T1 through a second via. The orthographic projection of the first transistor T1 on the substrate 602 at least partially overlaps with the orthographic projection of the second transistor T2 and / or the third transistor T3 on the substrate 602. In this way, by stacking multiple transistors of the pixel circuit in different functional film layers (e.g., the first functional film layer 6042 and the second functional film layer 6044) and electrically coupling them through vias, the area occupied by multiple transistors in the same film layer in the X direction of the display substrate is effectively reduced. This enables the display panel to achieve high resolution and can be better applied to high-resolution products such as virtual reality (VR) and products with partial free refresh. Furthermore, when multiple transistors are placed close together in the same film layer, signals are easily coupled due to parasitic capacitance. Voltage changes can easily affect nodes N1, N2, and N3, causing crosstalk and screen flickering, thus affecting the display. At the boundary between different refresh rates, the coupling voltage is even more likely to cause defects. Therefore, stacking multiple transistors in different film layers can mitigate these problems by controlling the distance between the film layers.

[0078] like Figure 4B As shown, in some embodiments, the pixel circuit may include a first storage capacitor Cst1, the first terminal of which is electrically coupled to the control electrode of the first transistor T1, and the second terminal of which is electrically coupled to the first electrode of the first transistor T1. It can be understood that when the first transistor T1 is a dual-gate transistor, the first transistor T1 may also include a control electrode 680.

[0079] In the display substrate 600, such as Figure 6A As shown, in some embodiments, the first functional film layer 6042 further includes a first storage capacitor Cst1 and a first conductive layer 614 and a second conductive layer 616 sequentially stacked along a direction away from the substrate 602. The first end 618 of the first storage capacitor Cst1 is located in the first conductive layer 614, and the second end 620 of the first storage capacitor Cst1 is located in the second conductive layer 616. The second end 620 of the first storage capacitor Cst1 is electrically coupled to the second electrode 622 of the first transistor T1 through a third via. The orthographic projections of the first end 618 and the second end 620 of the first storage capacitor Cst1 on the substrate 602 overlap.

[0080] like Figure 4BAs shown, in some embodiments, the control electrode of the first transistor T1 is electrically coupled to the first electrode of the second transistor T2, the first electrode of the first transistor T1 is electrically coupled to the first electrode of the third transistor T3, the second electrode of the second transistor T2 is electrically coupled to the first reset signal terminal Vref, the control electrode of the second transistor T2 is electrically coupled to the first drive signal terminal G1, the second electrode of the third transistor T3 is electrically coupled to the first power supply terminal VSS, and the control electrode of the third transistor T3 is electrically coupled to the first light emission control signal terminal EM1.

[0081] In the display substrate 600, such as Figure 6A As shown, in some embodiments, the display substrate 600 may further include a light-emitting functional layer 624 located on the side of the driving circuit layer 604 away from the substrate 602. The light-emitting functional layer 624 includes a first electrode 6242. The second functional film layer 6044 further includes a third conductive layer 626 and a fourth conductive layer 628 sequentially stacked along a direction away from the substrate 602. The control electrode 630 of the second transistor T2 and the control electrode 632 of the third transistor T3 are located in the third conductive layer 626, and the second electrode 634 of the second transistor T2 and the second electrode 638 of the third transistor T3 are located in the fourth conductive layer 628. The first electrode 6242 is electrically coupled to the second electrode 638 of the third transistor T3 through a fourth via.

[0082] In the display substrate 600, such as Figure 6A As shown, in some embodiments, the second transistor T2 includes a first active layer 640, the third transistor T3 includes a second active layer 642, the control electrode 630 of the second transistor T2 includes a first sub-control electrode 6302 and a second sub-control electrode 6304, and the control electrode 632 of the third transistor T3 includes a third sub-control electrode 6322 and a fourth sub-control electrode 6324.

[0083] The third conductive layer 626 includes a first sub-conductive layer 6262 and a second sub-conductive layer 6264. The first sub-conductive layer 6262 is located between the first active layer 640 and the first functional film layer 6042, and the second sub-conductive layer 6264 is located between the first active layer 640 and the fourth conductive layer 628. The first sub-control electrode 6302 and the third sub-control electrode 6322 are located in the first sub-conductive layer 6262, and the second sub-control electrode 6304 and the fourth sub-control electrode 6324 are located in the second sub-conductive layer 6264.

[0084] In the display substrate 600, such as Figure 6AAs shown, in some embodiments, the pixel circuit further includes a fourth transistor T4, and the first functional film layer 6042 further includes the fourth transistor T4 and a fifth conductive layer 644 and a sixth conductive layer 646 sequentially stacked on the side of the second conductive layer 616 away from the substrate 602. The fourth transistor T4 includes a third active layer 648, which is located between the first conductive layer 614 and the substrate 602. The control electrode 650 of the fourth transistor T4 is located in the first conductive layer 614, the second electrode 654 of the fourth transistor T4 is located in the fifth conductive layer 644, and the first electrode 652 of the fourth transistor T4 is located in the sixth conductive layer 646. The first electrode 652 of the fourth transistor T4 is electrically coupled to the third active layer 648 through a fifth via, and the second electrode 654 of the fourth transistor T4 is electrically coupled to the third active layer 648 through a sixth via.

[0085] like Figure 4B As shown, in some embodiments, the first terminal 652 of the fourth transistor T4 is electrically coupled to the control terminal of the first transistor T1, the second terminal of the fourth transistor T4 is electrically coupled to the data signal terminal Data, and the control terminal of the fourth transistor T4 is electrically coupled to the second drive signal terminal G2.

[0086] In the display substrate 600, such as Figure 6A As shown, in some embodiments, the first electrode 652 of the fourth transistor T4 is electrically coupled to the control electrode 608 of the first transistor T1 through a seventh via, and the first electrode 606 of the second transistor T2 is electrically coupled to the first electrode 652 of the fourth transistor T4 through an eighth via.

[0087] like Figure 6A As shown, in some embodiments, the control electrode 608 of the first transistor T1 is multiplexed as the first terminal 618 of the first storage capacitor Cst1, and the first electrode 612 of the first transistor T1 is multiplexed as the second terminal 620 of the first storage capacitor Cst1. This eliminates the need for an additional first terminal 618 of the first storage capacitor Cst1, effectively saving space.

[0088] like Figure 6A As shown, in some embodiments, the first transistor T1 includes a fourth active layer 656, which is located between the first conductive layer 614 and the substrate 602. The fourth active layer 656 is multiplexed as the second electrode 622 of the first transistor T1, thereby effectively utilizing space.

[0089] Figure 6B A schematic diagram of an exemplary display substrate 700 according to an embodiment of this application is shown.

[0090] like Figure 6BAs shown, in some embodiments, the first functional film layer 6042 further includes a first signal line 658 and a seventh conductive layer 660. The seventh conductive layer 660 is located between the second conductive layer 616 and the fifth conductive layer 644. The first signal line 658 is located in the seventh conductive layer 660 and is electrically coupled to the control electrode 608 of the first transistor T1 through a ninth via. The orthographic projections of the first signal line 658, the first end 618 of the first storage capacitor Cst1, and the second end 620 of the first storage capacitor Cst1 on the substrate 602 overlap. In this way, a capacitor can also be formed between the first signal line 658 and the second end 620 of the first storage capacitor Cst1, thereby effectively shielding noise, reducing crosstalk, and improving the stability of the display.

[0091] like Figure 4B As shown, in some embodiments, the pixel circuit further includes a fifth transistor T5, the first terminal of the fifth transistor T5 is electrically coupled to the second terminal of the first transistor T1, the second terminal of the fifth transistor T5 is electrically coupled to the second power supply terminal VDD, and the control terminal of the fifth transistor T5 is electrically coupled to the second light emission control signal terminal EM2.

[0092] In the display substrate 600, such as Figure 6A As shown, in some embodiments, the first functional film layer 6042 further includes a fifth transistor T5. The first electrode 662 of the fifth transistor T5 is located in the fifth conductive layer 644, and the control electrode 664 of the fifth transistor T5 is located in the first conductive layer 614. The fifth transistor T5 includes a fifth active layer 666, which is located between the first conductive layer 614 and the substrate 602. The first electrode 662 of the fifth transistor T5 is electrically coupled to the fifth active layer 666 through a tenth via. The fifth active layer 666 is multiplexed as the second electrode 668 of the fifth transistor T5, thereby effectively saving space.

[0093] like Figure 4B As shown, in some embodiments, the pixel circuit further includes a sixth transistor T6, the first terminal of the sixth transistor T6 being electrically coupled to the first terminal of the third transistor T3, the second terminal of the sixth transistor T6 being electrically coupled to the initial signal terminal Vinit, and the control terminal of the sixth transistor T6 being electrically coupled to the second reset signal terminal Reset.

[0094] In the display substrate 600, such as Figure 6AAs shown, in some embodiments, the first functional film layer 6042 further includes a sixth transistor T6. The first electrode 670 of the sixth transistor T6 is located in the fifth conductive layer 644, and the control electrode 672 of the sixth transistor T6 is located in the first conductive layer 614. The sixth transistor T6 includes a sixth active layer 674, which is located between the first conductive layer 614 and the substrate 602. The first electrode 670 of the sixth transistor T6 is electrically coupled to the sixth active layer 674 through an eleventh via. The sixth active layer 674 is multiplexed as the second electrode 676 of the sixth transistor T6, thereby effectively utilizing space.

[0095] In some embodiments, the first electrode 612 of the first transistor T1 is the source, and the second electrode 622 of the first transistor T1 is the drain. This allows the pixel circuit to implement a source-following driving mode, improving the stability of the signal output.

[0096] In some embodiments, the second transistor T2 and the third transistor T3 are oxide transistors, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are low-temperature polycrystalline silicon transistors. Oxide transistors have high field-effect mobility, which enables them to meet higher frame rates and resolution requirements when driving high-resolution display panels. In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are N-type metal-oxide-semiconductor field-effect transistors (NMOS transistors). NMOS transistors have low on-resistance and low power consumption.

[0097] like Figure 4D As shown, in some embodiments, the pixel circuit further includes a second storage capacitor Cst2, the first end of which is electrically coupled to the second power supply terminal VDD, and the second end of which is electrically coupled to the first terminal of the first transistor T1.

[0098] In some embodiments, the first functional film layer 6042 further includes a second storage capacitor Cst2 and an eighth conductive layer located on the side of the second conductive layer 616 away from the substrate 602. The first end of the second storage capacitor Cst2 is located in the eighth conductive layer, and the second end 620 of the first storage capacitor Cst1 is multiplexed as the second end of the second storage capacitor Cst2. The orthographic projections of the first end of the second storage capacitor Cst2 and the second end 620 of the first storage capacitor Cst1 on the substrate 602 overlap. The first end of the second storage capacitor Cst2 is electrically coupled to the first terminal 662 of the fifth transistor T5. The arrangement of the second storage capacitor Cst2 makes the voltage at node N2 more sufficient.

[0099] It should be noted that, as Figure 6AAs shown, taking the second transistor T2 as an example, the second electrode 634 of the second transistor T2 can be electrically coupled to the first active layer 640 through the signal line 678. This avoids impedance caused by excessively long traces. Alternatively, it can be electrically coupled directly to the first active layer 640 without using the signal line 678. This embodiment does not limit this approach. The electrodes of other transistors are similar and will not be described in detail here.

[0100] When fabricating the display substrate 600, a substrate can be provided, which may be a glass substrate. A polyimide layer (PI) is deposited on the glass substrate. In some embodiments, the thickness of the polyimide layer may be 7-10 μm, serving as the process substrate. Then, a first buffer layer (Buffer0) is deposited on it. The first buffer layer may have a thickness of [missing information]. The silicon nitride (SiNx) and thickness can be It consists of silicon oxide (SiOx), on which amorphous silicon (a-Si) is deposited (the thickness can be...). The process involves first creating an N-type silicon (N-Si) layer, then performing another patterning process, followed by exposure, development, and etching to create the active layer (Poly) pattern (used for switching transistors (SWTFT) and driving transistors (DTFT)). A small number of particles are then implanted, and the threshold voltage (Vth Doping) of the transistor is adjusted through a doping process.

[0101] A first insulating layer (GI1) is deposited on the active layer (the material can be SiOx, and the thickness can be...). Then, a first gate metal (the control electrode of the first transistor) is deposited on top (the material can be molybdenum (Mo), and the thickness can be [missing information - likely a thickness value]. The first gate metal pattern is formed using a single communication process (the gates and signal lines of the sixth transistor, the fourth transistor, the first transistor, and the fifth transistor are made respectively), and then a large number of particles are injected to form a better ohmic contact.

[0102] The second insulating layer (GI2) (the material can be SiNx, and the thickness can be...) (For the insulating layer of the storage capacitor), a via pattern is formed between the first and second insulating layers using a single patterning process to connect the active layer.

[0103] Then, a second gate metal (the first electrode of the fifth transistor) is deposited on top of the second insulating layer (the material can be Mo, and the thickness can be...). The pattern is formed using a single patterning process (the first electrode of the sixth transistor / fifth transistor and the drain of the first crystal are respectively made and connected to the active layer through vias; at the same time, the first storage capacitor is formed between points N1 and N2).

[0104] A third insulating layer (GI3) is deposited on top of the second gate metal (the material can be SiNx, and the thickness can be...). (The insulating layer for the storage capacitor) is used to create vias through the third and second insulating layers. The via pattern is formed through a patterning process and used for the connection between the two gates of the first transistor.

[0105] A third gate metal (the control electrode of the first transistor) is deposited on the third insulating layer (the material can be Mo, and the thickness can be...). The pattern is formed through a patterning process, and the other control electrode of the first transistor is connected through a via (to form the N1 node, and the first storage capacitor is formed between the N1 node and the N2 node).

[0106] A fourth insulating layer (GI4) is deposited on the third gate metal (the material can be SiNx, and the thickness can be...). The vias are formed through a patterning process (the first electrode (SD1) of the sixth transistor / fifth crystal is connected to the second gate metal, and the second electrode of the fourth transistor is connected to the active layer).

[0107] The second electrode of the fourth transistor is deposited on the fourth insulating layer (GI4). (The material can be aluminum (Al), and the thickness can be...) The pattern is formed through a patterning process, and the second gate metal is connected through a via to serve as the source signal (VDD) of the fifth transistor, the source signal (Vinit) of the sixth transistor, and the source signal (Data) of the fourth transistor.

[0108] An inter-layer dielectric (ILD) is deposited on the second electrode of the fourth transistor (the material can be SiNx, and the thickness can be...). The process involves vias and a patterning process to form a pattern (used for the first electrode of the fourth transistor to connect to the active layer, the first electrode of the fourth transistor to the N1 node of the third gate metal, and the first electrode of the fourth transistor to the N2 node of the second gate metal).

[0109] The first electrode metal of the fourth transistor is deposited on the interlayer dielectric (the material can be Al, and the thickness can be...). The pattern is formed through a patterning process, and the active layer of the fourth transistor is connected through a via to form the first electrode of the fourth transistor. The first electrode of the fourth transistor is connected to the N1 node of the third gate metal, and the first electrode of the fourth transistor is connected to the N2 node of the second gate metal.

[0110] A first planarization layer (PLN) (material can be PI, thickness can be 1.5 μm) is formed on the first electrode of the fourth transistor through a patterning process. Then, a second buffer layer (Buffer1) (material can be SiNx, thickness can be...) is deposited on top of it. Then, a fourth gate metal is deposited on top (the material can be Mo, and the thickness can be...). The pattern of the fourth gate metal is formed through a patterning process, which is then used as the bottom gate (e.g., the first sub-control electrode) of the second and third transistors.

[0111] A fifth insulating layer (GI5) is deposited on the fourth gate metal (the material can be SiOx, and the thickness can be...). The vias are formed through a patterning process (used for connecting the first terminal of the fourth transistor, i.e., nodes N1 and N2, through vias in Indium Gallium Zinc Oxide (IGZO)).

[0112] Indium gallium zinc oxide (IGZO) is deposited on the fifth insulating layer (GI5) (the thickness can be...). The pattern of indium gallium zinc oxide is formed through a patterning process to make the second and third transistors, and the first terminal (i.e., the N1 node and the N2 node) of the fourth transistor below is connected through vias.

[0113] A sixth insulating layer (GI6) is deposited on indium gallium zinc oxide (the material can be SiOx, and the thickness can be...). Then, a fifth gate metal is deposited on top (the material can be Mo, and the thickness can be [missing information]). The pattern of the fifth gate metal is formed through a patterning process, which is then used as the top gate (e.g., the second sub-control electrode) of the second and third transistors.

[0114] An interlayer dielectric is deposited on the fifth gate metal (the material can be SiNx, and the thickness can be [missing information]). The pattern is formed through a patterning process (for the second electrode connection of the second and third transistors IGZO).

[0115] A third gate metal is deposited on the interlayer dielectric (the material can be Al, and the thickness can be [missing information]). The second and third transistors are patterned through a patterning process, and the IGZO of the second and third transistors are connected through vias.

[0116] A second planarization layer (PLN2 layer) is formed on the second electrode of the second and third transistors through a patterning process (the material can be PI, and the thickness can be 1.5μm to 1.7μm). Vias are formed on the second electrode of the second and third transistors for connection with signal lines.

[0117] A fourth gate metal is deposited on top of the second planarization layer (the material can be Al, and the thickness can be...). The signal line pattern is formed through a patterning process, and the second transistor and the second electrode of the third transistor are connected through vias in the second planarization layer.

[0118] A third planarization layer (the material can be PI, and the thickness can be 1.7μm to 2.1μm) is formed on the signal line through a patterning process. A via is formed on the second electrode of the third transistor for the first electrode (e.g., the anode) to connect to the second electrode below.

[0119] The first electrode is deposited on the third planarization layer (the material can be indium tin oxide / silver / indium tin oxide (ITO / Ag / ITO), and the thickness can be...). The anode pattern is formed through a patterning process and then connected to the third transistor below via a via in the third planarization layer.

[0120] Finally, the anode is exposed to form a pixel definition layer (PDL) opening, and the R / G / B pixel definition layer is formed according to a certain opening ratio.

[0121] Figure 7 A schematic flowchart of an exemplary display substrate fabrication method 710 according to an embodiment of this application is shown. The fabrication method 710 may include the following steps.

[0122] In step 712, a substrate is provided.

[0123] In step 714, a driving circuit layer is formed on the substrate. The driving circuit layer includes multiple pixel circuits arranged in an array. Each pixel circuit includes a first transistor, a second transistor, and a third transistor.

[0124] In step 716, a plurality of sub-pixels are formed on the side of the driving circuit layer away from the substrate, and the plurality of sub-pixels are electrically coupled to a plurality of pixel circuits in a one-to-one correspondence.

[0125] The driving circuit layer includes a first functional film layer and a second functional film layer stacked sequentially along a direction away from the substrate. The first functional film layer includes a first transistor, and the second functional film layer includes a second transistor and a third transistor. The first electrode of the second transistor is electrically coupled to the control electrode of the first transistor through a first via. The first electrode of the third transistor is electrically coupled to the first electrode of the first transistor through a second via. The orthographic projection of the first transistor on the substrate at least partially overlaps with the orthographic projection of the second transistor and / or the third transistor on the substrate.

[0126] In some embodiments, the pixel circuit includes a first storage capacitor, a first end of which is electrically coupled to the control electrode of a first transistor, and a second end of which is electrically coupled to the first electrode of the first transistor. The first functional film layer further includes the first storage capacitor and a first conductive layer and a second conductive layer sequentially stacked along a direction away from the substrate. The first end of the first storage capacitor is located in the first conductive layer, and the second end of the first storage capacitor is located in the second conductive layer. The second end of the first storage capacitor is electrically coupled to the second electrode of the first transistor through a third via. The orthographic projections of the first end and the second end of the first storage capacitor on the substrate overlap.

[0127] In some embodiments, the control electrode of the first transistor is electrically coupled to the first electrode of the second transistor, the first electrode of the first transistor is electrically coupled to the first electrode of the third transistor, the second electrode of the second transistor is electrically coupled to the first reset signal terminal, the control electrode of the second transistor is electrically coupled to the first drive signal terminal, the second electrode of the third transistor is electrically coupled to the first power supply terminal, and the control electrode of the third transistor is electrically coupled to the first light emission control signal terminal.

[0128] The preparation method also includes:

[0129] A light-emitting functional layer is formed on the side of the driving circuit layer away from the substrate. The light-emitting functional layer includes a first electrode. The second functional film layer also includes a third conductive layer and a fourth conductive layer stacked sequentially in a direction away from the substrate. The control electrode of the second transistor and the control electrode of the third transistor are located in the third conductive layer. The second electrode of the second transistor and the second electrode of the third transistor are located in the fourth conductive layer. The first electrode is electrically coupled to the second electrode of the third transistor through a fourth via.

[0130] In some embodiments, the second transistor includes a first active layer, the third transistor includes a second active layer, the control electrode of the second transistor includes a first sub-control electrode and a second sub-control electrode, and the control electrode of the third transistor includes a third sub-control electrode and a fourth sub-control electrode; the third conductive layer includes a first sub-conductive layer and a second sub-conductive layer, the first sub-conductive layer being located between the first active layer and the first functional film layer, and the second sub-conductive layer being located between the first active layer and the fourth conductive layer; the first sub-control electrode and the third sub-control electrode are located in the first sub-conductive layer, and the second sub-control electrode and the fourth sub-control electrode are located in the second sub-conductive layer.

[0131] In some embodiments, the pixel circuit further includes a fourth transistor, and the first functional film layer further includes the fourth transistor and a fifth conductive layer and a sixth conductive layer sequentially stacked on the side of the second conductive layer away from the substrate; the fourth transistor includes a third active layer located between the first conductive layer and the substrate; the control electrode of the fourth transistor is located in the first conductive layer, the first electrode of the fourth transistor is located in the sixth conductive layer, and the second electrode of the fourth transistor is located in the fifth conductive layer; the first electrode of the fourth transistor is electrically coupled to the third active layer through a fifth via, and the second electrode of the fourth transistor is electrically coupled to the third active layer through a sixth via.

[0132] In some embodiments, the first terminal of the fourth transistor is electrically coupled to the control terminal of the first transistor, the second terminal of the fourth transistor is electrically coupled to the data signal terminal, and the control terminal of the fourth transistor is electrically coupled to the second drive signal terminal; the first terminal of the fourth transistor is electrically coupled to the control terminal of the first transistor through a seventh via, and the first terminal of the second transistor is electrically coupled to the first terminal of the fourth transistor through an eighth via.

[0133] In some embodiments, the control electrode of the first transistor is multiplexed to the first terminal of the first storage capacitor, and the first electrode of the first transistor is multiplexed to the second terminal of the first storage capacitor.

[0134] In some embodiments, the first transistor includes a fourth active layer located between the first conductive layer and the substrate, and the fourth active layer is multiplexed as the second electrode of the first transistor.

[0135] In some embodiments, the first functional film layer further includes a first signal line and a seventh conductive layer, the seventh conductive layer being located between the second conductive layer and the fifth conductive layer, the first signal line being located in the seventh conductive layer, and the first signal line being electrically coupled to the control electrode of the first transistor through a ninth via; the orthographic projections of the first signal line, the first end of the first storage capacitor, and the second end of the first storage capacitor on the substrate overlap.

[0136] In some embodiments, the pixel circuit further includes a fifth transistor, the first electrode of which is electrically coupled to the second electrode of the first transistor, the second electrode of which is electrically coupled to a second power supply terminal, and the control electrode of which is electrically coupled to a second light emission control signal terminal; the first functional film layer further includes a fifth transistor, the first electrode of which is located in a fifth conductive layer, the control electrode of which is located in a first conductive layer, the fifth transistor including a fifth active layer, the fifth active layer being located between the first conductive layer and the substrate, the first electrode of which is electrically coupled to the fifth active layer through a tenth via, and the fifth active layer being multiplexed as the second electrode of the fifth transistor.

[0137] In some embodiments, the pixel circuit further includes a sixth transistor, the first electrode of which is electrically coupled to the first electrode of the third transistor, the second electrode of which is electrically coupled to the initial signal terminal, and the control electrode of which is electrically coupled to the second reset signal terminal; the first functional film layer further includes a sixth transistor, the first electrode of which is located in the fifth conductive layer, the control electrode of which is located in the first conductive layer, the sixth transistor includes a sixth active layer, the sixth active layer is located between the first conductive layer and the substrate, the first electrode of which is electrically coupled to the sixth active layer through an eleventh via, and the sixth active layer is multiplexed as the second electrode of the sixth transistor.

[0138] In some embodiments, the first electrode of the first transistor is the source, and the second electrode of the first transistor is the drain.

[0139] In some embodiments, the second and third transistors comprise oxide transistors, and the first, fourth, fifth, and sixth transistors comprise low-temperature polycrystalline silicon transistors.

[0140] In some embodiments, the pixel circuit further includes a second storage capacitor, a first end of which is electrically coupled to a second power supply terminal, and a second end of which is electrically coupled to a first electrode of a first transistor; the first functional film layer further includes a second storage capacitor and an eighth conductive layer located on the side of the second conductive layer away from the substrate, the first end of the second storage capacitor is located on the eighth conductive layer, the second end of the first storage capacitor is multiplexed as the second end of the second storage capacitor, the orthographic projections of the first end of the second storage capacitor and the second end of the first storage capacitor on the substrate overlap, and the first end of the second storage capacitor is electrically coupled to a first electrode of a fifth transistor.

[0141] This application provides a display substrate, its fabrication method, a pixel circuit, and a display device. The display substrate includes a driving circuit layer, and the pixel circuit in the driving circuit layer includes a first transistor, a second transistor, and a third transistor. The driving circuit layer includes a first functional film layer and a second functional film layer sequentially stacked along a direction away from the substrate. The first functional film layer includes the first transistor, and the second functional film layer includes the second transistor and the third transistor. The first electrode of the second transistor is electrically coupled to the control electrode of the first transistor through a first via, and the first electrode of the third transistor is electrically coupled to the first electrode of the first transistor through a second via. The orthographic projection of the first transistor on the substrate at least partially overlaps with the orthographic projection of the second transistor and / or the third transistor on the substrate. By stacking multiple transistors of the pixel circuit in different functional film layers and electrically coupling them through vias, a high resolution of the display panel can be achieved.

[0142] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0143] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0144] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0145] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A display substrate, comprising: Substrate; A driving circuit layer is disposed on the substrate and includes multiple pixel circuits arranged in an array, wherein the pixel circuits include a first transistor, a second transistor and a third transistor; The array of multiple sub-pixels is electrically coupled to the multiple pixel circuits in a one-to-one correspondence, and is disposed on the side of the driving circuit layer away from the substrate. The driving circuit layer includes a first functional film layer and a second functional film layer sequentially stacked along a direction away from the substrate. The first functional film layer includes the first transistor, the second functional film layer includes the second transistor and the third transistor, the first electrode of the second transistor is electrically coupled to the control electrode of the first transistor through a first via, the first electrode of the third transistor is electrically coupled to the first electrode of the first transistor through a second via, and the orthographic projection of the first transistor on the substrate at least partially overlaps with the orthographic projection of the second transistor and / or the third transistor on the substrate.

2. The display substrate as claimed in claim 1, wherein, The pixel circuit includes a first storage capacitor, a first terminal of which is electrically coupled to the control electrode of the first transistor, and a second terminal of which is electrically coupled to the first electrode of the first transistor. The first functional film layer further includes the first storage capacitor and a first conductive layer and a second conductive layer sequentially stacked along a direction away from the substrate. The first end of the first storage capacitor is located on the first conductive layer, and the second end of the first storage capacitor is located on the second conductive layer. The second end of the first storage capacitor is electrically coupled to the second electrode of the first transistor through a third via. The orthographic projections of the first end and the second end of the first storage capacitor on the substrate overlap.

3. The display substrate as described in claim 1, wherein, The control electrode of the first transistor is electrically coupled to the first electrode of the second transistor, the first electrode of the first transistor is electrically coupled to the first electrode of the third transistor, the second electrode of the second transistor is electrically coupled to the first reset signal terminal, the control electrode of the second transistor is electrically coupled to the first drive signal terminal, the second electrode of the third transistor is electrically coupled to the first power supply terminal, and the control electrode of the third transistor is electrically coupled to the first light emission control signal terminal. The display substrate further includes: A light-emitting functional layer, located on the side of the driving circuit layer away from the substrate, includes a first electrode; The second functional film layer further includes a third conductive layer and a fourth conductive layer stacked sequentially along a direction away from the substrate. The control electrode of the second transistor and the control electrode of the third transistor are located in the third conductive layer, and the second electrode of the second transistor and the second electrode of the third transistor are located in the fourth conductive layer. The first electrode is electrically coupled to the second electrode of the third transistor through a fourth via.

4. The display substrate as described in claim 3, wherein, The second transistor includes a first active layer, the third transistor includes a second active layer, the control electrode of the second transistor includes a first sub-control electrode and a second sub-control electrode, and the control electrode of the third transistor includes a third sub-control electrode and a fourth sub-control electrode. The third conductive layer includes a first sub-conductive layer and a second sub-conductive layer. The first sub-conductive layer is located between the first active layer and the first functional film layer, and the second sub-conductive layer is located between the first active layer and the fourth conductive layer. The first sub-control electrode and the third sub-control electrode are located in the first sub-conductive layer, and the second sub-control electrode and the fourth sub-control electrode are located in the second sub-conductive layer.

5. The display substrate as claimed in claim 2, wherein, The pixel circuit further includes a fourth transistor, and the first functional film layer further includes the fourth transistor and a fifth and a sixth conductive layer sequentially stacked on the side of the second conductive layer away from the substrate. The fourth transistor includes a third active layer, which is located between the first conductive layer and the substrate. The control electrode of the fourth transistor is located in the first conductive layer, the first electrode of the fourth transistor is located in the sixth conductive layer, and the second electrode of the fourth transistor is located in the fifth conductive layer. The first terminal of the fourth transistor is electrically coupled to the third active layer through the fifth via, and the second terminal of the fourth transistor is electrically coupled to the third active layer through the sixth via.

6. The display substrate as claimed in claim 5, wherein, The first terminal of the fourth transistor is electrically coupled to the control terminal of the first transistor, the second terminal of the fourth transistor is electrically coupled to the data signal terminal, and the control terminal of the fourth transistor is electrically coupled to the second drive signal terminal. The first terminal of the fourth transistor is electrically coupled to the control terminal of the first transistor through a seventh via, and the first terminal of the second transistor is electrically coupled to the first terminal of the fourth transistor through an eighth via.

7. The display substrate as claimed in claim 2, wherein, The control electrode of the first transistor is multiplexed to the first terminal of the first storage capacitor, and the first electrode of the first transistor is multiplexed to the second terminal of the first storage capacitor.

8. The display substrate as claimed in claim 2, wherein, The first transistor includes a fourth active layer located between the first conductive layer and the substrate, and the fourth active layer is multiplexed as the second electrode of the first transistor.

9. The display substrate as claimed in claim 5, wherein, The first functional film layer further includes a first signal line and a seventh conductive layer. The seventh conductive layer is located between the second conductive layer and the fifth conductive layer. The first signal line is located in the seventh conductive layer. The first signal line is electrically coupled to the control electrode of the first transistor through a ninth via. The first signal line, the first end of the first storage capacitor, and the second end of the first storage capacitor have their orthogonal projections on the substrate overlap.

10. The display substrate as claimed in claim 5, wherein, The pixel circuit further includes a fifth transistor, the first terminal of which is electrically coupled to the second terminal of the first transistor, the second terminal of which is electrically coupled to a second power supply terminal, and the control terminal of which is electrically coupled to a second light emission control signal terminal. The first functional film layer further includes the fifth transistor, the first electrode of the fifth transistor is located in the fifth conductive layer, the control electrode of the fifth transistor is located in the first conductive layer, the fifth transistor includes a fifth active layer, the fifth active layer is located between the first conductive layer and the substrate, the first electrode of the fifth transistor is electrically coupled to the fifth active layer through a tenth via, and the fifth active layer is multiplexed as the second electrode of the fifth transistor.

11. The display substrate as claimed in claim 10, wherein, The pixel circuit further includes a sixth transistor, the first terminal of which is electrically coupled to the first terminal of the third transistor, the second terminal of which is electrically coupled to the initial signal terminal, and the control terminal of which is electrically coupled to the second reset signal terminal. The first functional film layer further includes the sixth transistor, the first electrode of the sixth transistor is located in the fifth conductive layer, the control electrode of the sixth transistor is located in the first conductive layer, the sixth transistor includes a sixth active layer, the sixth active layer is located between the first conductive layer and the substrate, the first electrode of the sixth transistor is electrically coupled to the sixth active layer through an eleventh via, and the sixth active layer is multiplexed as the second electrode of the sixth transistor.

12. The display substrate as claimed in claim 2, wherein, The first electrode of the first transistor is the source, and the second electrode of the first transistor is the drain.

13. The display substrate as claimed in claim 11, wherein, The second transistor and the third transistor comprise oxide transistors, while the first transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprise low-temperature polycrystalline silicon transistors.

14. The display substrate as claimed in claim 11, wherein, The pixel circuit further includes a second storage capacitor, the first end of which is electrically coupled to the second power supply terminal, and the second end of which is electrically coupled to the first electrode of the first transistor. The first functional film layer further includes the second storage capacitor and an eighth conductive layer located on the side of the second conductive layer away from the substrate. The first end of the second storage capacitor is located on the eighth conductive layer. The second end of the first storage capacitor is multiplexed as the second end of the second storage capacitor. The orthographic projections of the first end of the second storage capacitor and the second end of the first storage capacitor on the substrate overlap. The first end of the second storage capacitor is electrically coupled to the first electrode of the fifth transistor.

15. A pixel circuit, applied to a display substrate as described in any one of claims 1-14, wherein, The pixel circuit includes a driving unit, a first storage capacitor, a light-emitting unit, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, and a fifth switching unit; The first switching unit is electrically coupled to the first reset signal terminal and the first terminal of the first storage capacitor; The second switching unit is electrically coupled to the data signal terminal and the first terminal of the first storage capacitor; The third switching unit is electrically coupled to the light-emitting unit and the second terminal of the first storage capacitor; The light-emitting unit is electrically coupled to the first power supply terminal; The fourth switching unit is electrically coupled to the second power supply terminal and the driving unit; The driving unit is electrically coupled to a first terminal and a second terminal of the first storage capacitor. The fifth switching unit is electrically coupled to the initial signal terminal and the second terminal of the first storage capacitor.

16. The pixel circuit as claimed in claim 15, wherein, The driving unit includes a first transistor, the first switching unit includes a second transistor, the third switching unit includes a third transistor, the second switching unit includes a fourth transistor, the fourth switching unit includes a fifth transistor, and the fifth switching unit includes a sixth transistor. The control electrode of the first transistor is electrically coupled to the first electrode of the fourth transistor, the first terminal of the first storage capacitor, and the first electrode of the second transistor. The first electrode of the first transistor is electrically coupled to the second terminal of the first storage capacitor, the first electrode of the third transistor, and the first electrode of the sixth transistor. The second electrode of the first transistor is electrically coupled to the first electrode of the fifth transistor. The second terminal of the second transistor is electrically coupled to the first reset signal terminal, and the control terminal of the second transistor is electrically coupled to the first drive signal terminal; The second electrode of the third transistor is electrically coupled to the light-emitting unit, the light-emitting unit is electrically coupled to the first power supply terminal, and the control electrode of the third transistor is electrically coupled to the first light-emitting control signal terminal. The second terminal of the fourth transistor is electrically coupled to the data signal terminal, and the control terminal of the fourth transistor is electrically coupled to the second drive signal terminal. The second terminal of the fifth transistor is electrically coupled to the second power supply terminal, and the control terminal of the fifth transistor is electrically coupled to the second light-emitting control signal terminal. The second terminal of the sixth transistor is electrically coupled to the initial signal terminal, and the control terminal of the sixth transistor is electrically coupled to the second reset signal terminal.

17. The pixel circuit of claim 16, wherein, The pixel circuit further includes a second storage capacitor, the first end of which is electrically coupled to the second power supply terminal, and the second end of which is electrically coupled to the first electrode of the first transistor.

18. A display device comprising a display substrate as described in any one of claims 1-14.

19. A method for preparing a display substrate, comprising: Provide a substrate; A driving circuit layer is formed on the substrate, the driving circuit layer including a plurality of pixel circuits arranged in an array, the pixel circuit including a first transistor, a second transistor and a third transistor; A plurality of sub-pixels are formed in an array on the side of the driving circuit layer away from the substrate, and the plurality of sub-pixels are electrically coupled to the plurality of pixel circuits in a one-to-one correspondence. The driving circuit layer includes a first functional film layer and a second functional film layer sequentially stacked along a direction away from the substrate. The first functional film layer includes the first transistor, the second functional film layer includes the second transistor and the third transistor, the first electrode of the second transistor is electrically coupled to the control electrode of the first transistor through a first via, the first electrode of the third transistor is electrically coupled to the first electrode of the first transistor through a second via, and the orthographic projection of the first transistor on the substrate at least partially overlaps with the orthographic projection of the second transistor and / or the third transistor on the substrate.

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