Array substrate, preparation method thereof and display panel

Abstract

The present disclosure provides an array substrate, a preparation method thereof and a display panel. The array substrate comprises a substrate, a first functional layer, an insulating layer and a second functional layer. The first functional layer comprises a first functional part, and the second functional layer comprises a second functional part. The insulating layer is provided with a through hole. The second functional part is connected with the first functional part through the through hole. The through hole comprises a first hole segment, a second hole segment and a third hole segment which are sequentially connected in a direction perpendicular to the substrate. The first hole segment is close to the second functional layer, and the third hole segment is close to the first functional layer. The second hole segment is connected between the first hole segment and the third hole segment. The angle between the hole wall of the first hole segment and a first plane is a first slope angle. The angle between the hole wall of the second hole segment and the first plane is a second slope angle. The angle between the hole wall of the third hole segment and the first plane is a third slope angle. The first slope angle is greater than the second slope angle, and the third slope angle is greater than the second slope angle. The first plane is a plane parallel to the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology. More specifically, it relates to an array substrate and its fabrication method, and a display panel. Background Technology

[0002] In the manufacturing process of display panels, via structures are often used to connect different film layers. Among them, vias of inorganic insulating layers are mostly formed by dry etching process. During the etching process, the etching gas reacts with components such as photoresist and mask, which can easily produce polymer residues inside the channel and on the sidewall. In severe cases, it can even lead to via blockage or open circuit, causing problems such as uneven pixel brightness and abnormal signal transmission. Moreover, this polymer residue problem is more prominent in high-resolution (PPI) display panels. Summary of the Invention

[0003] The purpose of this disclosure is to provide an array substrate and a method for fabricating the same, as well as a display panel, to solve at least one of the aforementioned technical problems.

[0004] To achieve the above objectives, the present disclosure adopts the following technical solution: The first aspect of this disclosure provides an array substrate, comprising: Substrate; A first functional layer is disposed on one side of the substrate, and the first functional layer includes a first functional part; An insulating layer is disposed on the side of the first functional layer away from the substrate. A second functional layer is disposed on the side of the insulating layer away from the substrate, and the second functional layer includes a second functional part; The insulating layer has a through hole, and the second functional part is connected to the first functional part through the through hole, wherein: The via includes a first segment, a second segment, and a third segment that are sequentially connected on the substrate perpendicular to it. The first segment is close to the second functional layer, the third segment is close to the first functional layer, and the second segment connects the first segment and the third segment. The angle between the wall of the first segment and the first plane is a first slope angle, the angle between the wall of the second segment and the first plane is a second slope angle, and the angle between the wall of the third segment and the first plane is a third slope angle. The first slope angle is greater than the second slope angle, and the third slope angle is greater than the second slope angle. The first plane is a plane parallel to the substrate.

[0005] Optionally, the angle range of the first slope angle and the third slope angle is 70°~90°, and the angle range of the second slope angle is 20°~30°.

[0006] Optionally, in the direction perpendicular to the substrate, the ratio of the height of the second hole segment to the total height of the through hole is 1 / 6 to 1 / 4.

[0007] Optionally, the insulating layer includes at least two sub-insulating layers stacked sequentially along the direction away from the substrate, wherein the sub-insulating layer closest to the second functional layer among the at least two sub-insulating layers is the first sub-insulating layer, the first hole segment is located in the first sub-insulating layer, and the first sub-insulating layer is a silicon nitride layer.

[0008] Optionally, any one of the at least two sub-insulating layers other than the first sub-insulating layer is a silicon nitride layer or a silicon oxide layer, and in the direction perpendicular to the substrate, the height of the first hole segment is less than or equal to the height of the first sub-insulating layer.

[0009] Optionally, the walls of the first hole segment, the second hole segment, and the third hole segment transition continuously at the junction of adjacent hole segments.

[0010] Optionally, the first functional part is an active part or a conductive part, and the second functional part is a conductive part.

[0011] Optionally, the array substrate includes, sequentially stacked on one side of the substrate, a light-shielding metal layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, a first inorganic insulating layer, a second inorganic insulating layer, an organic planarization layer, a first electrode layer, a passivation layer, and a source / drain electrode layer. The light-shielding metal layer includes a first conductive portion, the active layer includes an active portion, and the source / drain electrode layer includes a second conductive portion and a third conductive portion, wherein: The second conductive part is connected to the first conductive part through a first sleeve hole. The first sleeve hole includes a first through hole and a second through hole. The first through hole penetrates the organic planarization layer. The passivation layer covers the sidewalls and bottom of the first through hole and extends to the surface of the organic planarization layer surrounding the first through hole. The second through hole penetrates the passivation layer, the second inorganic insulating layer, and the first inorganic insulating layer at the bottom of the first through hole. The second through hole includes a first segment, a second segment, and a third segment; and / or The third conductive part is connected to the active part through the second set of holes. The second set of holes includes a third through hole and a fourth through hole. The third through hole penetrates the organic planarization layer. The passivation layer covers the sidewall and bottom of the third through hole and extends to the surface of the organic planarization layer around the third through hole. The fourth through hole penetrates the passivation layer, the second inorganic insulating layer, the first inorganic insulating layer and the buffer layer at the bottom of the third through hole. The fourth through hole includes a first hole segment, a second hole segment and a third hole segment.

[0012] A second aspect of this disclosure provides a method for fabricating an array substrate, comprising the following steps: Provide substrates; A first functional layer is formed on one side of a substrate, the first functional layer including a first functional part; An insulating layer is formed on the side of the first functional part away from the substrate. Through-holes are formed on the insulating layer using an etching process. The through-holes include a first hole segment, a second hole segment, and a third hole segment that are connected in sequence perpendicular to the substrate. The third hole segment is close to the first functional layer, the first hole segment is away from the first functional layer, and the second hole segment connects the first hole segment and the third hole segment. The angle between the hole wall of the first hole segment and a first plane is a first slope angle, the angle between the hole wall of the second hole segment and the first plane is a second slope angle, and the angle between the hole wall of the third hole segment and the first plane is a third slope angle. The first slope angle is greater than the second slope angle, and the third slope angle is greater than the second slope angle. The first plane is a plane parallel to the substrate. A second functional layer is formed on the side of the insulating layer away from the substrate. The second functional layer includes a second functional part, which is connected to the first functional part through the through-hole.

[0013] Optionally, the step of creating a through-hole in the insulating layer using an etching process includes: First etching stage: The insulating layer is etched using the first etching conditions to form the first hole segment; Second etching stage: After the first etching stage, the insulating layer is etched from the bottom of the first hole segment toward the first functional layer under second etching conditions to form the second hole segment; Third etching stage: After the second etching stage, the insulating layer is etched from the bottom of the second hole segment toward the first functional layer under third etching conditions to form the third hole segment; The first etching stage, the second etching stage, and the third etching stage are performed sequentially and continuously, and the gas pressure of the first etching condition is greater than the gas pressure of the second etching condition and the third etching condition.

[0014] Optionally, the gas pressure of the first etching condition is 15mT~30mT, the etching gas includes NF3 and O2, the upper electrode power is 20K~25K, and the lower electrode power is 5K~15K; the gas pressure of the second etching condition is 5mT~15mT, the etching gas includes CF4 and O2, the upper electrode power is 20K~25K, and the lower electrode power is 15K~25K; the gas pressure of the third etching condition is 5mT~15mT, the etching gas includes CF4, O2, and Ar, the upper electrode power is 20K~30K, and the lower electrode power is 10K~15K.

[0015] A third aspect of this disclosure provides a display panel including an array substrate as described above.

[0016] Beneficial effects In this embodiment, the array substrate has a three-segment structure in which the vias of the insulating layer are connected sequentially along the direction perpendicular to the substrate. The slope angle of the middle second via segment is smaller than that of the first and third via segments on the top and bottom sides. During the dry etching process to prepare the vias, the deposition residue of polymer on the via walls and bottom can be reduced, avoiding defects such as via blockage and contact breakage. Furthermore, the three-segment via structure has a smaller horizontal width under the condition of fixed via depth, which can meet the high resolution requirements of the display panel while improving the polymer residue problem. Attached Figure Description

[0017] The specific embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0018] Figure 1 This is a schematic diagram of the membrane structure of a product in the relevant technology; Figure 2 This is a schematic diagram of the structure of the array substrate provided in this disclosure; Figure 3 for Figure 2 A partially enlarged schematic diagram of the through hole; Figure 4 This is a schematic diagram comparing the dimensions of the through hole in the three-section structure of this application with those of a traditional adapter hole; Figure 5 A schematic diagram of a specific example of the array substrate provided in this application; Figure 6 for Figure 5 The image shows a scanning electron microscope cross-sectional topography of the film layer at the location of the first set of holes on the array substrate. Figure 7 This is a schematic diagram of the film structure of an array substrate using a BCE structure. Figure 8 This is a schematic diagram of the film structure of an array substrate employing a top-gate structure; Figure 9 A flowchart illustrating an embodiment of the method for fabricating an array substrate provided in this application; Figure 10 This is a schematic diagram of the preparation process for the first set of holes. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0020] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0021] The inventors discovered during the research and development project that the product was prone to problems such as uneven pixel brightness and abnormal signal transmission. After analyzing the product, they found that the above-mentioned display abnormalities were mainly caused by polymer residue in the inorganic layer transition hole in the array substrate and damage to the active layer caused by the intrusion of etching solution into the deep hole during the deep hole etching process. This was more obvious in high resolution (PPI) products.

[0022] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the film structure of the product. In this product, the display panel includes, sequentially stacked on a substrate 200, a light-shielding layer (LS) 201, a first buffer layer 202, a second buffer layer 203, an active layer (ACT) 204, a gate insulating layer (GI) 205, a gate layer (Gate) 206, a first passivation layer (PVX1) 207, a second passivation layer (PVX2) 208, a planarization layer 209, a first transparent conductive layer (1 ITO) 210, a third passivation layer (PVX3) 211, a source / drain electrode layer (SD), and a second transparent conductive layer (2 ITO) 213, wherein the source and drain electrode layers include a first electrode 2121 and a second electrode 2122. The first electrode 2121 is connected to the active layer 204 through a transition hole H22, and the second electrode 2122 is connected to the active layer 204 through a transition hole H21 and extends to the light-shielding layer 201 to connect with the signal traces in the light-shielding layer 201. The first buffer layer 202, the second buffer layer 203, the first passivation layer 207, the second passivation layer 208 and the third passivation layer 211 are all made of inorganic materials, and the transition holes H21 and H22 are both sleeve structures.

[0023] For the adapter hole H21, its depth is relatively deep, and multiple inorganic film layers need to be etched sequentially during the etching process, including the third passivation layer 211, the second passivation layer 208, the first passivation layer 207, the second buffer layer 203, and the first buffer layer 202. The etching time is relatively long. During the dry etching process, the polymer generated by the reaction of fluorine-containing etching gas with components such as photoresist mask is difficult to fully dissipate in the narrow space of the deep hole, and is prone to be deposited in large quantities on the sidewalls and bottom of the hole. At the same time, the polymer will aggregate on the upper edge of the hole during the hole etching process, and act as a hard mask in subsequent etching, forming a sidewall structure. On the one hand, these residual polymers can easily cause the subsequent deposited overlapping metals to break. For example, the sidewall structure may puncture the deposited source / drain electrode layer 213, resulting in poor contact between the second electrode 2122 of the source / drain electrode layer and the signal trace in the light-shielding layer 201, or the first electrode 2121 and the active layer 204 may break contact. On the other hand, for the transition hole H22, the residual polymer or sidewall structure may prevent the source / drain electrode material from completely filling the transition hole H22. The etching solution in the subsequent wet etching process of the second transparent conductive layer 213 may enter the hole through the gaps in the transition hole H22, corroding the active layer and causing damage to the active layer.

[0024] Based on the above research findings, the inventors have proposed the array substrate, its preparation method, and the display panel of this application.

[0025] Please refer to Figures 2 to 3 , Figure 2 This is a schematic diagram of the film layer structure of an embodiment of the array substrate provided in this disclosure. Figure 3 for Figure 2 A partially enlarged schematic diagram of the through hole, as shown below. Figure 2 and Figure 3 As shown, the array substrate of this embodiment includes a substrate 10, a first functional layer 20, an insulating layer 30, and a second functional layer 40. The first functional layer 20 is disposed on one side of the substrate 10 and includes a first functional portion 210. The insulating layer 30 is disposed on the side of the first functional layer 20 away from the substrate 10. The second functional layer 40 is disposed on the side of the insulating layer 30 away from the substrate 10 and includes a second functional portion 410. A through-hole H is provided on the insulating layer 30, and the second functional portion 410 is connected to the first functional portion 210 through the through-hole H. The via H includes a first segment H1, a second segment H2, and a third segment H3 that are sequentially connected on the substrate perpendicular to it. The first segment H1 is close to the second functional layer 40, the third segment H3 is close to the first functional layer 20, and the second segment H2 is connected between the first segment H1 and the third segment H3. The angle between the wall of the first segment H1 and the first plane is a first slope angle θ1, the angle between the wall of the second segment H2 and the first plane is a second slope angle θ2, and the angle between the wall of the third segment H3 and the first plane is a third slope angle θ3. The first slope angle θ1 is greater than the second slope angle θ2, and the third slope angle θ3 is greater than the second slope angle θ2. The first plane is a plane parallel to the substrate 10.

[0026] The first functional layer 20 can be a conductive layer or a semiconductor layer in the array substrate, the second functional layer 40 can be another conductive layer in the array substrate, and the second functional part 410 is connected to the first functional part 210 through a through hole H. The conductive layer includes, but is not limited to, metal (such as molybdenum, aluminum, copper, titanium, etc.) layers, transparent conductive (such as indium tin oxide ITO, etc.) layers, or metal stacked structures, and the semiconductor layer can be made of amorphous silicon, low-temperature polycrystalline silicon, or metal oxide semiconductor materials.

[0027] Optionally, the first functional part 210 is an active part or a conductive part, and the second functional part 410 is a conductive part. The first functional part 210 is connected to the upper second functional part 410 through the through hole H.

[0028] For example, the first functional unit 210 is an active unit, and the second functional unit 410 is a source / drain electrode.

[0029] For example, the first functional part 210 is a conductive part, and the second functional part 410 is a source / drain electrode.

[0030] For example, the first functional unit 210 is the drain electrode in the source-drain electrode layer, and the second functional unit 410 is the pixel electrode.

[0031] In this embodiment, the slope angle θ refers to the angle between the hole wall and the plane of the substrate 10. The larger the slope angle θ, the gentler the hole wall; the smaller the slope angle θ, the steeper the hole wall.

[0032] The fact that θ1>θ2 and θ3>θ2 indicates that the walls of the first hole segment H1 and the third hole segment H3 are relatively steep, while the wall of the second hole segment H2 is relatively gentle. The through hole H presents a three-segment structure with a steep upper section, a gentle middle section, and a steep lower section. This design can improve the polymer residue problem, prevent polymer from forming sidewalls in the through hole, and effectively save the diameter of the through hole H, allowing more pixels to be arranged within a limited pixel area to meet the display requirements of high resolution.

[0033] Specifically, given a fixed via depth H, a gentler slope angle on the via wall results in a larger required lateral width W at the via opening, leading to a larger area occupied at the top of the via H. Conversely, a steeper slope angle results in a smaller lateral width W at the via opening, which is beneficial for high-density pixel layout. However, in high-resolution product structures, if the via H adopts a steeper single slope angle, although the top lateral width (TOP CD) of the via can be reduced to accommodate more pixels, the polymer generated during etching becomes more difficult to remove and is more likely to remain inside the via, resulting in polymer residue or even sidewall formation, affecting the reliability of electrical connections at the via location. If the via H adopts a gentler single slope angle, although the polymer residue problem can be improved, the top lateral width of the via will increase significantly, failing to meet the requirements of high resolution.

[0034] In this embodiment, the through hole H is configured as a three-section structure. The upper section (first hole section H1) and the lower section (third hole section H3) adopt a steeper slope angle, while the middle section (second hole section H2) adopts a gentler slope angle. This ensures that the top and bottom of the through hole H have a small opening size, while the gentle slope area in the middle section provides a discharge channel for etching byproducts, effectively reducing polymer residue on the hole wall.

[0035] Compared with related technologies, the array substrate of this disclosure sets the vias of the insulating layer as a three-segment structure that are sequentially connected along the direction perpendicular to the substrate, and makes the slope angle of the middle second via segment smaller than that of the first and third via segments on the upper and lower sides. In the process of preparing the vias by dry etching, the deposition residue of polymer on the via walls and bottoms can be reduced, avoiding defects such as via blockage and contact breakage. Moreover, the three-segment via structure has a smaller horizontal width under the condition of fixed via depth, which can meet the high resolution requirements of the display panel while improving the polymer residue problem.

[0036] For example, please refer to Figure 4 , Figure 4 This is a schematic diagram comparing the dimensions of the through hole in the three-section structure of this application with those of a traditional adapter hole. Figure 4 Figure (a) shows a schematic diagram of the dimensions of a conventional adapter hole, where θ0 represents the slope angle of the conventional adapter hole, h0 represents the depth of the conventional adapter hole, and W0 represents the lateral dimension of the orthographic projection of the hole wall on the plane of the substrate, i.e., the horizontal projection width or the lateral width CD. It can be seen that when the depth h0 is fixed, the smaller the slope angle θ0, the gentler the slope angle of the hole wall, and the larger the horizontal projection width W0. Figure (b) shows a schematic diagram of the dimensions of the through hole of the three-segment structure of this application, where W2 represents the horizontal projection width of the through hole H. It can be seen that when the depth of the through hole H is also h0, the horizontal projection width W2 of the through hole H is much smaller than W0.

[0037] It has been verified that, Figure 1In the product shown, if a traditional single-segment structure is used, W0 is approximately 965nm when θ0=40° and approximately 1400nm when θ0=30°. However, when using the three-segment structure of this embodiment, by setting the slope angle and depth values ​​of the three segments, W2 can be approximately 600nm, saving 365~800nm ​​of TOP CD space. That is, the three-segment through-hole structure of this embodiment effectively controls the lateral dimensions of the hole opening and bottom by using steep slope angles in the upper and lower segments, while using gentle slope angles in the middle segment to avoid polymer accumulation. At the same through-hole depth h0, the horizontal projection width W2 is significantly reduced compared to a single gentle slope angle structure. This improves the polymer residue problem, ensures the reliability of electrical connections, and can also meet the requirements of high-resolution displays.

[0038] Optionally, the first slope angle θ1 and the third slope angle θ3 are in the range of 70° to 90°, and the second slope angle θ2 is in the range of 20° to 30°.

[0039] For example, θ1 is 78°~80°, θ2 is 19°~21°, and θ3 is 77°~79°.

[0040] In a specific example, θ1 is 79°, θ2 is 20°, and θ3 is 78°.

[0041] Optionally, in the direction perpendicular to the substrate, the ratio of the height of the second hole segment H2 to the total height of the through hole is 1 / 6 to 1 / 4.

[0042] Wherein, the through hole H penetrates the insulating layer 30, and the total height of the through hole H is the thickness of the insulating layer 30 at the location where the through hole is opened. Assuming the total height of the through hole H is denoted as h, the height of the first hole segment H1 is denoted as h1, the height of the second hole segment H2 is denoted as h2, and the height of the third hole segment H3 is denoted as h3, then h = h1 + h2 + h3 is satisfied.

[0043] For example, in a specific example, θ1 is 79°, θ2 is 20°, θ3 is 78°, the total thickness of the insulating layer 30 is 810nm, that is, h=810nm, the height of the first hole segment H1 is h1=450nm, the height of the second hole segment H2 is h2=150nm, the height of the third hole segment H3 is h3=210nm, and h2 / h=150 / 810 ≈0.185.

[0044] In this embodiment, the second hole segment H2 is a gentle slope segment. If the ratio is less than 1 / 6, the gentle slope segment is too short, making it difficult to provide a sufficient discharge path for etching byproducts, and the improvement effect on polymer residue is not significant. If the ratio is greater than 1 / 4, the horizontal width occupied by the gentle slope segment in the horizontal direction is too large, resulting in a large top horizontal width (Top CD) of the through hole H, which is not conducive to the narrow bezel design of high-resolution display panels. In this embodiment, by controlling the ratio of the height h2 of the second hole segment H2 to the total height h of the through hole to be between 1 / 6 and 1 / 4, the gentle slope segment of the through hole H can provide a sufficient discharge channel for polymer while keeping the overall horizontal dimension of the through hole within a small range. Combined with the steep slope angle design of the upper and lower segments, the polymer residue problem can be improved and the electrical connection reliability can be ensured while also meeting the requirements of high-resolution display.

[0045] Optionally, the insulating layer 30 includes at least two sub-insulating layers stacked sequentially along the direction away from the substrate 10. The sub-insulating layer closest to the second functional layer 40 among the at least two sub-insulating layers is the first sub-insulating layer 310. The first hole segment H1 is located in the first sub-insulating layer 310. The first sub-insulating layer is a silicon nitride layer.

[0046] Depending on the specific structure and application scenario of the array substrate, the first functional layer 20 and the second functional layer 40 can be selected from different film layers, such as active layer, light-shielding metal layer, pixel electrode layer, common electrode layer, touch electrode layer, source / drain electrode layer, data line layer or signal trace layer, etc. The two are located at different film layer heights in the array substrate, and their specific types and interlayer distances depend on the film layer architecture of the array substrate and the product application scenario. Therefore, the insulating layer 30 between the two can be a single sub-insulating layer, or a composite layer composed of two, three or more sub-insulating layers stacked sequentially. The material of each sub-insulating layer is independently selected from inorganic insulating materials or organic insulating materials, as long as the top sub-insulating layer closest to the second functional layer 40 is a silicon nitride layer.

[0047] Optionally, in a specific example, such as Figure 5 As shown, the array substrate includes a light-shielding metal layer 101, a buffer layer 102, an active layer 103, a gate insulating layer 104, a gate layer 105, a first inorganic insulating layer 106, a second inorganic insulating layer 107, an organic planarization layer 108, a first electrode layer 109, a passivation layer 110, and a source / drain electrode layer, which are sequentially stacked on one side of the substrate 10. The light-shielding metal layer 101 includes a first conductive portion 101a, the active layer 103 includes an active portion 1031, and the source / drain electrode layer includes a second conductive portion 1111 and a third conductive portion 1112.

[0048] The active layer 103 includes an active portion, the gate layer 105 includes a gate, and the source / drain electrode layer includes a second conductive portion 1111 and a third conductive portion 1112. The second conductive portion 1111 can be one of the source electrode and the drain electrode, and the third conductive portion 1112 can be the other of the source electrode and the drain electrode. The active portion, gate, source electrode and drain electrode at the corresponding positions constitute a thin film transistor structure.

[0049] Specifically, a light-shielding metal layer 101 is disposed on the surface of the substrate 10. In addition to the first conductive portion 101a as shown above, the light-shielding metal layer 101 also includes a light-shielding portion 101b. The light-shielding portion 101b is used to block backlight from one side of the substrate 10 from illuminating the active layer 103, preventing the active layer 103 from generating photo-induced leakage current due to light exposure. The first conductive portion 101a can serve as part of the signal transmission path, electrically connected to the source / drain electrode layer through the second via TH2. The first conductive portion 101a can be used to transmit signals or connect to a fixed potential, thereby assisting in conductivity and reducing signal transmission resistance. A first inorganic insulating layer 106 and a second inorganic insulating layer 107 are sequentially stacked on the side of the gate layer 105 away from the substrate 10, serving as an interlayer insulating layer between the gate layer 105 and the upper first electrode layer 109. The material can be selected from silicon nitride (SiN), silicon oxide (SiO), or a combination of both. An organic planarization layer 108 is disposed on the side of the second inorganic insulating layer 107 away from the substrate 10, and is used to planarize the surface of the array substrate to improve the uniformity of subsequent film layer coverage. A first electrode layer 109 is disposed on the side of the organic planarization layer 108 away from the substrate 10. It can be a pixel electrode layer or a common electrode layer, and can be made of transparent conductive materials such as ITO. It achieves electrical isolation from the underlying gate layer 105 and other film layers through the organic planarization layer 108. A passivation layer 110 is disposed on the side of the first electrode layer 109 away from the substrate 10, and is used to protect the underlying film layer structure and prevent damage to the film layer from subsequent etching processes or external environments. Its material is typically silicon nitride (SiN) or silicon oxide (SiO).

[0050] Optionally, the second conductive part 1111 is connected to the active part 1031 through a first sleeve hole TH1. The first sleeve hole TH1 includes a first through hole TH11 and a second through hole TH12. The first through hole TH11 penetrates the organic planarization layer 108. The passivation layer 110 covers the sidewalls and bottom of the first through hole TH11 and extends to the surface of the organic planarization layer 108 surrounding the first through hole TH11. The second through hole TH12 penetrates the passivation layer 110, the second inorganic insulating layer 107, and the first inorganic insulating layer 106 at the bottom of the first through hole TH11. The second through hole TH12 includes a first segment, a second segment, and a third segment; and / or The third conductive part 1112 is connected to the first conductive part 101a through the second sleeve hole TH2. The second sleeve hole TH2 includes a third through hole TH21 and a fourth through hole TH22. The third through hole TH21 penetrates the organic planarization layer 108. The passivation layer 110 covers the sidewall and bottom of the third through hole TH21 and extends to the surface of the organic planarization layer 108 surrounding the third through hole TH21. The fourth through hole TH22 penetrates the passivation layer 110, the second inorganic insulating layer 107, the first inorganic insulating layer 106, and the buffer layer 102 at the bottom of the third through hole TH21. The fourth through hole TH22 includes a first hole segment, a second hole segment, and a third hole segment.

[0051] In this embodiment, the first conductive portion 101a of the light-shielding metal layer 101 is connected to the third conductive portion 1112 of the source / drain electrode layer through the second via TH2, and the active portion 1031 of the active layer 103 is connected to the second conductive portion 1111 of the source / drain electrode layer through the first via TH1.

[0052] In this embodiment, the via, also known as a stacked via, refers to a composite hole structure consisting of at least two vias that are interconnected in a direction perpendicular to the substrate. One via is opened in the lower film layer, and the other via is opened in the upper film layer. The two form a stacked relationship in space, with a large hole inside a small hole or a vertically connected relationship.

[0053] The first set of holes TH1 is formed by interconnecting the first through hole TH11 penetrating the organic planarization layer 108 and the second through hole TH12 penetrating the passivation layer 110, the first inorganic insulating layer 106 and the second inorganic insulating layer 107; similarly, the second set of holes TH2 is formed by the third through hole TH21 and the fourth through hole TH22.

[0054] The fabrication process of the first set of holes TH1, the second set of holes TH2, and the internal connection structure of the holes can be divided into the following steps: Process 1: After the second inorganic insulating layer 107 is formed, an organic planarization layer 108 is coated and photolithography is performed on it to form a first through-hole TH11 and a third through-hole TH21 in the organic planarization layer 108. The first through-hole TH11 and the third through-hole TH21 penetrate the organic planarization layer 108 to expose the surface of the underlying film layer.

[0055] Process 2: Based on the formation of the first via TH11 and the third via TH21, a first electrode layer 109 and a passivation layer 110 are sequentially deposited. The passivation layer 110 covers the sidewalls and bottom of the first via TH11 and the third via TH21, and extends to the surface of the organic planarization layer 108 surrounding the first via TH11 and the third via TH21. For an example, please refer to... Figure 10 , Figure 10 This is a schematic diagram of the preparation process of the first set of holes TH1. Figure 10 The diagram (a) in the figure shows Figure 5 The film structure after the passivation layer 110 is formed at position Q in the central region.

[0056] Process 3: Using a dry etching process, starting from the passivation layer 110 at the bottom of the first via TH11, the passivation layer 110, the second inorganic insulating layer 107, the first inorganic insulating layer 106 (and the buffer layer 102) are etched to form the second via TH12 (and the fourth via TH22), exposing the surface of the first conductive portion 101a of the light-shielding metal layer 101 or the active portion 1031 of the active layer 103. For example, ... Figure 10 As shown in Figure (b), it is Figure 5 The film structure at position Q in the central region after etching to form the second via TH12.

[0057] Process 4: Deposit source and drain electrode layers to fill the first through-hole TH11, the second through-hole TH12, the third through-hole TH21, and the fourth through-hole TH22, thereby achieving electrical connection between the second conductive part 1111 and the active part 1031, and between the third conductive part 1112 and the active part 1031.

[0058] Among them, the second through hole TH12 is shallower than the fourth through hole TH22. The second through hole TH12 can be described as a shallow hole, and the fourth through hole TH22 can be described as a deep hole.

[0059] It should be noted that in this embodiment, the first set of vias TH1 and the second set of vias TH2 are formed simultaneously through the same photolithography process (one mask). That is, in the photolithography step of the organic planarization layer 108, the first via TH11 and the third via TH21 are formed simultaneously using the same mask. Subsequently, the second via TH12 and the fourth via TH22 are formed simultaneously in the same dry etching process. Among them, the first set of vias TH1 is a shallow via, and the etching of its second via TH12 stops when the surface of the active part 1031 of the active layer 103 is exposed. Under this etching condition, the etching rate of the inorganic insulating layer is much greater than the etching rate of the active layer material (ACT). Therefore, the surface of the active part 1031 acts as a natural etching stop layer, effectively preventing the active layer from being over-etched and damaged. The second set of vias TH2 is a deep via, and its fourth via TH22 needs to be further etched through the buffer layer 102 until the surface of the first conductive part 101a of the light-shielding metal layer 101 is exposed. Thus, by utilizing the difference in film selectivity in the same dry etching process, the first set of holes TH1 and the second set of holes TH2 with different depths are formed simultaneously. The preparation of the two sets of holes can be completed simultaneously by using a mask in conjunction with a dry etching process.

[0060] The second through-hole TH12 includes the first hole segment, the second hole segment, and the third hole segment. This can be understood as the second through-hole TH12 adopting the three-segment through-hole structure of this application. For the second through-hole TH12, the insulating layer 30 at this location includes three sub-insulating layers: a passivation layer 110, a first inorganic insulating layer 106, and a second inorganic insulating layer 107. For an example, please refer to... Figure 6 , Figure 6 for Figure 5 The image shows a scanning electron microscope cross-sectional topography of the film layer at the first set of holes on the array substrate. 106 & 107 represent the stacked structure of the first inorganic insulating layer 106 and the second inorganic insulating layer 107. It can be seen that the second through hole H12 at this location is a three-segment through hole structure.

[0061] Similarly, the fourth through hole TH22, including the first hole segment, the second hole segment and the third hole segment, can be understood as the fourth through hole TH22 adopting the three-segment through hole structure in this application. For the fourth through hole TH22, the insulating layer 30 at this position includes four sub-insulating layers, namely the passivation layer 110, the second inorganic insulating layer 107, the first inorganic insulating layer 106 and the buffer layer 102.

[0062] It is understood that both the second through-hole TH12 and the fourth through-hole TH22 adopt the three-section through-hole structure of this application, and their principle is the same, that is, to form a hole wall morphology with a steep upper section, a gentle middle section, and a steep lower section in the depth direction of the through-hole, so as to balance the compactness of the hole diameter and the effective removal of etching by-products. The only difference between the two is the number of film layers and the total thickness at the location, so the hole depth is different. The height and slope angle of each hole segment can be adjusted according to the actual film layer structure and etching process. The specific values ​​can be the same or different. That is, the three-section through-hole structure of this application is not limited to a specific hole depth or film layer combination, but can be adjusted according to the actual needs of different products.

[0063] It should be noted that the three-segment through-hole structure of the present disclosure is not only applicable to TGBC (Top Gate Bottom Contact) structure, but can also be widely applied to other types of array substrate backplane structures, including but not limited to general BCE (Back Channel Etch) structure, TOP Gate structure, Dual Gate structure, etc.

[0064] For example, please refer to Figure 7 , Figure 7 This is a schematic diagram of the film structure of an array substrate using a BCE structure, as shown below. Figure 7As shown, the array substrate includes a substrate 300, a gate layer 301, a gate insulating layer 302, an active layer 303, a source / drain electrode layer 304, a first passivation layer 305, an organic planarization layer 306, a common electrode layer 307, a second passivation layer 308, and a pixel electrode layer 309 stacked sequentially. The pixel electrode in the pixel electrode layer 309 is connected to the source electrode or drain electrode in the source / drain electrode layer 304 through a transition hole H31.

[0065] In this array substrate, the transition hole H31 adopts a via structure. After the formation of the first passivation layer 305, an organic planarization layer 306 is formed, and a via structure penetrating the organic planarization layer 306 is formed at the transition position. Then, a common electrode layer 307 and a second passivation layer 308 are sequentially prepared. Before the formation of the pixel electrode layer 309, the first passivation layer 305 and the second passivation layer 308 at the via structure need to be etched by a dry etching process to expose the source electrode or drain electrode below. At this time, the via penetrating the first passivation layer 305 and the second passivation layer 308 can also adopt the three-segment via structure provided in the embodiments of this application.

[0066] For example, please refer to Figure 8 , Figure 8 This is a schematic diagram of the film structure of an array substrate using a TOP Gate structure, as shown below. Figure 8 As shown, the array substrate includes a substrate 400, a buffer layer 401, an oxide semiconductor layer 402, a gate insulating layer 403, a gate layer 404, an interlayer dielectric layer 405, a source / drain electrode layer 406, a passivation layer 407, an organic planarization layer 408, an anode layer 409, and a pixel defining layer 410 stacked sequentially.

[0067] In this array substrate, the source electrode and drain electrode in the source and drain electrode layer 406 need to be connected to the oxide semiconductor layer 402 through the transition hole H41 that penetrates the interlayer dielectric layer 405. The interlayer dielectric layer 405 is usually made of inorganic insulating material, which is equivalent to the insulating layer 30 in this application. At this time, the transition hole H41 can also adopt the three-section through-hole structure provided in the embodiment of this application.

[0068] It should be noted that, Figure 7 and Figure 8 The three-section through-hole structure of this application can be used in array substrates of various structures for illustration purposes only. Figure 7 and Figure 8 The specific structure of the three-section through hole is not shown in the image; it can be referenced from [other sources]. Figures 2 to 3 The illustrated embodiment.

[0069] The following description uses the second through hole TH12 as an example to illustrate the specific structure of the three-section through hole structure in this example.

[0070] Specifically, for the second via TH12, the active layer 103 corresponds to the first functional layer 20, the active portion 1031 corresponds to the first functional portion 210, the source / drain electrode layer corresponds to the second functional layer 40, the second conductive portion 1111 corresponds to the second functional portion 410, and the insulating layer 30 includes three insulating layers along the direction away from the substrate: a first inorganic insulating layer 106, a second inorganic insulating layer 107, and a passivation layer 110. The passivation layer 110 corresponds to the first sub-insulating layer 310 closest to the second functional layer. The materials of the first inorganic insulating layer 106, the second inorganic insulating layer 107, and the passivation layer 110 can all be silicon oxide or silicon nitride.

[0071] In a specific example, the passivation layer 110 is made of silicon nitride with a thickness of 200 nm, the second inorganic insulating layer 107 is made of silicon nitride with a thickness of 300 nm, the first inorganic insulating layer 106 is made of silicon oxide with a thickness of 300 nm, the total thickness of the insulating layer 30 is 800 nm, and the total height of the second via TH12 is also 800 nm. In this case, the first sub-insulating layer 310 is a silicon nitride layer, and the first via segment H1 is located in the first sub-insulating layer 310. It can be understood that the depth or height of the first via segment H1 is less than or equal to the thickness of the first sub-insulating layer 310, that is, the maximum depth of the first via segment H1 is the thickness of the first sub-insulating layer 310. With this setting, it can be ensured that the first via segment H1 is necessarily located in the silicon nitride layer.

[0072] Optionally, any one of the at least two sub-insulating layers other than the first sub-insulating layer is a silicon nitride layer or a silicon oxide layer, and in the direction perpendicular to the substrate, the height of the first hole segment is less than or equal to the height of the first sub-insulating layer.

[0073] For example, in Figure 5 In the array substrate shown, the second through hole TH12 adopts a three-segment hole structure, and the insulating layer 30 at this position includes a first inorganic insulating layer 106, a second inorganic insulating layer 107 and a passivation layer 110 stacked in sequence. The passivation layer 110 is equivalent to the first sub-insulating layer 310, while the first inorganic insulating layer 106 and the second inorganic insulating layer 107 are sub-insulating layers other than the first sub-insulating layer 310.

[0074] It should be noted that when both the passivation layer 110 and the second inorganic insulating layer 107 are silicon nitride layers, the first hole segment H1 can be located in both the passivation layer 110 and the second inorganic insulating layer 107. That is, the first sub-insulating layer 310 can be composed of multiple sub-insulating layers of the same material. In this case, the height h1 of the first hole segment H1 can be greater than the thickness of one of the sub-insulating layers, but not exceed the total thickness of the multiple silicon nitride sub-insulating layers. In other words, the definition of the first sub-insulating layer 310 in this application is not limited to a single film layer, but refers to the silicon nitride material region where the first hole segment H1 is located. This region can contain one silicon nitride sub-insulating layer or multiple silicon nitride sub-insulating layers, as long as the first hole segment H1 is located entirely in the silicon nitride material.

[0075] Meanwhile, the heights (h1, h2, h3) of the first hole segment H1, the second hole segment H2, and the third hole segment H3 in this application do not correspond one-to-one with the thickness of each sub-insulating layer in the insulating layer 30, and the insulating layer 30 can be a single-layer, double-layer, triple-layer, quadruple-layer, or more-layer insulating layer structure. Specifically, h1, h2, and h3 are height divisions formed by step-by-step control of the etching process, and their boundaries may or may not coincide with the film interface of each sub-insulating layer. In addition, this embodiment uses a silicon nitride layer as the passivation layer 110, and silicon nitride and silicon oxide layers as the first inorganic insulating layer 106 and the second inorganic insulating layer 107, respectively, as examples, but this does not constitute a limitation of this application. In actual products, the material of each sub-insulating layer of the insulating layer 30 can be any one or a combination of inorganic insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride. Regardless of the inorganic material used in each sub-insulating layer, the three-segment through-hole structure of this application can be applied.

[0076] Optionally, the walls of the first hole segment H1, the second hole segment H2, and the third hole segment H3 transition continuously at the junction of adjacent hole segments.

[0077] In this embodiment, continuous transition means that there are no horizontal steps, platforms or breaks at the junction of the hole walls of adjacent hole segments. That is, the hole wall smoothly changes from the first slope angle θ1 of the first hole segment H1 to the second slope angle θ2 of the second hole segment H2, and then smoothly changes from the second slope angle θ2 of the second hole segment H2 to the third slope angle θ3 of the third hole segment H3, forming a continuous and uninterrupted hole wall profile extending from the upper surface of the insulating layer 30 to the upper surface of the first functional layer 20.

[0078] For example, such as Figure 3 As shown, the junctions of the first hole segment H1 and the second hole segment H2, and the junctions of the second hole segment H2 and the third hole segment H3, are all connected at an angle. That is, the hole walls of adjacent hole segments are directly connected at the junction, but do not form sharp barbs or depressions. The tangential direction of the hole wall surface changes at the junction, but the hole wall itself is continuous and seamless.

[0079] The three-section through-hole structure in this embodiment can be achieved through a single mask process. Specifically, different hole sections have different slopes by controlling the etching conditions at different stages of the dry etching process. The etching conditions include, but are not limited to, parameters such as the etching gas used, the electrode plate power during the etching process, and the gas pressure.

[0080] Based on the same inventive concept, the second aspect of this disclosure provides a method for fabricating an array substrate, such as... Figure 9 As shown, it includes the following steps: Step S101: Provide a substrate.

[0081] Step S102: A first functional layer is formed on one side of the substrate, the first functional layer including a first functional part.

[0082] Step S103: An insulating layer is formed on the side of the first functional part away from the substrate. Through-holes are formed on the insulating layer using an etching process. The through-holes include a first hole segment, a second hole segment, and a third hole segment that are connected in sequence perpendicular to the substrate. The third hole segment is close to the first functional layer, the first hole segment is away from the first functional layer, and the second hole segment connects the first hole segment and the third hole segment. The angle between the hole wall of the first hole segment and a first plane is a first slope angle, the angle between the hole wall of the second hole segment and the first plane is a second slope angle, and the angle between the hole wall of the third hole segment and the first plane is a third slope angle. The first slope angle is greater than the second slope angle, and the third slope angle is greater than the second slope angle. The first plane is a plane parallel to the substrate.

[0083] Step S104: A second functional layer is formed on the side of the insulating layer away from the substrate. The second functional layer includes a second functional part, which is connected to the first functional part through the through-hole.

[0084] Optionally, the step of creating a through-hole in the insulating layer using an etching process includes: First etching stage: The insulating layer is etched using the first etching conditions to form the first hole segment; Second etching stage: After the first etching stage, the insulating layer is etched from the bottom of the first hole segment toward the first functional layer under second etching conditions to form the second hole segment; Third etching stage: After the second etching stage, the insulating layer is etched from the bottom of the second hole segment toward the first functional layer under third etching conditions to form the third hole segment; The first etching stage, the second etching stage, and the third etching stage are performed sequentially and continuously, and the gas pressure of the first etching condition is greater than the gas pressure of the second etching condition and the third etching condition.

[0085] Continue with Figure 5 Taking the second via TH12 (shallow via) in the array substrate as an example, the etching process of the three-segment via structure is described. The second via TH12 penetrates the passivation layer 110, the second inorganic insulating layer 107, and the first inorganic insulating layer 106, exposing the surface of the first conductive portion 101a of the light-shielding metal layer 101. This allows the second conductive portion 1111 of the subsequent source / drain electrode layer to be electrically connected to the first conductive portion 101a through this via. The total depth of the second via TH12 is the sum of the thicknesses of the passivation layer 110, the first inorganic insulating layer 106, and the second inorganic insulating layer 107.

[0086] Specifically, the etching process of the second via TH12 includes three etching stages: First etching stage (forming the first hole segment H1): The passivation layer 110 is dry etched using the first etching conditions to form the first hole segment H1. The gas pressure of the first etching conditions is 15mT~30mT, the etching gas includes NF3 and O2, the upper electrode power is 20K~25K, and the lower electrode power is 5K~15K.

[0087] Specifically, in the first etching stage, a mixed gas of NF3 and O2 is used as the etching gas, with an NF3 flow rate of 1500 sccm to 3000 sccm and an O2 flow rate of 500 sccm to 1500 sccm. The source power is set to 20K to 25K, and the bias power is set to 5K to 15K. The chamber pressure is set to 15mT to 30mT. Under these first etching conditions, the use of a relatively high gas pressure (15mT to 30mT) in conjunction with the NF3 and O2 gas system to etch the silicon nitride material allows for the formation of a first hole segment H1 with a steeper wall in the passivation layer 110. The etching time in the first etching stage is determined based on the thickness and etching rate of the passivation layer 110 to ensure that the bottom of the first hole segment H1 is located at the interface between the passivation layer 110 and the second inorganic insulating layer 107. In this way, the first hole segment H1 is located entirely within the silicon nitride material layer (passivation layer 110), which is beneficial for obtaining a steep hole wall morphology.

[0088] Second etching stage (forming the second via H2): After the first etching stage, the etching conditions are switched to the second etching conditions, and etching continues from the bottom of the first via H1 towards the first functional layer 20. The gas pressure of the second etching conditions is 5mT~15mT, the etching gas includes CF4 and O2, the upper electrode power is 20K~25K, and the lower electrode power is 15K~25K.

[0089] Specifically, in the second etching stage, a mixture of CF4 and O2 is used as the etching gas, with the flow rate of CF4 being 500 sccm to 1500 sccm and the flow rate of O2 being 500 sccm to 1500 sccm; the upper electrode power is set to 20K to 25K and the lower electrode power is set to 15K to 25K; the chamber pressure is set to 5mT to 15mT.

[0090] Compared to the first etching condition, the second etching condition features a lower gas pressure (5mT~15mT) and a higher lower electrode power (15K~25K), with the etching gas switching to a CF4 and O2 system. Under this condition, the etching directionality is weakened, with longitudinal etching accompanied by a certain amount of transverse etching, causing the hole wall slope angle to gradually decrease, thus forming the second hole segment H2. The etching time of the second etching stage is determined according to the preset height h2 of the second hole segment H2. The beginning of the hole wall of the second hole segment H2 naturally connects with the end of the hole wall of the first hole segment H1 at the interface, forming a continuous transition.

[0091] The third etching stage (forming the third hole segment H3): After the second etching stage, the etching conditions are switched to the third etching conditions, and etching continues from the bottom of the second hole segment H2 toward the first functional layer 20. The gas pressure of the third etching conditions is 5mT~15mT, the etching gas includes CF4, O2 and Ar, the upper electrode power is 20K~30K, and the lower electrode power is 10K~15K.

[0092] Specifically, in the third etching condition, a mixed gas of CF4, O2 and Ar is used as the etching gas, wherein the flow rate of CF4 is 500 sccm~1500 sccm, the flow rate of O2 is 400 sccm~1000 sccm, and the flow rate of Ar is 0~500 sccm; the upper electrode power is set to 20K~30K, the lower electrode power is set to 10K~15K, and the chamber gas pressure is set to 5mT~15mT.

[0093] Compared with the second etching condition, the third etching condition introduces Ar gas, which enhances the physical bombardment effect of Ar ions and significantly improves the anisotropy of etching, causing the slope angle of the hole wall to change from gentle to steep, thus forming the third hole segment H3. The third etching stage continues to etch the remaining film layer from the bottom of the second hole segment H2 until the surface of the active layer 104 is exposed. The etching time is determined according to the preset height h3 of the third hole segment H3 to ensure that the second through hole TH12 completely penetrates the passivation layer 110, the first inorganic insulating layer 107, and the second inorganic insulating layer 106 without damaging the active layer 104. The beginning of the hole wall of the third hole segment H3 and the end of the hole wall of the second hole segment H2 naturally connect at the junction to form a continuous transition.

[0094] It should be noted that by adjusting the process parameters of each etching stage, such as adjusting the chamber pressure, upper / lower electrode power, type and flow ratio of etching gas, and etching time of each stage, the slope angle and height of each hole segment can be independently controlled. That is, the preparation method disclosed herein can flexibly adjust the etching conditions of each stage according to the requirements of different products for hole diameter, hole depth and hole wall morphology, so as to form a three-section through hole structure with specific slope angle distribution and depth ratio.

[0095] Based on the same inventive concept, a third aspect of this disclosure provides a display panel including an array substrate as described above.

[0096] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. An array substrate, characterized in that, include: Substrate; A first functional layer is disposed on one side of the substrate, and the first functional layer includes a first functional part; An insulating layer is disposed on the side of the first functional layer away from the substrate. A second functional layer is disposed on the side of the insulating layer away from the substrate, and the second functional layer includes a second functional part; The insulating layer has a through hole, and the second functional part is connected to the first functional part through the through hole, wherein: The via includes a first segment, a second segment, and a third segment that are sequentially connected on the substrate perpendicular to it. The first segment is close to the second functional layer, the third segment is close to the first functional layer, and the second segment connects the first segment and the third segment. The angle between the wall of the first segment and the first plane is a first slope angle, the angle between the wall of the second segment and the first plane is a second slope angle, and the angle between the wall of the third segment and the first plane is a third slope angle. The first slope angle is greater than the second slope angle, and the third slope angle is greater than the second slope angle. The first plane is a plane parallel to the substrate.

2. The array substrate according to claim 1, characterized in that, The first slope angle and the third slope angle are in the range of 70° to 90°, and the second slope angle is in the range of 20° to 30°.

3. The array substrate according to claim 1, characterized in that, In the direction perpendicular to the substrate, the ratio of the height of the second hole segment to the total height of the through hole is 1 / 6 to 1 / 4.

4. The array substrate according to claim 1, characterized in that, The insulating layer includes at least two sub-insulating layers stacked sequentially along the direction away from the substrate. The sub-insulating layer closest to the second functional layer among the at least two sub-insulating layers is the first sub-insulating layer. The first hole segment is located in the first sub-insulating layer, and the first sub-insulating layer is a silicon nitride layer.

5. The array substrate according to claim 4, characterized in that, In the at least two sub-insulating layers, any sub-insulating layer other than the first sub-insulating layer is a silicon nitride layer or a silicon oxide layer, and in the direction perpendicular to the substrate, the height of the first hole segment is less than or equal to the height of the first sub-insulating layer.

6. The array substrate according to claim 1, characterized in that, The walls of the first, second, and third hole segments transition continuously at the junctions of adjacent hole segments.

7. The array substrate according to claim 1, characterized in that, The first functional part is an active part or a conductive part, and the second functional part is a conductive part.

8. The array substrate according to claim 1, characterized in that, The array substrate includes, sequentially stacked on one side of the substrate, a light-shielding metal layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, a first inorganic insulating layer, a second inorganic insulating layer, an organic planarization layer, a first electrode layer, a passivation layer, and a source / drain electrode layer. The light-shielding metal layer includes a first conductive portion, the active layer includes an active portion, and the source / drain electrode layer includes a second conductive portion and a third conductive portion, wherein: The second conductive part is connected to the active part through a first sleeve hole. The first sleeve hole includes a first through hole and a second through hole. The first through hole penetrates the organic planarization layer. The passivation layer covers the sidewalls and bottom of the first through hole and extends to the surface of the organic planarization layer surrounding the first through hole. The second through hole penetrates the passivation layer, the second inorganic insulating layer, and the first inorganic insulating layer at the bottom of the first through hole. The second through hole includes a first segment, a second segment, and a third segment; and / or The third conductive part is connected to the first conductive part through the second set of holes. The second set of holes includes a third through hole and a fourth through hole. The third through hole penetrates the organic planarization layer. The passivation layer covers the sidewall and bottom of the third through hole and extends to the surface of the organic planarization layer around the third through hole. The fourth through hole penetrates the passivation layer, the second inorganic insulating layer, the first inorganic insulating layer and the buffer layer at the bottom of the third through hole. The fourth through hole includes the first hole segment, the second hole segment and the third hole segment.

9. A method for fabricating an array substrate, characterized in that, Includes the following steps: Provide substrates; A first functional layer is formed on one side of a substrate, the first functional layer including a first functional part; An insulating layer is formed on the side of the first functional part away from the substrate. Through-holes are formed on the insulating layer using an etching process. The through-holes include a first hole segment, a second hole segment, and a third hole segment that are connected in sequence perpendicular to the substrate. The third hole segment is close to the first functional layer, the first hole segment is away from the first functional layer, and the second hole segment connects the first hole segment and the third hole segment. The angle between the hole wall of the first hole segment and a first plane is a first slope angle, the angle between the hole wall of the second hole segment and the first plane is a second slope angle, and the angle between the hole wall of the third hole segment and the first plane is a third slope angle. The first slope angle is greater than the second slope angle, and the third slope angle is greater than the second slope angle. The first plane is a plane parallel to the substrate. A second functional layer is formed on the side of the insulating layer away from the substrate. The second functional layer includes a second functional part, which is connected to the first functional part through the through-hole.

10. The method for fabricating an array substrate according to claim 9, characterized in that, The steps of creating through-holes in the insulating layer using an etching process include: First etching stage: The insulating layer is etched using the first etching conditions to form the first hole segment; Second etching stage: After the first etching stage, the insulating layer is etched from the bottom of the first hole segment toward the first functional layer under second etching conditions to form the second hole segment; Third etching stage: After the second etching stage, the insulating layer is etched from the bottom of the second hole segment toward the first functional layer under third etching conditions to form the third hole segment; The first etching stage, the second etching stage, and the third etching stage are performed sequentially, and the gas pressure of the first etching condition is greater than the gas pressure of the second etching condition and the third etching condition.

11. The method for fabricating an array substrate according to claim 10, characterized in that, The first etching condition has a gas pressure of 15mT~30mT, the etching gas includes NF3 and O2, the upper electrode power is 20K~25K, and the lower electrode power is 5K~15K. The second etching condition has a gas pressure of 5mT~15mT, the etching gas includes CF4 and O2, the upper electrode power is 20K~25K, and the lower electrode power is 15K~25K. The third etching condition has a gas pressure of 5mT~15mT, the etching gas includes CF4, O2 and Ar, the upper electrode power is 20K~30K, and the lower electrode power is 10K~15K.

12. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 8.

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