Ultra-low junction capacitance ESD realized by an ultra-deep trench etching process

Abstract

The application provides an ultra-low junction capacitance ESD structure realized by an ultra-deep trench etching process. A high aspect ratio trench is formed by a step-by-step gradient Bosch process, and a composite dielectric filling and multi-step doping design are combined to reduce the junction capacitance while improving the current discharge capacity. The stress matching design of the dielectric layer and the stepped impurity distribution effectively suppress the interface defects, and are suitable for high-speed SerDes interface, radio frequency front-end module and other scenes.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit ESD protection technology, specifically to an ultra-low junction capacitance ESD structure achieved through an ultra-deep trench etching process and its manufacturing method. Background Technology

[0002] Traditional planar ESD protection devices have high junction capacitance (Cj) (>5pF), affecting the signal integrity of high-speed I / O interfaces. While existing deep trench structures can reduce capacitance, the steep sidewalls (tilt angle >85°) of conventional etching processes lead to electric field concentration and large fluctuations in breakdown voltage (Vt1). In addition, single dielectric filling is prone to cracking due to thermal expansion mismatch, reducing reliability. Summary of the Invention

[0003] Technical issues: 1. There is a trade-off between the junction capacitance and breakdown voltage of deep-groove ESD devices; 2. Leakage current issues caused by sidewall damage in high aspect ratio etching processes; 3. Mechanical stress caused by the difference in thermal expansion coefficients between the dielectric layer and the silicon substrate.

[0004] Technical solution: 1. Stepwise gradient etching process: The morphology of the sidewall micro-trenches is controlled by alternating Bosch processes to reduce plasma-induced damage; 2. Composite dielectric filling technology: Silicon nitride and oxygen-rich SiO2 are deposited in a matched manner to balance stress and dielectric strength; 3. Multi-stage doping synergistic design: Gradient impurity distribution expands the depletion region width and reduces the capacitance density per unit area.

[0005] Technical effects: - Junction capacitance (Cj) ≤ 0.8pF@1MHz, 85% lower than planar structure; - The discharge current capability (It2) has been increased to 20A (conventional structure ≤12A); - Breakdown voltage consistency fluctuation ≤3%; - Verified by JEDEC ESD 2kV HBM standard. Attached Figure Description Figure 1: Cross-sectional schematic diagram of an ultra-deep trench ESD structure; Figure 2: Flowchart of alternating Bosch etching process; Figure 3: Comparison of secondary ion mass spectrometry (SIMS) curves of impurity concentration distribution in multi-step doped regions; Figure 4: Comparison of ESD performance data between the conventional structure and the present invention. In this figure, A represents the present invention, and B represents the conventional technology.

Claims

1. An ultra-low junction capacitance ESD protection structure achieved through an ultra-deep trench etching process, characterized in that, include: - Ultra-deep trench structure: trenches (100) with a depth-to-width ratio exceeding 10:1, a depth of 30–100 μm, and a sidewall inclination angle ≤85°; - Composite dielectric filling layer: A double-layer dielectric filling the trench, comprising a low-stress silicon nitride layer (201) adjacent to the silicon substrate and an oxygen-rich silicon dioxide layer (202) on the surface, with a thickness ratio of 1:2–1:4; - Multi-step doped region: Multiple N-type implantation regions (301) and P-type implantation regions (302) are distributed along the trench sidewall to form a stepped depletion capacitance structure; - Conductive channel layer: a titanium-tungsten alloy conductive layer (400) covering a composite dielectric filling layer, which is connected to an external ESD discharge network through a via (401).

2. Claim 2: The etching process of the ultra-deep trench structure adopts an alternating Bosch process, which includes a cyclic passivation gas (C4F8) deposition step and a main etching gas (SF6 / O2) reaction step, with the etching depth increasing by 1–1.5 μm per cycle.

3. Claim 3: The distance between adjacent N-type and P-type regions in the multi-step doped region is 0.5–1 μm, the doping concentration gradient is 1e18 / cm³ to 1e16 / cm³, and an inverted pyramid-shaped impurity distribution is formed by high-energy ion implantation (energy ≥200keV).

4. Claim 4: A tantalum nitride passivation layer (500) with a thickness of 50–100 nm is provided between the composite dielectric filling layer and the conductive channel layer to suppress the accumulation of interface charge.

Images