Bilateral asymmetric pnp structure esd device and method of manufacturing the same

Abstract

The application provides a bidirectional asymmetric PNP structure ESD device and a preparation method thereof. The device comprises a substrate with a first conductive type; a first well region with a second conductive type arranged in the substrate; a second well region with the first conductive type and adjacent to the first well region arranged in the substrate; a first heavily doped region connected with a first port arranged in the second well region; and a second heavily doped region connected with a second port arranged in the first well region. The application integrates high and low voltage protection in a single device, meets the bidirectional asymmetric protection demand of high voltage resistance in positive direction and low voltage resistance in negative direction, greatly reduces the layout area, reduces the parasitic effect, improves the signal integrity, and can flexibly adjust the breakdown voltage by adjusting the well region spacing.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a bidirectional asymmetric PNP structure ESD device and its fabrication method. Background Technology

[0002] In integrated circuit design, electrostatic discharge (ESD) protection circuits are an indispensable and important component of chips. They are used to prevent external electrostatic charges from entering the chip through input / output (I / O) ports or power ports, thereby avoiding irreversible physical damage to the internal core circuitry.

[0003] In some power bus or industrial communication chip applications, negative voltage signals frequently appear on the bus. To ensure normal system operation, the chip needs to be able to properly acquire these negative voltage signals or remain transparent to them. This requires that the negative voltage on the chip's I / O port must not cause leakage to ground (GND). At the same time, the port still needs to maintain a certain level of ESD protection.

[0004] Even more demanding is that, in the aforementioned application scenarios, the voltage withstand requirements for positive and negative potentials at the ports are often different (for example, the positive direction needs to withstand high voltage, while the negative direction only needs to withstand low voltage). To meet this bidirectional ESD protection requirement with different withstand voltages, a common solution in existing technologies is to use two ESD devices with different withstand voltage specifications (i.e., one high-voltage ESD device and one low-voltage ESD device) connected in series back-to-back to achieve bidirectional protection.

[0005] However, the existing technology has at least the following drawbacks: the scheme of using two independent ESD devices in series will not only significantly increase the chip layout area, leading to increased manufacturing costs; but the series structure will also introduce additional parasitic resistance and parasitic capacitance, which will seriously affect the signal integrity and transmission rate in industrial chips for high-speed communication or high-precision acquisition.

[0006] Therefore, there is an urgent need in the field for an asymmetric ESD protection solution that can be integrated into a single device structure and simultaneously meet bidirectional different withstand voltage requirements. Summary of the Invention

[0007] The technical problem to be solved by this invention is: in order to meet the bidirectional different withstand voltage requirements, high voltage and low voltage ESD devices are connected in series, which results in a large layout area and introduces additional parasitic effects that affect signal integrity. This invention provides a bidirectional asymmetric PNP structure ESD device and its fabrication method.

[0008] To address the aforementioned technical problems, this invention provides a bidirectional asymmetric PNP structure ESD device, comprising:

[0009] The substrate has a first type of conductivity;

[0010] A first well region, having a second conductivity type, is disposed in the substrate;

[0011] A second well region having the first conductivity type is disposed in the substrate and is adjacent to the first well region;

[0012] A first heavily doped region, having the first conductivity type, is disposed in the second well region and connected to the first port;

[0013] The second doped region, having the first conductivity type, is disposed in the first well region and connected to the second port.

[0014] Preferably, the first conductivity type is P-type, the second conductivity type is N-type; the substrate is a P-type substrate, the first well region is an N-type well, the second well region is a P-type well, and the first heavily doped region and the second heavily doped region are P-type heavily doped regions.

[0015] Preferably, a low-voltage PNP structure is formed from the first port to the second port, and the breakdown voltage of the low-voltage PNP structure is determined by the PN junction formed by the first well region and the second heavily doped region; a high-voltage PNP structure is formed from the second port to the first port, and the breakdown voltage of the high-voltage PNP structure is determined by the PN junction formed by the first well region and the second well region.

[0016] Preferably, there is a preset distance between the first well region and the second well region, and the breakdown voltage of the high-voltage PNP structure is positively correlated with the preset distance.

[0017] Preferably, the doping concentration of the first well region and the doping concentration of the second heavily doped region determine the breakdown voltage of the low-voltage PNP structure.

[0018] Preferably, it further includes: a deep well region having the second conductivity type, disposed in the substrate below the first well region.

[0019] Preferably, it further includes: an isolation ring, which is disposed as an outer ring around the first well region and the second well region; the isolation ring includes an isolation buried layer, an isolation well region and an isolation heavily doped region stacked sequentially from bottom to top; the isolation buried layer, the isolation well region and the isolation heavily doped region all have the first conductivity type.

[0020] Preferably, it further includes: an internal buried layer having the second conductivity type, disposed in the substrate below the first well region.

[0021] Preferably, it further includes: an epitaxial layer having the first conductivity type, disposed on the substrate; and the first well region and the second well region disposed in the epitaxial layer.

[0022] Preferably, the preset spacing is 0 to 2 μm, and the breakdown voltage of the high-voltage PNP structure is 17 to 53 V.

[0023] This invention also provides a method for fabricating the bidirectional asymmetric PNP structure ESD device as described above, comprising:

[0024] Step 1: Provide a substrate having a first conductivity type;

[0025] Step 2: Form a first well region having a second conductivity type and a second well region having the first conductivity type in the substrate, such that the second well region is adjacent to the first well region;

[0026] Step 3: Form a first heavily doped region having the first conductivity type in the second well region, and form a second heavily doped region having the first conductivity type in the first well region;

[0027] Step 4: Form a first port connecting the first heavily doped region and a second port connecting the second heavily doped region.

[0028] Preferably, in step two, the breakdown voltage of the device in the direction from the second port to the first port is adjusted by controlling the injection spacing between the first well region and the second well region.

[0029] Preferably, in step two or three, implantation regions with the same conductivity type and doping concentration are formed in the same process step.

[0030] As described above, the bidirectional asymmetric PNP structure ESD device and its fabrication method of the present invention have the following beneficial effects:

[0031] This invention ingeniously constructs a bidirectional asymmetric PNP structure by integrating adjacent first and second well regions within a single device and setting heavily doped regions connecting different ports. This structure allows the device to form a low-voltage PNP structure in the direction from the first port to the second port and a high-voltage PNP structure in the direction from the second port to the first port, thus perfectly meeting the bidirectional asymmetric protection requirements of high voltage resistance in the positive direction and low voltage resistance in the negative direction in scenarios such as industrial communication buses. Compared with the traditional series connection scheme of high and low voltage devices, this invention significantly reduces the chip layout area, lowers manufacturing costs, and eliminates the additional parasitic resistance and capacitance introduced by series connection, significantly improving signal integrity during high-speed communication. Furthermore, this invention only requires adjusting the physical spacing between the well regions on the layout to flexibly adjust the breakdown voltage of the high-voltage end, without adding additional masks or changing the underlying implantation process, exhibiting extremely high process flexibility and compatibility. Attached Figure Description

[0032] Figure 1 The diagram shown is a structural schematic of a bidirectional asymmetric PNP structure ESD device according to the present invention.

[0033] Figure 2 The diagram shown is a structural schematic of another bidirectional asymmetric PNP structure ESD device according to the present invention.

[0034] Figure 3 The diagram shown is a structural schematic of another bidirectional asymmetric PNP structure ESD device according to the present invention.

[0035] Figure 4 The diagram shown is a structural schematic of another bidirectional asymmetric PNP structure ESD device according to the present invention.

[0036] Figure 5 The diagram shows the current-voltage characteristic test curves of the low-voltage PNP structure of the present invention.

[0037] Figure 6 The diagram shows a test curve illustrating the relationship between the current-voltage characteristics of the high-voltage PNP structure of the present invention and the physical spacing of the well regions.

[0038] Figure 7 The diagram shows a process flow diagram of a method for fabricating a bidirectional asymmetric PNP structure ESD device according to the present invention. Detailed Implementation

[0039] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] This disclosure provides a bidirectional asymmetric PNP structure ESD device and its fabrication method.

[0041] In some power bus or industrial communication chip applications, negative voltage signals are frequently coupled onto the bus. To ensure normal system operation, the receiver or transceiver inside the chip needs to be able to properly acquire this negative voltage signal or remain transparent to it. This requires that the negative voltage on the input / output port cannot create a leakage path to ground, otherwise it will lead to signal distortion or communication interruption. At the same time, the port still needs to maintain electrostatic discharge (ESD) protection capabilities that meet industry standards. More specifically, in the above applications, the withstand voltage requirements for positive and negative potentials are often different. Traditional solutions typically use two independent ESD protection devices, namely a high-voltage ESD protection device and a low-voltage ESD protection device, connected in series back-to-back to achieve bidirectional protection. However, this series structure not only occupies a large amount of silicon wafer area, increasing manufacturing costs, but also introduces additional parasitic resistance and capacitance, which can cause severe RC delay during high-speed data transmission, reducing signal integrity. The structure disclosed herein can be integrated into a single semiconductor device. Through asymmetric physical structure design, it meets the bidirectional asymmetric protection requirements of positive high voltage resistance and negative low voltage resistance, thereby optimizing the layout area while improving parasitic effects in radio frequency or high-speed communication applications.

[0042] Please refer to Figure 4 , Figure 4 This invention demonstrates a basic embodiment of a bidirectional asymmetric PNP structure ESD device.

[0043] A bidirectional asymmetric PNP structure ESD device includes a substrate 101 having a first conductivity type.

[0044] In some embodiments, the first conductivity type is P-type, and the second conductivity type is N-type; the substrate 101 is a P-type substrate. The P-type substrate can be a bulk silicon wafer doped with P-type impurities such as boron, boron difluoride, or indium. Using a P-type substrate facilitates compatibility with existing standard complementary metal-oxide-semiconductor (CMOS) processes. In other alternative embodiments, the substrate 101 may also comprise a silicon-on-insulator (SiI) wafer, a germanium wafer, a silicon-germanium wafer, a silicon carbide wafer, a gallium arsenide wafer, or other suitable III-V compound semiconductor materials. The substrate 101 may have a specific crystal orientation, for example... <100> or <111> The crystal orientation can be selected, and light or heavy doping can be chosen based on the overall power consumption and leakage current requirements of the device. Furthermore, the first conductivity type can also be N-type, and the second conductivity type can be P-type, to form a bidirectional asymmetric NPN structure, which also falls within the scope of this disclosure.

[0045] The first well region 102, having a second conductivity type, is disposed in the substrate 101.

[0046] In some embodiments, the first well region 102 is an N-type well. The N-type well can be formed by implanting N-type impurities into the substrate 101 using an ion implantation device. The N-type impurities may include phosphorus, arsenic, or antimony. To form a well region with a specific concentration gradient, a chain implantation process with multiple energies and doses can be employed, for example, including deep high-energy implantation to prevent punch-through and shallow low-energy implantation to modulate the surface threshold voltage.

[0047] The second well region 103, having a first conductivity type, is disposed in the substrate 101 and is adjacent to the first well region 102.

[0048] In some embodiments, the second well region 103 is a P-type well. A P-type well can be formed by ion implantation of impurities such as boron or boron difluoride. A PN junction is formed at the adjacent junction of the first well region 102 and the second well region 103. The depletion region width and internal electric field distribution of this PN junction are determined by the doping concentration distribution of the two well regions, which provides a physical basis for subsequent high-voltage protection.

[0049] The first heavily doped region 105, having a first conductivity type, is disposed in the second well region 103 and connected to the first port.

[0050] The second doped region 104, having a first conductivity type, is disposed in the first well region 102 and connected to the second port.

[0051] In some embodiments, the first heavily doped region 105 and the second heavily doped region 104 are P-type heavily doped regions. Heavily doped regions typically have impurity concentrations several orders of magnitude higher than those in well regions. High doping concentrations facilitate the formation of ohmic contacts on the semiconductor surface. In some embodiments, a metal silicide layer, such as titanium silicide, cobalt silicide, or nickel silicide, may also be formed on the surfaces of the first heavily doped region 105 and the second heavily doped region 104 to further reduce contact resistance. Reducing contact resistance can decrease localized Joule heating generated during high current electrostatic discharge, preventing electromigration or thermal melting of the metal in the contact hole region.

[0052] In some embodiments, a low-voltage PNP structure is formed from the first port to the second port, and the breakdown voltage of the low-voltage PNP structure is determined by the PN junction formed by the first well region 102 and the second heavily doped region 104; a high-voltage PNP structure is formed from the second port to the first port, and the breakdown voltage of the high-voltage PNP structure is determined by the PN junction formed by the first well region 102 and the second well region 103. Figure 4As can be seen from the diode symbol, this asymmetric bidirectional PNP structure design allows the device to provide different voltage withstand capabilities in both forward and reverse directions. Specifically, when a negative voltage signal is applied to the first port relative to the second port, the low-voltage PNP structure is in a reverse-biased state. As long as the negative voltage does not reach its breakdown voltage, the device remains transparent and does not leak to ground. However, when a positive high-voltage electrostatic pulse is applied to the second port relative to the first port, the PN junction formed by the first well region 102 and the second well region 103 in the high-voltage PNP structure undergoes avalanche breakdown, and the parasitic bipolar transistor quickly turns on, safely discharging the electrostatic current. This integrated design avoids the area waste caused by the series connection of high-voltage and low-voltage devices in traditional solutions and optimizes the chip layout.

[0053] In some embodiments, the doping concentration of the first well region 102 and the doping concentration of the second heavily doped region 104 determine the breakdown voltage of the low-voltage PNP structure. For example, the breakdown voltage can be around 12V. The avalanche breakdown voltage of the PN junction mainly depends on the concentration of the side with lower doping concentration on both sides of the junction. By precisely adjusting the doping dosage and annealing conditions of the first well region 102 and the second heavily doped region 104, the electric field gradient at the junction interface can be changed, thereby flexibly setting the trigger voltage of the low-voltage PNP structure to match the protection requirements of different low-voltage application scenarios.

[0054] In some embodiments, a preset spacing exists between the first well region 102 and the second well region 103, and the breakdown voltage of the high-voltage PNP structure is positively correlated with this preset spacing. For example, if the preset spacing is 0 to 2 μm, the breakdown voltage of the high-voltage PNP structure is 17 to 53 V. By adjusting the physical spacing between the first well region 102 and the second well region 103 on the layout, the width of the depletion region extending to both sides under reverse bias can be changed. The larger the spacing, the greater the voltage drop that the depletion region can withstand, and the lower the maximum electric field strength inside, thereby leading to an increase in avalanche breakdown voltage. This method of adjusting the breakdown voltage by adjusting the layout spacing rather than by adding an additional mask or changing the implantation process provides chip designers with great process flexibility, enabling the implementation of devices with different breakdown voltage specifications on the same wafer.

[0055] Please refer to Figure 3 , Figure 3 Another embodiment of this disclosure is illustrated. In some embodiments, a deep well region 110 having a second conductivity type is further included, disposed in the substrate 101 below the first well region 102. Figure 3As shown, the deep well region 110 is a deep N-well with an implantation depth greater than that of the first well region 102, typically formed using a high-energy ion implanter at the megaelectronvolt level. The deep well region 110 spans beneath multiple first well regions 102 and second well regions 103. The arrangement of the deep well region 110, in conjunction with the surrounding isolation structure, forms a complete junction isolation system, effectively isolating noise coupling at the bottom of the substrate 101. Furthermore, the deep well region 110 can collect minority carriers injected into the substrate 101 during electrostatic discharge events, preventing these carriers from triggering the accidental turn-on of parasitic transistors, thereby suppressing latch-up effects and improving the reliability of the device in complex industrial environments.

[0056] Continue to refer to Figure 3 In some embodiments, an isolation ring is further included as an outer ring surrounding the first well region 102 and the second well region 103. The isolation ring includes an isolation buried layer 106, an isolation well region 107, and an isolation heavily doped region 108 stacked sequentially from bottom to top. The isolation buried layer 106, the isolation well region 107, and the isolation heavily doped region 108 all have a first conductivity type. The isolation ring is a P-type isolation ring, with the isolation buried layer 106 being a P-type buried layer, the isolation well region 107 being a P-type well, and the isolation heavily doped region 108 being a P-type heavily doped region. The isolation ring is typically formed as a closed ring structure, completely surrounding the core electrostatic discharge protection device. When the device is operating or electrostatic discharge occurs, the isolation ring can act as a collector for majority or minority carriers, absorbing and guiding outwardly diffused stray electrons or holes, safely guiding them to the ground terminal. This prevents carriers generated during electrostatic discharge from being injected into adjacent substrate regions and interfering with other core logic circuits or analog circuits inside the chip, improving the overall system's anti-interference capability. In alternative embodiments, the isolation rings may also be designed as multi-turn structures, or P-type and N-type isolation rings may be alternately arranged to provide a higher level of isolation.

[0057] Please refer to Figure 2 , Figure 2 Another embodiment of this disclosure is illustrated. In some embodiments, an inner buried layer 110 having a second conductivity type is further included, disposed in the substrate 101 below the first well region 102. Figure 2 As shown, the inner buried layer 110 is an N-type buried layer, typically formed by high-dose ion implantation onto the surface of substrate 101 followed by a high-temperature advance annealing process. The inner buried layer 110 has a higher impurity concentration than the first well region 102. The inner buried layer 110 can significantly reduce the parasitic resistance at the bottom of the first well region 102, providing a low-impedance current discharge path during electrostatic discharge events, accelerating the discharge rate of electrostatic discharge current, reducing the device's sustaining voltage, and thus improving the overall secondary breakdown current handling capability of the device. In some alternative solutions, the inner buried layer 110 can also be formed by in-situ doping during epitaxial growth.

[0058] Please refer to Figure 1 , Figure 1 This illustrates one of the most comprehensive embodiments of the structure disclosed herein. In some embodiments, an epitaxial layer having a first conductivity type is further included, disposed on a substrate 101; a first well region 102 and a second well region 103 are disposed in the epitaxial layer. Figure 1 As shown, the epitaxial layer can be epitaxially grown on the surface of substrate 101 using chemical vapor deposition, molecular beam epitaxy, or atomic layer deposition. The material of the epitaxial layer can be the same as substrate 101, such as single-crystal silicon, or can include silicon-germanium alloys used for strain engineering. The precursor gas for growing the epitaxial layer can include silane, dichlorosilane, or trichlorosilane, and the growth process is typically carried out in a high-temperature reaction chamber. By providing an epitaxial layer with the same conductivity type as substrate 101, a purer lattice structure than bulk silicon can be provided for the device, significantly reducing oxygen deposition and surface defects in the bulk, thereby reducing leakage current under normal operating conditions, improving carrier mobility, and enhancing the breakdown characteristics and thermal stability of electrostatic discharge protection devices. Simultaneously, Figure 1 In the embodiment, a deep well region 109 and an inner buried layer 110 are combined. The deep well region 109 is located between the first well region 102 and the inner buried layer 110. This composite structure can optimize the longitudinal electric field distribution and current discharge capability to the greatest extent.

[0059] In some embodiments, a plurality of isolation structures are further included on the surface of each well region to isolate adjacent heavily doped regions. The isolation structures can be shallow trench isolation structures or localized silicon oxide isolation structures. The formation process of a shallow trench isolation structure typically involves etching trenches into the semiconductor surface, filling the trenches with an insulating material, such as silicon oxide deposited by high-density plasma chemical vapor deposition, and finally planarizing them using a chemical mechanical polishing process. The isolation structures effectively prevent surface leakage between adjacent active regions and define the active boundaries of each heavily doped region.

[0060] Please refer to Figure 5 , Figure 5The current-voltage characteristic test curves of the low-voltage PNP structure in this embodiment are shown. The test data reflects the breakdown characteristics from the first port to the second port. The horizontal axis represents the applied voltage, and the vertical axis represents the current flowing through the device. It can be clearly observed from the figure that within the normal operating range of approximately 12 to 13 volts, the leakage current of the device remains at an extremely low level in the picoampere range. This indicates that the low-voltage PNP structure remains highly transparent to the bus signal in the untriggered state, without causing signal attenuation or leakage to ground. When the applied voltage reaches approximately 13 volts, the curve exhibits an extremely steep upward trend, indicating that a strong avalanche breakdown has occurred in the PN junction formed by the first well region and the second heavily doped region. This rapid turn-on characteristic allows the device to quickly provide a low-impedance discharge path at the moment of an electrostatic discharge event, effectively protecting the internal core circuitry from electrostatic damage at the low-voltage ports.

[0061] Please refer to Figure 6 , Figure 6 Test curves illustrating the relationship between the current-voltage characteristics of the high-voltage PNP structure and the physical spacing of the well regions in embodiments of this disclosure are presented. The test data reflects the breakdown characteristics from the second port to the first port. The figure includes multiple independent current-voltage curves, each corresponding to different preset spacing parameters between the first and second well regions. The test results visually verify a significant positive correlation between the breakdown voltage of the high-voltage PNP structure and the preset spacing. Specifically, when the preset spacing is zero micrometers, the device breakdown voltage is approximately 16 to 17 volts; as the preset spacing gradually increases, the breakdown voltage exhibits a regular shift towards higher voltage. When the spacing parameter increases to the maximum value shown in the figure, the breakdown voltage can be significantly increased to approximately 52 to 53 volts. Throughout the voltage scan range, all curves maintain extremely low leakage current levels before breakdown. This test result fully demonstrates that the asymmetric structure provided by this disclosure can precisely customize the trigger voltage of the high-voltage end within a very wide voltage range by simply adjusting the physical spacing on the layout, thereby meeting the stringent high-voltage protection requirements of different industrial communication buses, without adding any additional masks or changing the underlying injection process.

[0062] Please see Figure 7 A method for fabricating a bidirectional asymmetric PNP structure ESD device, comprising:

[0063] Step 1: Provide a substrate 101 having a first conductivity type.

[0064] In some embodiments, the step of providing substrate 101 can be performed by an automated material handling system that delivers a wafer cassette containing a silicon wafer into the process chamber of a semiconductor manufacturing apparatus. Substrate 101 can undergo an initial wet cleaning process, such as using a mixture of sulfuric acid and hydrogen peroxide to remove organic contaminants from the surface, followed by the removal of the native oxide layer using dilute hydrofluoric acid. After cleaning, high-temperature oxidation can be performed in a thermal oxidation furnace under oxygen or water vapor conditions to grow a silicon dioxide sacrificial layer of controllable thickness on the wafer surface. This sacrificial layer can mitigate channeling effects during subsequent ion implantation processes and protect the crystal structure from direct bombardment damage by high-energy ions.

[0065] Step 2: Form a first well region 102 having a second conductivity type and a second well region 103 having a first conductivity type in the substrate 101, such that the second well region 103 is adjacent to the first well region 102.

[0066] In some embodiments, in step two, the breakdown voltage of the device in the direction from the second port to the first port is adjusted by controlling the implantation spacing between the first well region 102 and the second well region 103. In the photolithography process, a layer of photoresist is first spin-coated onto the wafer surface, and then the photomask is exposed using ultraviolet, deep ultraviolet, or extreme ultraviolet light by a photolithography machine. By adjusting the physical distance between the light-transmitting patterns corresponding to the first well region 102 and the second well region 103 on the photomask, an opening pattern with a specific spacing can be formed on the developed photoresist. Subsequently, using the patterned photoresist as a barrier layer, specific impurity ions are implanted into the substrate 101 using an ion implanter. This method does not require changing the energy or dosage settings of the implanter; different breakdown voltage levels can be customized simply by adjusting the pattern during the layout design stage, reducing process complexity and R&D costs.

[0067] In some embodiments, in step two, implantation regions with the same conductivity type and doping concentration are formed in the same process step. For example, when an isolation well region 107 with a first conductivity type needs to be formed around the device periphery, this isolation well region 107 can share the same mask as the internal second well region 103. In the same photolithography exposure and the same ion implantation process, impurity ions simultaneously enter the predetermined positions of the isolation well region 107 and the second well region 103. This process integration strategy reduces the total number of photolithography masks, reduces repetitive process steps such as resist coating, exposure, development, implantation, and resist removal, thereby significantly shortening the production cycle, reducing manufacturing costs, and reducing overlay errors that may be caused by multiple photolithography alignments.

[0068] Step 3: A first heavily doped region 105 with a first conductivity type is formed in the second well region 103, and a second heavily doped region 104 with a first conductivity type is formed in the first well region 102.

[0069] In some embodiments, in step three, implanted regions with the same conductivity type and doping concentration are formed in the same process step. Since both the first heavily doped region 105 and the second heavily doped region 104 have the first conductivity type and typically have the same doping concentration requirement, they can be formed using the same mask in the same high-dose ion implantation process. If there is an outer isolation heavily doped region 108, it can also be formed at this time. After ion implantation, plasma ashing and wet cleaning equipment are typically used to remove the photoresist on the surface. Subsequently, the wafer is fed into a rapid thermal annealing or peak annealing equipment for short-term annealing at high temperature. The annealing process can activate the implanted impurity ions, causing them to enter the substitution sites in the crystal lattice, while repairing the lattice damage caused by ion bombardment and restoring the electrical properties of the semiconductor material.

[0070] Step 4: Form a first port connecting the first heavily doped region 105 and a second port connecting the second heavily doped region 104.

[0071] In some embodiments, the process of forming ports typically includes a back-end process for multilayer interconnects.

[0072] Before forming contact holes, a contact etch stop layer can be conformally deposited on the wafer surface. The material can include silicon nitride, silicon carbonitride, or silicon oxynitride to protect the underlying silicon surface and provide stress engineering during subsequent etching.

[0073] Subsequently, one or more interlayer dielectric layers are deposited on the contact etch stop layer using high-density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, or plasma-enhanced chemical vapor deposition processes. The materials of the interlayer dielectric layers may include undoped silicate glass, borosilicate glass, fluorinated silicate glass, phosphosilicate glass, or carbon-doped silicon oxide, porous low-dielectric-constant materials, and spin-coated dielectric materials used to further reduce parasitic capacitance.

[0074] Next, a bottom anti-reflective layer and photoresist are sequentially coated on the surface of the interlayer dielectric layer. The pattern of the contact hole is defined by exposure and development processes using a photolithography machine. Subsequently, an anisotropic reactive ion etching process is employed, using fluorine-containing plasma gas to etch downwards through the interlayer dielectric layer and the contact etch stop layer, exposing the surfaces of the first and second heavily doped regions of the underlying substrate. After etching, residual photoresist and etching polymer are removed by ashing and wet cleaning. To prevent the diffusion of subsequently filled metal atoms into the silicon substrate, which could lead to junction leakage, and to simultaneously reduce contact resistance, a conformal barrier layer or adhesion layer is typically deposited on the sidewalls and bottom of the contact hole. This barrier layer can be formed by physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes, and its material can include titanium, titanium nitride, tantalum, tantalum nitride, tungsten, or a composite stack thereof. For example, a layer of pure titanium can be deposited first to react with the underlying silicon to form a low-resistance titanium silicide contact, and then a layer of titanium nitride can be deposited as a barrier layer.

[0075] Subsequently, conductive metal is filled into the contact holes. For tungsten plugs, tungsten metal can be deposited using tungsten hexafluoride gas reduction deposition via chemical vapor deposition. For copper interconnects, a thin copper seed layer can be formed first via physical vapor deposition, followed by electrochemical plating to fill the holes with copper metal from bottom to top. In some mature processes, aluminum or aluminum-copper alloys can also be used for filling via physical vapor deposition. After metal filling, the wafer surface is ground using chemical mechanical polishing to remove excess metal and barrier layer material from the interlayer dielectric layer, achieving a high degree of surface planarization, thereby forming the metal plug embedded in the dielectric layer.

[0076] Finally, by repeating the single-damascene or double-damascene processes described above, including dielectric layer deposition, photolithography, etching, and metal filling, multilayer metal interconnects and interlayer vias are sequentially formed. A passivation layer composed of high-density silicon nitride, undoped silicate glass, or polyimide is deposited on top of the outermost metal layer to provide mechanical protection and moisture isolation. Finally, by openings in the passivation layer, the first and second ports are led out to aluminum pads, copper pillars, or solder bumps on the top layer of the chip to achieve electrical connection and signal transmission between the device and external package pins.

[0077] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0078] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A bidirectional asymmetric PNP structure ESD device, characterized in that... include: The substrate has a first type of conductivity; A first well region, having a second conductivity type, is disposed in the substrate; A second well region having the first conductivity type is disposed in the substrate and is adjacent to the first well region; A first heavily doped region, having the first conductivity type, is disposed in the second well region and connected to the first port; The second doped region, having the first conductivity type, is disposed in the first well region and connected to the second port.

2. The bidirectional asymmetric PNP structure ESD device according to claim 1, characterized in that: The first conductivity type is P-type, and the second conductivity type is N-type; the substrate is a P-type substrate, the first well region is an N-type well, the second well region is a P-type well, and the first heavily doped region and the second heavily doped region are P-type heavily doped regions.

3. The bidirectional asymmetric PNP structure ESD device according to claim 1, characterized in that: A low-voltage PNP structure is formed from the first port to the second port, and the breakdown voltage of the low-voltage PNP structure is determined by the PN junction formed by the first well region and the second heavily doped region; a high-voltage PNP structure is formed from the second port to the first port, and the breakdown voltage of the high-voltage PNP structure is determined by the PN junction formed by the first well region and the second well region.

4. The bidirectional asymmetric PNP structure ESD device according to claim 3, characterized in that: There is a preset distance between the first well region and the second well region, and the breakdown voltage of the high-voltage PNP structure is positively correlated with the preset distance.

5. The bidirectional asymmetric PNP structure ESD device according to claim 3, characterized in that: The doping concentration of the first well region and the doping concentration of the second heavily doped region determine the breakdown voltage of the low-voltage PNP structure.

6. The bidirectional asymmetric PNP structure ESD device according to claim 1, characterized in that: Also includes: A deep well region, having the second conductivity type, is disposed in the substrate below the first well region.

7. The bidirectional asymmetric PNP structure ESD device according to claim 1, characterized in that: Also includes: An isolation ring is disposed as an outer ring around the first well region and the second well region; the isolation ring includes an isolation buried layer, an isolation well region and an isolation heavily doped region stacked sequentially from bottom to top; The buried isolation layer, the isolation trap region, and the heavily doped isolation region all have the first conductivity type.

8. The bidirectional asymmetric PNP structure ESD device according to claim 1, characterized in that: Also includes: An internal buried layer, having the second conductivity type, is disposed in the substrate below the first well region.

9. The bidirectional asymmetric PNP structure ESD device according to claim 1, characterized in that: Also includes: An epitaxial layer having the first conductivity type is disposed on the substrate; The first well region and the second well region are disposed in the epitaxial layer.

10. The bidirectional asymmetric PNP structure ESD device according to claim 4, characterized in that: The preset spacing is 0 to 2 μm, and the breakdown voltage of the high-voltage PNP structure is 17 to 53 V.

11. A method for fabricating a bidirectional asymmetric PNP structure ESD device as described in any one of claims 1 to 10, characterized in that, include: Step 1: Provide a substrate having a first conductivity type; Step 2: Form a first well region having a second conductivity type and a second well region having the first conductivity type in the substrate, such that the second well region is adjacent to the first well region; Step 3: Form a first heavily doped region having the first conductivity type in the second well region, and form a second heavily doped region having the first conductivity type in the first well region; Step 4: Form a first port connecting the first heavily doped region and a second port connecting the second heavily doped region.

12. The method for fabricating a bidirectional asymmetric PNP structure ESD device according to claim 11, characterized in that: In step two, the breakdown voltage of the device in the direction from the second port to the first port is adjusted by controlling the injection spacing between the first well region and the second well region.

13. The method for fabricating a bidirectional asymmetric PNP structure ESD device according to claim 11, characterized in that: In step two or three, implantation regions with the same conductivity type and doping concentration are formed in the same process step.

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