A protection circuit, integrated circuit and protection method

Abstract

The embodiment of the present application provides a protection circuit, an integrated circuit and a protection method, the circuit comprising a substrate, a P-type isolation region, a plurality of N-type wells, a first P-type doping structure arranged in each N-type well, and an N-type doping structure in contact with the first P-type doping structure, the P-type isolation region being arranged in the substrate, the plurality of N-type wells being arranged in the P-type isolation region, and the protection circuit further comprising an insulating structure arranged in the P-type isolation region and located between two adjacent N-type wells. In the two adjacent N-type wells, the N-type doping structure of one of the N-type wells is electrically connected to a signal interface, and the N-type doping structure of the other of the N-type wells is electrically connected to a ground interface. The technical scheme can improve the electrostatic discharge capacity of the protection circuit to the chip under a smaller layout area.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a protection circuit, integrated circuit, and protection method. Background Technology

[0002] Currently, PNP transistors can be used to construct chip protection circuits so that when the chip experiences electrostatic discharge, the electrostatic discharge can be promptly released through the chip protection circuit, thereby achieving the purpose of protecting the chip.

[0003] In related technologies, chip protection circuits constructed with PNP transistors have limited electrostatic discharge capability per unit area, requiring the use of larger area protection circuits to provide a certain level of protection for the chip. Summary of the Invention

[0004] The purpose of this application is to provide a protection circuit, integrated circuit, and protection method to improve the electrostatic discharge capability of the protection circuit for the chip with a smaller layout area.

[0005] In a first aspect, embodiments of this application provide a protection circuit for protecting a target chip, the target chip having a signal interface and a ground interface. The protection circuit includes: a substrate, a P-type isolation region, a plurality of N-type wells, a first P-type doped structure disposed in each of the plurality of N-type wells, and an N-type doped structure in contact with the first P-type doped structure. The P-type isolation region is disposed in the substrate, and the plurality of N-type wells are disposed in the P-type isolation region. The protection circuit also includes an insulating structure disposed in the P-type isolation region between two adjacent N-type wells.

[0006] The plurality of N-type wells include a first N-type well and a second N-type well. The N-type doped structure in the first N-type well is electrically connected to the signal interface, and the N-type doped structure in the second N-type well is electrically connected to the ground interface. The first P-type doped structure, the first N-type well, and the P-type isolation region in the first N-type well constitute a first PNP transistor. The first N-type well, the P-type isolation region, and the second N-type well constitute an NPN transistor. The first P-type doped structure, the second N-type well, and the P-type isolation region in the second N-type well constitute a second PNP transistor.

[0007] The NPN transistor has a bidirectional conduction function. The first PNP transistor is used to conduct when electrostatic discharge occurs at the signal interface, so as to control the NPN transistor to conduct along the direction from the first N-type well to the second N-type well, so that the static electricity generated at the signal interface is discharged to the ground interface through the NPN transistor. The second PNP transistor is used to conduct when electrostatic discharge occurs at the ground interface, so as to control the NPN transistor to conduct along the direction from the second N-type well to the first N-type well, so that the static electricity generated at the ground interface is discharged to the signal interface through the NPN transistor.

[0008] In the protection circuit of this application embodiment, when multiple N-type wells include a first N-type well and a second N-type well, the first P-type doped structure, the first N-type well, and the P-type isolation region in the first N-type well constitute a first PNP transistor. Therefore, when the N-type doped structure in the first N-type well is electrically connected to the signal interface, if electrostatic discharge occurs at the signal interface, causing a sudden increase in the voltage of the signal interface, the signal interface current can enter the N-type doped structure of the first PNP transistor. Under high voltage, the N-type doped structure and the first P-type doped structure of the first PNP transistor undergo reverse breakdown, causing the signal interface current to enter the first P-type doped structure mainly through the N-type doped structure of the first PNP transistor, and also through the N-type doped structure of the first PNP transistor into the first N-type well. Therefore, in the first PNP transistor, the potential of the first P-type doped structure, which serves as the emitter, is higher than that of the first N-type well, which serves as the base. At this time, the first PNP transistor is turned on, and the signal interface current can enter the P-type isolation region through the N-type doped structure, the first P-type doped structure, and the first N-type well of the first PNP transistor. Since the first N-type well, the P-type isolation region, and the second N-type well constitute an NPN transistor, and the N-type doped structure in the second N-type well is electrically connected to the ground interface, when the first PNP transistor transmits the signal interface current to the P-type isolation region, the P-type isolation region acts as the base, and its potential is higher than that of the second N-type well, which acts as the emitter. Therefore, under the control of the potential output of the first transistor, the NPN transistor conducts along the direction from the first N-type well to the second N-type well, so that the current in the first N-type well can enter the second N-type well through the P-type isolation region, and then enter the N-type doped structure in the second N-type well, and is released through the ground interface.

[0009] Furthermore, since the first P-type doped structure, the second N-type well, and the P-type isolation region in the second N-type well constitute the second PNP transistor, if electrostatic discharge occurs at the ground interface, causing a sudden increase in the voltage of the ground interface, the ground interface current can enter the N-type doped structure in the second N-type well, and then enter the P-type isolation region through the first P-type doped structure and the second N-type well of the second PNP transistor. The NPN transistor composed of the first N-type well, the P-type isolation region, and the second N-type well has bidirectional conduction function. Therefore, when the ground interface current reaches the P-type isolation region, the base potential of the NPN transistor can be controlled to be higher than the potential of the first N-type well in the NPN transistor. Thus, under the control of the P-type isolation region, the NPN transistor can conduct along the direction from the second N-type well to the first N-type well, allowing the ground interface current to enter the NPN transistor from the second N-type well, then enter the N-type doped structure in the first N-type well through the first N-type well of the NPN transistor, and finally be released through the signal interface.

[0010] As can be seen, the protection circuit of this application embodiment, by designing multiple N-type wells and using insulating structures to ensure that no signal interference occurs between different N-type wells, further discharges static electricity released from the signal interface and the ground interface by forming first P-type doped structures and N-type doped structures within the N-type wells. Moreover, since the first P-type doped structures and N-type doped structures are placed within the N-type wells, the forward voltage of the protection circuit can be increased. Thus, this protection circuit does not require a large number of PNP transistors connected in series to achieve circuit protection when high-voltage electrostatic discharge occurs at the signal interface and the ground interface. Therefore, the protection circuit of this application embodiment requires a relatively small layout area.

[0011] In addition, the first P-type doped structure, the N-type doped structure, the P-type isolation region, the first N-type well and the second N-type well that constitute the first PNP transistor, the second PNP transistor and the NPN transistor are all integrated in the same P-type isolation region disposed on the substrate, making the structure of the protection circuit more compact, thereby further reducing the layout area of ​​the protection circuit.

[0012] In one possible implementation, the protection circuit further includes a second P-type doped structure disposed in each of the plurality of N-type wells. The N-type doped structure is located between the first P-type doped structure and the second P-type doped structure, and the N-type doped structure is in contact with the second P-type doped structure.

[0013] In one possible implementation, the depth of the N-type well is less than a first preset depth, and the concentration of N-type doped ions in the N-type well is less than the first preset concentration.

[0014] In one possible implementation, the depth of the N-type well is greater than a second preset depth, the second preset depth is greater than a first preset depth, and the N-type dopant concentration of the N-type well is greater than a second preset concentration.

[0015] Furthermore, by increasing the series resistance through a deeper N-type well, the base current of the first PNP transistor and the second PNP transistor can be limited, the trigger current can be reduced, and the first PNP transistor and the second PNP transistor can be turned on more stably and controllably during ESD release. In addition, by increasing the series resistance, the current surge caused by transient large current can be reduced, the risk of local hot spots and thermal failure can be reduced, and the reliability of the device can be improved.

[0016] In one possible implementation, the N-type well includes a first N-type well region and a second N-type well region. The first N-type well region is located within a P-type isolation region, and the second N-type well region is located within the first N-type well region. The depth of the first N-type well region is greater than the depth of the second N-type well region. The second N-type well region, the first P-type doped structure, and the N-type doped structure are all located within the first N-type well region, and the N-type dopant concentration in the second N-type well region is higher than the N-type dopant concentration in the first N-type well region.

[0017] In one possible implementation, in two adjacent N-type wells, one includes an N-type doped structure electrically connected to a ground interface, and the other includes an N-type doped structure electrically connected to a signal interface.

[0018] In one possible implementation, the protection circuit further includes an N-type isolation region. This N-type isolation region is disposed within the substrate, and a P-type isolation region is disposed within the N-type isolation region. The N-type isolation region is electrically connected to the power supply terminal.

[0019] In one possible implementation, the substrate is a P-type substrate, and the protection circuit further includes a third P-type doped structure disposed on the substrate, which is connected to the ground interface.

[0020] Secondly, embodiments of this application also provide a protection circuit, including: a first PNP transistor, a second PNP transistor, and an NPN transistor. The first PNP transistor, the second PNP transistor, and the NPN transistor are integrated within the same P-type isolation region disposed on a substrate.

[0021] The base and emitter of the first PNP transistor are both electrically connected to the signal interface; the base of the NPN transistor is electrically connected to the collector of the first PNP transistor, the first electrode of the NPN transistor is electrically connected to the signal interface, and the second electrode of the NPN transistor is electrically connected to the ground interface; the base and emitter of the second PNP transistor are both electrically connected to the ground interface, and the collector of the second PNP transistor is electrically connected to the collector of the first PNP transistor.

[0022] The first PNP transistor is used to turn on when electrostatic discharge occurs at the signal interface, so as to control the NPN transistor to conduct along the direction from the first electrode to the second electrode, so that the static electricity generated at the signal interface is discharged to the ground interface through the NPN transistor; the second PNP transistor is used to turn on when electrostatic discharge occurs at the ground interface, so as to control the NPN transistor to conduct along the direction from the second electrode to the first electrode, so that the static electricity generated at the ground interface is discharged to the signal interface through the NPN transistor.

[0023] As can be seen, the protection circuit of this application embodiment utilizes a combination of a first PNP transistor, a second PNP transistor, and an NPN transistor with bidirectional conduction function. When electrostatic discharge occurs at the signal interface and ground interface, it simulates the working principle of a silicon controlled rectifier (SCR) transistor to discharge the static electricity generated at these interfaces, thereby protecting the target chip. Furthermore, this protection circuit does not require a large number of PNP transistors connected in series, effectively reducing the layout area required for the protection circuit. Moreover, the integration of the first PNP transistor, the second PNP transistor, and the NPN transistor within the same P-type isolation region on the substrate makes the protection circuit structure more compact, further reducing the layout area of ​​the protection circuit.

[0024] In one possible implementation, the protection circuit further includes a first equivalent resistor and a second equivalent resistor. The signal interface is electrically connected to the first electrode of the NPN transistor via the first equivalent resistor; the second electrode of the NPN transistor is electrically connected to the ground interface via the second equivalent resistor.

[0025] Thirdly, embodiments of this application also provide an integrated circuit, including a target chip and a protection circuit. The target chip has a signal interface and a ground interface. The protection circuit includes the protection circuit described in the first aspect of the embodiments of this application or any possible implementation of the first aspect, or the protection circuit described in the second aspect of the embodiments of this application or any possible implementation of the second aspect.

[0026] The protection circuit includes a first PNP transistor whose emitter and the first electrode of an NPN transistor are both electrically connected to the signal interface, and a second PNP transistor whose emitter and the second electrode of an NPN transistor are both electrically connected to the ground interface.

[0027] Fourthly, embodiments of this application also provide a protection method applied to an integrated circuit having a target chip and a protection circuit. The target chip has a signal interface and a ground interface, and the protection circuit includes a first PNP transistor, an NPN transistor, and a second PNP transistor, wherein the NPN transistor has bidirectional conduction functionality. The method includes: When electrostatic discharge occurs at the signal interface, the first PNP transistor is turned on to control the NPN transistor to conduct along the direction from the first electrode of the NPN transistor to the second electrode of the NPN transistor, so that the electrostatic discharge generated at the signal interface is discharged to the ground interface through the NPN transistor. When electrostatic discharge occurs at the grounding interface, the second PNP transistor is turned on to control the NPN transistor to conduct along the direction from the second electrode of the NPN transistor to the first electrode of the NPN transistor, so that the static electricity generated at the grounding interface is discharged to the signal interface through the NPN transistor.

[0028] The beneficial effects of the technical solutions of the third and fourth aspects of the embodiments of this application can be referred to the beneficial effects of the protection current described in the first aspect or any one of the first aspects of the embodiments of this application, or the beneficial effects of the protection circuit described in the second aspect or a possible implementation of the second aspect of the embodiments of this application. Attached Figure Description

[0029] Further details, features, and advantages of this application are claimed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which: Figure 1 A schematic structural diagram of an integrated circuit according to a preferred embodiment of this application is shown; Figure 2 A schematic diagram of the semiconductor structure of the protection circuit according to an embodiment of this application is shown; Figure 3 This invention illustrates the electrostatic discharge principle of the signal interface when electrostatic discharge occurs according to an embodiment of the present application. Figure 4 This invention illustrates the electrostatic discharge principle when the grounding interface of this application experiences electrostatic discharge. Figure 5 The diagram shows a schematic of the protection circuit according to an embodiment of this application when the depth of the N-type well is relatively large; Figure 6 This paper shows a schematic diagram of the structure of an embodiment of the present application, taking a first N-type well as an example; Figure 7 This paper shows a schematic diagram of the equivalent circuit structure of the protection circuit of this application when electrostatic discharge occurs at the signal interface. Figure 8 A schematic diagram of the equivalent circuit structure of the protection circuit according to an embodiment of this application is shown when electrostatic discharge occurs at the grounding interface. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this disclosure more apparent, exemplary embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments of this disclosure. It should be understood that this disclosure is not limited to the exemplary embodiments described herein.

[0031] High-voltage signal interfaces, also known as high-voltage I / O, typically operate at a voltage positive relative to ground voltage. To prevent high-voltage I / O latch-up, the protection circuit for high-voltage I / O usually includes a PNP transistor. This PNP transistor utilizes its high trigger voltage and high hysteresis voltage characteristics to discharge the electrostatic discharge (ESD) current generated by the high-voltage I / O, thereby achieving the purpose of discharging static electricity and preventing high-voltage I / O latch-up.

[0032] However, protection circuits using PNP transistors have limited electrostatic discharge capacity per unit area, making them ineffective at protecting high-voltage I / O. To improve the protection capability of protection circuits for high-voltage I / O, protection circuits typically require a larger layout area.

[0033] This application provides an integrated circuit that can use a protection circuit to protect a target chip from ESD. This protection circuit can improve the electrostatic discharge capability of the chip with a small layout area.

[0034] Figure 1 A schematic structural diagram of an integrated circuit according to an embodiment of this application is shown. For example... Figure 1As shown, the integrated circuit 100 of this application embodiment includes a target chip 101 and a protection circuit 102. The target chip 101 has a signal interface IO and a ground interface VSS. The protection circuit 102 may include a first PNP transistor, a second PNP transistor, and an NPN transistor. The emitter of the first PNP transistor and the first electrode of the NPN transistor are both electrically connected to the signal interface IO, and the emitter of the second PNP transistor and the second electrode of the NPN transistor are both electrically connected to the ground interface VSS.

[0035] Optionally, when the target chip 101 has multiple signal interfaces (IO), the number of protection circuits 102 is also multiple, and each circuit corresponds one-to-one with a signal interface (IO). Different protection circuits 102 can be connected to the same ground interface (VSS) simultaneously. If the target chip 101 has multiple ground interfaces (VSS), the signal interface (IO) can also be connected to different ground interfaces (VSS).

[0036] Optionally, the target chip 101 also has a power interface VDD, and the protection circuit 102 can also be connected to the power interface VDD, which can provide a reference voltage for the protection circuit 102. When there are multiple protection circuits 102, multiple protection circuits 102 can be connected to the power interface VDD simultaneously.

[0037] When the target chip 101 of this application is working normally, the silicon controlled rectifier (SCR) transistor with a PNPN structure composed of the first PNP transistor and the NPN transistor is in a high-resistance state, which will not affect the normal transmission of the target chip 101.

[0038] When the signal interface IO of the target chip 101 in this embodiment of the application experiences electrostatic discharge, the voltage of the signal interface IO surges and exceeds the trigger voltage threshold of the silicon controlled rectifier (SCR) transistor, which is a PNPN structure composed of a first PNP transistor and an NPN transistor. At this time, the SCR transistor is in a positive feedback state, and both the first PNP transistor and the NPN transistor are turned on. Therefore, the SCR transistor quickly enters a low configuration state, and the emitter of the first PNP transistor becomes the electrostatic inlet, discharging to the ground interface VSS through the first PNP transistor and the NPN transistor.

[0039] When the ground interface VSS of the target chip 101 in this embodiment of the application experiences electrostatic discharge, the voltage of the ground interface VSS surges and exceeds the voltage of the signal interface IO, and the difference between the two exceeds the trigger voltage threshold of the thyristor of the PNPN structure composed of the second PNP transistor and the NPN transistor. At this time, both the second PNP transistor and the NPN transistor are turned on, and the electrostatic discharge is discharged to the ground interface VSS through the emitter of the second PNP transistor and the NPN transistor.

[0040] When electrostatic discharge occurs at the signal interface (IO), the conduction direction of the NPN transistor differs from that when electrostatic discharge occurs at the ground interface (VSS). When electrostatic discharge occurs at the signal interface (IO), the conduction direction of the NPN transistor can be from its first electrode to its second electrode; when electrostatic discharge occurs at the ground interface (VSS), the conduction direction of the NPN transistor can be from its second electrode to its first electrode.

[0041] As can be seen, in the integrated circuit 100 of this application embodiment, the protection circuit 102 can utilize a combination of a first PNP transistor, a second PNP transistor, and an NPN transistor with bidirectional conduction function to simulate the working principle of a silicon controlled rectifier transistor when electrostatic discharge occurs at the signal interface IO and the ground interface VSS, thereby discharging the static electricity generated at the signal interface IO and the ground interface VSS, thus achieving the purpose of protecting the target chip 101; moreover, the protection circuit 102 does not need to connect a large number of PNP transistors in series, which can effectively reduce the layout area required by the protection circuit 102.

[0042] This application also provides a protection circuit for protecting a target chip, which has a signal interface (IO) and a ground interface. The signal interface can be connected to the internal signal lines of the target chip. This protection circuit can improve the electrostatic discharge capability of the chip while maintaining a small layout area.

[0043] Figure 2 A schematic diagram of the semiconductor structure of the protection circuit according to an embodiment of this application is shown. Figure 2 As shown, the protection circuit 200 of this embodiment includes a substrate 201, a P-type isolation region 202, a plurality of N-type wells, a first P-type doped structure disposed in each of the plurality of N-type wells, and an N-type doped structure in contact with the first P-type doped structure. The P-type isolation region 202 is disposed in the substrate 201, and the plurality of N-type wells are disposed in the P-type isolation region 202.

[0044] Optionally, the substrate 201 can be a silicon substrate or other semiconductor substrates, such as germanium substrates, silicon-germanium substrates, etc., but is not limited to these. The substrate 201 can be a P-type substrate doped with P-type elements or an N-type substrate doped with N-type elements.

[0045] Optionally, the N-type doped structure and the first P-type doped structure can be distributed along the surface extension direction of the substrate 201 and formed on the surface of the N-type well. For example, the N-type well can be a lightly doped N-type well, and a heavily doped first P-type doped structure and a heavily doped N-type doped structure can be formed on the surface of the N-type well by thermal diffusion.

[0046] like Figure 2 As shown, the protection circuit 200 of this application embodiment also includes an insulation structure 203 disposed in the P-type isolation region 202 between two adjacent N-type wells, which can prevent electrical signal interference between different N-type wells and ensure that the electrical signals between each N-type well can be transmitted according to a preset path.

[0047] Optionally, the P-type isolation region 202 can be a deep P-well, within which multiple N-type wells can be formed. This P-type isolation region 202 can enhance the electrical performance of the protection circuit 200, provide isolation between multiple N-type wells and the substrate 201, and improve the triggering characteristics and breakdown voltage of the devices in the protection circuit 200.

[0048] In a plurality of N-type wells, in two adjacent pairs, one includes an N-type doped structure electrically connected to the ground interface VSS, and the other includes an N-type doped structure electrically connected to the signal interface IO. That is, for two adjacent N-type wells, the interface potentials connected to the N-type doped structures in one N-type well and the N-type doped structures in the other N-type well are different.

[0049] Optional, such as Figure 2 As shown, the multiple N-type wells include a first N-type well 2041 and a second N-type well 2042. For ease of description, the first P-type doped structure formed in the first N-type well 2041 is defined as the first left-side P-type doped structure 2051A, and the N-type doped structure formed in the first N-type well 2041 can be defined as the left-side N-type doped structure 2052A. The first P-type doped structure formed in the second N-type well 2042 is defined as the first right-side P-type doped structure 2051B, and the N-type doped structure formed in the second N-type well 2042 can be defined as the right-side N-type doped structure 2052B.

[0050] In this embodiment, the first N-type well 2041 and the second N-type well 2042 can be adjacent and isolated by an insulating structure 203. The left-side N-type doped structure 2052A is electrically connected to the signal interface IO, and the right-side N-type doped structure 2052B is electrically connected to the ground interface VSS. The first left-side P-type doped structure 2051A, the first N-type well 2041, and the P-type isolation region 202 in the first N-type well 2041 constitute a first PNP transistor. Here, the first left-side P-type doped structure 2051A can serve as the emitter of the first PNP transistor, the P-type isolation region 202 can serve as the collector of the first PNP transistor, and the first N-type well 2041 can serve as the base of the first PNP transistor.

[0051] The first N-type well 2041, the P-type isolation region 202, and the second N-type well 2042 in this embodiment constitute an NPN transistor. The first N-type well 2041 can be used as the first electrode of the NPN transistor, the second N-type well 2042 can be used as the second electrode of the NPN transistor, and the P-type isolation region 202 can be used as the base of the NPN transistor.

[0052] Figure 3 A schematic diagram illustrating the electrostatic discharge principle of the signal interface in an embodiment of this application is shown. Figure 2 and Figure 3 As shown, the first PNP transistor is used to turn on when electrostatic discharge occurs at the signal interface IO, so as to control the NPN transistor to turn on in the direction from the first N-type well 2041 to the second N-type well 2042, so that the electrostatic discharge generated by the signal interface IO is discharged to the ground interface VSS through the NPN transistor. For example, when the N-type doped structure in the first N-type well 2041 is electrically connected to the signal interface IO, if the signal interface IO experiences electrostatic discharge, causing a sudden increase in its voltage, the signal interface IO current can enter the left N-type doped structure 2052A. Under high voltage, the left N-type doped structure 2052A and the first left P-type doped structure 2051A undergo reverse breakdown, causing the signal interface IO current to enter the first left P-type doped structure 2051A primarily through the left N-type doped structure 2052A of the first PNP transistor, and also through the left N-type doped structure 2052A into the first N-type well 2041. Therefore, in the first PNP transistor, the potential of the first left P-type doped structure 2051A, which serves as the emitter, is higher than that of the first N-type well 2041, which serves as the base.

[0053] When the potential of the first left-side P-type doped structure 2051A, which serves as the emitter, is higher than that of the first N-type well 2041, which serves as the base, the first PNP transistor is turned on, and the signal interface IO current can enter the P-type isolation region 202 through the left-side N-type doped structure 2052A, the first left-side P-type doped structure 2051A, and the first N-type well 2041 of the first PNP transistor. Since the first N-type well 2041, the P-type isolation region 202, and the second N-type well 2042 constitute an NPN transistor, and the left-side N-type doped structure 2052A in the second N-type well 2042 is electrically connected to the ground interface VSS, when the first PNP transistor transmits the signal interface IO current to the P-type isolation region 202, the P-type isolation region 202 acts as the base, and its potential is higher than that of the second N-type well 2042, which acts as the emitter. Therefore, under the potential control of the first transistor output, the NPN transistor conducts along the direction from the first N-type well 2041 to the second N-type well 2042, so that the current in the first N-type well 2041 can enter the second N-type well 2042 through the P-type isolation region 202, and then enter the right-side N-type doped structure 2052B in the second N-type well 2042, and is released through the ground interface VSS.

[0054] The second N-type well 2042, consisting of the first right-side P-type doped structure 2051B, the second N-type well 2042, and the P-type isolation region 202, constitutes the second PNP transistor. Here, the P-type isolation region 202 can serve as the collector of the second PNP transistor, the first right-side P-type doped structure 2051B can serve as the collector of the second PNP transistor, and the second N-type well 2042 can serve as the base of the second PNP transistor.

[0055] Figure 4 A schematic diagram illustrating the electrostatic discharge principle when an electrostatic discharge occurs at the grounding interface according to an embodiment of this application is shown. Figure 2 and 4 As shown, since the NPN transistor has bidirectional conduction function, the first PNP transistor is used to conduct when electrostatic discharge occurs at the signal interface IO, so as to control the NPN transistor to conduct along the direction from the first N-type well 2041 to the second N-type well 2042, so that the static electricity generated at the signal interface IO is discharged to the ground interface VSS through the NPN transistor; the second PNP transistor is used to conduct when electrostatic discharge occurs at the ground interface VSS, so as to control the NPN transistor to conduct along the direction from the second N-type well 2042 to the first N-type well 2041, so that the static electricity generated at the ground interface VSS is discharged to the signal interface IO through the NPN transistor.

[0056] The second PNP transistor is used to turn on when electrostatic discharge occurs at the ground interface VSS, controlling the NPN transistor to conduct along the direction from the second N-type well 2042 to the first N-type well 2041, so that the static electricity generated at the ground interface VSS is discharged to the signal interface IO through the NPN transistor. For example, when the first right-side P-type doped structure 2051B, the second N-type well 2042, and the P-type isolation region 202 constitute the second PNP transistor, if electrostatic discharge occurs at the ground interface VSS, causing a sudden increase in the voltage of the ground interface VSS, the current of the ground interface VSS can enter the right-side N-type doped structure 2052B in the second N-type well 2042, and enter the P-type isolation region 202 through the first right-side P-type doped structure 2051B and the second N-type well 2042 of the second PNP transistor; and the NPN transistor composed of the first N-type well 2041, the P-type isolation region 202, and the second N-type well 2042 has With bidirectional conduction, when the ground interface VSS current reaches the P-type isolation region 202, the base potential of the NPN transistor can be controlled to be higher than the potential of the first N-type well 2041 in the NPN transistor. Therefore, under the control of the P-type isolation region 202, the NPN transistor can conduct along the direction from the second N-type well 2042 to the first N-type well 2041, so that the ground interface VSS current can enter the NPN transistor from the second N-type well 2042, and then enter the N-type doped structure in the first N-type well 2041 through the first N-type well 2041 of the NPN transistor, and finally be released through the signal interface IO.

[0057] As can be seen, the protection circuit 200 of this application embodiment, by designing multiple N-type wells and insulating them with the insulating structure 203, ensures that no signal interference occurs between different N-type wells. Furthermore, by forming a first P-type doped structure and an N-type doped structure within the N-type wells, it discharges static electricity released from the signal interface IO and the ground interface VSS. For example, when the signal interface IO discharges static electricity, the ground interface VSS can serve as a static electricity discharge outlet; when the ground interface VSS discharges static electricity, the signal interface IO can serve as a static electricity discharge outlet, thereby effectively protecting the target chip from damage caused by static electricity released from the signal interface IO (forward static electricity) and the ground interface VSS (reverse static electricity).

[0058] Furthermore, since the protection circuit 200 can increase its turn-on voltage by placing the first P-type doped structure and the N-type doped structure in the N-type well, the protection circuit 200 does not need to connect a large number of PNP transistors in series to achieve circuit protection when the signal interface IO and the ground interface VSS are subjected to high voltage electrostatic discharge. Therefore, the protection circuit 200 of this application embodiment requires a relatively small layout area.

[0059] from Figures 1-4As can be seen, the first P-type doped structure, the N-type doped structure, the P-type isolation region, the first N-type well, and the second N-type well that constitute the first PNP transistor, the second PNP transistor, and the NPN transistor are all integrated in the same P-type isolation region provided on the substrate, making the structure of the protection circuit more compact and thus further reducing the layout area of ​​the protection circuit.

[0060] It should be noted that N-type doping in the embodiments of this application can refer to doping with N-type elements. N-type elements can include at least one of phosphorus and germanium, and P-type doping can refer to doping with P-type elements, which can include at least one of boron and gallium.

[0061] In one possible implementation, such as Figure 2 As shown, the protection circuit 200 in this embodiment may further include a second P-type doped structure disposed in each of the plurality of N-type wells. The N-type doped structure is located between the first P-type doped structure and the second P-type doped structure, and the N-type doped structure is in contact with the second P-type doped structure.

[0062] Taking multiple N-type wells, including a first N-type well 2041 and a second N-type well 2042, as an example, the second P-type doped structure of the first N-type well 2041 can be referred to as the second left-side P-type doped structure 2053A, and the second P-type doped structure of the second N-type well 2042 can be referred to as the second right-side P-type doped structure 2053B.

[0063] like Figure 2 and 3 As shown, when electrostatic discharge occurs at the signal interface IO, the signal interface IO current can not only, as mentioned above, flow along the first left-side P-type doped structure 2051A, the first N-type well 2041, the P-type isolation region 202, the second N-type well 2042, and the right-side N-type doped structure 2052B, and then be released from the ground interface VSS, but it can also flow along the second left-side P-type doped structure 2053A, the first N-type well 2041, the P-type isolation region 202, the second N-type well 2042, and the right-side N-type doped structure 2052B, and then be released from the ground interface VSS.

[0064] like Figure 2 and 3 As shown, when electrostatic discharge occurs at the grounding interface VSS, the grounding interface VSS current can not only, as mentioned above, flow along the first right-side P-type doped structure 2051B, the second N-type well 2042, the P-type isolation region 202, the first N-type well 2041, and the left-side N-type doped structure 2052A, and then be released from the signal interface, but it can also flow along the second right-side P-type doped structure 2053B, the second N-type well 2042, the P-type isolation region 202, the first N-type well 2041, and the left-side N-type doped structure 2052A, and then be released from the signal interface IO.

[0065] As can be seen, in the protection circuit 200 of this application embodiment, by adding a second P-type doped structure in the N-type well, on the one hand, the first P-type doped structure and the second P-type doped structure formed in the N-type well can divide the current injected into the N-type doped structure to prevent transistor damage caused by excessive voltage. On the other hand, the second P-type doped structure, the N-type well and the P-type isolation region 202 can be used to form a new discharge channel, providing more ways for electrostatic discharge.

[0066] In one possible implementation, the depth of the N-type well is less than a first preset depth, resulting in a shallower N-type well. The N-type dopant concentration in this well is lower than the first preset concentration, leading to lower resistivity. This allows it to be used as the base or collector of an NPN transistor, reducing the trigger voltage and enabling rapid static discharge.

[0067] In one possible implementation, Figure 5 This diagram illustrates the structure of the protection circuit according to an embodiment of this application when the depth of the N-type well is relatively large. For example... Figure 5 As shown, the depth of the N-type well is greater than the second preset depth, which in turn is greater than the first preset depth, making it a relatively deep N-type well. The N-type doped ion concentration in this N-type well is greater than the second preset concentration. In this case, the resistance of the N-type well is relatively high, and as a series resistor, it can increase the resistance of the transistor's base or emitter. Therefore, the trigger voltage of the SCR transistor can be increased through the N-type well, preventing false triggering of the protection circuit 200.

[0068] Furthermore, by increasing the series resistance through a deeper N-type well, the base current of the first PNP transistor and the second PNP transistor can be limited, the trigger current can be reduced, and the first PNP transistor and the second PNP transistor can be turned on more stably and controllably during ESD release. In addition, by increasing the series resistance, the current surge caused by transient large current can be reduced, the risk of local hot spots and thermal failure can be reduced, and the reliability of the device can be improved.

[0069] In one possible implementation, the N-type well in this embodiment may include a first N-type well region and a second N-type well region. The first N-type well region is disposed within the P-type isolation region 202, and the second N-type well region is disposed within the first N-type well region. The depth of the first N-type well region is greater than the depth of the second N-type well region. The second N-type well region, the first P-type doped structure, and the N-type doped structure are all located within the first N-type well region, and the N-type dopant concentration in the second N-type well region is higher than the N-type dopant concentration in the first N-type well region.

[0070] Figure 6 A schematic diagram of the structure of an embodiment of this application, taking a first N-type well as an example, is shown. Figure 6As shown, in the first N-type well 2041, the depth of the first N-type well region 2041A is greater than the depth of the second N-type well region 2041B. When the N-type doped ion concentration of the second N-type well region 2041B is higher than that of the first N-type well region 2041A, the resistivity of the second N-type well region 2041B is lower, and the resistivity of the first N-type well region 2041A is higher. This is equivalent to connecting a controllable resistor in series in the first PNP transistor to adjust the trigger current and trigger voltage of the first PNP transistor, so that the protection circuit 200 will not be easily triggered under the normal operating voltage of the target chip, thereby ensuring the normal operation of the target chip.

[0071] Furthermore, since the first N-type well region 2041A is formed in the P-type isolation region 202, the two can form a PN junction. The N-type doped ion concentration in the first N-type well region 2041A is relatively high, while the P-type doped ion concentration in the P-type isolation region 202 is relatively low. Therefore, the first N-type well 2041 can effectively suppress the reverse leakage current of the PN junction, which is beneficial to reducing static power consumption.

[0072] In one possible implementation, such as Figure 2 As shown, the protection circuit 200 in this embodiment further includes an N-type isolation region 206. The N-type isolation region 206 is disposed in the substrate 201, and a P-type isolation region 202 is disposed within the N-type isolation region 206. The N-type isolation region 206 is electrically connected to the power interface VDD of the target chip. The N-type isolation region 206 provides a reference voltage to the protection circuit 200, ensuring its normal operation.

[0073] Optional, such as Figure 2 As shown, a third N-type well 207 can be provided within the N-type isolation region 206, and an N-type doped structure connected to the power interface VDD can be provided within the third N-type well 207. This N-type doped structure can be defined as an edge N-type doped structure 208. The power supply voltage of the power interface VDD can be input to the N-type isolation region 206 through this edge N-type doped structure 208, so that the P-type isolation region 202 can use the power supply voltage of the N-type isolation region 206 as a reference to provide a reference voltage for the protection circuit 200.

[0074] Optionally, the substrate 201 is a P-type substrate. In this case, the protection circuit 200 further includes a third P-type doped structure 209 disposed on the substrate 201, and the third P-type doped structure 209 is connected to the ground interface VSS. When leakage current occurs in the P-type substrate, it can be released through the ground interface VSS connected to the third P-type doped structure 209.

[0075] Since the P-type isolation region 202 is formed within the N-type isolation region 206, and the substrate 201 is a P-type substrate, it can be considered that a PN junction is formed outside the P-type isolation region 202. The voltage of the N-terminal (N-type isolation region 206) of the PN junction is relatively high, while the potential of the P-terminal (P-type substrate) of the PN junction is relatively low, which enables the outer periphery of the P-type isolation region 202 to effectively suppress the reverse leakage current of the PN junction.

[0076] Figure 7 This diagram shows the equivalent circuit structure of the protection circuit according to an embodiment of the present application when electrostatic discharge occurs at the signal interface. Figure 8 A schematic diagram of the equivalent circuit structure of the protection circuit according to an embodiment of this application is shown when electrostatic discharge occurs at the grounding interface. Figure 7 and Figure 8 As shown, the protection circuit 200 of this embodiment includes a first PNP transistor Q1, a second PNP transistor Q2, and an NPN transistor Q3. The first PNP transistor Q1, the second PNP transistor Q2, and the NPN transistor Q3 are integrated within the same P-type isolation region disposed on the substrate. In this case, it is not necessary to isolate the first PNP transistor Q1, the second PNP transistor Q2, and the NPN transistor Q3 in the substrate; they can be constructed in the substrate. Therefore, the protection circuit of this embodiment has a relatively compact structure, which can effectively reduce the layout area of ​​the protection circuit 200.

[0077] like Figure 7 and Figure 8 As shown, the base and emitter of the first PNP transistor Q1 are both electrically connected to the signal interface IO. The base of the NPN transistor Q3 is electrically connected to the collector of the first PNP transistor Q1. The first electrode of the NPN transistor Q3 is electrically connected to the signal interface IO, and the second electrode of the NPN transistor Q3 is electrically connected to the ground interface VSS. Figure 7 As shown, the first PNP transistor Q1 is turned on when electrostatic discharge occurs at the signal interface IO, so as to control the NPN transistor Q3 to turn on along the direction from the first electrode to the second electrode, so that the electrostatic discharge generated by the signal interface IO is discharged to the ground interface VSS through the NPN transistor Q3.

[0078] like Figure 7 and Figure 8 As shown, the base and emitter of the second PNP transistor Q2 are both electrically connected to the ground interface VSS, and the collector of the second PNP transistor Q2 is electrically connected to the collector of the first PNP transistor Q1. Figure 8As shown, the second PNP transistor Q2 is turned on when electrostatic discharge occurs at the ground interface VSS, so as to control the NPN transistor Q3 to turn on along the direction from the second electrode to the first electrode, so that the electrostatic discharge generated at the ground interface VSS is discharged to the signal interface IO through the NPN transistor Q3.

[0079] Optional, such as Figure 7 and Figure 8 As shown, the protection circuit 200 also includes a first equivalent resistor R1 and a second equivalent resistor R2. The signal interface IO is electrically connected to the first electrode of the NPN transistor Q3 through the first equivalent resistor R1; the second electrode of the NPN transistor Q3 is electrically connected to the ground interface VSS through the second equivalent resistor R2.

[0080] like Figure 7 As shown, the resistance of the first equivalent resistor R1 is equivalent to Figure 2 The resistance of the first N-type well 2041 can also be equivalent to Figure 5 The resistance value of the first N-type well 2041 in the middle can also be Figure 6 The total resistance of the first N-type well 2041, including the first N-type well region 2041A and the second N-type well region 2041B.

[0081] The resistance value of the first equivalent resistor R1 is equivalent to Figure 2 When the resistance of the first N-type well 2041 is set, the resistance of the first equivalent resistor R1 is less than the first preset resistance value. At this time, the trigger sensitivity of the first PNP transistor Q1 is relatively high, to prevent insufficient protection capability caused by excessively high trigger voltage of the first PNP transistor Q1.

[0082] The resistance value of the first equivalent resistor R1 is equivalent to Figure 5 When the resistance of the first N-type well 2041 is set, the resistance of the first equivalent resistor R1 is greater than the second preset resistance value, and the second preset resistance value is greater than the first preset resistance value. In this case, the base current of the first PNP transistor Q1 can be limited, reducing the trigger current of the first PNP transistor Q1. This allows the signal interface IO to conduct more stably and controllably during electrostatic discharge, reducing current surges caused by transient large currents, lowering the risk of local hot spots and thermal failure, and improving device reliability.

[0083] The resistance value of the first equivalent resistor R1 is equivalent to Figure 5The total resistance of the first N-type well region 2041A and the second N-type well region 2041B is specified. The trigger current and trigger voltage of the first PNP transistor Q1 can be controlled by the second N-type well region 2041B and the first N-type well region 2041A. Therefore, the first PNP transistor Q1 (or SCR transistor) is not easily triggered by false triggering under the normal operating voltage of the target chip, and is only triggered when electrostatic discharge occurs.

[0084] Similarly, the resistance value of the second equivalent resistor can be referenced from the relevant description of the resistance value of the first equivalent resistor in order to adjust the protection capability of the protection circuit 200 for the ground interface VSS of the target chip.

[0085] This application also provides a protection method applicable to an integrated circuit having a target chip and a protection circuit. The target chip has a signal interface and a ground interface, and the protection circuit includes a first PNP transistor, an NPN transistor, and a second PNP transistor, wherein the NPN transistor has bidirectional conduction functionality. The method includes: When electrostatic discharge occurs at the signal interface, the first PNP transistor turns on to control the NPN transistor to conduct along the direction from the first electrode to the second electrode of the NPN transistor, so that the static electricity generated at the signal interface is discharged to the ground interface through the NPN transistor; when electrostatic discharge occurs at the ground interface, the second PNP transistor turns on to control the NPN transistor to conduct along the direction from the second electrode to the first electrode of the NPN transistor, so that the static electricity generated at the ground interface is discharged to the signal interface through the NPN transistor.

[0086] It should be noted that the beneficial effects of the method in the embodiments of this application can be referred to the description of the relevant beneficial effects of the protection circuit mentioned above, and will not be repeated here.

[0087] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0088] The block diagrams of elements, devices, equipment, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, equipment, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0089] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0090] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise expressly specified. "Several" means one or more, unless otherwise expressly specified.

[0091] In the description of this application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0092] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.

[0093] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.

[0094] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0095] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A protection circuit, characterized in that, For protecting a target chip, the target chip has a signal interface and a ground interface. The protection circuit includes: a substrate, a P-type isolation region, a plurality of N-type wells, and a first P-type doped structure disposed in each of the plurality of N-type wells and an N-type doped structure in contact with the first P-type doped structure; the P-type isolation region is disposed in the substrate, the plurality of N-type wells are disposed in the P-type isolation region, and the protection circuit further includes an insulating structure disposed in the P-type isolation region between two adjacent N-type wells; The plurality of N-type wells include a first N-type well and a second N-type well. The N-type doped structure in the first N-type well is electrically connected to the signal interface, and the N-type doped structure in the second N-type well is electrically connected to the ground interface. The first P-type doped structure in the first N-type well, the first N-type well, and the P-type isolation region constitute a first PNP transistor. The first N-type well, the P-type isolation region, and the second N-type well constitute an NPN transistor. The first P-type doped structure in the second N-type well, the second N-type well, and the P-type isolation region constitute a second PNP transistor. The NPN transistor has a bidirectional conduction function. The first PNP transistor is turned on when electrostatic discharge occurs at the signal interface to control the NPN transistor to conduct along the direction from the first N-type well to the second N-type well, so that the static electricity generated at the signal interface is discharged to the ground interface through the NPN transistor. The second PNP transistor is turned on when electrostatic discharge occurs at the ground interface to control the NPN transistor to conduct along the direction from the second N-type well to the first N-type well, so that the static electricity generated at the ground interface is discharged to the signal interface through the NPN transistor.

2. The protection circuit according to claim 1, characterized in that, The protection circuit further includes a second P-type doped structure disposed in each of the plurality of N-type wells, wherein the N-type doped structure is located between the first P-type doped structure and the second P-type doped structure, and the N-type doped structure is in contact with the second P-type doped structure.

3. The protection circuit according to claim 1, characterized in that, The N-type well includes a first N-type well region and a second N-type well region. The first N-type well region is located within the P-type isolation region, and the second N-type well region is located within the first N-type well region. The depth of the first N-type well region is greater than the depth of the second N-type well region. The second N-type well region, the first P-type doped structure, and the N-type doped structure are all located in the first N-type well region, and the N-type dopant concentration in the second N-type well region is higher than that in the first N-type well region.

4. The protection circuit according to claim 1, characterized in that, Of the plurality of N-type wells, in two adjacent pairs, one includes an N-type doped structure electrically connected to the ground interface, and the other includes an N-type doped structure electrically connected to the signal interface.

5. The protection circuit according to any one of claims 1 to 4, characterized in that, The protection circuit further includes an N-type isolation region disposed in the substrate, a P-type isolation region disposed in the N-type isolation region, and the N-type isolation region being electrically connected to the power supply terminal.

6. The protection circuit according to any one of claims 1 to 4, characterized in that, The substrate is a P-type substrate, and the protection circuit further includes a third P-type doped structure disposed on the substrate, the third P-type doped structure being connected to the grounding interface.

7. A protection circuit, characterized in that, include: The first PNP transistor, the base of the first PNP transistor and the emitter of the first PNP transistor are both electrically connected to the signal interface; The NPN transistor has its base electrically connected to the collector of the first PNP transistor, its first electrode electrically connected to the signal interface, and its second electrode electrically connected to the ground interface. And a second PNP transistor, the base and emitter of which are both electrically connected to the ground interface, and the collector of which is electrically connected to the collector of the first PNP transistor; wherein, The first PNP transistor, the second PNP transistor, and the NPN transistor are integrated in the same P-type isolation region disposed on the substrate. The first PNP transistor is used to turn on when electrostatic discharge occurs at the signal interface, so as to control the NPN transistor to turn on along the direction from the first electrode to the second electrode, so that the electrostatic discharge generated at the signal interface is discharged to the ground interface through the NPN transistor. The second PNP transistor is turned on when electrostatic discharge occurs at the grounding interface, so as to control the NPN transistor to turn on in the direction from the second electrode to the first electrode, so that the electrostatic discharge generated at the grounding interface is discharged to the signal interface through the NPN transistor.

8. The protection circuit according to claim 7, characterized in that, The protection circuit also includes a first equivalent resistor and a second equivalent resistor. The signal interface is electrically connected to the first electrode of the NPN transistor through the first equivalent resistor; the second electrode of the NPN transistor is electrically connected to the ground interface through the second equivalent resistor.

9. An integrated circuit, characterized in that, The device includes a target chip and a protection circuit, wherein the target chip has a signal interface and a ground interface, and the protection circuit includes the protection circuit described in any one of claims 1 to 8. The emitter of the first PNP transistor and the first electrode of the NPN transistor in the protection circuit are both electrically connected to the signal interface, and the emitter of the second PNP transistor and the second electrode of the NPN transistor in the protection circuit are both electrically connected to the ground interface.

10. A protection method, characterized in that, An integrated circuit having a target chip and a protection circuit, wherein the target chip has a signal interface and a ground interface, and the protection circuit includes a first PNP transistor, an NPN transistor, and a second PNP transistor, wherein the NPN transistor has bidirectional conduction functionality, the method comprising: When electrostatic discharge occurs at the signal interface, the first PNP transistor is turned on to control the NPN transistor to turn on along the direction from the first electrode of the NPN transistor to the second electrode of the NPN transistor, so that the static electricity generated at the signal interface is discharged to the ground interface through the NPN transistor. When electrostatic discharge occurs at the grounding interface, the second PNP transistor is turned on to control the NPN transistor to conduct along the direction from the second electrode of the NPN transistor to the first electrode of the NPN transistor, so that the static electricity generated at the grounding interface is discharged to the signal interface through the NPN transistor.

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