Pixel array and image sensor comprising the same

Abstract

Embodiments of this disclosure provide a pixel array and an image sensor including the same. The pixel array includes: a plurality of pixels, wherein each of the plurality of pixels includes: a substrate including an avalanche amplification region and having a first surface on which light from the outside is incident; and a plasma pattern formed on the first surface of the substrate, wherein the plasma pattern includes one or more holes.

Description

Technical Field

[0001] The present invention relates to pixel arrays and image sensors including such pixel arrays. Background Technology

[0002] Recently, the demand for high-resolution and high-performance image sensors has grown rapidly in various applications such as video recording, digital cameras, smartphones, and automotive ADAS (Advanced Driver Assistance Systems). An image sensor is a semiconductor device that converts light (optical signals) received from an object into electrical signals. Typically, it includes a pixel array consisting of multiple pixels, and signal processing circuitry for reading the signal generated from each pixel.

[0003] Furthermore, with the increasing demand for image sensors capable of detecting wavelengths in the SWIR (short-wavelength infrared) region, image sensors employing III-V compound semiconductors (e.g., InGaAs) are typically used. However, such InGaAs-based sensors suffer from high manufacturing costs and low compatibility with existing CMOS processes, thus limiting the realization of large-area arrays and mass production.

[0004] Therefore, in recent years, techniques have been studied to ensure sensitivity in the SWIR region while maintaining conventional CMOS processes. Summary of the Invention

[0005] One embodiment of the present invention relates to providing a pixel array in which light absorption efficiency at SWIR wavelengths is maximized by using a plasma pattern structure to induce wavelength conversion.

[0006] Another embodiment of the invention relates to providing an image sensor comprising such a pixel array.

[0007] The embodiments of the present invention for achieving the above-mentioned technical objectives relate to providing a pixel array comprising a plurality of pixels, wherein each of the plurality of pixels comprises: a substrate including an avalanche amplification region and having a first surface, light from the outside being incident on the first surface; and a plasma pattern formed on the first surface of the substrate, wherein the plasma pattern includes one or more holes.

[0008] Another embodiment of the present invention relates to providing an image sensor comprising: a plurality of pixels; and a pixel isolation structure that separates the plurality of pixels from one another, wherein each of the plurality of pixels comprises: a substrate disposed on a readout circuit and having a first surface on which light from the outside is incident; and a plasma pattern formed on the first surface of the substrate, wherein the plasma pattern comprises a plurality of holes. Attached Figure Description

[0009] The above and other objects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a block diagram of an image sensor according to the present invention.

[0010] Figure 2 This is a plan view of the pixel array according to the present invention.

[0011] Figure 3 It is shown Figure 2 A plan view of the arrangement of doped regions in a pixel array.

[0012] Figure 4 It is along Figure 2 The cross-sectional view taken from line I-I'.

[0013] Figure 5 It is based on Figure 2 A plan view of the pixel array in another embodiment.

[0014] Figure 6 It is along Figure 5 The cross-sectional view taken from line II-II'.

[0015] Figure 7 It is based on Figure 2 A plan view of the pixel array in another embodiment.

[0016] Figure 8 This is a table showing the wavelength conversion based on the aspect ratio of the aperture.

[0017] Figure 9 This is a table showing the wavelength conversion based on the aperture width. Detailed Implementation

[0018] The advantages and features of the present invention, as well as the methods for implementing them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and fully informs those skilled in the art of the scope of the invention.

[0019] The shapes, dimensions, ratios, angles, numbers, etc., disclosed in the accompanying drawings to describe embodiments of the present invention are merely illustrative, and the present invention is not limited to what is shown in the drawings. Throughout the specification, the same components may be represented by the same reference numerals. Furthermore, in describing the present invention, detailed descriptions of relevant known technologies will be omitted where it is determined that such detailed descriptions may unnecessarily obscure the spirit of the present invention.

[0020] In this specification, when the terms "comprising," "having," or "consisting of" are used, other elements may be added unless the expression "only" is used. When a component is represented in the singular, it is intended to include the plural unless otherwise expressly stated.

[0021] When explaining components, it should be understood that they include a range of error, even if not explicitly stated.

[0022] For example, when using terms such as “above,” “over,” “below,” or “next to” to describe the positional relationship between two elements, one or more other elements may be inserted between the two elements unless the expressions “directly” or “immediately” are used.

[0023] Spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used to facilitate the description of the relationship between one element or component and another element or component shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device during use or operation. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements would be oriented as “above” other elements. Thus, the exemplary term “below” can include both lower and upper directions. Similarly, the exemplary terms “above” or “upper” can include both upper and lower directions.

[0024] When describing temporal relationships, such as when time sequence is described as “after,” “follow,” “next,” or “before,” such descriptions may include non-continuous cases unless the expressions “exactly” or “directly” are used.

[0025] Although terms such as "first" and "second" can be used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one element from another. Therefore, within the scope of the present invention, the first element mentioned below can also be the second element.

[0026] The term "at least one" should be understood to include all possible combinations that may consist of one or more related items. For example, "at least one of the first, second, and third items" may mean any one of the first, second, or third items, and any combination of two or more of the first, second, and third items.

[0027] Features of the various embodiments of the present invention can be combined or associated with each other in part or in whole, and various technical interactions and operations are possible. Each embodiment can be implemented independently or together in an associated relationship.

[0028] When assigning reference numerals to components in the accompanying drawings describing embodiments of the invention, the same reference numerals may be assigned to the same components as much as possible, even if they are shown in different drawings.

[0029] Figure 1 This is a block diagram of an image sensor (600) including a pixel array (100). For example... Figure 1 As shown, an image sensor (600) including a pixel array (100) according to an embodiment of the present invention emits light signals to an object, converts the light signals reflected from the object into electrical signals, and outputs the electrical signals to a processor (610) of an electronic device (not shown) that applies the image sensor (600).

[0030] In this context, as described above, in addition to automotive LiDAR sensors, tablet PCs, or portable terminals, electronic devices can also include cameras, wearable devices, Internet of Things (IoT) devices, home appliances, robots, robotic vacuum cleaners, portable multimedia players (PMPs), navigation devices, drones, and advanced driver assistance systems (ADAS). Furthermore, electronic devices can be components incorporated into vehicles, furniture, manufacturing equipment, doors, or various measuring instruments.

[0031] like Figure 1 As shown, the image sensor (600) includes a pixel array (100), a line driver (630), a timing generator (640), an analog processing circuit (650), an analog-to-digital converter (660), and an output buffer (670).

[0032] The readout circuit (700) according to the present invention may include a timing generator (640), an analog processing circuit (650), an analog-to-digital converter (660), and an output buffer (670). The readout circuit (700) can collect photocharge from multiple pixels (P) row by row.

[0033] The pixel array (100) comprises multiple pixels (P). The multiple pixels (P) can be arranged in a two-dimensional array. For example, the multiple pixels (P) can be arranged in a matrix comprising M rows (where M is an integer of 2 or greater) and N columns (where N is an integer of 2 or greater). Each pixel (P) included in the pixel array (100) uses a single-photon avalanche diode (SPAD) to detect an optical signal and convert the optical signal into an electrical signal, i.e., a pixel signal.

[0034] Each pixel (P) can be driven by a control signal received from the row driver (630). The signal converted by each pixel (P) and the reset signal corresponding to the reset component are provided to the analog processing circuit (650).

[0035] The row driver (630) drives each pixel (P) in the pixel array (100) based on the control of the timing generator (640). In one embodiment, the row driver (630) can control all pixels (P) in the pixel array (100) simultaneously, or it can control individual pixels (P) of the pixel array (100) row by row. To do this, the row driver (630) can send control signals to the pixels (P).

[0036] In one implementation, the line driver (630) can send control signals to each pixel (P) under the control of the timing generator (640).

[0037] The timing generator (640) can control the pixel array (100) via the row driver (630) and can output control signals for controlling the analog processing circuit (650), the analog-to-digital converter (660), and the output buffer (670).

[0038] The analog processing circuit (650) can sample and hold the output signal provided from the pixel (P) according to the correlated double sampling (CDS) scheme, and can double sample specific noise levels such as reset level and signal level.

[0039] The analog processing circuit (650) can generate a comparison result signal corresponding to the reset level and a comparison result signal corresponding to the signal level. Here, the method of reading the reset level and then reading the signal level can be called a complete CDS (correlated double sampling) scheme, and the method of reading the signal level and then reading the reset level can be called an incomplete CDS (non-complete CDS) scheme or a DRS (incremental reset sampling) scheme.

[0040] An analog-to-digital converter (660) can convert the output signal from the analog processing circuit (650) into a digital signal and provide the digital signal to the output buffer (670). Although Figure 1 The analog processing circuitry (650) and the analog-to-digital converter (660) are shown as separate components, but in another embodiment, the analog-to-digital converter (660) may be included in or integrated with the analog processing circuitry (650).

[0041] The output buffer (670) can latch the digital signal sent from the analog-to-digital converter (660) and output the latched signal sequentially.

[0042] The processor (610) of the electronic device can perform signal processing on the digital signal output from the output buffer (670) and output the processed signal to an external device or store it in a storage device such as a memory.

[0043] Figure 2 This is a plan view of the pixel array according to the present invention. Figure 3 It is shown Figure 2 A plan view of the arrangement of doped regions in a pixel array. Figure 4 It is along Figure 2 The cross-sectional view taken from line I-I'.

[0044] Reference Figures 2 to 4 The pixel array (100) may include a first pixel (P1), a second pixel (P2), and a pixel isolation structure (140) surrounding each of the first pixel (P1) and the second pixel (P2).

[0045] Figure 3 The floor plan shown illustrates Figure 2 The state in which no plasma pattern (151) is set.

[0046] Figure 4 The cross-sectional structure of the first pixel (P1) shown can correspond to Figure 2 and 3 The cross-sectional structure of the second pixel (P2) is shown.

[0047] like Figures 2 to 4 As shown, the pixel array (100) according to an embodiment of the present invention includes a plurality of pixels (P1, P2), and each of the plurality of pixels (P1, P2) includes a substrate (110). The substrate (110) has a first surface (110a) and a second surface (110b). In one embodiment, the first surface (110a) of the substrate (110) may be a surface on which light is incident from the outside, and the second surface (110b) of the substrate (110) may be opposite to the first surface (110a). In the present invention, the first surface (110a) may be the upper surface of the substrate (110), and the second surface (110b) may be the lower surface of the substrate (110). The substrate (110) may be a silicon (Si) substrate.

[0048] The substrate (110) can be a region lightly doped with a dopant of a first conductivity type or a dopant of a second conductivity type, and can be formed by epitaxial growth. When the substrate (110) is doped with a dopant of the first conductivity type, the PN junction region formed by the first doped region (121) in the substrate (110) becomes the avalanche amplification region (130), and the first doped region (121) is doped with a dopant of the second conductivity type opposite to the first conductivity type.

[0049] In one embodiment of the invention, the dopant of the first conductivity type can be a P-type dopant, and the dopant of the second conductivity type can be an N-type dopant. However, in another example, the dopant of the first conductivity type can be an N-type dopant, and the dopant of the second conductivity type can be a P-type dopant.

[0050] When the dopant of the first conductivity type is a P-type dopant and the dopant of the second conductivity type is an N-type dopant, the P-type dopant may include at least one of boron (B), aluminum (Al), gallium (Ga) and indium (In), and the N-type dopant may include at least one of phosphorus (P), arsenic (As) and antimony (Sb).

[0051] According to an embodiment of the present invention, the pixel isolation structure (140) can electrically isolate each of the pixels (P1, P2) by penetrating the substrate (110). That is, the region in which the pixels (P1, P2) are formed is defined by the pixel isolation structure (140), and the pixels (P1, P2) are electrically isolated from each other by the pixel isolation structure (140). According to one embodiment of the present invention, the pixel isolation structure (140) extends from a first surface (110a) of the substrate (110) to a second surface (110b) of the substrate (110).

[0052] According to one embodiment of the present invention, the pixel isolation structure (140) may be formed as a deep trench isolation (DTI) structure, wherein an insulating layer is filled in a deep trench, the deep trench being formed to penetrate the substrate (110) from the first surface (110a) toward the second surface (110b).

[0053] As described above, according to the present invention, since the pixel isolation structure (140) for isolating each of the pixels (P1, P2) is continuously formed from the first surface (110a) to the second surface (110b) of the substrate (110), leakage current between adjacent pixels (P1, P2) can be prevented. Specifically, the pixel isolation structure (140) can be configured to surround each of the plurality of pixels (P1, P2). Furthermore, in a plan view, the pixel isolation structure (140) can be configured to surround a plasma pattern (151), which will be described below.

[0054] A first doped region (121) heavily doped with a dopant of a second conductivity type is formed on the second surface (110b) of the substrate (110). The first doped region (121) may be formed to have a predetermined thickness on the second surface (110b) of the substrate (110). The first doped region (121) may form the cathode region of a single-photon avalanche diode. As described above, the avalanche amplification region (130) is formed by a PN junction between the region of the substrate (110) doped with a dopant of the first conductivity type and the first doped region (121) doped with a dopant of the second conductivity type.

[0055] In one embodiment of the present invention, such as Figure 3 and Figure 4 As shown, the first doped region (121) can be formed to be surrounded by a pixel isolation structure (140) in a planar view. That is, in a planar view, the pixel isolation structure (140) formed in the substrate (110) can have a closed-loop shape surrounding the first doped region (121).

[0056] The avalanche amplification region (130) is the region where electrons and holes multiply. In the avalanche amplification region (130), a very strong electric field is formed under reverse bias conditions to allow electrons to move rapidly. As a result, electron-hole pairs generated by a single photon generate additional electrons, and the generated electrons are accelerated by the electric field and collide with other atoms to generate additional electron-hole pairs in a chain reaction, thereby producing a very high current.

[0057] Due to the avalanche amplification region (130), the single-photon avalanche diode can detect a single photon, thus enabling the detection of extremely low light signals. Therefore, it can be effectively applied to sensing in low-light environments.

[0058] A second doped region (122) heavily doped with a dopant of a first conductivity type is formed on the second surface (110b) of the substrate (110). The second doped region (122) may be formed to have a predetermined thickness on the second surface (110b) of the substrate (110). The second doped region (122) may form the anode region of a single-photon avalanche diode.

[0059] Reference Figure 3 and Figure 4 The second doped region (122) may have a closed-loop shape around the first doped region (121).

[0060] According to one embodiment of the invention, a plasma pattern (151) may be disposed on a first surface (110a) of a substrate (110). The plasma pattern (151) according to the invention may include one or more holes (155). Specifically, the holes (155) according to the invention are openings that expose the first surface (110a) of the substrate (110) and refer to the area surrounded by the remaining portion of the plasma pattern (151) after etching.

[0061] although Figure 2 The plasma pattern (151) is shown as having a rectangular shape, but the invention is not limited thereto. (See also...) Figure 2 and Figure 4 The holes (155) of the plasma pattern (151) can be arranged in rows along a predetermined direction and can be spaced apart from each other. However, the arrangement of the plasma pattern (151) is not limited to this and can be determined as needed. The spacing of the plasma pattern (151) can be in the range of several nanometers (nm) to several micrometers (μm).

[0062] Furthermore, according to the present invention, a plasma pattern (151) can be set for each of the plurality of pixels (P). For example, see reference to Figure 2 A plasma pattern (151) can be set in each of the first pixel (P1) and the second pixel (P2).

[0063] The plasma pattern (151) can be an ultrathin metal film and can include a metallic material with a high free electron density to induce plasma excitation. For example, the plasma pattern (151) can include aluminum (Al), gold (Au), or silver (Ag). However, the invention is not limited thereto, and the plasma pattern (151) can be formed of a metallic material capable of forming a Schottky barrier with the substrate (110).

[0064] This Schottky barrier forms at the junction between the metal and semiconductor substrates and facilitates the efficient injection of excited electrons generated in the plasma pattern (151) into the substrate (110). Therefore, the efficiency of converting light energy generated by the plasma structure into electrical signals is improved, rather than being lost through simple reflection or heat.

[0065] Plasma patterns (151) can be precisely formed using, for example, atomic layer deposition (ALD) processes. Plasma phenomena occur at the surface or interface of the plasma pattern (151), particularly near the boundary with the dielectric layer (160), thereby generating a strong near field.

[0066] This near-field concentrates and transfers light energy to the avalanche amplification region below (130), thereby improving light absorption efficiency and maximizing charge generation efficiency.

[0067] As a result, the plasma pattern (151) according to an embodiment of the present invention effectively compensates for the optical losses that may occur between the dielectric layer (160) and the substrate (110), while enhancing the charge collection efficiency through the Schottky barrier junction.

[0068] Therefore, compared with conventional structures, the pixel array (100) including the plasma pattern (151) according to the present invention can realize a high-sensitivity image sensor with excellent sensitivity and signal conversion efficiency, while minimizing optical loss.

[0069] However, even when plasma patterns are included, the wavelengths that the substrate can absorb are limited to about 1100 nm or less due to the band gap characteristics of the silicon (Si) substrate (e.g., about 1.1 eV). Therefore, even if the plasma pattern exhibits high light absorption properties, there is a limitation that light in the SWIR (short wavelength infrared) region cannot be absorbed by the silicon substrate.

[0070] To overcome this limitation, the plasma pattern (151) according to the invention can be configured to include a plurality of holes (155). This hole structure is used to convert incident light in the SWIR (short-wavelength infrared) region to a shorter wavelength region that can be absorbed by the substrate (110) through scattering or resonance effects. As a result, light with SWIR wavelengths can be effectively absorbed by the silicon substrate, thereby significantly improving the overall photodetection efficiency.

[0071] According to one embodiment of the invention, the plasma pattern (151) can be formed as a single structure. The plasma pattern (151) forms a Schottky barrier with the substrate (110), and simultaneously generates a strong near field by exciting plasma on the surface of the plasma pattern (151) due to incident photons. In order to effectively generate this plasma effect, the collective oscillation of free electrons within the plasma pattern (151) must be continuously transmitted throughout the entire plasma pattern (151).

[0072] Furthermore, the plasma pattern (151) forms a Schottky barrier with the substrate (110) and serves as a path for the efficient injection of electrons generated by optical excitation. If the plasma pattern (151) is discontinuous, the electron injection path may be formed unevenly, or the current path may be interrupted in some regions, thereby reducing the charge collection efficiency.

[0073] Therefore, the plasma pattern (151) should be formed integrally in order to stably maintain the collective oscillation of the plasma and uniformly ensure the charge injection path through the Schottky barrier.

[0074] According to one embodiment of the invention, when the wavelength of the incident light is λ, the thickness of the plasma pattern (151) can be maintained in the range of λ / 10 to λ / 1.3. For example, when the wavelength of the incident light is 1550 nm (which is the center wavelength in the SWIR (short wavelength infrared) region), the thickness of the plasma pattern (151) can be formed in the range of 155 nm to 1192 nm. Within this thickness range, the free electron density inside the metal and the surface plasmon resonance conditions can be optimally matched, thereby maximizing the plasmon resonance intensity relative to the incident light.

[0075] Within this thickness range, the collective oscillation of free electrons in the plasma pattern (151) is optimally matched with the internal electron density and surface plasmon resonance conditions of the metal, thereby maximizing the plasmon resonance intensity relative to the incident light. In other words, the thickness of the plasma pattern (151) is a key factor determining the resonance frequency and resonance intensity of the plasma, and when the thickness is controlled within the aforementioned range, a strong near field can be induced at the metal surface.

[0076] If the thickness of the plasma pattern (151) is thinner than the aforementioned lower limit, the collective oscillation of free electrons within the plasma pattern (151) may not be sufficiently formed, resulting in incomplete plasma resonance and weakened near-field intensity. Consequently, the light energy generated in the plasma pattern (151) may not be sufficiently transferred to the substrate (110), thereby reducing charge generation and injection efficiency.

[0077] Conversely, if the thickness of the plasma pattern (151) exceeds the aforementioned upper limit, the electronic oscillations within the plasma pattern (151) may be attenuated or the plasma resonance mode may be suppressed, resulting in reduced light absorption efficiency. Furthermore, excessive thickness may lead to uneven gap filling during the etching of the plasma pattern (151) or the deposition of the dielectric layer (160), thereby impairing the stability of the manufacturing process.

[0078] Therefore, by limiting the thickness of the plasma pattern (151) to approximately 1 / 10 to 1 / 1.3 of the incident light wavelength λ, the present invention can maximize the plasma resonance effect while ensuring manufacturing process stability and electrical and optical uniformity.

[0079] According to one embodiment of the invention, the hole (155) may have a first length in a first direction (X) and a second length different from the first length in a second direction (Y) perpendicular to the first direction (X). For example, the hole (155) according to the invention may have a slit shape.

[0080] For example, such as Figure 2As shown, multiple holes (155) can be provided, and the multiple holes (155) may include a first hole (155a) having a first length shorter than the second length and a second hole (155b) having a first length longer than the second length.

[0081] According to one embodiment of the invention, one of the first length and the second length may be at least three times larger than the other length. For example, in the case of the first hole (155a), the second length may be at least three times larger than the first length.

[0082] According to one embodiment of the invention, a plurality of holes (155) may be formed to have a predetermined aspect ratio in order to improve the light transmittance and wavelength conversion efficiency of the substrate (110) when the wavelength of the incident light falls within the SWIR region.

[0083] For example, the second aperture (155b) may have a first length (Lx) in a first direction (X) and a second length (Ly) in a second direction (Y) perpendicular to the first direction (X). The ratio (Lx:Ly) of the first length (Lx) in the first direction (X) to the second length (Ly) in the second direction (Y) may be about 3:1 or greater. For example, the second aperture (155b) may have a second length (Ly) of 200 nm or greater. Preferably, the second aperture (155b) may have a second length (Ly) of 1.5 μm. However, the invention is not limited thereto.

[0084] By satisfying this aspect ratio, the electromagnetic field distribution generated when incident light passes through the aperture (155) becomes more strongly localized in the vertical direction, thereby increasing the intensity of the near field caused by plasmon resonance. Thus, light scattering loss is minimized while simultaneously improving transmittance and wavelength conversion efficiency.

[0085] Conversely, if the aspect ratio of the aperture (155) is less than 1:3, the effective aperture area within the aperture is reduced, making it difficult to ensure the light transmission efficiency in the SWIR region. As a result, the light absorption rate and charge generation efficiency in the silicon substrate (110) may decrease.

[0086] Therefore, by forming a hole (155) such that the aspect ratio between the first direction (X) and the second direction (Y) is about 1:3 or greater (or 3:1 or greater in the case of the second hole (155b)), the present invention can maximize wavelength conversion and near-field enhancement effects, thereby enabling the silicon substrate to effectively absorb light in the SWIR band.

[0087] According to one embodiment of the present invention, in a planar diagram, a pixel (P) may include a first region (area1) and a second region (area2) that are different from each other. For example, Figure 2The diagram shows that the first pixel (P1) includes a first region (area1) and a second region (area2). The first region (area1) can be located on one side of the pixel (P), and the second region (area2) can be located on the other side of the pixel (P).

[0088] A first hole (155a) can be disposed in a first region (area1), and a second hole (155b) can be disposed in a second region (area2). Specifically, holes extending in different directions can be disposed in the first region (area1) and the second region (area2) respectively. For example, in the first region (area1), a first hole (155a) extending in a first direction (X) can be disposed, and in the second region (area2), a second hole (155b) extending in a second direction (Y) perpendicular to the first direction (X) can be disposed. However, the present invention is not limited thereto, and the second hole (155b) can be disposed in the first region (area1), while the first hole (155a) can be disposed in the second region (area2).

[0089] In this invention, the reason for configuring the pixel (P) to include regions with holes arranged in different directions is to prevent the problem of selective plasma resonance occurring according to the polarization orientation of the incident light.

[0090] In other words, since the surface plasma of the plasma pattern (151) is excited mainly along the longitudinal direction of the hole (155), if the hole (155) is aligned in only one direction, a strong near field can be formed only for a specific polarization, while the resonant efficiency of the polarization perpendicular to it can be significantly reduced.

[0091] Therefore, the pixel (P) according to the invention is designed such that the holes (155a, 155b) provided in the first region (area1) and the second region (area2) are arranged in mutually orthogonal directions, thereby ensuring that the wavelength conversion effect in the SWIR region is stably maintained, regardless of the polarization direction of the incident light.

[0092] Therefore, a first hole (155a) extending in the first direction (X) can be provided in the first area (area1), and a second hole (155b) extending in the second direction (Y) perpendicular to the first direction (X) can be provided in the second area (area2).

[0093] As described above, by arranging aperture structures extending in mutually perpendicular directions within the pixels, surface plasmon resonance in the plasmon pattern (151) can occur uniformly, regardless of the polarization state (horizontal, vertical, or diagonal polarization) of the incident light. Therefore, wavelength conversion efficiency and light energy transfer efficiency to the substrate (110) are significantly improved throughout the entire SWIR wavelength range.

[0094] According to one embodiment of the invention, a barrier layer (145) may be disposed on a first surface (110a) of a substrate (110). The barrier layer (145) may include titanium nitride (TiN). However, the invention is not limited thereto, and the barrier layer (145) may include a conductive material. In a plan view, the barrier layer (145) may have the same area as the plasma pattern (151). Specifically, the barrier layer (145) may be formed by the same etching process used to form the plasma pattern (151).

[0095] According to the invention, the barrier layer (145) can be disposed between the substrate (110) and the plasma pattern (151), and can contact the first surface (110a) of the substrate (110) and the plasma pattern (151) respectively.

[0096] The barrier layer (145) according to the invention is used to ensure the junction stability between the substrate (110) and the plasma pattern (151) to suppress the interfacial reaction between the metal and the semiconductor and improve the uniformity of the charge injection path.

[0097] More specifically, when a metal layer directly contacts a semiconductor substrate, metal atoms can diffuse into the substrate or form a reactive layer at the interface depending on the process temperature or extended operation, thus destabilizing the junction characteristics. To prevent these problems, the present invention forms a barrier layer (145) with a thickness of tens of nanometers (nm) on the substrate (110), thereby stabilizing the formation of the Schottky barrier between the metal and the semiconductor. For example, the barrier layer (145) can have a thickness of 10 nm to 90 nm.

[0098] Furthermore, since the barrier layer (145) is conductive, electrons excited in the plasma pattern (151) can be smoothly injected into the substrate (110) through the barrier layer (145). As a result, the charge transfer resistance between the metal layer and the semiconductor substrate is reduced, and electron-hole pairs caused by plasma resonance are effectively collected, thereby improving the signal conversion efficiency.

[0099] According to one embodiment of the present invention, a dielectric layer (160) may be disposed on a plasma pattern (151). Specifically, the dielectric layer (160) may contact the plasma pattern (151) and may fill the vias (155). (See also...) Figure 4The dielectric layer (160) is used to planarize the surface of the pixel array (100), thereby improving the accuracy of subsequent processes and compensating for the surface height difference between individual device layers.

[0100] Furthermore, the dielectric layer (160) can control the surface plasmon resonance phenomenon occurring within the plasma pattern (151). In other words, the electric field intensity of the near field formed within the aperture (155) of the plasma pattern (151) varies according to the refractive index (n) of the dielectric layer (160), thereby enabling fine adjustment of the wavelength conversion efficiency.

[0101] Therefore, the dielectric layer (160) is used to stably maintain the plasma resonance conditions and enhance the optical signal responsivity.

[0102] Furthermore, the dielectric layer (160) can be made of materials such as silicon oxide (SiO2, n≈1.4), titanium oxide (TiO2, n>2.0), or silicon nitride (SiN). x Materials such as n≈2.0 are formed. The resonance condition with the plasma pattern (151) can vary depending on the refractive index of the material.

[0103] An image sensor (600) according to one embodiment of the present invention may include a substrate (110), an intermediate layer (690) disposed below the substrate (110), and a readout circuit (700) disposed below the intermediate layer (690). Specifically, the intermediate layer (690) may be disposed between the substrate (110) and the readout circuit (700).

[0104] In the intermediate layer (690) according to the present invention, a first contact portion (164), a second contact portion (165), a first metal pad (167), and a second metal pad (168) may be provided.

[0105] According to one embodiment of the present invention, the first contact portion (164) and the first metal pad (167) may constitute the cathode electrode portion, and the second contact portion (165) and the second metal pad (168) may constitute the anode electrode portion.

[0106] According to the present invention, a plurality of metal interconnects (710) may be disposed in the readout circuit (700). Although Figure 4 Not shown, but multiple metal interconnects (710) can be spaced apart from each other by multiple interlayer insulating films (not shown).

[0107] Figure 5 It is based on Figure 2 A plan view of the pixel array (101) of another embodiment. Figure 6 It is along Figure 5 The cross-sectional view taken from line II-II'. Figure 7 It is based on Figure 2 A plan view of the pixel array (102) of another embodiment.

[0108] and Figure 2 and Figure 4 The pixel array (100) shown is different, see reference. Figure 5 The plasma pattern (152) may include a hole (156) having a first length in a first direction (X) and a second length equal to the first length in a second direction (Y) perpendicular to the first direction (X). For example, Figure 5 A hole (156) with a square shape is shown. However, the invention is not limited to this, and the hole (156) can also have a circular shape (see [reference]). Figure 7 ).

[0109] According to one embodiment of the present invention, the holes (156) included in the plasma pattern (152) may have a square structure with equal lengths in the first direction (X) and the second direction (Y), or a circular structure with a constant radius. That is, the holes (156) may have an aspect ratio of 1:1.

[0110] The aperture (156) with this aspect ratio allows the electromagnetic field components in the vertical and horizontal directions to be uniformly distributed relative to the propagation direction of the incident light, thereby providing isotropic plasma resonance conditions independent of polarization. Therefore, a constant wavelength conversion efficiency can be maintained regardless of the polarization state or incident angle of the incident light.

[0111] Furthermore, the width or diameter of the aperture (156) can be maintained in the range of λ / 4 to λ / 1.5 relative to the wavelength (λ) of the incident light, and more specifically, in the range of λ / 2.6 to λ / 1.5. Within this size range, the aperture (156) can induce strong electromagnetic field coupling in a region corresponding to half the wavelength (λ / 2) of the incident light, thereby maximizing the plasma effect within the plasma pattern (152).

[0112] Therefore, the width or diameter of the aperture (156) can be maintained in the range of λ / 4 to λ / 1.5 relative to the wavelength (λ) of the incident light.

[0113] If the above range is not met, it may be difficult to achieve the pattern through etching, or it may be difficult to achieve the desired plasma effect.

[0114] Therefore, the plasma pattern (152) according to the invention can be designed such that the width or diameter of the aperture (156) is maintained in the range of 200 nm to 1000 nm to achieve effective wavelength conversion in the SWIR band (e.g., center wavelength 1550 nm). More specifically, it can be designed to be maintained in the range of 400 nm to 1000 nm. Preferably, it can be in the range of 600 nm to 1000 nm. With this structure, even if the aperture (156) has a simple configuration, the electromagnetic field distribution in the vertical and horizontal directions can be maintained uniformly. Thus, the plasma resonance conditions are stabilized, thereby simultaneously improving the light absorption efficiency and conversion efficiency.

[0115] Figure 7 The pixel array (102) shown includes a plasma pattern (153) with a circular aperture (157). Figure 7 In the case of the pixel array (102) shown, it is possible to achieve the same as Figure 5 and Figure 6 The pixel array (101) shown has the same technical effect. (The details regarding...) Figure 5 and Figure 6 The provided descriptions are overlapping and repetitive.

[0116] Reference Figures 5 to 7 When the wavelength of the incident light is λ, the thickness of the plasma pattern (152, 153) can be maintained in the range of λ / 10 to λ / 1.3. For example, when the wavelength of the incident light is 1550 nm (i.e., the center wavelength of the SWIR (short-wavelength infrared) region), the thickness of the plasma pattern (152, 153) can be formed in the range of 155 nm to 1192 nm. Since the thickness of the plasma pattern (152, 153) is related to... Figure 4 The provided descriptions overlap, so their detailed descriptions will be omitted.

[0117] Figure 8 This is a table showing the wavelength conversion based on the aspect ratio of the aperture.

[0118] Reference Figure 2 , Figure 4 and Figure 8 It can be confirmed that as the aspect ratio of the aperture (155) increases, the electromagnetic field distribution (E field distribution) and wavelength conversion characteristics change significantly.

[0119] Specifically, distributed( Figure 8The second row represents the results obtained through FDTD simulation. As the aspect ratio of the aperture (155) increases from 1:1 to 1:5, the electric field in the region of the aperture (155) of the plasma pattern (151) becomes more concentrated in the stripe pattern. This indicates that the near field formed when incident light passes through the aperture becomes more strongly localized with increasing aspect ratio. Specifically, the upper part of the image represents the region in which the plasma pattern is set, and the lower part represents the substrate (110). The vertical axis at 0 (z = 0) corresponds to the first surface (110a) or upper surface of the substrate (110).

[0120] In addition, In the distribution, the periodic repetition corresponds to the electric field intensity ( The fringes represent the region where the intensity reaches its maximum value (i.e., the intensity maxima band), and the spacing between adjacent intensity maxima bands corresponds to half the wavelength (λ / 2). Figure 8 The overall results confirm that the half-wavelength gradually decreases as the aspect ratio increases (from 1:1 to 1:5). This indicates that when the same incident light (1550 nm) is irradiated, the electric field period within the aperture shortens, thus achieving more efficient wavelength conversion.

[0121] exist Figure 8 The same trend is observed in the E-field plot shown in the third row. The horizontal axis of this plot represents based on Figure 4 The cross-sectional view shows the position along the z-axis, where 0 corresponds to the upper surface of the substrate (110), the positive (+) direction indicates the direction toward the plasma pattern (151), and the negative (-) direction indicates the direction toward the interior of the substrate (110). In the figure, the region where the real and imaginary components of the electric field intersect and exhibit an increased amplitude corresponds to the location where plasma resonance occurs. When the aspect ratio is 1:3 or greater, this amplitude increases significantly, indicating a more pronounced near-field enhancement and wavelength shortening effect.

[0122] The last row of the table (labeled WL Conv (μm)) represents the converted effective wavelength (1550 nm) relative to the incident light. At an aspect ratio of 1:1, the effective wavelength is approximately 1.419 μm, indicating almost no change. However, at an aspect ratio of 1:5, the effective wavelength shortens significantly to approximately 0.7 μm. This means that as the aspect ratio increases, the electromagnetic resonance within the aperture strengthens, and therefore, the wavelength of light entering the substrate (110) becomes shorter.

[0123] Based on these results, it can be confirmed that in this invention, wavelength conversion and electric field localization are effectively achieved when the aspect ratio of the aperture (155) is 1:3 or greater. Therefore, by designing the aspect ratio to be 1:3 or greater, incident light in the SWIR (short wavelength infrared) region can be effectively absorbed by the substrate (110), thereby improving the light-to-charge conversion efficiency while minimizing optical losses and achieving an optimal structure.

[0124] Figure 9 This is a table showing the wavelength conversion based on the aperture width.

[0125] Reference Figures 5 to 7 and Figure 9 It can be confirmed that as the width of the apertures (156, 157) increases, the electromagnetic field distribution (E-field distribution) and wavelength conversion characteristics change significantly. Specifically, the width can correspond to... Figure 6 The spacing between the plasma patterns (152) shown, or corresponding to Figure 7 The diameter of the hole (157) shown.

[0126] More specifically, distributed( Figure 9 The second row represents the results obtained through FDTD simulation. As the width of the apertures (156, 157) increases from 400 nm to 1000 nm, the electric field in the aperture regions of the plasma patterns (152, 153) becomes more concentrated in the stripe patterns. This indicates that the near field formed when incident light passes through the apertures becomes more strongly localized with increasing width. Specifically, the upper part of the image represents the region where the plasma patterns are set, and the lower part represents the substrate (110). The vertical axis at 0 (z = 0) corresponds to the first surface (110a) or upper surface of the substrate (110).

[0127] In addition, In the distribution, the periodic repetition corresponds to the electric field intensity ( The fringes represent the region where the intensity reaches its maximum value (i.e., the intensity maxima band), and the spacing between adjacent intensity maxima bands corresponds to half the wavelength (λ / 2). From Figure 9 The overall results confirm that the half-wavelength gradually decreases as the width increases (from 400 nm to 1000 nm). This indicates that when the same incident light (1550 nm) is irradiated, the electric field period within the aperture shortens, thus enabling more efficient wavelength conversion.

[0128] exist Figure 9 The same trend is observed in the E-field plot shown in the third row. The horizontal axis of this plot represents based on Figure 6The cross-sectional view is shown along the z-axis, where 0 corresponds to the upper surface of the substrate (110), the positive (+) direction indicates the direction toward the plasma pattern (152), and the negative (-) direction indicates the direction toward the interior of the substrate (110). The region where the real and imaginary components of the electric field intersect and exhibit an increased amplitude corresponds to the plasma resonance location. This amplitude increases significantly when the width is in the range of 400 nm to 1000 nm, resulting in a more significant near-field enhancement and wavelength shortening effect.

[0129] The last row of the table (labeled WL Conv (μm)) represents the converted effective wavelength (1550 nm) relative to the incident light. When the width is 200 nm, 1200 nm, or 1400 nm, it is difficult to measure the effective wavelength. However, when the width is in the range of 400 nm to 1000 nm, a clear wavelength variation is observed. This indicates that electromagnetic resonance is enhanced within the aperture in the 400 nm to 1000 nm width range relative to the incident wavelength of 1550 nm, thus resulting in a shorter wavelength of light entering the substrate (110).

[0130] Based on these results, it can be confirmed that in this invention, wavelength conversion and electric field localization are effectively achieved when the width of the apertures (156, 157) relative to the incident wavelength (λ) is in the range of λ / 4 to λ / 1.5. Therefore, by designing the width of the apertures (156, 157) to be in the range of λ / 4 to λ / 1.5 relative to the incident wavelength (λ), the incident light in the SWIR region can be effectively absorbed by the substrate (110), thereby improving the light-to-charge conversion efficiency while minimizing light loss and achieving an optimal structure.

[0131] The following advantages can be obtained from this disclosure.

[0132] According to one embodiment of the present invention, a pixel array can maximize the light absorption efficiency at SWIR wavelengths by using a structure with a plasma pattern to induce wavelength conversion.

[0133] In addition to the effects mentioned above, other features and advantages of the present invention are described below, or may be clearly understood by those skilled in the art from such description and explanation.

[0134] It will be apparent to those skilled in the art that this disclosure is not limited to the above-described embodiments and drawings, and that various substitutions, modifications, and variations may be made in this disclosure without departing from the spirit or scope thereof. Therefore, the scope of this disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of this disclosure.

[0135] Cross-reference to related applications

[0136] This application claims the benefit of priority to Korean Patent Application No. 10-2025-0035597, filed on March 19, 2025; Korean Patent Application No. 10-2025-0066446, filed on May 21, 2025; and Korean Patent Application No. 10-2026-0007459, filed on January 14, 2026, which are incorporated herein by reference as if fully set forth herein.

Claims

1. A pixel array, the pixel array comprising: Multiple pixels, Each of the plurality of pixels includes: A substrate, the substrate including an avalanche amplification region and having a first surface, on which light from the outside is incident; and Plasma pattern, the plasma pattern being formed on the first surface of the substrate. The plasma pattern includes one or more holes.

2. The pixel array according to claim 1, in, A plasma pattern is set for each of the plurality of pixels, and The plasma pattern disposed in any one of the plurality of pixels is formed as an integral structure.

3. The pixel array according to claim 1, in, The plasma pattern includes a plurality of holes arranged along a predetermined direction, and The plurality of holes are spaced apart from each other.

4. The pixel array according to claim 1, in, The hole has a first length in a first direction and a second length, different from the first length, in a second direction perpendicular to the first direction. In this case, one of the first length and the second length is at least three times larger than the other.

5. The pixel array according to claim 4, in, In a planar view, the pixels include a first region and a second region that are distinct from each other. The plasma pattern includes multiple holes disposed in the first region and the second region, and The plurality of holes disposed in the first region and the plurality of holes disposed in the second region extend in directions perpendicular to each other.

6. The pixel array according to claim 1, in, The hole has a square shape in the plan view or a circular shape with a constant radius in the plan view.

7. The pixel array according to claim 6, in, When the wavelength of the incident light is λ, the width of the aperture is in the range of λ / 4 to λ / 1.

5.

8. The pixel array according to claim 7, in, The width of the aperture is in the range of 400 nm to 1000 nm.

9. The pixel array according to claim 1, wherein the pixel array comprises: A barrier layer is disposed between the substrate and the plasma pattern, and is in contact with the first surface of the substrate and the plasma pattern; as well as A dielectric layer is disposed on the plasma pattern and fills the holes.

10. An image sensor, the image sensor comprising: Multiple pixels; as well as A pixel isolation structure that separates the plurality of pixels from each other. Each of the plurality of pixels includes: A substrate, the substrate being disposed on a readout circuit and having a first surface, on which external light is incident; and Plasma pattern, the plasma pattern being formed on the first surface of the substrate. The plasma pattern includes multiple holes.

Images