A preparation method of thinning the back surface of an infrared detector chip to be flush with a glue wall

Abstract

The application provides a preparation method for thinning the back of an infrared detector chip to the level of a glue wall, and belongs to the field of infrared detector preparation; solves the reliability problem of the bottom filling glue wall after thinning in the existing flip welding process; the method comprises the following steps: forming a groove in the scribe lane area of a wafer that has completed mesa etching, passivation, electrode preparation and indium column preparation processes; flip welding the focal plane chip end with the groove to a silicon-based readout circuit to achieve electrical interconnection through an indium column; filling the gap between the focal plane chip end and the silicon-based readout circuit with bottom filling glue; after the filling glue overflows from the gap, it enters the groove in the scribe lane area of the chip edge and naturally forms a glue wall in the groove; curing the filling glue; mechanically grinding, chemically mechanically polishing and silicon oxide fine polishing the back of the flip welding and glue-filled chip to thin the chip to a target thickness; the application is suitable for semiconductor devices using flip welding + bottom filling glue + back thinning processes.

Description

Technical Field

[0001] This application relates to the field of infrared detector fabrication technology, and in particular to a method for fabricating an infrared detector chip by thinning the back side to be flush with the adhesive wall. Background Technology

[0002] Type II superlattice cooled infrared detectors typically employ a flip-chip bonding process to interconnect the focal plane array chip with the silicon-based readout circuitry. The gaps between the flip-chips are then filled with an underfill adhesive (such as epoxy resin) to buffer thermal stress, protect interconnect bumps, and improve mechanical reliability. The adhesive flows naturally under capillary action, overflowing from around the chip to form a crescent-shaped adhesive wall.

[0003] In actual tape-out processes, existing technologies have the following problems: The height of the adhesive wall is uncontrollable and protrudes from the chip surface: The purpose of the adhesive wall is mainly to prevent edge cracking during subsequent back thinning. The height and shape of the adhesive wall formed by the existing process are difficult to control precisely: Affected by factors such as adhesive amount, gap size, and surface tension, the height of the adhesive wall usually fluctuates between tens and hundreds of micrometers and is unevenly distributed circumferentially. The protruding part will form stress concentration points during subsequent mechanical thinning, polishing and other processes, which will cause chip edge cracking and reduce the yield. Subsequent coating (such as zinc sulfide) followed by cracking: The mismatch between thermal stress in the coating process and the height of the adhesive wall exacerbates the risk of edge cracking; Poor surface flatness of the chip after thinning: Because the adhesive walls at the edges do not react with the polishing solution after chemical mechanical polishing, there will be a height difference between them and the central GaSb substrate surface, causing arc-shaped warping of the chip edges, such as... Figure 1 The existing grinding and polishing process has drawbacks in the adhesive wall effect; the height difference depends on the amount of material removed by chemical mechanical polishing, such as... Figure 2 The step profiler shows the height difference at the edge position. The left measurement area is the center of the array, and the right measurement area is the adhesive wall position. It can be observed that the adhesive wall is about 17μm higher than the chip center. There is a gradually decreasing height difference from the adhesive wall to the chip center, with a width of about 600μm, which has entered the photosensitive area and affects the uniformity of light absorption and the accuracy of the measurement.

[0004] Non-uniformity of mid-measurement results: The adhesive wall causes local height differences. After thinning and polishing, there is a height difference between the pixel area near the adhesive wall and the central area, which can easily cause chip warping. Uneven thinning thickness leads to inconsistent substrate parasitic absorption or interference effects, resulting in non-uniformity of quantum efficiency (QE) between pixels, which seriously affects the accuracy of mid-measurement results.

[0005] Existing glue wall control methods have poor compatibility: physical barrier or surface treatment methods require additional photolithography, deposition or modification steps, which increases process complexity and is incompatible with the sensitivity of type II superlattice materials; Existing technologies include optimization methods such as setting physical dams, modifying surface wettability, or using dicing grooves to constrain the adhesive wall. However, these methods have limitations such as complex processes, poor compatibility with existing FPA processes, or inability to completely solve the adhesive wall protrusion problem. Therefore, there is an urgent need for a solution that can effectively control the adhesive wall height and seamlessly integrate with existing flip-chip welding and thinning processes. Summary of the Invention

[0006] To address the reliability issues arising from the thinning of the adhesive wall at the bottom of the existing flip-chip bonding process, this application proposes a fabrication method for thinning the back of an infrared detector chip to be flush with the adhesive wall.

[0007] The technical solution adopted in this application is: a method for preparing an infrared detector chip by thinning the back side to be flush with the adhesive wall, comprising the following steps: Step 1: Provide a wafer that has completed mesa etching, passivation, electrode fabrication and indium pillar fabrication processes. Form grooves in the dicing area of ​​the wafer and then perform a dicing process to divide the wafer into focal plane chip ends to be flip-bonded. Step 2: The focal plane chip end with the groove is flip-chip bonded to the silicon-based readout circuit, and electrical interconnection is achieved through indium pillars. The whole after flip-chip bonding is called a chip. Step 3: Fill the gap between the focal plane chip and the silicon-based readout circuit with bottom filler. After the filler overflows from the gap, it enters the groove of the scribe line area on the chip edge and naturally forms a glue wall in the groove. Step 4: Curing of the filler adhesive; Step 5: Perform mechanical grinding, chemical mechanical polishing, and silicon oxide polishing on the back of the chip to thin the chip to the target thickness.

[0008] Furthermore, it also includes step six: after completing the chip back thinning, perform chip back coating and intermediate performance testing processes.

[0009] Furthermore, the width of the groove is the same as the width of the dicing channel, and the depth is 20~50μm.

[0010] Furthermore, the grooves are formed using laser grooving, dry etching, or wet etching.

[0011] Furthermore, the cross-section of the groove is rectangular, inverted trapezoidal, V-shaped, or arc-shaped.

[0012] Furthermore, in step one, after forming the groove, photoresist is used to coat the front side of the wafer for protection.

[0013] Furthermore, when using laser grooving, acid treatment is required on the focal plane chip end after the photoresist coating and dicing process.

[0014] Furthermore, in step five, the remaining substrate thickness H after the chip is thinned satisfies H=D±3μm with the groove depth D.

[0015] Furthermore, in step five, a single-point diamond ultra-precision turning machine tool can be used to thin the chip.

[0016] Furthermore, this method is applicable to the fabrication of semiconductor devices using flip-chip bonding + underfill adhesive + backside thinning processes.

[0017] The advantages of this application over the prior art are as follows: (1) The height of the adhesive wall is precisely controllable, eliminating process uncertainties; The groove depth is precisely controlled by laser grooving (error ±1μm), and the adhesive wall height is limited within the groove depth range, no longer relying on process parameters that are difficult to control precisely, such as epoxy adhesive volume, dispensing path, gap size, and surface tension. Even if there are fluctuations in epoxy adhesive viscosity or surface wettability between different batches, the adhesive wall height remains stable, thereby significantly improving process consistency and repeatability.

[0018] (2) Pickling after laser grooving reduces the risk of damage; During laser grooving, the high heat generated can produce slag, microcracks, or heat-affected zones. This application employs a short-term acid treatment with a wet solution (such as dilute hydrochloric acid, citric acid, or phosphoric acid solution) after grooving to effectively remove slag and damaged layers, restoring the integrity of the groove sidewalls. This treatment avoids edge cracking caused by microcrack propagation during subsequent thinning and coating processes, further improving the mechanical reliability of the chip.

[0019] (3) After thinning, the back of the chip is flat, eliminating warping; After the back side is thinned to the depth of the groove, the top of the adhesive wall is basically flush with the back of the chip (height difference ≤2μm), eliminating the height difference between the edge and the center and avoiding chip warping caused by local support of the adhesive wall. The flat back side provides an ideal substrate surface for subsequent photolithography, coating, and measurement processes.

[0020] (4) The uniformity of the middle measurement is greatly improved; Because the back side of the chip is flat, the substrate thickness after back-side thinning is highly consistent within the chip surface, avoiding local thickness differences caused by excessively raised adhesive walls. This results in: uniform back-side coating thickness (such as zinc sulfide antireflection coating) and consistent film optical properties; uniform substrate parasitic absorption across the entire chip, significantly reducing inter-pixel non-uniformity of quantum efficiency (QE); and fundamentally improved consistency between the responsivity of edge pixels and the center pixel, greatly enhancing the accuracy and reliability of mid-measurement results.

[0021] (5) Seamlessly compatible with existing FPA processes; This application does not change the core process parameters of existing flip-chip bonding, dispensing, CMP thinning, etc., and only requires adding a laser grooving step in the dicing area of ​​the chip front-end process. No new physical barriers, surface modification layers or expensive equipment are required, and it is fully compatible with the existing FPA manufacturing process, making it easy to quickly implement on mass production lines.

[0022] (6) Improve the thinning process window and reduce the difficulty of process control; In traditional CMP processes, endpoint detection requires precise control of the thinning thickness to avoid excessive adhesive wall protrusion, resulting in a narrow process window and significant control challenges. In this application, the adhesive wall is naturally exposed when the thinning reaches the bottom of the groove, and endpoint detection can be achieved by observing the color change of the epoxy resin or monitoring its reflectivity using an optical microscope. This significantly widens the process window, reducing the technical threshold for operators and the risk of process runaway.

[0023] (7) Applicable to various chip sizes and material systems; This application is not limited to Type II superlattice cooled infrared detectors, but is also applicable to other semiconductor devices employing flip-chip bonding + underfill adhesive + backside thinning processes, such as mercury cadmium telluride detectors, indium gallium arsenide detectors, and silicon-based image sensors. The groove depth can be flexibly adjusted according to the target thickness of different chips, exhibiting good versatility and portability.

[0024] (8) No additional materials are required, resulting in low cost and easy implementation; Compared with physical barrier methods (which require additional photolithography, electroplating, and deposition) or surface wettability modification methods (which require special chemical treatment), this application only utilizes the original dicing area of ​​the chip to form grooves through laser grooving, without adding any additional materials or complex process steps. It is low in cost, simple to implement, and easy to promote. Attached Figure Description

[0025] The following description, in conjunction with the accompanying drawings, further illustrates this application: Figure 1 This is a schematic diagram showing edge curling after conventional grinding and polishing; Figure 2 A test diagram showing the height difference measured by a step gauge for the raised steps of the edge adhesive wall after polishing using existing processes; Figure 3 This is a flowchart of the method described in this application; Figure 4 This is a schematic diagram showing the wafer and dicing track positions after the indium pillars have been grown. Figure 5 This is a schematic diagram of the focal plane chip end after laser grooving and scribing, where (a) is a front view and (b) is a cross-sectional view; Figure 6 This is a schematic diagram of laser grooving. Figure 7 This is a schematic diagram showing the width and depth after slotting; Figure 8 This is a schematic diagram showing the process of filling and thinning after inverted welding, without any protruding adhesive walls. Figure 9 Test diagram of the height difference measured by a stepper after thinning using the method of this application; In the figure: 1 is the wafer, 2 is the dicing track, 3 is the focal plane chip end, 4 is the focal plane pixel area array, 5 is the indium pillar, 6 is the mesa, 7 is the GaSb substrate to be thinned, 8 is the adhesive wall, and 9 is the silicon-based readout circuit. Detailed Implementation

[0026] like Figures 3 to 9 As shown, this application provides a method for fabricating an infrared detector chip by thinning the back side to be flush with the adhesive wall. Step 1: Provide wafer 1 and form grooves in the dicing area; Wafer 1 for a type II superlattice infrared detector is provided. Wafer 1 has completed front-end processes such as mesa etching, passivation, electrode fabrication, and indium pillar fabrication. Figure 4 As shown. The scribe lines 2 are distributed around the chip end 3 at the focal plane. In this embodiment, the width of the scribe line 2 is set to 200 μm. In the scribe line area of ​​wafer 1, a groove is formed by laser grooving. The depth of the groove is 20~50 μm (preferably 30 μm), and the width is equivalent to the width of the scribe line 2 (200 μm). A three-dimensional schematic diagram after laser grooving is shown below. Figure 6 As shown, Figure 7 The dimensions of the cross-section after grooving are shown; the width is approximately 200 μm, and the depth is approximately 30 μm. After grooving, AZ6130 photoresist is used for homogenization and protection of the front side of wafer 1. After baking, a dicing process is performed. Due to the dicing blade width of 40 μm and the inherent wobble of the dicing machine spindle, the width of the dicing track 2 after dicing is approximately 60 μm. Therefore, the laser-grooved pits around the individual focal plane chip end 3 after dicing are approximately 70 μm wide and 30 μm deep. The front view and cross-sectional view of the focal plane chip end 3 after laser grooving and dicing are shown below. Figure 5 As shown, the focal plane pixel array 4 and the scribe line 2 after laser grooving still have a safe distance of >300μm, and the laser grooving process will not affect the chip array area. During the laser grooving heating process, slag or microcracks are easily generated, which requires short-time acid washing to remove the heat-affected zone. In this embodiment, acid treatment is performed after scribe. At this time, the array is protected by adhesive, and acid treatment will not affect the chip performance. Phosphoric acid, citric acid, hydrogen peroxide, and DI water are used in a ratio of 1:1:2:20 for a short 30s treatment.

[0027] In other embodiments, dry etching or wet etching (such as citric acid-based etching solutions) can be used to form rectangular, inverted trapezoidal, V-shaped, or arc-shaped grooves to improve epoxy resin filling and stress distribution. However, the isotropic nature of wet etching must be considered, and the etching width on both sides needs to be reduced by about 30 μm, that is, the groove width during wet etching is set to 140 μm; this method is suitable for materials that are sensitive to etching damage.

[0028] Step 2: Flip-chip bonding; The focal plane chip end 3 with etched grooves is flip-chip bonded to the silicon-based readout circuit 9 (ROIC), and electrical interconnection is achieved through indium pillars 5.

[0029] Step 3: Apply adhesive for filling; In the gap between the focal plane chip end 3 and the silicon-based readout circuit 9, an underfill adhesive (such as epoxy resin) is filled using capillary action or pressure injection. After the epoxy resin overflows from the gap, it enters the groove of the scribe line 2 at the edge of the focal plane chip end 3, and naturally forms an adhesive wall 8 in the groove. Due to the limitation of the sidewall of the groove, the height of the adhesive wall 8 is constrained within the groove depth range, and the top of the adhesive wall 8 maintains a certain distance from the back side (i.e., the substrate surface) of the focal plane chip end 3 before thinning.

[0030] Step 4: Curing of the filler adhesive (epoxy adhesive); The epoxy adhesive is heat-cured according to the filling process requirements to shape the adhesive wall in the groove. The bottom filler will shrink to a certain extent during the curing process. The slight shrinkage of the adhesive wall height is beneficial to the continuous coverage of the subsequent coating.

[0031] Step 5: Thinning the back side; Mechanical grinding and chemical mechanical polishing (CMP) followed by silicon oxide polishing are performed on the back side of the focal plane chip end 3, i.e., the GaSb substrate 7 to be thinned, to reduce the focal plane chip end 3 to the target thickness. Figure 8 As shown. The remaining substrate thickness H after thinning satisfies the relationship with the groove depth D: H = D ± 3μm. For example, when the groove depth is 30μm, the remaining substrate thickness after thinning is controlled to be ≤30μm (preferably 30μm). When CMP exposes the epoxy resin color, it means that the target thickness is close, and it can be switched to silicon oxide polishing to remove ~1μm. At this time, the top of the adhesive wall at the bottom of the groove is exactly flush or basically flush with the back side of the thinned focal plane chip end 3, such as... Figure 9 As shown by the profilometer, the height difference between the adhesive wall and the focal plane chip end 3 surface decreased to 550nm.

[0032] In other embodiments, besides mechanical grinding, a single-point diamond ultra-precision turning machine (single-point equipment) can be used for thinning. This approach also avoids the problem of the cutting tool encountering irregular boundaries between soft and hard materials during turning. For example, overflowing crescent-shaped adhesive walls (such as epoxy resin) are large, irregularly shaped, and relatively soft polymers, while infrared detector substrates (such as GaSb) are hard and brittle materials. When the cutting tool forcibly cuts into the hard and brittle substrate from the outer thick adhesive wall at extremely high speed, the cutting force will change drastically. This change will cause the cutting tool to vibrate at high frequency (chatter / tool ​​deflection), which can easily cause microcracks or even chipping at the chip edge. By confining the adhesive wall within the dicing groove, the cutting resistance of the cutting tool is extremely stable during thinning, greatly reducing the probability of tool vibration and edge chipping.

[0033] Step Six: Subsequent Zinc Sulfide Process; After thinning is completed, subsequent processes such as back-side coating (e.g., zinc sulfide antireflection coating) and mid-testing are performed. Since the adhesive wall is flush with the back of the chip, edge stress concentration and height difference issues are greatly reduced.

[0034] The principle of this method is as follows: by pre-etching grooves in the dicing channel 2, the formation area of ​​the adhesive wall is transferred from "above the chip surface" to "within the chip substrate". When the back side is thinned to the depth of the grooves, the adhesive wall is just exposed and flush with the back side of the chip, thereby fundamentally eliminating the stress concentration and height difference problems caused by the protruding adhesive wall.

[0035] The differences between the method of this application and the prior art are shown in Table 1 below: Table 1. Differences between this application and prior art; .

[0036] The groove in this application is located inside the dicing channel area, maintaining a safe distance (>300μm) from the active area of ​​the chip. This groove simultaneously performs multiple functions: serving as a container for adhesive walls during the filling stage; acting as a reference marker for endpoint detection during the thinning stage; and assisting in guiding the dicing blade during the dicing stage.

[0037] This application utilizes the difference in optical properties between the colloid in the groove and the substrate material, and uses the exposure of the colloid color under a microscope as the endpoint detection signal for chemical mechanical polishing, thereby achieving precise and repeatable control of the thinning endpoint.

[0038] This application effectively solves a series of problems caused by protruding adhesive walls after thinning, such as edge stress concentration, chip warping, uneven thinning thickness, and mid-surface non-uniformity. Furthermore, it achieves flush integration between the adhesive wall and the back surface, structurally eliminating stress concentration sources and resulting in a flat chip back surface, controllable thinning endpoint, and significantly improved mid-surface uniformity.

[0039] This application integrates the three functions of the slab marking channel, the adhesive wall container, and the thinning endpoint, thus achieving structural function reuse. Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating an infrared detector chip with its back side thinned to be flush with the adhesive wall, characterized in that: Includes the following steps: Step 1: Provide a wafer that has completed mesa etching, passivation, electrode fabrication and indium pillar fabrication processes. Form grooves in the dicing area of ​​the wafer and then perform a dicing process to divide the wafer into focal plane chip ends to be flip-bonded. Step 2: The focal plane chip end with the groove is flip-chip bonded to the silicon-based readout circuit, and electrical interconnection is achieved through indium pillars. The whole after flip-chip bonding is called a chip. Step 3: Fill the gap between the focal plane chip and the silicon-based readout circuit with bottom filler. After the filler overflows from the gap, it enters the groove of the scribe line area on the chip edge and naturally forms a glue wall in the groove. Step 4: Curing of the filler adhesive; Step 5: Perform mechanical grinding, chemical mechanical polishing, and silicon oxide polishing on the back of the chip to thin the chip to the target thickness.

2. The method for fabricating an infrared detector chip with its back side thinned and flush with the adhesive wall according to claim 1, characterized in that: It also includes step six: after completing the chip back thinning, perform chip back coating and intermediate performance testing processes.

3. The method for fabricating an infrared detector chip with its back side thinned to be flush with the adhesive wall according to claim 1 or 2, characterized in that: The width of the groove is the same as the width of the dicing channel, and the depth is 20~50μm.

4. The method for fabricating an infrared detector chip with its back side thinned to be flush with the adhesive wall according to claim 1 or 2, characterized in that: The grooves are formed by laser grooving, dry etching, or wet etching.

5. A method for fabricating an infrared detector chip with its back side thinned to be flush with the adhesive wall according to claim 1 or 2, characterized in that: The cross-section of the groove can be rectangular, inverted trapezoidal, V-shaped, or arc-shaped.

6. The method for fabricating an infrared detector chip with its back side thinned and flush with the adhesive wall according to claim 4, characterized in that: In step one, after the groove is formed, photoresist is used to coat the front side of the wafer for protection.

7. The method for fabricating an infrared detector chip with its back side thinned and flush with the adhesive wall according to claim 6, characterized in that: When using laser grooving, acid treatment is also required on the focal plane chip end after the photoresist coating and dicing process.

8. The method for fabricating an infrared detector chip with its back side thinned and flush with the adhesive wall according to claim 3, characterized in that: In step five, the remaining substrate thickness H after chip thinning and the groove depth D satisfy H=D±3μm.

9. The method for fabricating an infrared detector chip with its back side thinned and flush with the adhesive wall according to claim 3, characterized in that: Step five can also use a single-point diamond ultra-precision turning machine to thin the chip.

10. A method for fabricating an infrared detector chip with its back side thinned to be flush with the adhesive wall according to claim 1 or 2, characterized in that: This method is applicable to the fabrication of semiconductor devices using flip-chip bonding, underfill adhesive, and back-side thinning processes.

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