Method for improving dark current of cmos image sensor product

Abstract

The application provides a method for improving dark current of a CMOS image sensor product, comprising: providing a semiconductor substrate, forming a shallow trench isolation groove on the semiconductor substrate; forming a first liner layer on the inner wall of the shallow trench isolation groove; forming a fluorine-containing second liner layer on the first liner layer; and depositing an isolation medium layer on the fluorine-containing second liner layer to fill the shallow trench isolation groove. By introducing fluorine elements into the second liner layer, the fluorine atoms diffuse to the interface to passivate defects such as dangling bonds, and at the same time, the fluorine ions form fixed negative charges in the thin film to establish an internal electric field to repel the diffusion of electrons to the interface. Through the double mechanisms of defect passivation and electric field shielding, the probability of electron capture and recombination by interface defects is reduced, the dark current performance is improved, and the imaging quality is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method for improving dark current in CMOS image sensor products. Background Technology

[0002] Dark current is a key parameter for evaluating the performance of CMOS image sensors (CIS), referring to the current signal generated by a pixel unit under dark conditions. This parameter not only determines the imaging quality of the sensor under low-light conditions but also directly affects the signal-to-noise ratio (SNR), dynamic range, power consumption, and image stability and consistency. In modern CIS technology, dark current mainly originates from three sources: electron-hole pairs generated by thermal excitation in the bulk region, recombination current of surface / interface states, and current generated in the depletion region. Among these, dark current related to surface / interface states dominates in small-pixel technology nodes.

[0003] During the fabrication of shallow trench isolation (STI), plasma etching generates numerous lattice damages and dangling bonds on the silicon surface. These defects can evolve into deep-level traps during subsequent oxidation and annealing processes. Furthermore, the geometric features of the STI structure (such as sharp corners and edges) lead to electric field concentration, further exacerbating carrier generation and recombination. After thermal oxidation, most interface vacancies are occupied by oxygen atoms, but some excess dangling bonds remain (vacancies may be occupied by hydrogen atoms during wet oxidation).

[0004] To address the dark current issue associated with STI (Surface Tilt) etching, various technical solutions have been developed, including optimizing STI etching processes, improving oxide layer quality, and employing specialized interface passivation techniques. However, these traditional methods have limitations in terms of effectiveness and process compatibility. Therefore, developing more effective dark current control techniques for STI regions has become an important direction for the development of CIS (Computer Integrated Systems) technology. Summary of the Invention

[0005] The technical problem this invention aims to solve is that during the shallow trench isolation (STI) manufacturing process of CMOS image sensors (CIS), plasma etching generates lattice damage and dangling bonds on the silicon surface, leading to an increase in surface and interface state-related dark currents, which severely affects the imaging quality of the sensor under low-light conditions. To address the aforementioned dark current problem related to shallow trench isolation, this invention provides a method for improving the dark current of CMOS image sensor products.

[0006] A method for improving dark current in CMOS image sensor products includes:

[0007] Step 1: Provide a semiconductor substrate and form shallow trench isolation trenches on the semiconductor substrate;

[0008] Step 2: Form a first liner layer on the inner wall of the shallow trench isolation channel;

[0009] Step 3: Form a fluorine-containing second liner layer on the first liner layer;

[0010] Step 4: Deposit an isolation medium layer on the fluorine-containing second liner layer to fill the shallow trench isolation groove.

[0011] Preferably, in step one, a first mask layer and a second mask layer are sequentially formed on the semiconductor substrate, and the second mask layer, the first mask layer and the semiconductor substrate are etched to form the shallow trench isolation trench; after forming the shallow trench isolation trench, the second mask layer is further subjected to a pull-back process.

[0012] Preferably, in step one, the first mask layer is a pad oxide layer and the second mask layer is a pad silicon nitride layer.

[0013] Preferably, the first pad layer is a pad oxide layer, and the second pad layer is a pad silicon nitride layer.

[0014] Preferably, in step two, the first liner layer is formed using an in-situ water vapor generation process, and an in-situ water vapor generation pre-cleaning is performed before using the in-situ water vapor generation process.

[0015] Preferably, in step two, the thickness of the first liner layer is 50 to 70 angstroms.

[0016] Preferably, in step three, a plasma-enhanced chemical vapor deposition process or an atomic layer deposition process is used, and a fluorinated silicon precursor is used as the reactant gas to introduce fluorine atoms into the silicon nitride lattice of the second liner layer to form the fluorinated second liner layer.

[0017] Preferably, in step three, the thickness of the fluorine-containing second liner layer is 70 to 90 angstroms.

[0018] Preferably, in step three, fluoride ions replace N3- in the Si-N bond or H+ in the Si-H bond in the second liner layer to form a fixed negative charge in the fluorine-containing second liner layer; by adjusting the ratio of fluorine to silicon in the fluorine-containing silicon precursor, the density of the fixed negative charge is made to range from 1×10^12 cm^-2 to 5×10^12 cm^-2.

[0019] Preferably, in step four, the isolation medium layer is deposited using a high aspect ratio process; after depositing the isolation medium layer, a shallow trench isolation annealing process is also performed.

[0020] Preferably, in step four, the deposition thickness of the isolation medium layer is 5000 to 6000 angstroms.

[0021] Preferably, in step four, the shallow tank isolation annealing treatment is carried out at a temperature of 1000°C to 1100°C for a time of 20 to 40 minutes.

[0022] Preferably, after step four, the method further includes:

[0023] Step 5: Perform chemical mechanical planarization, stopping on the second mask layer and completely removing the first liner layer and the fluorine-containing second liner layer located above the second mask layer; after performing the chemical mechanical planarization, a planarization annealing process is also performed;

[0024] Step 6: Remove a portion of the second mask layer and a portion of the fluorine-containing second liner layer to expose the first liner layer located in the middle;

[0025] Step 7: Adjust the step height and remove the exposed first padding layer;

[0026] Step 8: Remove the remaining second mask layer and stop on the first mask layer; wherein, the over-etching time is controlled to avoid loss of the fluorine-containing second liner layer;

[0027] Step 9: Remove the exposed first pad layer and adjust the thickness of the first mask layer.

[0028] Preferably, in step five, the planarization annealing treatment is carried out at a temperature of 850°C to 950°C for a time of 20 to 40 minutes.

[0029] Preferably, in step seven, the required height for adjusting the step height is 200 to 300 angstroms.

[0030] Preferably, in step nine, the adjusted thickness of the first mask layer is maintained between 70 angstroms and 110 angstroms.

[0031] As described above, the method for improving dark current in CMOS image sensor products according to the present invention has the following beneficial effects:

[0032] This invention forms a fluorine-containing second pad layer on a first pad layer. Fluorine atoms, due to their small physical size, penetrate the first pad layer to reach the interface between the semiconductor substrate and the first pad layer, reacting with unbonded silicon atoms to form stable silicon-fluorine bonds. This fills dangling bonds and other structural defects at the interface, reducing interface trap centers capable of capturing charge carriers. Simultaneously, the fluorine doped in the second pad layer introduces a fixed negative charge into the thin film network, generating a built-in electric field pointing inwards towards the semiconductor substrate in the sidewall region of the shallow trench isolation area. This electric field electrostatically repels thermally excited electrons, hindering their movement towards the interface. Through this dual mechanism of defect passivation and electric field shielding, the probability of electrons being trapped and recombinating by interface defects is reduced, improving dark current performance and enhancing imaging quality. Attached Figure Description

[0033] Figure 1 The diagram shows a process flow diagram of the method for improving dark current in CMOS image sensor products according to the present invention.

[0034] Figure 2 The diagram shows a cross-sectional structure of the present invention after the formation of the first liner layer;

[0035] Figure 3 The diagram shows a cross-sectional structure of the present invention after the formation of the fluorine-containing second liner layer;

[0036] Figure 4 The diagram shows a cross-sectional structure of the deposition isolation medium layer according to the present invention.

[0037] Figure 5 The diagram shown is a cross-sectional structure of the present invention after undergoing chemical mechanical planarization treatment.

[0038] Figure 6 The diagram shows a cross-sectional structure of the present invention after the first liner layer has been exposed.

[0039] Figure 7 The diagram shown is a cross-sectional structural schematic of the present invention after adjusting the step height.

[0040] Figure 8 The diagram shows a cross-sectional structure of the present invention after the remaining second mask layer has been removed.

[0041] Figure 9 The diagram shows a cross-sectional structure of the present invention after removing the exposed first padding layer and adjusting the thickness of the first mask layer. Detailed Implementation

[0042] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the process flow for a method to improve dark current in CMOS image sensor products. (Combined with...) Figure 1 As shown, the method includes:

[0044] Step 1: Provide a semiconductor substrate 101 and form shallow trench isolation trenches on the semiconductor substrate 101.

[0045] Combination Figure 2 As shown, semiconductor substrate 101 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer serving as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0046] In semiconductor manufacturing processes, the pattern of isolation regions is typically defined through a series of patterning processes. The patterning process includes coating a photoresist over a semiconductor substrate 101, followed by exposure and development to form a photoresist mask with specific openings.

[0047] Anisotropic dry etching processes, such as inductively coupled plasma etching or capacitively coupled plasma etching, are then used to transfer the photoresist pattern onto the semiconductor substrate 101, thereby forming shallow isolation trenches. During the etching process, halogen-containing gases, such as chlorine, hydrogen bromide, or sulfur hexafluoride, can be introduced, along with fluorocarbon gases, to form a polymer protective layer on the trench sidewalls. This allows for precise control of the trench morphology, depth, and sidewall perpendicularity. After etching, residual photoresist and etching byproducts are typically removed through ashing and wet cleaning processes.

[0048] In some embodiments, in step one, a first mask layer 102 and a second mask layer 103 are sequentially formed on a semiconductor substrate 101, and the second mask layer 103, the first mask layer 102 and the semiconductor substrate 101 are etched to form a shallow trench isolation trench; after forming the shallow trench isolation trench, the second mask layer 103 is further subjected to a pull-back process.

[0049] In some embodiments, in step one, the first mask layer 102 is a pad oxide layer and the second mask layer 103 is a pad silicon nitride layer.

[0050] Continue to refer to Figure 2 The first mask layer 102 can be formed by thermal oxidation, low-pressure chemical vapor deposition, or atomic layer deposition. As a feasible implementation, the thermal oxidation process can be carried out in a high-temperature furnace tube through which dry oxygen or water vapor is introduced. The first mask layer 102 formed mainly serves as a buffer layer to release the lattice stress between the upper, harder second mask layer 103 and the lower semiconductor substrate 101, preventing dislocation defects in the silicon lattice.

[0051] The second mask layer 103 can be formed using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), with the reaction gas being a mixture of dichlorosilane and ammonia. The second mask layer 103 exhibits high mechanical strength and chemical stability, serving as a reliable stop layer in subsequent chemical mechanical planarization (CMP) processes. Besides the silicon nitride layer, the second mask layer 103 can also be replaced with other hard mask materials with high etch selectivity, such as silicon oxynitride, amorphous carbon, or spin-coated glass.

[0052] Pullback is typically achieved through isotropic wet etching processes, such as using heated phosphoric acid solutions. Due to the isotropic nature of wet etching, pullback exposes and rounds the top edges of shallow trench isolation trenches. This rounded edge shape prevents electric field concentration in the sharp corner region during subsequent device operation.

[0053] Step 2: Form the first liner layer 104 on the inner wall of the shallow trench isolation ditch.

[0054] In some embodiments, the first liner layer 104 is a liner oxide layer.

[0055] In some embodiments, in step two, the first liner layer 104 is formed using an in-situ water vapor generation process, and in-situ water vapor generation pre-cleaning is performed before using the in-situ water vapor generation process.

[0056] In some embodiments, in step two, the thickness of the first liner layer 104 is 50 to 70 angstroms.

[0057] In-situ pre-cleaning for water vapor generation can be performed using standard cleaning solutions or dilute hydrofluoric acid solutions. For example, a mixture of ammonia and hydrogen peroxide can be used sequentially to remove particles and organic matter, a mixture of hydrochloric acid and hydrogen peroxide can be used to remove metal ions, and finally dilute hydrofluoric acid can be used to remove natural oxides and etching residues from the surface of the shallow trench isolation channels, ensuring absolute cleanliness of the silicon interface.

[0058] The in-situ water vapor generation process can generate water vapor directly by burning hydrogen and oxygen in a rapid thermal treatment reaction chamber with a lower thermal budget, thereby growing a dense and high-quality first liner layer 104 on the inner wall of the trench. Compared with conventional furnace tube oxidation, the oxygen free radicals generated by the in-situ water vapor generation process have stronger reactivity, enabling the formation of a more uniform conformal film on the sidewalls and bottom of the trench. Alternatively, the first liner layer 104 can also be formed by high-density plasma oxidation or atomic layer deposition oxidation.

[0059] The first pad layer 104 can repair the lattice damage caused to the surface of the semiconductor substrate 101 by the previous dry etching process and initially passivate the dangling bonds on the surface. The thickness of the first pad layer 104 is controlled within the above range to ensure sufficient surface repair effect without excessively consuming the silicon material of the semiconductor substrate 101, thereby maintaining the effective light-emitting or photosensitive area of ​​the pixel unit and ensuring that the full-well capacity of the image sensor is not affected.

[0060] Step 3: Form a fluorine-containing second liner 105 on the first liner 104.

[0061] In some embodiments, the second pad layer 105 is a pad silicon nitride layer.

[0062] In some embodiments, in step three, a plasma-enhanced chemical vapor deposition process or an atomic layer deposition process is used, and a fluorine-containing silicon precursor is used as a reaction gas to introduce fluorine atoms into the silicon nitride lattice of the second liner layer 105 to form a fluorine-containing second liner layer 105.

[0063] In some embodiments, in step three, the thickness of the fluorinated second liner 105 is 70 to 90 angstroms.

[0064] In some embodiments, in step three, fluorine ions replace N3- in the Si-N bond or H+ in the Si-H bond in the second liner layer 105 to form a fixed negative charge in the fluorine-containing second liner layer 105; by adjusting the ratio of fluorine to silicon in the fluorine-containing silicon precursor, the density of the fixed negative charge is made to range from 1×10^12 cm^-2 to 5×10^12 cm^-2.

[0065] refer to Figure 3The fluorinated silicon precursor may include silicon tetrafluoride, hexafluorosilane, or other suitable fluorinated gases, reacting with ammonia or nitrogen instead of traditional silicon source gases. When using atomic layer deposition (ALD), the process involves alternating introduction of the fluorinated silicon precursor and nitrogen precursor, followed by purging with an inert gas such as argon or nitrogen after each introduction. This deposition method, based on a surface-limited reaction, provides excellent step coverage and atomic-level thickness control precision, ensuring highly consistent film quality across all trench locations, thereby forming a uniform second liner layer 105.

[0066] During the formation of the fluorine-containing second pad layer 105, fluorine atoms, due to their small physical size, can penetrate the first pad layer 104 and reach the interface between the semiconductor substrate 101 and the first pad layer 104. At the interface, fluorine atoms react with unbonded silicon atoms to form stable silicon-fluorine bonds. The formation of this chemical bond fills dangling bonds and other structural defects at the interface, thereby reducing interface trap centers capable of trapping charge carriers. Simultaneously, the fluorine doping in the second pad layer 105 introduces fixed negative charges into the thin film network. These negative charges generate a built-in electric field pointing towards the interior of the semiconductor substrate 101 in the sidewall region of the shallow trench isolation trench. When electrons are generated in the semiconductor substrate 101 due to thermal excitation, this built-in electric field electrostatically repels the electrons, hindering their movement to the interface between the semiconductor substrate 101 and the first pad layer 104. On the one hand, the number of interface defects is reduced, and on the other hand, electrons are less likely to approach the interface. The combination of these two factors reduces the probability of electrons being captured by interface defects and recombination, thus reducing leakage current under no-light conditions, improving the dark current performance of the image sensor, and thereby enhancing the imaging clarity and signal consistency of the device in low-light environments.

[0067] Step 4: Deposit an isolation medium layer 106 on the fluorine-containing second liner layer 105 to fill the shallow trench isolation channel.

[0068] In some embodiments, in step four, an isolation medium layer 106 is deposited using a high aspect ratio process; after depositing the isolation medium layer 106, a shallow trench isolation annealing process is also performed.

[0069] In some embodiments, in step four, the deposition thickness of the isolation medium layer 106 is 5000 angstroms to 6000 angstroms.

[0070] In some embodiments, in step four, the temperature of the shallow tank isolation annealing treatment is 1000°C to 1100°C, and the time is 20 minutes to 40 minutes.

[0071] refer to Figure 4The insulating dielectric layer 106 may include silicon oxide, silicon oxynitride, or other dielectric materials with good insulating properties. The high aspect ratio process can employ a sub-atmospheric pressure chemical vapor deposition process based on ozone and tetraethyl orthosilicate. This process exhibits liquid-like flowability during deposition, enabling seamless bottom-up filling of high aspect ratio trenches and avoiding the formation of voids or gaps within shallow isolation trenches. Alternatively, the insulating dielectric layer 106 can also be formed using a flowable chemical vapor deposition process, a high-density plasma chemical vapor deposition process, or a spin-coating insulating dielectric process.

[0072] Shallow trench isolation annealing is typically performed in a high-temperature nitrogen, oxygen, or water vapor atmosphere. The purpose of annealing is to remove residual moisture, hydrocarbons, and other impurities from the isolation dielectric layer 106, causing the deposited loose film to densify. Simultaneously, high-temperature annealing releases accumulated mechanical stress within the film, repairs microstructural defects, and further improves the electrical insulation properties of the isolation structure, preventing electrical crosstalk between adjacent pixel units.

[0073] In some embodiments, after step four, the method further includes:

[0074] Step 5: Perform chemical mechanical planarization, stop on the second mask layer 103, and completely remove the first liner layer 104 and the fluorine-containing second liner layer 105 located above the second mask layer 103; after performing chemical mechanical planarization, planarization annealing is also performed.

[0075] In some embodiments, in step five, the planarization annealing process is carried out at a temperature of 850°C to 950°C for a time of 20 to 40 minutes.

[0076] refer to Figure 5 In step five, the chemical mechanical planarization process utilizes an abrasive slurry containing cerium dioxide or silicon dioxide, combined with the mechanical friction of the abrasive pad, to remove excess isolation medium layer 106 and pad material from the outside of the trench. During planarization, the grinding progress can be monitored in real time using an optical endpoint detection system or a friction endpoint detection system to ensure that grinding precisely stops on the surface of the second mask layer 103. Planarization annealing helps repair surface micro-scratches and lattice damage generated during the grinding process and releases surface stress.

[0077] Step 6: Wet etching can be used to remove part of the second mask layer 103 and part of the fluorine-containing second liner layer 105 to expose the first liner layer 104 located in the middle.

[0078] refer to Figure 6In step six, wet etching can be performed using a hot phosphoric acid solution at a specific temperature. Because hot phosphoric acid has an extremely high etching selectivity for silicon nitride, the downward pull-back of the second mask layer 103 and the fluorine-containing second backing layer 105 can be precisely controlled with almost no damage to the oxide material. At this point, the exposed first backing layer 104 is physically supported by silicon nitride on both sides, thus avoiding the risk of peeling.

[0079] Step 7: Adjust the step height and remove the exposed first liner layer 104.

[0080] In some embodiments, in step seven, the required step height adjustment is 200 to 300 angstroms.

[0081] refer to Figure 7 In step seven, the step height adjustment can be achieved by dilute hydrofluoric acid solution or buffered oxide etching solution to accurately remove the protruding first pad layer 104, prevent the formation of parasitic transistors or local electric field distortion in subsequent processes, and ensure the smoothness of the surface morphology.

[0082] Step 8: The remaining second mask layer 103 can be removed by wet etching, and the etching can be stopped on the first mask layer 102; wherein, the over-etching time is controlled to avoid loss of the fluorine-containing second liner layer 105.

[0083] refer to Figure 8 In step eight, the remaining second mask layer 103 is removed again using hot phosphoric acid solution. By strictly controlling the concentration, temperature and over-etching time of the etching solution, the fluorine-containing second liner layer 105 inside the trench can be protected from damage, maintaining its long-term interface passivation and electric field shielding function.

[0084] Step 9: Remove the exposed first backing layer 104 using an etching process, and adjust the thickness of the first mask layer 102.

[0085] In some embodiments, in step nine, the thickness of the adjusted first mask layer 102 is maintained between 70 angstroms and 110 angstroms.

[0086] refer to Figure 9 In step nine, the etching process can employ advanced process control technology combined with dilute hydrofluoric acid solution to precisely adjust the thickness of the first mask layer 102 to the target range while removing the remaining exposed first backing layer 104.

[0087] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0088] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving dark current in CMOS image sensor products, characterized in that, At least including: Step 1: Provide a semiconductor substrate and form shallow trench isolation trenches on the semiconductor substrate; Step 2: Form a first liner layer on the inner wall of the shallow trench isolation channel; Step 3: Form a fluorine-containing second liner layer on the first liner layer; Step 4: Deposit an isolation medium layer on the fluorine-containing second liner layer to fill the shallow trench isolation groove.

2. The method for improving dark current in CMOS image sensor products according to claim 1, characterized in that: In step one, a first mask layer and a second mask layer are sequentially formed on the semiconductor substrate, and the second mask layer, the first mask layer and the semiconductor substrate are etched to form the shallow trench isolation trench; After forming the shallow trench isolation groove, the process also includes pulling back the second mask layer.

3. The method for improving dark current in CMOS image sensor products according to claim 1, characterized in that: In step one, the first mask layer is a pad oxide layer, and the second mask layer is a pad silicon nitride layer.

4. The method for improving dark current in CMOS image sensor products according to claim 1, characterized in that: The first pad layer is a pad oxide layer, and the second pad layer is a pad silicon nitride layer.

5. The method for improving dark current in CMOS image sensor products according to claim 1, characterized in that: In step two, the first liner layer is formed using an in-situ water vapor generation process, and in-situ water vapor generation pre-cleaning is performed before using the in-situ water vapor generation process.

6. The method for improving dark current in CMOS image sensor products according to claim 5, characterized in that: In step two, the thickness of the first liner layer is 50 to 70 angstroms.

7. The method for improving dark current in CMOS image sensor products according to claim 4, characterized in that: In step three, a plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) process is used, and a fluorinated silicon precursor is used as the reactant gas to introduce fluorine atoms into the silicon nitride lattice of the second liner layer to form the fluorinated second liner layer.

8. The method for improving dark current in CMOS image sensor products according to claim 1, characterized in that: In step three, the thickness of the fluorine-containing second liner layer is 70 to 90 angstroms.

9. The method for improving dark current in CMOS image sensor products according to claim 7, characterized in that: In step three, fluoride ions replace N3- in the Si-N bond or H+ in the Si-H bond in the second liner layer to form a fixed negative charge in the fluorine-containing second liner layer; by adjusting the ratio of fluorine to silicon in the fluorine-containing silicon precursor, the density of the fixed negative charge is made to range from 1×10^12 cm^-2 to 5×10^12 cm^-2.

10. The method for improving dark current in CMOS image sensor products according to claim 1, characterized in that: In step four, the isolation dielectric layer is deposited using a high aspect ratio process; After depositing the isolation medium layer, a shallow trench isolation annealing process is also included.

11. The method for improving dark current in CMOS image sensor products according to claim 10, characterized in that: In step four, the deposition thickness of the isolation medium layer is 5000 to 6000 angstroms.

12. The method for improving dark current in CMOS image sensor products according to claim 10, characterized in that: In step four, the shallow tank isolation annealing treatment is carried out at a temperature of 1000°C to 1100°C for 20 to 40 minutes.

13. The method according to claim 2, characterized in that, Following step four, the following is also included: Step 5: Perform chemical mechanical planarization, stopping on the second mask layer and completely removing the first liner layer and the fluorine-containing second liner layer located above the second mask layer; after performing the chemical mechanical planarization, a planarization annealing process is also performed; Step 6: Remove a portion of the second mask layer and a portion of the fluorine-containing second liner layer to expose the first liner layer located in the middle; Step 7: Adjust the step height and remove the exposed first padding layer; Step 8: Remove the remaining second mask layer and stop on the first mask layer; wherein, the over-etching time is controlled to avoid loss of the fluorine-containing second liner layer; Step 9: Remove the exposed first pad layer and adjust the thickness of the first mask layer.

14. The method for improving dark current in CMOS image sensor products according to claim 13, characterized in that: In step five, the planarization annealing treatment is carried out at a temperature of 850°C to 950°C for a time of 20 to 40 minutes.

15. The method for improving dark current in CMOS image sensor products according to claim 16, characterized in that: In step seven, the required height for adjusting the step height is 200 to 300 angstroms.

16. The method for improving dark current in CMOS image sensor products according to claim 16, characterized in that: In step nine, the adjusted thickness of the first mask layer is maintained between 70 and 110 angstroms.

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