A method of manufacturing a backside illuminated image sensor
Patent Information
- Application Number
- CN202510332885.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-19
- Publication Date
- 2026-09-22
AI Technical Summary
所述负载效应具体表现为：因刻蚀区域密度差异，高密度区域(如密集沟槽阵列)消耗过量钝化气体，导致孔口介质层的钝化保护层厚度显著减薄(常规工艺下厚度<10nm)，因而使得孔口介质层3容易因等离子体持续轰击而损耗加剧，如图1b所示，所述孔口介质层过薄将削弱其绝缘性能，引发金属与硅衬底间的电子隧穿效应，导致漏电流升高、信噪比劣化；现有脉冲参数(如占空比、频率)难以兼顾刻蚀深度与孔口介质层的完整性
[0027]本发明通过三个步骤逐步刻蚀打开硅通孔底部的第二介质层、第一介质层，暴露出底部金属填充层，且孔口介质层在第二介质层的保护下不受损伤，避免了孔口电子穿透风险。具体来说，采用第一刻蚀气体，刻蚀去除所述硅通孔底部的第二介质层，且至少部分保留所述硅通孔侧壁及顶角上表面的第二介质层；保留的第二介质层可以作为孔口介质层(第一介质层)的保护层，避免孔口介质层在等离子体持续轰击下受到损伤。然后，采用第二刻蚀气体，刻蚀去除所述硅通孔底部的第一介质层，暴露出所述金属填充层；所述第二刻蚀气体对于第一介质层、第二介质层具有选择比，可以优先刻蚀第一介质层，从而在打开硅通孔底部的第一介质层时，几乎不影响孔口介质层的保护层的厚度。最后再采用第一刻蚀气体，刻蚀去除所述保留的第二介质层，即，去除孔口介质层的保护层。
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Figure CN122803407A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of image sensor technology, and specifically relates to a method for manufacturing a back-illuminated image sensor. Background Technology
[0002] In the fabrication of back-illuminated CMOS image sensor (CIS) chips, through-silicon vias (TSVs), as a key structure connecting the front-end photoelectric sensing unit and the back-end metal interconnect layer, require high aspect ratio etching processes. The TSV etching process has stringent requirements: while ensuring the exposure of the bottom metal filling layer 2 (e.g., tungsten) of the TSV 1, plasma damage to the dielectric layer 3 at the via opening must be minimized. Figure 1a As shown. This is because if the aperture dielectric layer 3 (e.g., silicon oxide) becomes too thin due to losses, it will cause problems with the penetration of metal and silicon electrons, which will seriously affect the performance of the image sensor chip.
[0003] To achieve through-silicon via (TSV) etching, the mainstream technology currently employs deep silicon trench etching equipment combined with pulsed plasma technology: 1) High-energy ion sources and radio frequency power modulation are used to ensure sufficient exposure of the bottom metal while reducing physical bombardment damage to the dielectric layer at the via opening; 2) During the etching process, passivating gas is used to form a protective layer to suppress excessive etching of the sidewalls. Through these methods, while ensuring sufficient bottom etching depth, the dielectric layer at the via opening is protected as much as possible, minimizing plasma damage and preventing excessive loss of the dielectric layer at the opening, which could lead to metal and silicon electron penetration and affect chip performance.
[0004] However, with the increasing complexity of sensor chip design, existing through-silicon via (TSV) etching processes have revealed new problems. For example, with the increasing integration of image sensor chips (such as multi-level TSV and trench coexistence designs), the simultaneous etching of TSVs and adjacent silicon trenches can trigger a significant loading effect. Specifically, this loading effect manifests as follows: due to density differences in the etched areas, high-density regions (such as dense trench arrays) consume excessive passivation gas, leading to a significant reduction in the passivation protection layer thickness at the aperture (<10nm under conventional processes). Consequently, the aperture dielectric layer 3 is more susceptible to accelerated wear due to continuous plasma bombardment. Figure 1bAs shown, an excessively thin dielectric layer at the orifice weakens its insulation performance, triggering an electron tunneling effect between the metal and the silicon substrate, leading to increased leakage current and degraded signal-to-noise ratio. Existing pulse parameters (such as duty cycle and frequency) are insufficient to balance etching depth and orifice dielectric layer integrity. To balance bottom etching depth and orifice protection, strict control of pulse timing and gas ratio is required, resulting in low process tolerance (<5%), insufficient yield stability, and a narrowed process window. Summary of the Invention
[0005] The purpose of this invention is to provide a novel etching process for effectively protecting silicon oxide at the aperture in high-load-effect scenarios. By improving the process steps, selecting different etching gases, and implementing multiple measures such as radio frequency power control, plasma damage control of the dielectric layer at the aperture is achieved in the high aspect ratio through-silicon via (TSV) etching process. This avoids the problem that the protective layer of the dielectric layer at the aperture is too thin to form effective protection, resulting in the risk of electron penetration at the aperture and a narrow process window.
[0006] To achieve the above objectives, the present invention provides a method for manufacturing a back-illuminated image sensor, comprising:
[0007] Step 1: Provide a semiconductor structure comprising a plurality of through-silicon vias for connecting a metal filling layer below its bottom, wherein a first dielectric layer and a second dielectric layer are sequentially deposited on the bottom, sidewalls and top corner surfaces of the through-silicon vias;
[0008] Step 2: Using a first etching gas, the second dielectric layer at the bottom of the through-silicon via (TSV) is etched away to expose the first dielectric layer at the bottom of the TSV, while at least partially retaining the second dielectric layer on the sidewalls and top corner surfaces of the TSV.
[0009] Step 3: Using a second etching gas and the remaining second dielectric layer as a mask, the first dielectric layer at the bottom of the through-silicon via is etched away to expose the metal filling layer;
[0010] Step 4: Use a first etching gas to etch and remove the retained second dielectric layer.
[0011] Optionally, the second dielectric layer is a silicon nitride layer.
[0012] Optionally, the first etching gas contains C x H y F z A gas, wherein x > 0, y > 0, z > 0.
[0013] Optionally, the first etching gas contains at least one of CH2F2, CH3F, and CHF3.
[0014] Optionally, in step 2, the HF radio frequency power is 800W to 1500W, and the LF radio frequency power is 200W to 300W.
[0015] Optionally, the first dielectric layer is a silicon oxide layer.
[0016] Optionally, the second etching gas contains C m F n Gas, m>0, n>0.
[0017] Optionally, the second etching gas contains at least one of C4F6 and C4F8.
[0018] Optionally, in step 3, the HF radio frequency power is 1800W to 2000W, and the LF radio frequency power is 1500W to 3000W.
[0019] Optionally, in step 3, the LF radio frequency power is applied using a pulse signal control.
[0020] Optionally, the duty cycle of the pulse signal is 30% to 70%.
[0021] Optionally, in step 4, the HF radio frequency power is 400W to 750W, and the LF radio frequency power is 100W to 150W.
[0022] Optionally, the process temperature is 60℃~150℃.
[0023] Optionally, the aspect ratio of the through-silicon via is greater than or equal to 3:1.
[0024] Optionally, a third dielectric layer is further provided on the metal filler layer, which is located below the first dielectric layer at the bottom of the through silicon via, for protecting the metal filler layer.
[0025] Optionally, the third dielectric layer is made of the same material as the first dielectric layer.
[0026] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects:
[0027] This invention employs a three-step process to progressively etch and open the second dielectric layer and the first dielectric layer at the bottom of a through-silicon via (TSV), exposing the bottom metal filling layer. The dielectric layer at the via opening remains undamaged under the protection of the second dielectric layer, thus avoiding the risk of electron penetration through the via opening. Specifically, a first etching gas is used to etch and remove the second dielectric layer at the bottom of the TSV, while at least partially retaining the second dielectric layer on the sidewalls and the upper surface of the top corner of the TSV. This retained second dielectric layer serves as a protective layer for the via opening dielectric layer (first dielectric layer), preventing damage to the via opening dielectric layer under continuous plasma bombardment. Then, a second etching gas is used to etch and remove the first dielectric layer at the bottom of the TSV, exposing the metal filling layer. The second etching gas has a selectivity ratio for the first and second dielectric layers, preferentially etching the first dielectric layer, thus minimally affecting the thickness of the protective layer of the via opening dielectric layer when opening the first dielectric layer at the bottom of the TSV. Finally, the first etching gas is used again to etch and remove the retained second dielectric layer, i.e., to remove the protective layer of the via opening dielectric layer.
[0028] Furthermore, the present invention selects etching gases with different etching selectivity ratios and different HF and / or LF radio frequency powers by different steps to achieve a balance between bottom etching depth and orifice protection, resulting in a wider process window. Attached Figure Description
[0029] Figure 1a This is a cross-sectional view of the through-silicon via (TSV) required by the manufacturing process.
[0030] Figure 1b A cross-sectional view of a through-silicon via (TSV) fabricated using conventional processes.
[0031] Figure 2 This is a cross-sectional schematic diagram of a through-silicon via (TSV) in a prior art process, where a represents a cross-sectional view of the TSV to be processed, b represents a cross-sectional view of the TSV after the first etching step, and c represents a cross-sectional view of the TSV after the second etching step.
[0032] Figure 3 This is a process flow diagram of a method for manufacturing a back-illuminated image sensor according to the present invention.
[0033] Figure 4 This is a cross-sectional schematic diagram of a through-silicon via (TSV) in the manufacturing process of a back-illuminated image sensor according to the present invention. In the diagram, a represents a cross-sectional view of the TSV to be processed, b represents a cross-sectional view of the TSV after etching in step S2, c represents a cross-sectional view of the TSV after etching in step S3, and d represents a cross-sectional view of the TSV after etching in step S4.
[0034] Attached image labels:
[0035] Through-silicon vias 1 and 10
[0036] Orifice medium layer 3
[0037] First dielectric layer 11
[0038] Second dielectric layer 12, 12', 12"
[0039] Silicon substrate layer 20
[0040] Metal layer 21
[0041] Metal filler layers 2 and 30. Detailed Implementation
[0042] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0043] In the description of this invention, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0044] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0045] The “orifice dielectric layer” mentioned in this article refers to the first dielectric layer covering the orifice of the through-silicon via, and its material can be silicon oxide.
[0046] As described in the background section, during simultaneous etching of through-silicon vias (TSVs) and silicon trenches, the loading effect causes the dielectric layer at the via opening to become increasingly thin, thus failing to effectively block the penetration of tungsten and silicon electrons. This, in turn, affects the performance of back-illuminated CMOS image sensor chips, reducing their reliability and stability. Existing technologies cannot achieve uniform protection of the dielectric layer at the via opening in highly complex chip structures (such as simultaneous etching of TSVs and trenches with different feature structures).
[0047] like Figure 2 The image shown is a cross-sectional schematic diagram of a through-silicon via (TSV) in a prior art process. Figure 2 As shown in Figure a, a first dielectric layer 11 and a second dielectric layer 12 are sequentially deposited on the bottom, sidewalls, and top corner surface of the through-silicon via 10 to be processed. The etching target is to expose the metal filling layer 30 at the bottom. As an example, the first dielectric layer 11 is a silicon oxide layer. The second dielectric layer 12 is a silicon nitride layer. The prior art uses a two-step method: the first step is to etch away the second dielectric layer 12 (silicon nitride) on the surface, such as... Figure 2 As shown in b, the second dielectric layer 12 is completely removed; in the second step, pulsed plasma technology is used to selectively etch the first dielectric layer 11 (such as silicon oxide) at the bottom of the silicon via, exposing the bottom metal filling layer 30. However, in this step, even with strict control of pulse timing and RF power, the via dielectric layer 3 will inevitably become thinner due to wear, such as... Figure 2 As shown in Figure c, if the dielectric layer 3 at the aperture is too thin, it will weaken its insulation performance, trigger the electron tunneling effect between the metal and the silicon substrate, resulting in increased leakage current and deterioration of the signal-to-noise ratio.
[0048] The main reason for the above problems is that, with the increasing complexity of sensor chip design and the growing number of structures and functional units on the chip, the loading effect during the etching process becomes more significant when simultaneously etching silicon vias and trenches with different feature structures. On the one hand, while high-energy ion bombardment achieves deep silicon etching, it also exacerbates the physical sputtering loss of silicon oxide at the via opening. During simultaneous etching, the energy distribution of the plasma on high aspect ratio vias and shallow trenches is uneven. The area at the via opening is more susceptible to ion bombardment due to the concentrated electric field, resulting in over-etching of the silicon oxide protective layer at the via opening, which gradually thins. On the other hand, the coverage capability of traditional passivation gases on complex surface structures is insufficient, and the gas transport efficiency of traditional pulsed plasma processes is limited by high aspect ratio structures. It is difficult for passivation gases to uniformly cover densely etched areas, leading to localized thinning of the protective layer.
[0049] To address this, the present invention improves the process steps by employing a three-step method, where the etching gas and radio frequency power are changed at each step according to the process objective: First, an etching gas that preferentially etches the second dielectric layer is used. By controlling the radio frequency power, the second dielectric layer at the bottom of the via is selectively removed, while the second dielectric layer on the sidewalls and top corners of the via is retained, thus protecting the via opening dielectric layer (first dielectric layer). Second, an etching gas that preferentially etches the first dielectric layer is used, and the radio frequency power is controlled to selectively remove the first dielectric layer at the bottom of the via, while the second dielectric layer on the sidewalls and top corners of the via is almost undamaged. Third, an etching gas that preferentially etches the second dielectric layer is selected, and the radio frequency power is controlled to selectively remove the remaining second dielectric layer, ensuring that the via opening dielectric layer is almost undamaged, thus avoiding the risk of electron penetration through the via opening.
[0050] like Figure 3 As shown, the present invention provides a method for manufacturing a back-illuminated image sensor, comprising:
[0051] Step S1: A semiconductor structure is provided, which includes a plurality of through-silicon vias for connecting a metal filling layer below its bottom. A first dielectric layer and a second dielectric layer are sequentially deposited on the bottom, sidewalls and top corner surfaces of the through-silicon vias.
[0052] See Figure 4 Figure 'a' is a partial schematic diagram of a wafer bonding structure, showing only a cross-sectional view of a through-silicon via (TSV) to be processed. The TSV 10 is formed by etching a silicon substrate layer 20 and connects to the underlying metal fill layer 30. A first dielectric layer 11 and a second dielectric layer 12 are sequentially deposited on the bottom, sidewalls, and top corner surface of the TSV 10. As an example, the first dielectric layer 11 is a silicon oxide layer. The second dielectric layer 12 is a silicon nitride layer. In some embodiments, a metal layer 21 is also disposed on the surface of the silicon substrate 20. The first dielectric layer 11 covers the metal layer 21, forming an isolation and protection.
[0053] Step S2: Using a first etching gas, the second dielectric layer at the bottom of the through-silicon via (TSV) is etched away to expose the first dielectric layer at the bottom of the TSV, while at least partially retaining the second dielectric layer on the sidewalls and top corner surfaces of the TSV.
[0054] One objective of the etching process in step S2 is to remove the second dielectric layer 12 at the bottom of the through-silicon via. For this purpose, a suitable first etching gas can be selected based on the material of the second dielectric layer 12. For example, when the second dielectric layer 12 is silicon nitride, the first etching gas contains C. x H y F z The first etching gas (a hydrocarbon gas) wherein x > 0, y > 0, z > 0. As an example, the first etching gas contains at least one of CH2F2, CH3F, and CHF3.
[0055] Another objective of the etching process in step S2 is to preserve the second dielectric layer 12 on the sidewalls and top corner surface of the through-silicon via (TSV). To achieve this, the source RF (HF) power and bias RF (LF) power settings are designed to control the first etching gas to penetrate as much as possible into the bottom of the TSV 10, maximizing vertical etching while minimizing lateral etching. In this example, the HF RF power is 800W–1500W, and the LF RF power is 200W–300W.
[0056] See Figure 4In step S2, during the etching process to form the through-silicon via 10, the bottom second dielectric layer 12 is completely etched to facilitate further selective etching of the bottom first dielectric layer 11, thereby connecting to the underlying metal filler layer 30. The second dielectric layer 12 on the sidewalls and top corners of the through-silicon via 10 is partially etched, leaving a thin layer as the second dielectric layer 12'. The second dielectric layer 12' acts as a protective shield for the first dielectric layer 11 it covers. As a protective layer for the via opening dielectric layer (the first dielectric layer covering the via opening), the second dielectric layer 12' is unaffected by the load effect and effectively protects the via opening dielectric layer from continuous plasma bombardment and wear.
[0057] Step S3: Using a second etching gas and the remaining second dielectric layer as a mask, the first dielectric layer at the bottom of the through-silicon via is etched away to expose the metal filling layer.
[0058] The purpose of step S3 is to etch the first dielectric layer 11 at the bottom of the through-silicon via (TSV) to expose the metal filling layer. During the etching process, it is necessary to avoid loss of the dielectric layer at the TSV opening. Therefore, the second etching gas should preferably be selected to have a certain selectivity ratio for the materials of the first dielectric layer 11 and the second dielectric layer 12. That is, the second etching gas should preferentially react with the material of the first dielectric layer 11 and react less or almost no with the material of the second dielectric layer 12. Thus, the second dielectric layer 12' covering the surface of the first dielectric layer 11 acts as a shield, preventing the first dielectric layer 11 (the opening dielectric layer) at the opening from being lost. Since fluorocarbon gas has a selectivity ratio relative to silicon oxide (SiO2) / silicon nitride (SiN), in this example, to preferentially etch the first dielectric layer 11 (material SiO2), the second etching gas contains C... m F n The gas (fluorocarbon gas), m > 0, n > 0. As an example, the second etching gas may contain at least one of C4F6 and C4F8. Since the present invention uses the retained second dielectric layer 12' as a protective layer (mask), the etching process in step S3 does not require the addition of passivation gas, thus avoiding the problem of uneven protective layer formation caused by the loading effect.
[0059] like Figure 4As shown in Figure c, in step S3, the first dielectric layer 11 is longitudinally etched at the bottom of the through-silicon via 10, exposing the metal filling layer 30. The sidewalls and top corners of the through-silicon via 30 are still covered by the second dielectric layer 12". After etching in step S3, the second dielectric layer 12" is thinner than the second dielectric layer 12' etched in step S2. Since the second dielectric layer 12" needs to be etched away in the next step, the source RF (HF) power and bias RF (LF) power settings need to balance efficiently opening the first dielectric layer 11 at the bottom of the through-silicon via while maintaining a suitable thickness for the second dielectric layer 12". The suitable thickness means that the thickness of the second dielectric layer 12" can effectively protect the first dielectric layer 11 it covers, but it does not need to be too thick; otherwise, it will affect the efficiency of subsequent etching to remove the second dielectric layer 12". As an example, in step 3, the HF RF power is 1800W to 2000W, and the LF RF power is 1500W to 3000W. In other embodiments, a pulse signal is used to control the application of LF radio frequency power, making the etching process in step S3 more precise and efficient, leaving no dead corners and ensuring a vertical etching profile. As an example, the duty cycle of the pulse signal is 30% to 70%.
[0060] Step S4: Use a first etching gas to etch and remove the retained second dielectric layer.
[0061] The purpose of step S4 is to completely remove the second dielectric layer 12” covering the surface of the through-silicon via 10, exposing the first dielectric layer 11 on the sidewalls and top corner surface of the through-silicon via. For this purpose, the etching gas needs to be selected based on the material of the second dielectric layer 12”. In this example, a hydrocarbon gas can be selected. Since the material of the second dielectric layer 12” removed in step S4 is the same as the material of the second dielectric layer 12 removed in step 2, the etching gas used in step S4 can be the same as in step S2, i.e., the first etching gas can be used. The first etching gas generally has a certain selectivity ratio relative to the second dielectric layer / first dielectric layer, and can preferentially etch the material of the second dielectric layer.
[0062] Another objective of step S4 is to ensure that the first dielectric layer 11 at the aperture is not damaged or is damaged as little as possible. This is achieved in this application through source radio frequency (HF) power and bias radio frequency (LF) power control. In this example, the HF radio frequency power is 400W to 750W, and the LF radio frequency power is 100W to 150W.
[0063] like Figure 4 As shown in d, after removing the second dielectric layer 12” in step S4, the orifice dielectric layer 3 is almost undamaged.
[0064] In some embodiments, the process temperature of the method of the present invention is 60°C to 150°C.
[0065] In some embodiments, a third dielectric layer is further provided on the metal filler layer, located below the first dielectric layer at the bottom of the through-silicon via, to protect the metal filler layer. In some embodiments, the third dielectric layer is made of the same material as the first dielectric layer.
[0066] The method of the present invention is particularly suitable for etching processes that require opening the bottom of a through-silicon via with a high aspect ratio without damaging the dielectric layer at the orifice. It can result in a wider process window and higher product yield. The aspect ratio of the through-silicon via is greater than or equal to 3:1, but is not limited thereto.
[0067] In summary, this invention employs a three-step etching method: First, the second dielectric layer at the bottom of the via is selectively etched, leaving the second dielectric layer on the sidewalls and top corners of the via as a protective layer for the next etching step, effectively protecting the dielectric layer at the via opening and preventing loss. In the second etching step, the first dielectric layer at the bottom of the via is selectively etched to expose the underlying metal filler layer. Finally, the remaining second dielectric layer is selectively etched away. This invention, through improved process steps and the selection of process gases and RF power for different steps, synergistically achieves the goal of opening the bottom of the via without damaging the dielectric layer at the via opening, avoiding the risk of electron penetration at the via opening, and providing a wider process window.
[0068] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims
1. A method for manufacturing a back-illuminated image sensor, characterized in that, Include: Step 1: Provide a semiconductor structure comprising a plurality of through-silicon vias for connecting a metal filling layer below its bottom, wherein a first dielectric layer and a second dielectric layer are sequentially deposited on the bottom, sidewalls and top corner surfaces of the through-silicon vias; Step 2: Using a first etching gas, the second dielectric layer at the bottom of the through-silicon via (TSV) is etched away to expose the first dielectric layer at the bottom of the TSV, while at least partially retaining the second dielectric layer on the sidewalls and top corner surfaces of the TSV. Step 3: Using a second etching gas and the remaining second dielectric layer as a mask, the first dielectric layer at the bottom of the through-silicon via is etched away to expose the metal filling layer; Step 4: Use a first etching gas to etch and remove the retained second dielectric layer.
2. The method for manufacturing a back-illuminated image sensor as described in claim 1, characterized in that, The second dielectric layer is a silicon nitride layer.
3. The method for manufacturing a back-illuminated image sensor as described in claim 2, characterized in that, The first etching gas contains C x H y F z A gas, wherein x > 0, y > 0, z > 0.
4. The method for manufacturing a back-illuminated image sensor as described in claim 3, characterized in that, The first etching gas contains at least one of CH2F2, CH3F, and CHF3.
5. The method for manufacturing a back-illuminated image sensor as described in claim 1, characterized in that, In step 2, the HF radio frequency power is 800W to 1500W, and the LF radio frequency power is 200W to 300W.
6. The method for manufacturing a back-illuminated image sensor as described in claim 1, characterized in that, The first dielectric layer is a silicon oxide layer.
7. The method for manufacturing a back-illuminated image sensor as described in claim 6, characterized in that, The second etching gas contains C m F n Gas, m>0, n>0.
8. The method for manufacturing a back-illuminated image sensor as described in claim 7, characterized in that, The second etching gas contains at least one of C4F6 and C4F8.
9. The method for manufacturing a back-illuminated image sensor as described in claim 1, characterized in that, In step 3, the HF radio frequency power is 1800W to 2000W, and the LF radio frequency power is 1500W to 3000W.
10. The method for manufacturing a back-illuminated image sensor as described in claim 9, characterized in that, In step 3, pulse signals are used to control the application of LF radio frequency power.
11. The method for manufacturing a back-illuminated image sensor as described in claim 10, characterized in that, The duty cycle of the pulse signal is 30% to 70%.
12. The method for manufacturing a back-illuminated image sensor as described in claim 1, characterized in that, In step 4, the HF radio frequency power is 400W to 750W, and the LF radio frequency power is 100W to 150W.
13. The method for manufacturing a back-illuminated image sensor as described in claim 1, characterized in that, The process temperature is 60℃~150℃.
14. The method for manufacturing a back-illuminated image sensor as described in claim 1, characterized in that, The aspect ratio of the through-silicon via is greater than or equal to 3:
1.
15. A method for manufacturing a back-illuminated image sensor as described in any one of claims 1-14, characterized in that, A third dielectric layer is also provided on the metal filler layer, which is located below the first dielectric layer at the bottom of the through silicon via, and is used to protect the metal filler layer.
16. The method for manufacturing a back-illuminated image sensor as described in claim 15, characterized in that, The third dielectric layer is made of the same material as the first dielectric layer.