Image sensor pixel, method of forming an image sensor, and image sensor

Abstract

This application relates to an image sensor pixel, a method of forming an image sensor, and an image sensor. The image sensor pixel may include one or more stepped-shielded vertical transfer gates that transfer charge generated by a photodiode to a floating diffusion region. The stepped-shielded vertical transfer gate may include a first portion having a first gate oxide thickness and a second portion having a second gate oxide thickness less than the first thickness. The first portion may be interposed between the photodiode and the second portion. Due to the difference in gate oxide thickness, the first portion may have a higher threshold voltage (Vt) than the second portion. This difference in Vt may guide charge from the photodiode to the floating diffusion region and may reduce or prevent charge overflow back into the photodiode when the stepped-shielded vertical transfer gate is turned off. The stepped-shielded vertical transfer gate may extend partially or completely through the substrate of the image sensor pixel.

Description

Cross-reference to related applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 774,501, filed March 19, 2025, and U.S. Patent Application No. 19 / 444,062, filed January 8, 2026, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates generally to imaging devices, and more specifically to image sensor pixels, methods for forming image sensors, and image sensors. Background Technology

[0003] Image sensors are commonly used in electronic devices such as mobile phones, cameras, and computers and / or other systems to capture images. In a typical arrangement, an image sensor has an array of image pixels arranged in rows and columns.

[0004] Conventional image sensors may include pixels with photodiodes and transfer gates to transfer charge generated by the photodiodes. However, these transfer gates may transfer charge slowly and / or incompletely, and / or the transfer gates may result in a large pixel footprint. For example, when the transfer gate is turned off, charge may overflow from the transfer gate back into the photodiode, resulting in incomplete charge transfer.

[0005] The implementation scheme described in this article emerged in this context. Summary of the Invention

[0006] In a first aspect, an image sensor pixel is provided, the image sensor pixel comprising: a floating diffusion region; a photodiode; and a stepped-shielded vertical transfer gate configured to selectively transfer charge from the photodiode to the floating diffusion region.

[0007] In a second aspect, a method for forming an image sensor is provided, the method comprising: etching grooves in a substrate; applying an oxide having a first thickness to the substrate; filling the grooves of the substrate with a material; etching and curing the material; etching the oxide into each groove of the grooves to a certain distance; and applying an additional oxide having a second thickness to the substrate to form a stepped-shielded vertical transfer gate in the substrate.

[0008] In a third aspect, an image sensor is provided, comprising: a floating diffusion region; a photodiode overlapped by the floating diffusion region; and a first vertical transfer gate and a second vertical transfer gate configured to selectively transfer charge from the photodiode to the floating diffusion region, wherein the first vertical transfer gate and the second vertical transfer gate include a first portion having a first threshold voltage and a second portion having a second threshold voltage less than the first threshold voltage. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of an exemplary electronic device having an image sensor according to some embodiments, the image sensor including a vertical transfer gate.

[0010] Figure 2 This is a diagram of an exemplary pixel with a stepped-shielded vertical transfer gate according to some implementation schemes.

[0011] Figure 3 It is an illustrative circuit diagram of pixels based on some implementation schemes.

[0012] Figures 4A to 4E This is a diagram illustrating exemplary method steps for forming pixels with stepped-shielded vertical transfer gates, according to some implementation schemes.

[0013] Figure 5 This is a diagram of an exemplary pixel with a deep trench stepped shielded vertical transfer gate according to some implementation schemes. Detailed Implementation

[0014] Implementations of this technology relate to an image sensor having image sensor pixels with vertical transfer gates. Specifically, the image sensor pixel may include a stepped-shielded vertical transfer gate having multiple regions, each region having a different gate oxide thickness, to generate a threshold voltage (Vt) difference across the transfer gate. The Vt difference can increase the rate of charge transfer between the pixel's photodiode and the pixel's floating diffusion region, and also prevent charge backflow when the transfer gate is turned off due to the internal potential difference of the transfer gate.

[0015] Image sensor pixels with stepped-shielded vertical transfer gates can be integrated into any suitable imaging device. Figure 1 An exemplary electronic device with an image sensor is shown, in which image sensor pixels with stepped-shielded vertical transfer gates can be incorporated.

[0016] Figure 1The electronic device 10 (sometimes referred to as an imaging system or imaging device) may be a digital camera, computer, mobile phone, medical device, or other electronic device. Additionally or alternatively, the electronic device 10 may be part of a broader system and / or integrated into a broader system, such as a vehicle or building.

[0017] Camera module 12 (sometimes referred to as imaging module) may include one or more image sensors 14 and one or more lenses 28. During operation, lens 28 may focus light onto image sensor 14. Image sensor 14 includes photosensitive elements (e.g., pixels) that convert light into digital data. For example, each pixel may include a photodiode that generates an electric charge (e.g., photocurrent) in response to incident light, and the generated charge may be converted into digital data using the pixels and / or circuitry in camera module 12.

[0018] Image sensors can have any number (e.g., hundreds, thousands, millions, or more) of pixels. A typical image sensor may have, for example, millions of pixels (e.g., megapixels) arranged in an array (such as a two-dimensional pixel array). Additionally, image sensor 14 may include bias circuitry (e.g., source follower load circuitry), sample-and-hold circuitry, correlated double sampling (CDS) circuitry, amplifier circuitry, analog-to-digital (ADC) converter circuitry, data output circuitry, memory (e.g., buffer circuitry), address circuitry, etc., which can be used to generate image data in response to the charge generated by a photodiode.

[0019] Still and video image data from image sensor 14 can be provided to image processing and data formatting circuitry 16 via path 26, for example. Image processing and data formatting circuitry 16 can be used to perform image processing functions such as autofocus, depth sensing, data formatting, white balance and exposure adjustment, video image stabilization, face detection, etc. For example, during autofocus operation, image processing and data formatting circuitry 16 can process data collected by the three-dimensional imaging pixels in image sensor 14 to determine the magnitude and direction of the lens movement (e.g., movement of lens 28) required to bring the object of interest into focus.

[0020] The image processing and data formatting circuitry 16 can also be used to compress raw camera image files when needed, such as compressing them to the Joint Image Experts Group (JPEG) format. In a typical arrangement (sometimes referred to as a system-on-a-chip (SOC) arrangement), the image sensor 14 and the image processing and data formatting circuitry 16 are implemented on a common integrated circuit. Using a single integrated circuit to implement the image sensor 14 and the image processing and data formatting circuitry 16 can help reduce costs. However, this is merely illustrative. If desired, the image sensor 14 and the image processing and data formatting circuitry 16 can be implemented using separate integrated circuits. For example, the image sensor 14 and the image processing and data formatting circuitry 16 can be formed using separate integrated circuits stacked relative to each other (e.g., vertically stacked).

[0021] Camera module 12 can transmit acquired image data to host subsystem 20 via path 18. In other words, image processing and data formatting circuitry 16 can transmit image data to subsystem 20 via path 18. Electronic device 10 typically provides users with numerous advanced functions. For example, in a computer or mobile phone, it may provide the user with the ability to run user applications. To implement these functions, host subsystem 20 of electronic device 10 may include storage and processing circuitry 24 and input / output devices 22, such as keypad, keyboard, touchpad, mouse, input / output ports, joystick, and display. Input / output devices 22 may also include light sources such as light-emitting diodes (LEDs), which can be used in conjunction with image sensor 14 to obtain time-of-flight depth sensing information. Input / output devices 22 may include light sources that emit, for example, visible or infrared light.

[0022] The storage and processing circuitry 24 may include volatile and non-volatile memory (such as random access memory, flash memory, hard disk drive, solid-state drive, etc.). The storage and processing circuitry 24 may also include a microprocessor, microcontroller, digital signal processor, application-specific integrated circuit (ASIC), or other processing circuitry.

[0023] Each pixel of the image sensor 14 may include: a photodiode that generates charge in response to light incident on it; and a floating diffusion (FD) region. The FD region may then be coupled to readout circuitry within the pixel. Thus, in operation, the charge generated by the photodiode is transferred to the FD region.

[0024] In some implementations, it may be desirable to include a vertical transfer gate that transfers charge from the photodiode to the FD region. Specifically, the vertical transfer gate may reduce the size of each pixel (e.g., lateral footprint), and the vertical transfer gate may be designed to direct the charge generated by the photodiode to the FD while preventing overflow back to the photodiode when the vertical transfer gate is turned off. Therefore, a stepped-shielded vertical transfer gate with portions having different gate oxide thicknesses can be used. Figure 2 An illustrative example of an image sensor pixel with a stepped-shielded vertical transfer gate is shown.

[0025] like Figure 2 As shown, it can be included in image sensors (such as...) Figure 1 The pixel 200 in the image sensor 14) may include a substrate 202. The substrate 202 may be formed of a dielectric material such as silicon or another suitable semiconductor material.

[0026] The photodiode 204 may be formed in the substrate 202. The photodiode 204 may include a doped portion of the substrate 202 (e.g., a P-type doped portion and / or an N-type doped portion of a silicon substrate) and / or may contain other materials, such as doped epitaxial materials.

[0027] A floating diffusion (FD) region 208 surrounded by a P-well 209 may be formed on a surface of the substrate 202 (such as surface 211). The FD region 208 may overlap with a photodiode 204. In other words, the photodiode 204 may be overlapped with the FD region 208.

[0028] exist Figure 2 In this example, pixel 200 is a back-illuminated (BSI) image sensor pixel, and surface 211 is the front surface of substrate 202. However, this is merely illustrative. In some embodiments, the pixel may be a front-illuminated image sensor pixel, and FD region 208 may be formed on the rear surface of the substrate.

[0029] Trench 206 separates pixel 200 from adjacent pixels within the image sensor. Trench 206 can be formed of a dielectric material such as oxide. Figure 2 In the example, trench 206 is a deep trench isolation (DTI) trench extending from the rear surface 207 to the front surface 211. However, this is merely illustrative. In some embodiments, trench 206 may extend partially within substrate 202. Regardless of how far trench 206 extends within substrate 202, in some embodiments, trench 206 may be biased to reduce or prevent crosstalk between adjacent pixels of the image sensor.

[0030] Pixel 200 may include a vertical transfer gate 210 (e.g., a first vertical transfer gate and a second vertical transfer gate 210) interposed between photodiode 204 and FD region 208. Each vertical transfer gate 210 may comprise a gate oxide 212 and a semiconductor material 214. The gate oxide 212 may be formed of silicon dioxide or another suitable material. The semiconductor material 214 may be formed of polysilicon or another suitable material.

[0031] exist Figure 2 In the example, both vertical transfer gates 210 are stepped-shielded vertical transfer gates. Therefore, the vertical transfer gate 210 may be referred to herein as a stepped-shielded vertical transfer gate. Specifically, each stepped-shielded vertical transfer gate 210 has a first portion 210A and a second portion 210B. The first portion 210A of each vertical transfer gate 210 is interposed between the photodiode 204 and the second portion 210B of the vertical transfer gate 210.

[0032] The first portion 210A may have a first gate oxide thickness T1, and the second portion 210B may have a second gate oxide thickness T2. The first gate oxide thickness T1 may be, for example, at least 400 angstroms, at least 600 angstroms, at least 1000 angstroms, at least 1500 angstroms, between 500 angstroms and 2000 angstroms, less than 2000 angstroms, or another suitable thickness. The second gate oxide thickness T2 may be, for example, less than 400 angstroms, less than 300 angstroms, between 100 angstroms and 300 angstroms, at least 200 angstroms, at least 25 angstroms, at least 50 angstroms, or another suitable thickness. Generally, the first gate oxide thickness T1 may be greater than the second gate oxide thickness T2. Specifically, by forming a first portion 210A having a gate oxide thickness greater than that of the second portion 210B, the first portion 210A may have a first threshold voltage (Vt) higher than the second threshold voltage (Vt) of the second portion 210B.

[0033] The stepped-shielded transfer gate 210 may have a height H2, which may be at least 2 micrometers, at least 3 micrometers, between 1 and 4 micrometers, less than 5 micrometers, or another suitable height. The substrate 202 may have a height H1 of at least 6 micrometers, at least 8 micrometers, between 7 and 12 micrometers, or another suitable height. In some embodiments, the height H2 may be less than half the height H1. However, this is merely illustrative. If desired, the height H2 may be equal to or greater than half the height H1.

[0034] The second portion 210B may have a height H3, which may be less than 1 micrometer, less than 1.5 micrometers, between 0.5 micrometers and 1.5 micrometers, or another suitable height. In some embodiments, the height H3 of the second portion 210B may be less than half the height of the first portion 210A or less than one-third the height of the first portion (e.g., height H2 minus height H3). However, this is merely illustrative. The height H3 of the second portion 210B may be equal to or greater than half the height of the first portion 210A (e.g., height H2 minus height H3).

[0035] The first portion 210A may extend from the second portion 210B at an angle 216. The angle 216 may be at least 30°, at least 35°, 45°, between 35° and 55°, or another suitable angle. In some embodiments, the first portion 210A and the second portion 210B may have continuous gate oxide portions 212 and semiconductor material portions 214. In other words, the gate oxide 212 of the first portion 210A may be in physical contact with the gate oxide 212 of the second portion 210B, and the semiconductor material 214 of the first portion 210A may be in physical contact with the gate oxide 212 of the second portion 210B.

[0036] In operation, photodiode 204 can generate charge (e.g., photocurrent) in response to incident light 220. To transfer the generated charge to FD region 208, vertical transfer gate 210 can be turned on (e.g., using current bias). In response to vertical transfer gate 210 being turned on, the charge generated by photodiode 204 can move in direction 218 to FD region 208. Specifically, the charge generated along the interface between gate oxide 212 and substrate 202 (e.g., Si-SiO2 interface) can be directed in direction 218 toward FD region 208. In this way, when stepped-shielded vertical transfer gate 210 is turned on, stepped-shielded vertical transfer gate 210 can selectively transfer charge from photodiode to floating diffusion region in parallel with each other.

[0037] Because the first portion 210A has a thicker gate oxide 212 than the second portion 210B, the first portion 210A has a higher Vt than the second portion 210B. The Vt difference between the first portion 210A and the second portion 210B helps to direct charge toward the FD region 208 (e.g., due to the potential difference between the first portion 210A and the second portion 210B). Additionally, when the vertical transfer gate 210 is turned off, the Vt difference pushes the charge toward the FD region 208 due to the internal potential difference of the vertical transfer gate 210, thereby preventing charge backflow to the photodiode 204. In this way, the stepped-shielded vertical transfer gate 210 can direct the charge generated by the photodiode 204 toward the FD region 208 while preventing charge backflow to the photodiode 204. This improves the efficiency of complete charge transfer between the photodiode 204 and the FD region 208 and reduces image artifacts such as ghosting and hysteresis caused by incomplete charge transfer.

[0038] Although Figure 2 A pixel 200 with two stepped-shielded vertical transfer gates 210 is shown, but this is merely illustrative. In some embodiments, pixel 200 may include a single stepped-shielded vertical transfer gate 210 to direct the charge generated by photodiode 204 to FD region 208. For example, pixel 200 may have a single vertical transfer gate as a stepped-shielded vertical transfer gate, or pixel 200 may have a stepped-shielded vertical transfer gate and another non-stepped-shielded vertical transfer gate. Generally, any suitable number of stepped-shielded vertical transfer gates 210, other vertical transfer gates, and / or horizontal transfer gates may be incorporated into pixel 200.

[0039] In addition, although Figure 2 The diagram shows an FD region 208 formed on surface 211, but this is merely illustrative. In some embodiments, the FD region 208 may be formed within a portion of substrate 202 (e.g., embedded in a portion of the substrate), such as at surface 211.

[0040] Figure 3 An exemplary circuit diagram of pixel 200 is shown. (For example...) Figure 3 As shown, pixel 200 may have a photodiode PD204, which is connected via a transfer gate 210 (e.g., as shown in the figure). Figure 2The stepped-shielded vertical transfer gate (shown herein) is coupled to FD region 208 (also referred to herein as FD node 208). A reset transistor 304, controlled by signal RST, may be coupled between power line Vaapix 306 and FD node 208. A source follower transistor SF 308 may have a drain terminal coupled to power line Vaapix 306, a gate terminal shorted to FD node 208, and a source terminal coupled to pixel output line Pixout 312 via row select transistor 310 controlled by signal RS. The p-type terminal of photodiode PD 204 may (typically via a p-type structure) be shorted to ground power line Vss 302. This pixel circuit implementation is merely illustrative. In general, pixel 200 may include any number of photodiodes and / or storage diodes, any number of transfer gates (e.g., two stepped-shielded vertical transfer gates) and storage gates, and any number of associated readout / control circuitry.

[0041] Regardless of the arrangement of pixels (such as pixel 200), a pixel may include one or more stepped-masked vertical transfer gates, such as Figure 2 The stepped shielded vertical transfer gate 210. Figures 4A to 4E The illustration shows exemplary method steps that can be used to form a stepped-shielded vertical transfer gate.

[0042] like Figure 4A As shown, at step 400, the substrate 202 may be etched with a groove 402. The groove 402 may have a depth of 5 micrometers or less, 4 micrometers or less, 3 micrometers or less, between 1 micrometer and 6 micrometers, at least 2 micrometers, or into another suitable depth of the substrate 202. The substrate 202 may be a semiconductor substrate, such as a silicon substrate.

[0043] Oxide 404 may be applied to substrate 202 (including within recess 402). Oxide 404 may be a gate oxide, such as silicon dioxide or another suitable oxide. Oxide 404 may be applied at a first thickness, such as at least 400 angstroms, at least 600 angstroms, at least 1000 angstroms, at least 1500 angstroms, between 500 angstroms and 2000 angstroms, less than 2000 angstroms, or another suitable thickness.

[0044] After oxide 404 has been applied to substrate 202, Figure 4B At step 410, material 406 may be applied to substrate 202 (including in groove 402), covering the top of oxide 404. Material 406 may be a photoresist, such as an organic photoresist material, may be a polycrystalline silicon material, or may be another suitable material. Material 406 may be applied at a thickness of at least 3 micrometers, at least 2 micrometers, between 2 and 6 micrometers, less than 5 micrometers, or another suitable thickness.

[0045] After material 406 has been applied, Figure 4C At step 420, material 406 can be etched and cured. For example, material 406 can be etched from the upper surface of oxide 404 to a depth D1 of at least 0.5 micrometers, at least 0.7 micrometers, at least 0.85 micrometers, between 0.6 micrometers and 1 micrometer, less than 1.2 micrometers, or another suitable depth. After material 406 has been etched, it can be cured, for example, using a UV curing process.

[0046] Although Figure 4C A single etching of material 406 is shown, but this is merely illustrative. In some embodiments, material 406 may be etched multiple times. For example, material 406 may be etched onto the upper surface of oxide 404, cured, and then etched to depth D1. In general, material 406 may be etched any suitable number of times.

[0047] After material 406 has cured, Figure 4D At step 430, oxide 404 may be etched. For example, oxide 404 may be etched from surface 408 of substrate 202 to depth D2 in each recess of recess 402. Depth D2 may be less than 1 micrometer, less than 1.5 micrometers, between 0.5 micrometers and 1.5 micrometers, or another suitable depth. As an illustrative example, depth D2 may be less than half the distance into each recess (e.g., the depth of each recess in the recess).

[0048] After the 404 oxide has been etched, Figure 4E At step 440, material 406 may be stripped from substrate 202 / oxide 404, and additional oxide 404' may be deposited on oxide 404 / substrate 202. The additional oxide 404' may be deposited at a second thickness of less than 400 angstroms, less than 300 angstroms, between 100 and 300 angstroms, at least 200 angstroms, at least 25 angstroms, at least 50 angstroms, or another suitable thickness. As an illustrative example, the second thickness of the additional oxide 404' may be less than half or less than one-third of the first thickness of oxide 404.

[0049] The recess 402 may be filled with a semiconductor material, such as polysilicon, to form a stepped-shielded vertical transfer gate, such as... Figure 2The stepped-shielded vertical transfer gate 210. Specifically, the stepped-shielded vertical transfer gate will have a first portion formed of oxide 404 (plus additional oxide 404') and a second portion formed of additional oxide 404'. The first portion will have a gate oxide thickness that is thicker than that of the second portion. Therefore, the first portion will have a higher Vt than the second portion, thereby guiding charge from the underlying photodiode to the overlying FD region and preventing backflow when the vertical transfer gate is turned off.

[0050] Although Figures 4A to 4E The illustration shows two grooves etched into substrate 202 to form two stepped-masked vertical transfer gates, but this is merely illustrative. In some embodiments, more grooves may be etched into substrate 202 to form additional vertical transfer gates and / or other structures. If other structures are formed through the grooves, it is possible to... Figure 4D The groove may be masked before etching the oxide in step 430 and / or before any other suitable step.

[0051] exist Figure 2 and Figures 4A to 4E In the example, the stepped-shielded vertical transfer gate is shown as extending partially through the pixel substrate. However, this is merely illustrative. In some embodiments, the stepped-shielded vertical transfer gate may be a deep trench stepped-shielded vertical transfer gate. Figure 5 An illustrative example is shown.

[0052] like Figure 5 As shown, pixel 500 may include a substrate 502 having a rear surface 507 and a front surface 511, a photodiode 504, an FD region 508, and a P-well 509, which may correspond to respectively Figure 2 The substrate 202 has a rear surface 207 and a front surface 211, a photodiode 204, an FD region 208, and a P-well 209. In other words, each of these corresponding portions of pixel 500 can be formed by combining the above... Figure 2 The same material described by pixel 200 is formed and functions in the same way.

[0053] The deep trench stepped-shielded vertical transfer gate 510 extends from the rear surface 507 of the substrate 502 to the front surface 511 of the substrate 502. The deep trench stepped-shielded vertical transfer gate 510 may include a first portion 510A of gate oxide 512 having a first thickness and a second portion 510B of gate oxide 512 having a second thickness less than the first thickness. Therefore, when the deep trench stepped-shielded vertical transfer gate 510 is turned on, it can guide the charge generated by the photodiode 504 to the FD region 508 in direction 518, and can prevent charge from overflowing back into the photodiode 504 when the deep trench stepped-shielded vertical transfer gate 510 is turned off.

[0054] Semiconductor material 514 can fill the stepped-shielded vertical transfer gate 510 and can correspond to Figure 2 Semiconductor material 214.

[0055] Because the deep trench stepped-shielded vertical transfer gate 510 extends from the front surface 511 to the rear surface 507 of the substrate 502, the deep trench stepped-shielded vertical transfer gate 510 can isolate adjacent pixels within the image sensor, and additional deep trench structures can be omitted from pixel 500 (e.g., Figure 2 (Trench 206). To prevent crosstalk between adjacent pixels of the image sensor, the deep trench stepped-shielded vertical transfer gate 510 can be biased. In other words, in addition to biasing the deep trench stepped-shielded vertical transfer gate 510 to guide the charge generated from the photodiode 504 to the FD region 508, the deep trench stepped-shielded vertical transfer gate 510 can also be biased to prevent / reduce crosstalk between adjacent pixels.

[0056] Those skilled in the art will understand that exemplary embodiments of the present invention can be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail to avoid unnecessarily obscuring embodiments of the invention.

[0057] The above description is merely illustrative and various modifications can be made to the described implementation scheme. The above implementation scheme can be implemented individually or in any combination.

Claims

1. An image sensor pixel, the image sensor pixel comprising: Floating diffusion region; Photodiode; and A stepped-shielded vertical transfer gate is configured to selectively transfer charge from the photodiode to the floating diffusion region.

2. The image sensor pixel according to claim 1, wherein, The stepped-shielded vertical transfer gate includes a first portion having a first thickness and a second portion having a second thickness less than the first thickness.

3. The image sensor pixel according to claim 2, wherein, The stepped-shielded vertical transfer gate comprises a gate oxide, and the gate oxide has a first thickness in the first portion and a second thickness in the second portion.

4. The image sensor pixel according to claim 3, wherein, The first portion extends from the second portion and is inserted between the photodiode and the second portion.

5. The image sensor pixel according to claim 4, wherein, The first part has a first height, and the second part has a second height that is less than the first height.

6. The image sensor pixel according to claim 5, wherein, The second height is less than half the height of the first height.

7. The image sensor pixel according to claim 4, wherein, The stepped-shielded vertical transfer gate has a first threshold voltage at the first portion and a second threshold voltage at the second portion that is less than the first threshold voltage.

8. The image sensor pixel according to claim 1, wherein, The stepped-shielded vertical transfer gate is a first-step-shielded vertical transfer gate, and the image sensor pixel further includes: A second-step shielded vertical transfer gate is configured to selectively transfer charge from the photodiode to the floating diffusion region in parallel with the first-step shielded vertical transfer gate.

9. The image sensor pixel according to claim 8, wherein, The first stepped shielded vertical transfer gate and the second stepped shielded vertical transfer gate are deep trench stepped shielded vertical transfer gates.

10. The image sensor pixel according to claim 1, wherein, The photodiode and the stepped-shielded vertical transfer gate are formed in a substrate having a first height, and the stepped-shielded vertical transfer gate has a second height, which is less than half of the first height.

11. A method for forming an image sensor, the method comprising: Etch grooves in the substrate; An oxide having a first thickness is applied to the substrate; The grooves in the substrate are filled with material; Etch and cure the material; The oxide is etched into each of the grooves to a certain distance; as well as An additional oxide having a second thickness is applied to the substrate to form a stepped-shielded vertical transfer gate in the substrate.

12. The method according to claim 11, wherein, Etching the groove in the substrate includes etching the groove at a height less than half the height of the substrate.

13. The method according to claim 11, wherein, Applying the additional oxide having the second thickness includes applying the additional oxide having a thickness less than one-third of the first thickness.

14. The method according to claim 11, wherein, Etching the oxide into each of the grooves to the specified distance includes etching the oxide into each of the grooves to less than half of the specified distance.

15. The method according to claim 11, further comprising: At least some of the grooves in the grooves are masked before etching the oxide.

16. An image sensor, the image sensor comprising: Floating diffusion region; A photodiode, wherein the photodiode is overlapped by the floating diffusion region; and A first vertical transfer gate and a second vertical transfer gate, the first vertical transfer gate and the second vertical transfer gate being configured to selectively transfer charge from the photodiode to the floating diffusion region, wherein the first vertical transfer gate and the second vertical transfer gate include a first portion having a first threshold voltage and a second portion having a second threshold voltage less than the first threshold voltage.

17. The image sensor according to claim 16, wherein, The first portion has a first gate oxide thickness, and the second portion has a second gate oxide thickness that is less than the first gate oxide thickness.

18. The image sensor according to claim 17, wherein, The first vertical transfer gate and the second vertical transfer gate are interposed between the photodiode and the floating diffusion region.

19. The image sensor according to claim 18, wherein, The first part is inserted between the photodiode and the second part.

20. The image sensor according to claim 19, wherein, The first part has a first height, and the second part has a second height that is less than the first height.

Images