Image sensor and method of manufacturing the same

Abstract

The present disclosure relates to a kind of image sensor preparation method and image sensor, it relates to integrated circuit technical field, including: P-type substrate, and photodiode, buried gate and readout diode inlayed in substrate and sequentially distributed along the first direction parallel to substrate;Photodiode, readout diode are made in the same process step simultaneously;Photodiode, readout diode all include N-type epitaxial stack, P-type epitaxial layer sequentially stacked along the second direction away from substrate;Buried gate includes first control gate, channel layer and second control gate sequentially stacked along the second direction, and the bottom surface of channel layer is lower than the top surface of substrate.At least can improve the electronic transmission efficiency of image sensor.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to an image sensor and a method for fabricating the image sensor. Background Technology

[0002] The CMOS image sensor (CIS) is the core light-sensing element of a camera. Simply put, its function is to convert the light captured by the lens into a digital image that can be processed by electronic devices.

[0003] However, the electron transfer speed in traditional CMOS image sensors is relatively slow, which cannot meet the requirements. Therefore, improving the electron transfer efficiency in image sensors has become one of the urgent technical problems to be solved. Summary of the Invention

[0004] Therefore, it is necessary to provide an image sensor and an image sensor fabrication method to address the technical problem of slow electronic transmission speed in existing image sensors.

[0005] In a first aspect, this disclosure provides an image sensor, including a P-type substrate, and a photodiode, a buried gate, and a readout diode embedded in the substrate and sequentially distributed along a first direction parallel to the substrate.

[0006] Photodiodes and readout diodes are fabricated simultaneously in the same process steps.

[0007] Both the photodiode and the readout diode include N-type epitaxial layers and P-type epitaxial layers stacked sequentially along a second direction away from the substrate.

[0008] The buried gate includes a first control gate, a channel layer and a second control gate stacked sequentially along the second direction, wherein the bottom surface of the channel layer is lower than the top surface of the substrate.

[0009] In the above embodiments, a channel layer is added to the image sensor to form a superchannel, thereby improving electron transport efficiency. Furthermore, the bottom surface of the channel layer is lower than the top surface of the substrate to ensure that the channel layer can effectively transport electrons.

[0010] In some embodiments, the N-type epitaxial stack includes multiple sub-epitaxy layers stacked sequentially along a second direction, wherein adjacent sub-epitaxy layers include different Group 5 elements. This allows the multiple sub-epitaxy layers stacked in the N-type epitaxial stack to generate a concentration gradient within them after optical excitation, optimizing the transport path of photogenerated carriers, reducing the recombination rate during diffusion, and improving the quantum efficiency of photodiodes and readout diodes. Furthermore, since pentavalent elements have a higher atomic mass than silicon and lower mobility during epitaxial growth, resulting in uneven doping concentration in a single doped layer, growing pentavalent elements with different dopants multiple times can improve the uniformity of doping concentration in the pixel region.

[0011] In some embodiments, the channel layer covers the entire top surface of the first control gate. Complete coverage of the top surface by the channel layer ensures a uniform and flat potential along the entire transmission path, allowing all photogenerated electrons to flow unimpeded to the readout diode, improving charge transfer efficiency and fundamentally eliminating image retention.

[0012] In some embodiments, the photodiode and the readout diode are fabricated before the buried gate. This avoids damage to the buried gate during the formation of the photodiode and the readout diode.

[0013] In some embodiments, the top surface of the N-type epitaxial stack is not higher than the top surface of the substrate, which ensures that the photogenerated electrons collected by the N-type epitaxial stack can be transferred to the readout diode.

[0014] In some embodiments, the N-type epitaxial stack includes a first SiAs epitaxial layer, a SiP epitaxial layer, and a second SiAs epitaxial layer stacked sequentially along a second direction.

[0015] In some embodiments, the P-type epitaxial layer includes a SiIn epitaxial layer.

[0016] In some embodiments, the channel layer includes a SiGe epitaxial layer.

[0017] Secondly, this disclosure provides a method for fabricating an image sensor, including:

[0018] A P-type substrate is provided, the top surface of which includes a dummy gate;

[0019] A protective layer is formed covering the dummy gate and the top surface of the substrate;

[0020] The protective layer and substrate on both sides of the dummy gate are etched to form the first trench and the second trench, with the dummy gate located between the first trench and the second trench;

[0021] During the process of forming a photodiode in the first trench, a readout diode is formed in the second trench;

[0022] After depositing the passivation layer, the dummy gate and the substrate directly beneath it are etched away to form the gate trench;

[0023] A first control gate, a channel layer, and a second control gate are sequentially stacked in a second direction away from the substrate within a gate trench. The bottom surface of the channel layer is lower than the top surface of the substrate. The first control gate, the channel layer, and the second control gate are used to form a buried gate.

[0024] In some embodiments, forming a photodiode and a readout diode includes:

[0025] A first SiAs epitaxial layer is formed at the bottom of the first trench and the second trench using a selective epitaxial growth process;

[0026] A SiP epitaxial layer is formed on the top surface of the first SiAs epitaxial layer in the first trench and the second trench using a selective epitaxial growth process.

[0027] A second SiAs epitaxial layer is formed on the top surface of the SiP epitaxial layer in the first trench and the second trench using a selective epitaxial growth process.

[0028] A SiIn epitaxial layer is formed on the top surface of the second SiAs epitaxial layer using a selective epitaxial growth process; the first SiAs epitaxial layer, SiP epitaxial layer, second SiAs epitaxial layer, and SiIn epitaxial layer located on the first trench are used to form a photodiode, and the first SiAs epitaxial layer, SiP epitaxial layer, second SiAs epitaxial layer, and SiIn epitaxial layer located on the second trench are used to form a readout diode.

[0029] In some embodiments, forming a buried grid includes:

[0030] After forming a first gate dielectric layer on the inner surface of the gate trench, a first gate conductive layer is filled into the gate trench.

[0031] After etching back the first gate conductive layer and the first gate dielectric layer, a channel layer is grown inside and outside the gate trench, with the bottom surface of the channel layer being lower than the top surface of the substrate.

[0032] A second control gate is formed on the channel layer.

[0033] In some embodiments, forming the second control gate includes:

[0034] A second gate dielectric layer is epitaxially grown on the top surface of the channel layer;

[0035] A second gate conductive layer is deposited on the top surface of the second gate dielectric layer.

[0036] The image sensor and its fabrication method in this disclosure have the following unexpected technical effects:

[0037] By embedding a gate layer to create a superchannel, electron transport efficiency is improved. Furthermore, the bottom surface of the channel layer is lower than the top surface of the substrate to ensure that the channel layer can effectively transport electrons.

[0038] Furthermore, during the fabrication of the photodiode, the readout diode is fabricated simultaneously, eliminating the need for a separate fabrication step for the readout diode and reducing the complexity and cost of the fabrication process.

[0039] Furthermore, both the photodiode and the readout diode include N-type epitaxial layers and P-type epitaxial layers stacked sequentially along a second direction away from the substrate. That is, the photodiode and the readout diode are formed using an epitaxial growth process. Compared with the high-energy ion implantation used to form the photodiode and the floating diffusion region in the image sensor in a comparative embodiment, it is less likely to cause damage, thereby improving the electron transmission efficiency compared with the transmission gate in a comparative embodiment.

[0040] Furthermore, the photodiode comprises an N-type epitaxial layer and a P-type epitaxial layer forming a PN junction, achieving a low dark current and low noise "pinning" effect, which also determines the photosensitivity. The readout diode also comprises an N-type epitaxial layer and a P-type epitaxial layer forming a PN junction, thereby achieving high-sensitivity charge-to-voltage conversion compared to the floating diffusion region in the image sensor of a comparative embodiment. The photodiode and the readout diode form a perfect potential barrier, ensuring that electrons can be efficiently and cleanly transferred from the photodiode to the readout diode. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of the structure of an image sensor in a comparative embodiment;

[0043] Figure 2 This is a schematic flowchart of an image sensor fabrication method provided in one embodiment;

[0044] Figure 3 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a protective layer covering the dummy gate and the top surface of the substrate in step S20 of the image sensor fabrication method provided in one embodiment.

[0045] Figure 4 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after etching the protective layer and substrate on both sides of the dummy gate to form the first trench and the second trench in step S30 of the image sensor fabrication method provided in one embodiment.

[0046] Figure 5 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a readout diode in the second trench during step S40 of the image sensor fabrication method provided in one embodiment, in the process of forming a photodiode in the first trench.

[0047] Figure 6This is a schematic diagram of the longitudinal cross-section of the semiconductor structure obtained after depositing a passivation layer in step S50 of the image sensor fabrication method provided in one embodiment.

[0048] Figure 7 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after etching away the dummy gate and the substrate directly below it to form a gate trench in step S50 of the image sensor fabrication method provided in one embodiment;

[0049] Figure 8 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the first control gate in the gate trench in step S60 of the image sensor fabrication method provided in one embodiment;

[0050] Figure 9 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after etching back the first gate conductive layer and the first gate dielectric layer in an image sensor fabrication method provided in one embodiment.

[0051] Figure 10 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after step S60 of the image sensor fabrication method provided in one embodiment, in which a first control gate, a channel layer and a second control gate are sequentially stacked in the gate trench along the direction away from the substrate.

[0052] Figure 11 This is a schematic diagram of the structure of an image sensor provided in one embodiment.

[0053] Explanation of reference numerals in the attached figures:

[0054] 310. Substrate; 321. Protective layer; 322. Passivation layer; 330. Buried gate; 331. Dummy gate; 332. First gate dielectric layer; 333. First gate conductive layer; 334. Channel layer; 335. SiO2 layer; 336. HfO2 layer; 337. Second gate conductive layer; 341. First trench; 342. Second trench; 343. Gate trench; 350. Photodiode; 351. First SiAs epitaxial layer; 352. SiP epitaxial layer; 353. Second SiAs epitaxial layer; 354. SiIn epitaxial layer; 360. Readout diode; 200. Pixel circuit. Detailed Implementation

[0055] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0057] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0058] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0059] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0060] Embodiments of the invention are described herein with reference to longitudinal sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0061] In this embodiment, neglecting the flatness of the substrate surface, the direction parallel to the substrate surface is, for example, a first direction, and the stacking direction or the direction away from the substrate surface (the thickness direction of the substrate) is, for example, a second direction. In this embodiment, the first direction can be the ox direction, and the second direction can be the oz direction. The "longitudinal section" in this embodiment is perpendicular to the surface of the substrate.

[0062] Please refer to Figure 1 In a comparative embodiment of the CMOS image sensor, high-energy ion implantation is required in the front-end process to form the photodiode (PD) and floating diffusion region (FD), which causes damage and slows down the electron transport speed of the transfer gate (Tx). Figure 1 The use of ion implantation to form photodiodes and floating diffusion regions in image sensors is one of the reasons for low electron transport efficiency.

[0063] Please refer to Figure 2 In some embodiments, this application provides a method for fabricating an image sensor, comprising:

[0064] Step S10: Provide a P-type substrate, the top surface of which includes a dummy gate;

[0065] Step S20: A protective layer is formed covering the dummy gate and the top surface of the substrate;

[0066] Step S30: Etch the protective layer and substrate on both sides of the dummy gate to form a first trench and a second trench, with the dummy gate located between the first trench and the second trench;

[0067] In step S40, during the process of forming a photodiode in the first trench, a readout diode is formed in the second trench;

[0068] Step S50: After depositing the passivation layer, the dummy gate and the substrate directly below it are etched away to form a gate trench.

[0069] In step S60, a first control gate, a channel layer, and a second control gate are sequentially stacked in a second direction away from the substrate within the gate trench. The bottom surface of the channel layer is lower than the top surface of the substrate. The first control gate, the channel layer, and the second control gate are used to form a buried gate.

[0070] In the image sensor fabrication method of this disclosure, a gate-added channel layer is embedded to form a superchannel, thereby improving electron transport efficiency. Furthermore, the bottom surface of the channel layer is lower than the top surface of the substrate to ensure that the channel layer can effectively transport electrons.

[0071] Furthermore, during the fabrication of the photodiode, the readout diode is fabricated simultaneously, eliminating the need for a separate fabrication step for the readout diode and reducing the complexity and cost of the fabrication process.

[0072] Please refer to Figure 3 In step S10, a P-type substrate 310 is provided. The substrate 310 can be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate 310 can be a single-layer structure or a multi-layer structure. For example, the substrate 310 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates, or II / VI semiconductor substrates. Alternatively, for example, the substrate 310 can be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. In this embodiment, the substrate 310 is a P-type substrate, and boron (B) can be doped into the substrate 310 material. In addition, trivalent elements such as indium (In) and gallium (Ga) can also be used. The type of substrate 310 should not limit the scope of this disclosure.

[0073] The top surface of substrate 310 includes a dummy gate 331. The top surface of substrate 310 can refer to its back side, thus forming a back-side illuminated (BSI) CMOS image sensor. The dummy gate 331 on the top surface of substrate 310 can be made of polycrystalline silicon, amorphous silicon, silicon nitride, dielectric materials, or a composite stacked structure. The dummy gate material can be deposited on substrate 310 first, and then patterned and etched to form the dummy gate structure. The position of the dummy gate 331 on substrate 310 should correspond to the position of the buried gate formed later in substrate 310. This can be understood as the buried gate occupying positions directly above, below, or above the dummy gate 331. When the buried gate is formed later, the dummy gate 331 will be removed. The dummy gate 331, which temporarily exists on the substrate 310, can protect the substrate 310 below during the formation of the photodiode and the readout diode, and prevent the process of forming the photodiode and the readout diode from damaging the substrate 310 below the dummy gate 331.

[0074] Please continue to refer to this. Figure 3 In step S20, a protective layer 321 is formed covering the dummy gate 331 and the top surface of the substrate 310. The material of the protective layer 321 can be silicon nitride (SiN) or silicon dioxide (SiO2), or it can be a multilayer stacked structure, etc. The protective layer 321 can be formed by processes such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0075] Please refer to Figure 4 In step S30, the protective layer 321 and substrate 310 on both sides of the dummy gate 331 are etched to form a first trench 341 and a second trench 342, with the dummy gate 331 located between the first trench 341 and the second trench 342. Specifically, a photoresist layer can be spin-coated on top of the protective layer 321 first. Then, at the positions of the photodiode and readout diode on both sides of the dummy gate 331, the photoresist is patterned to form corresponding windows exposing the underlying protective layer 321. Then, the protective layer 321 and substrate 310 are dry-etched sequentially to form the first trench 341 and the second trench 342 on both sides, respectively. The first trench 341 is used for subsequent formation of the photodiode, and the second trench 342 is used for subsequent formation of the readout diode. The specific shape and size of the first trench 341 can be defined according to the requirements of the photodiode, and the shape and size of the second trench 342 can be defined according to the requirements of the readout diode. The dummy gate 331 is located between the first trench 341 and the second trench 342, enabling the buried gate ultimately formed at the corresponding position of the dummy gate 331 to control the transfer of electrons from the photodiode located in the first trench 341 to the readout diode located in the second trench 342. Other conventional steps, such as removing excess photoresist, will not be described in detail.

[0076] Please refer to Figure 4 and Figure 5In step S40, during the formation of the photodiode 350 in the first trench 341, a readout diode 360 ​​is formed in the second trench 342. The photodiode 350 and the readout diode 360 ​​are fabricated simultaneously in the same process, and the resulting photodiode 350 and readout diode 360 ​​have the same hierarchical structure and materials. Specifically, both the photodiode 350 and the readout diode 360 ​​include N-type epitaxial layers and P-type epitaxial layers sequentially stacked along a second direction away from the substrate 310. The N-type epitaxial layer is a multilayer sub-epitaxy layer sequentially formed along the second direction using a selective epitaxial growth process, compared to... Figure 1 In image sensors, high-energy ion implantation is used to form photodiodes and floating diffusion regions, which is less prone to damage compared to traditional methods. Figure 1 The transmission gate in the middle improves the efficiency of electron transmission.

[0077] Adjacent sub-epitaxial layers are made of different materials; for example, adjacent sub-epitaxial layers may contain different Group 5 elements. This causes a concentration gradient to form within the multiple sub-epitaxial layers stacked in the N-type epitaxial stack after photoexcitation, optimizing the transport path of photogenerated carriers, reducing the recombination rate during diffusion, and improving the quantum efficiency of photodiode 350 and readout diode 360. Furthermore, since pentavalent elements have a higher atomic mass than silicon and lower mobility during epitaxial growth, the doping concentration in a single doped layer is uneven. Growing pentavalent elements with different dopants multiple times can improve the uniformity of doping concentration in the pixel area. The P-type epitaxial layer is a P-type doped layer formed using a selective epitaxial growth process. In this embodiment, photodiode 350 includes an N-type epitaxial stack and a P-type epitaxial layer forming a PN junction, achieving a low dark current, low noise "pinning" effect, and simultaneously determining the photosensitivity. Readout diode 360 ​​includes an N-type epitaxial stack and a P-type epitaxial layer forming a PN junction, compared to... Figure 1 The floating diffusion region in the image sensor enables highly sensitive charge-to-voltage conversion. The photodiode 350 and the readout diode 360 ​​form a perfect potential barrier, ensuring efficient and clean electron transfer from the photodiode 350 to the readout diode 360. During the fabrication of the photodiode 350, the readout diode 360 ​​is fabricated simultaneously, eliminating the need for separate fabrication of the readout diode 360 ​​and reducing the complexity and cost of the fabrication process.

[0078] In some embodiments, the top surface of the N-type epitaxial stack is not higher than the top surface of the substrate 310, which ensures that the photogenerated electrons collected by the N-type epitaxial stack can be transferred to the readout diode 360.

[0079] In some embodiments, please refer to Figure 4 and Figure 5The formation of photodiode 350 and readout diode 360 ​​includes: forming a first SiAs epitaxial layer 351 at the bottom of a first trench 341 and a second trench 342 using a selective epitaxial growth process; forming a SiP epitaxial layer 352 on the top surface of the first SiAs epitaxial layer 351 within the first trench 341 and the second trench 342 using a selective epitaxial growth process; forming a second SiAs epitaxial layer 353 on the top surface of the SiP epitaxial layer 352 within the first trench 341 and the second trench 342 using a selective epitaxial growth process; and forming a SiIn epitaxial layer 354 on the top surface of the second SiAs epitaxial layer 353 within the first trench 341 and the second trench 342 using a selective epitaxial growth process. The SiAs epitaxial layer characterizes silicon material containing As, the SiP epitaxial layer characterizes silicon material containing P, and the SiIn epitaxial layer 354 characterizes silicon material containing In. The thickness of the first SiAs epitaxial layer 351 can range from 5nm to 7nm, specifically 5nm, 6nm, or 7nm. The SiIn epitaxial layer 354 can serve as a capping layer for the photodiode 350 and the readout diode 360. The first SiAs epitaxial layer 351, the SiP epitaxial layer 352, and the second SiAs epitaxial layer 353 constitute an N-type epitaxial stack, while the SiIn epitaxial layer 354 forms a P-type epitaxial layer. The first SiAs epitaxial layer 351, SiP epitaxial layer 352, the second SiAs epitaxial layer 353, and the SiIn epitaxial layer 354 located on the first trench 341 form the photodiode 350, and the first SiAs epitaxial layer 351, SiP epitaxial layer 352, the second SiAs epitaxial layer 353, and the SiIn epitaxial layer 354 located on the second trench 342 form the readout diode 360.

[0080] In some embodiments, one or more of the first SiAs epitaxial layer 351, SiP epitaxial layer 352, second SiAs epitaxial layer 353, and SiIn epitaxial layer 354 may be doped with a small amount of boron (B).

[0081] Please refer to Figures 6 to 7 After depositing the passivation layer 322 in step S50, the dummy gate 331 and its directly beneath substrate 310 are etched away to form a gate trench 343. The material of the passivation layer 322 can be SiN or SiO2, or a multilayer stacked structure, etc. The material of the passivation layer 322 can be the same as or different from the material of the protective layer 321. At least one of the processes such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition can be used to form the passivation layer 322. The formed passivation layer 322 covers the protective layer 321, the photodiode 350, and the readout diode 360. The thickness of the formed passivation layer 322 can range from 5nm to 15nm, specifically 5nm, 8nm, 10nm, 12nm, 15nm, etc.

[0082] Please refer to Figure 7 Specifically, a photoresist layer can be spin-coated onto the surface of the passivation layer 322 first. Then, the photoresist is patterned at the dummy gate 331 to form a corresponding window exposing the underlying passivation layer 322. Next, the passivation layer 322, protective layer 321, dummy gate 331, and substrate 310 are dry-etched to form a gate trench 343 in the buried gate region. The gate trench 343 is used for subsequent buried gate formation. The specific shape and size of the gate trench 343 can be defined according to the requirements of the buried gate. The final height of the bottom of the gate trench 343 can be close to the bottom height of the photodiode 350. Other conventional steps, such as removing excess photoresist, will not be described in detail.

[0083] Please refer to Figures 7 to 10 In step S60, a first control gate, a channel layer 334, and a second control gate are sequentially formed within the gate trench 343 along a second direction away from the substrate 310. The bottom surface of the channel layer 334 is lower than the top surface of the substrate 310. The first control gate, the channel layer 334, and the second control gate are used to form a buried gate 330. Compared to Figure 1 The image sensor in the image sensor has an added channel layer 334 to form a superchannel, thereby improving electron transport efficiency. Furthermore, the bottom surface of the channel layer 334 is lower than the top surface of the substrate 310 to ensure that the channel layer 334 can play its role in transporting electrons.

[0084] Please refer to Figures 7 to 10 In some embodiments, forming the buried gate 330 includes: forming a first gate dielectric layer 332 on the inner surface of the gate trench 343, and then filling the gate trench 343 with a first gate conductive layer 333. After etching back the first gate conductive layer 333 and the first gate dielectric layer 332, a channel layer 334 is epitaxially grown inside and outside the gate trench 343, the bottom surface of the channel layer 334 being lower than the top surface of the substrate 310; and a second control gate is formed on the channel layer 334.

[0085] For details, please continue to refer to [the website / information]. Figure 7 and Figure 8 A first gate dielectric layer 332 can be formed on the sidewall of the gate trench 343 using processes such as epitaxial growth. The material of the first gate dielectric layer 332 can be titanium nitride (TiN) or tantalum nitride (TaN), or a multilayer stacked structure can be adopted. Then, a first gate conductive layer 333 can be formed on the surface of the first gate dielectric layer 332 using processes such as physical vapor deposition or atomic layer deposition. The material of the first gate conductive layer 333 can be titanium aluminide (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), or tantalum aluminum carbide (TaAlC), etc.

[0086] Please refer to Figure 9 and Figure 10For example, a cyclic etching process can be used to etch the first gate conductive layer 333 and the first gate dielectric layer 332 to form the desired morphology, and a selective epitaxial growth process can be used to form a channel layer 334 on the top surface of the first gate conductive layer 333 and the first gate dielectric layer 332. The material of the channel layer 334 can be, for example, silicon germanium (SiGe), or indium gallium arsenide (InGaAs). In this embodiment, the addition of the channel layer 334 can improve the electron transport efficiency. The bottom surface of the channel layer 334 is lower than the top surface of the substrate 310, which can ensure that the channel layer 334 can play a role in transporting electrons.

[0087] In some embodiments, the channel layer 334 covers the entire top surface of the first control gate. Specifically, the channel layer 334 can completely cover the top surface of the first gate conductive layer 333 and the first gate dielectric layer 332, thereby ensuring that the potential of the entire transmission path is uniform and flat. This allows all photogenerated electrons to flow unimpeded to the readout diode 360, improving charge transfer efficiency and helping to fundamentally eliminate image retention.

[0088] Please continue to refer to this. Figure 10 In some embodiments, forming the second control gate includes: epitaxially growing a second gate dielectric layer on the top surface of the channel layer 334; and depositing a second gate conductive layer 337 on the top surface of the second gate dielectric layer. Specifically, the second gate dielectric layer may include a SiO2 layer 335 and an HfO2 layer 336, etc. SiO2 can also be replaced by other low-k materials, and HfO2 can be replaced by other high-k materials. Then, physical vapor deposition, atomic layer deposition, or other processes can be used on the surface of the second gate dielectric layer. In this embodiment, the second gate conductive layer 337 may be formed on the top surface of the HfO2 layer 336. The material of the second gate conductive layer 337 may be aluminum (Al), etc. In other examples, tungsten (W) or cobalt (Co) or other alloy materials may be used instead of aluminum. The first control gate, the channel layer 334, and the second control gate constitute a buried gate 330, and the finally formed buried gate 330 may be a vertical transfer gate (VTG) in an image sensor.

[0089] Please refer to Figure 10 and Figure 11In some embodiments, an image sensor is provided, which is fabricated using the image sensor fabrication method described in any of the foregoing embodiments. The image sensor includes a P-type substrate 310, and a photodiode 350, a buried gate 330, and a readout diode 360 ​​embedded in the substrate 310 and sequentially distributed along a first direction parallel to the substrate 310; the photodiode 350 and the readout diode 360 ​​are fabricated simultaneously in the same process steps; both the photodiode 350 and the readout diode 360 ​​include an N-type epitaxial layer and a P-type epitaxial layer sequentially stacked along a second direction away from the substrate 310; the buried gate 330 includes a first control gate, a channel layer 334, and a second control gate sequentially stacked along the second direction, wherein the bottom surface of the channel layer 334 is lower than the top surface of the substrate 310.

[0090] In the above embodiments, the image sensor adds a channel layer 334 to form a superchannel, thereby improving electron transport efficiency. Furthermore, the bottom surface of the channel layer 334 is lower than the top surface of the substrate 310 to ensure that the channel layer 334 can effectively transport electrons.

[0091] Furthermore, both the photodiode 350 and the readout diode 360 ​​include N-type epitaxial layers and P-type epitaxial layers sequentially stacked along a second direction away from the substrate 310, i.e., the photodiode 350 and the readout diode 360 ​​are formed using epitaxial growth processes, compared to Figure 1 In image sensors, high-energy ion implantation is used to form photodiodes and floating diffusion regions, which is less prone to damage compared to traditional methods. Figure 1 The transmission gate in the middle improves the efficiency of electron transmission.

[0092] Furthermore, the photodiode 350 comprises an N-type epitaxial layer and a P-type epitaxial layer forming a PN junction, achieving a low dark current and low noise "pinning" effect, which also determines the photosensitivity. The readout diode 360 ​​comprises an N-type epitaxial layer and a P-type epitaxial layer forming a PN junction, thus compared to... Figure 1 The floating diffusion region in the image sensor enables highly sensitive charge-to-voltage conversion. Furthermore, the photodiode 350 and the readout diode 360 ​​form a perfect potential barrier, ensuring efficient and clean charge transfer from the photodiode 350 to the readout diode 360. During the fabrication of the photodiode 350, the readout diode 360 ​​is fabricated simultaneously, eliminating the need for separate fabrication of the readout diode 360 ​​and reducing the complexity and cost of the fabrication process.

[0093] In some embodiments, the N-type epitaxial stack includes multiple sub-epitaxy layers stacked sequentially along a second direction, wherein adjacent sub-epitaxy layers include different Group 5 elements. This causes a concentration gradient to form within the multiple sub-epitaxy layers of the N-type epitaxial stack after optical excitation, optimizing the transport path of photogenerated carriers, reducing the recombination rate during diffusion, and improving the quantum efficiency of the photodiode 350 and the readout diode 360. Furthermore, since pentavalent elements have a higher atomic mass than silicon and lower mobility during epitaxial growth, resulting in uneven doping concentration in a single doped layer, growing pentavalent elements with different dopants multiple times can improve the uniformity of doping concentration in the pixel region.

[0094] In some embodiments, the channel layer 334 covers the entire top surface of the first control gate. The complete coverage of the top surface by the channel layer 334 ensures that the potential of the entire transmission path is uniform and flat, which allows all photogenerated electrons to flow unimpeded to the readout diode 360, improving charge transfer efficiency and helping to fundamentally eliminate image retention.

[0095] In some embodiments, the photodiode 350 and the readout diode 360 ​​are fabricated before the buried gate 330. This avoids damage to the buried gate 330 during the formation of the photodiode 350 and the readout diode 360.

[0096] In some embodiments, the top surface of the N-type epitaxial stack is not higher than the top surface of the substrate 310, which ensures that the photogenerated electrons collected by the N-type epitaxial stack can be transferred to the readout diode 360.

[0097] In some embodiments, at least one of the following features is included: the N-type epitaxial stack includes a first SiAs epitaxial layer 351, a SiP epitaxial layer 352, and a second SiAs epitaxial layer 353 stacked sequentially along a second direction; the P-type epitaxial layer includes a SiIn epitaxial layer 354; and the channel layer 334 includes a SiGe epitaxial layer.

[0098] In some embodiments, please refer to Figure 11 The image sensor may also include a pixel circuit 200, wherein the source of the reset transistor (RST) and the gate of the source follower (SF) in the pixel circuit 200 are connected to the readout diode 360 ​​in the above embodiment. The image sensor operates as follows:

[0099] Reset: Turn on the reset transistor (RST), connect the pixel power supply (VAAPIX) to the readout diode 360, and reset the readout diode 360 ​​to a high level (clear electrons).

[0100] Transfer: When the embedded gate 330 is turned on, all the electrons collected by the photodiode 350 are transferred to the readout diode 360. The electrons neutralize the positive charge of the readout diode 360, causing the potential of the readout diode 360 ​​to decrease (the decrease is proportional to the light intensity).

[0101] Readout: The readout diode 360 ​​directly controls the gate of the source follower (SF). The source follower (SF) is a buffer / amplifier that converts and drives the small voltage changes of the readout diode 360 ​​to the row select transistor (RS).

[0102] Output: The row selector (RS) is a switch that turns on when a row of pixels is selected, sending the voltage signal output by the source follower (SF) to the pixel output bus.

[0103] It should be understood that, although Figure 2 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 2 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0104] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The embodiments described above are merely illustrative of several implementation methods of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these modifications and improvements all fall within the scope of protection of this disclosure.

Claims

1. An image sensor, characterized in that, It includes a P-type substrate, and a photodiode, a buried gate, and a readout diode embedded in the substrate and sequentially distributed along a first direction parallel to the substrate; The photodiode and the readout diode are fabricated simultaneously in the same process steps. Both the photodiode and the readout diode include N-type epitaxial layers and P-type epitaxial layers stacked sequentially along a second direction away from the substrate. The buried gate includes a first control gate, a channel layer and a second control gate stacked sequentially along the second direction, wherein the bottom surface of the channel layer is lower than the top surface of the substrate.

2. The image sensor according to claim 1, characterized in that, The N-type epitaxial stack includes multiple sub-epitaxy layers stacked sequentially along the second direction, wherein adjacent sub-epitaxy layers include different fifth group elements.

3. The image sensor according to claim 1, characterized in that, The channel layer covers the entire top surface of the first control gate.

4. The image sensor according to claim 1, characterized in that, The photodiode and the readout diode are fabricated prior to the embedded gate.

5. The image sensor according to claim 1, characterized in that, The top surface of the N-type epitaxial stack is not higher than the top surface of the substrate.

6. The image sensor according to claim 1, characterized in that, Includes at least one of the following features: The N-type epitaxial stack includes a first SiAs epitaxial layer, a SiP epitaxial layer, and a second SiAs epitaxial layer stacked sequentially along the second direction; The P-type epitaxial layer includes a SiIn epitaxial layer; The channel layer includes a SiGe epitaxial layer.

7. A method for fabricating an image sensor, characterized in that, include: A P-type substrate is provided, wherein the top surface of the substrate includes a dummy gate; A protective layer is formed covering the dummy gate and the top surface of the substrate; The protective layer and the substrate on both sides of the dummy gate are etched to form a first trench and a second trench, and the dummy gate is located between the first trench and the second trench; During the process of forming a photodiode in the first trench, a readout diode is formed in the second trench; After depositing the passivation layer, the dummy gate and the substrate directly below it are etched away to form a gate trench; A first control gate, a channel layer, and a second control gate are sequentially stacked in the gate trench along a second direction away from the substrate. The bottom surface of the channel layer is lower than the top surface of the substrate. The first control gate, the channel layer, and the second control gate are used to form a buried gate.

8. The image sensor fabrication method according to claim 7, characterized in that, The photodiode and the readout diode are formed by: A first SiAs epitaxial layer is formed at the bottom of the first trench and the second trench using a selective epitaxial growth process; A SiP epitaxial layer is formed on the top surface of the first SiAs epitaxial layer in the first trench and the second trench using a selective epitaxial growth process. A second SiAs epitaxial layer is formed on the top surface of the SiP epitaxial layer in the first trench and the second trench using a selective epitaxial growth process. A SiIn epitaxial layer is formed on the top surface of the second SiAs epitaxial layer using a selective epitaxial growth process; the first SiAs epitaxial layer, the SiP epitaxial layer, the second SiAs epitaxial layer, and the SiIn epitaxial layer located on the first trench are used to form the photodiode, and the first SiAs epitaxial layer, the SiP epitaxial layer, the second SiAs epitaxial layer, and the SiIn epitaxial layer located on the second trench are used to form the readout diode.

9. The image sensor fabrication method according to claim 7, characterized in that, Forming the embedded grid includes: After forming a first gate dielectric layer on the inner surface of the gate trench, a first gate conductive layer is filled into the gate trench. After etching back the first gate conductive layer and the first gate dielectric layer, the channel layer is epitaxially grown inside and outside the gate trench, and the bottom surface of the channel layer is lower than the top surface of the substrate; The second control gate is formed on the channel layer.

10. The image sensor fabrication method according to claim 9, characterized in that, Forming the second control gate includes: A second gate dielectric layer is epitaxially grown on the top surface of the channel layer; A second gate conductive layer is deposited on the top surface of the second gate dielectric layer.

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