image sensor

Abstract

An image sensor includes a substrate including pixel regions each including a photodiode, a floating diffusion region disposed in each of the pixel regions on one surface of the substrate and configured to store charge transferred from the photodiode, a circuit element configured to transmit a photoelectric signal according to charge of the floating diffusion region, and a first interlayer insulating layer covering the floating diffusion region on the one surface of the substrate, wherein at least one of the circuit elements includes a conductive material layer disposed on the first interlayer insulating layer and including a source region and a drain region, and a gate electrode disposed on the conductive material layer between the source region and the drain region, and wherein the source region is connected to one of the pixel regions and the drain region is connected to another of the pixel regions.

Description

Technical Field

[0001] The exemplary embodiments disclosed herein relate to image sensors. Background Technology

[0002] An image sensor can be a semiconductor-based sensor capable of receiving light and generating electrical signals, and can include a pixel array having multiple pixels and logic circuitry configured to drive the pixel array and generate an image. Each pixel may include a photodiode and pixel circuitry configured to convert the charge generated by the photodiode into an electrical signal. As the number of pixels included in an image sensor increases and the size of each pixel decreases, various methods are needed for efficiently forming the elements, contact plugs, and interconnections disposed in each pixel and providing the pixel circuitry. Summary of the Invention

[0003] An exemplary embodiment of this disclosure is to provide an image sensor in which circuit elements are shared as stacked transistors in a region of multiple pixels.

[0004] An exemplary embodiment of this disclosure provides an image sensor that prevents blooming by forming a floating diffusion region connecting two adjacent pixel regions in a region physically separated from the photodiode.

[0005] According to an exemplary embodiment of the present disclosure, an image sensor includes: a substrate including pixel regions, each pixel region including a photodiode; a floating diffusion region disposed on a surface of the substrate in each pixel region and configured to store charge transferred from the photodiode; a circuit element configured to transmit a photoelectric signal based on the charge of the floating diffusion region; and a first interlayer insulating layer covering the floating diffusion region on the surface of the substrate, wherein at least one of the circuit elements includes: a conductive material layer disposed on the first interlayer insulating layer and including a source region and a drain region; and a gate electrode disposed on the conductive material layer between the source region and the drain region, wherein the source region is connected to one of the pixel regions, and the drain region is connected to another pixel region.

[0006] According to an example embodiment of this disclosure, an image sensor includes: a substrate including a first pixel region and a second pixel region, the first pixel region including a first photodiode and the second pixel region including a second photodiode; a first isolation pattern defining the first pixel region and the second pixel region in the substrate; a first floating diffusion region located on a surface of the substrate and configured to store charge transferred from the first photodiode in the first pixel region; a second floating diffusion region located on the one surface of the substrate and configured to store charge transferred from the second photodiode in the second pixel region; and a source follower transistor. A body transistor is located on one surface of the substrate and configured to amplify the charge of the first floating diffusion region and the charge of the second floating diffusion region and transmit a signal; a first interlayer insulating layer covers the source follower transistor and the first floating diffusion region and the second floating diffusion region on the one surface of the substrate; and a switching element disposed on the first interlayer insulating layer and perpendicularly overlapping the first isolation pattern located between the first pixel region and the second pixel region, wherein the switching element includes a gate electrode and source and drain regions located on both sides of the gate electrode, and wherein the drain and source regions are electrically connected to the first floating diffusion region and the second floating diffusion region, respectively.

[0007] According to an example embodiment of this disclosure, an image sensor includes: a pixel array comprising a plurality of pixel regions arranged in a direction parallel to a surface of a substrate, each of the plurality of pixel regions including at least one photodiode located in the substrate, a color filter disposed on another surface of the substrate opposite to the first surface, and at least one element disposed on the first surface; and logic circuitry configured to acquire pixel signals from the plurality of pixel regions, wherein the pixel array includes: a floating diffusion region disposed in each of the plurality of pixel regions on the first surface of the substrate and configured to store signals from the photodiode. The at least one element is configured to transmit photoelectric signals based on the charge of the floating diffusion region; and a first interlayer insulating layer covers the floating diffusion region on one surface of the substrate, wherein the at least one element comprises: a conductive material layer disposed on the first interlayer insulating layer and including a source region and a drain region; and a gate electrode disposed on the conductive material layer between the source region and the drain region, wherein the source region is connected to one of the plurality of pixel regions, and the drain region is connected to another of the plurality of pixel regions.

[0008] According to an example embodiment of this disclosure, a method of manufacturing an image sensor includes: forming a first isolation pattern defining pixel regions in a substrate and forming a second isolation pattern on the first isolation pattern from a surface of the substrate; forming a transfer transistor and a floating diffusion region in each pixel region on the one surface of the substrate; forming a first interlayer insulating layer covering the transfer transistor and the floating diffusion region; and forming a thin-film transistor on the first interlayer insulating layer connecting a source region and a drain region to each different pixel region.

[0009] Forming the thin-film transistor includes: forming a conductive material layer on the first interlayer insulating layer; forming a gate insulating layer covering the conductive material layer; and forming a gate electrode on the gate insulating layer.

[0010] As the conductive material layer, a material different from the substrate can be deposited.

[0011] As the conductive material layer, oxide semiconductors or polycrystalline silicon can be deposited.

[0012] Forming the thin-film transistor may further include: forming a source region and a drain region by ion implantation of conductive impurities on both sides of the conductive material layer using the gate electrode as a mask.

[0013] The source region can be configured to overlap with a pixel region in the vertical direction, and the drain region can be configured to overlap with another pixel region adjacent to the pixel region in the vertical direction.

[0014] The method further includes: forming a via in the first interlayer insulating layer that exposes a portion of the one pixel region and a portion of the other pixel region; and forming contact plugs in the vias, wherein the contact plugs can contact the source region and the drain region respectively.

[0015] The lower surfaces of the source region and the drain region can directly contact the upper surface of the contact plug.

[0016] The thin-film transistor can be formed at a horizontal height higher than that of one surface of the substrate.

[0017] The thin-film transistor can be configured as a switching element that electrically connects the floating diffusion regions of different pixel regions to each other. Attached Figure Description

[0018] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a block diagram illustrating an image sensor according to an exemplary embodiment of the present disclosure; Figure 2 This is a diagram illustrating a pixel circuit according to an exemplary embodiment of the present disclosure; Figure 3 It is shown Figure 2 A diagram showing the pixel arrangement of the image sensor; Figure 4 It is shown Figure 3 A top view of one of the pixel regions shown; Figure 5 It is shown Figure 4 The image sensor shown is a cross-sectional view. Figure 6 It is shown Figure 5 A magnified view of a portion shown; Figure 7 , Figure 8 and Figure 9 This is a cross-sectional view showing an image sensor according to an exemplary embodiment of the present disclosure; Figure 10 This is a circuit diagram illustrating a pixel circuit according to an exemplary embodiment of the present disclosure; Figure 11 This is a top view showing a pixel circuit according to an exemplary embodiment of the present disclosure; Figure 12 It is shown Figure 11 A cross-sectional view of the image sensor in the image sensor; Figure 13 This is a cross-sectional view showing an image sensor according to an exemplary embodiment of the present disclosure; Figure 14A , Figure 14B , Figure 14C and Figure 14D It shows the manufacturing process. Figure 5 A cross-sectional view of the image sensor method shown. Detailed Implementation

[0019] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0020] Figure 1 This is a block diagram illustrating an image sensor according to an example embodiment.

[0021] refer to Figure 1 The image sensor 1 may include a pixel array 10 and logic circuitry 20.

[0022] The pixel array 10 may include a plurality of pixels PX arranged in an array along a plurality of rows and columns. Each of the plurality of pixels PX may include at least one photodiode configured to generate charge in response to light and pixel circuitry configured to generate a pixel signal corresponding to the charge generated by the photodiode. The photodiode may include a photodiode formed of a semiconductor material and / or an organic photodiode formed of an organic material.

[0023] For example, a pixel circuit may include a floating diffusion region, a transfer transistor, a reset transistor, a source follower transistor, and a selection transistor. In example embodiments, the configuration of the pixel PX can vary. For instance, each pixel PX may include an organic photodiode containing organic material, or it may be implemented as a digital pixel. When a pixel PX is implemented as a digital pixel, each pixel PX may include an analog-to-digital converter for outputting digital pixel signals.

[0024] The logic circuit 20 may include circuitry for controlling the pixel array 10. For example, the logic circuit 20 may include a row driver 21, a readout circuit 22, a column driver 23, and control logic 24. The row driver 21 can drive the pixel array 10 as row line units. For example, the row driver 21 can generate transfer control signals for controlling transfer transistors of the pixel circuitry, reset control signals for controlling reset transistors, and selection control signals for controlling source follower transistors, and can input signals to the pixel array 10 on a row line basis.

[0025] The readout circuit 22 may include a correlated double sampler (CDS) and an analog-to-digital converter (ADC). The correlated double sampler can be connected to the pixel PX via column lines. The correlated double sampler can read pixel signals from the pixel PX connected to the row line selected by the row line selection signal of the row driver 21 via the column lines. The ADC can convert the pixel signals detected by the correlated double sampler into digital pixel signals and can transfer the signals to the column driver 23.

[0026] Column driver 23 may include latch or buffer circuitry and amplifier circuitry for temporarily storing digital pixel signals, and may process digital pixel signals received from readout circuitry 22. Row driver 21, readout circuitry 22, and column driver 23 may be controlled by control logic 24. Control logic 24 may include a timing controller for controlling the operating timing of row driver 21, readout circuitry 22, and column driver 23.

[0027] Within a pixel PX, pixels PX positioned at the same horizontal location can share the same column lines. For example, pixels PX positioned at the same vertical location can be simultaneously selected by the row driver 21 and pixel signals can be output via the column lines. In an example embodiment, the readout circuit 22 can simultaneously obtain pixel signals from the pixels PX selected by the row driver 21 via the column lines. The pixel signals may include a reset voltage and a pixel voltage, and the pixel voltage can be configured such that the charge generated in each pixel PX in response to light is reflected in the reset voltage.

[0028] Figure 2 This is a diagram illustrating the pixel circuitry of an image sensor according to an example embodiment.

[0029] refer to Figure 2 According to the example embodiment, the unit pixel PX of the image sensor 1 may include at least two photodiodes PD1 and PD2, and an electrical signal may be output using the charge generated by the first photodiode PD1, and an electrical signal may be output using the charge generated by the second photodiode PD2. The operation of the active elements included in the pixel PX may be controlled by a controller included in the image sensor 1.

[0030] Image sensor 1 may include a first switching element SW1, a second switching element SW2, a storage capacitor SC, a reset transistor RX, a first transfer transistor TX1 and a second transfer transistor TX2, a source follower transistor SF, a dual-conversion gain transistor DCG, and a selection transistor SEL. A first photodiode PD1 can be connected to a first floating diffusion region FD1 via the first transfer transistor TX1. A second photodiode PD2 can be connected to a second floating diffusion region FD2 via the second transfer transistor TX2.

[0031] The first transfer transistor TX1 can transfer the charge accumulated in the first photodiode PD1 to the first floating diffusion region FD1 based on the first transfer control signal TS1 transferred from the row driver 21. The first photodiode PD1 can generate electrons as the primary charge carriers. The source follower transistor SF can operate as a source follower buffer amplifier using the charge accumulated in the first floating diffusion region FD1. The source follower transistor SF can amplify the charge accumulated in the first floating diffusion region FD1 and can transfer the charge to the source follower transistor SF.

[0032] The source follower transistor SF can operate via a selection control signal input from the row driver 21 and can perform switching and addressing operations. When the selection control signal is applied from the row driver 21, a voltage can be output to the column line COL connected to the source follower transistor SF. This voltage can be detected by the column driver 23 and the readout circuit 22 connected to the column line COL. The column driver 23 and the readout circuit 22 can detect the reset voltage when no charge has accumulated in the first floating diffusion region FD1, and can detect the pixel voltage when charge has accumulated in the first floating diffusion region FD1. In the example embodiment, the image sensor can generate an image by calculating the difference between the reset voltage and the pixel voltage.

[0033] The second photodiode PD2 can be connected to the second switching element SW2 and the storage capacitor SC via the second transfer transistor TX2. Similar to the first photodiode PD1, the second photodiode PD2 can also generate electrons as the primary charge carriers. When the second transfer transistor TX2 is turned on, the charge generated by the second photodiode PD2 can move to the storage capacitor SC.

[0034] The storage capacitor SC can be configured as a component for storing the charge generated by the second photodiode PD2. The storage capacitor SC can be a stacked capacitor and can be implemented as a MIM capacitor, PIP capacitor, etc. The second power supply voltage VSC connected to the storage capacitor SC can be higher than the first power supply voltage V of the entire pixel circuit. PIX The value is smaller than the value. However, its example embodiments are not limited to this.

[0035] The storage capacitor SC can store charge in response to the amount of charge generated by the second photodiode PD2 and the operation of the second transfer transistor TX2.

[0036] A first switching element SW1 can be connected between a second floating diffusion region FD2 and a first floating diffusion region FD1, and the charge of the storage capacitor SC can be transferred to the first floating diffusion region FD1, or the charge of the second floating diffusion region FD2 can be transferred to the first floating diffusion region FD1 through the on / off operation of the first switching element SW1. To adjust the conversion gain of the charge generated by the first photodiode PD1 or the capacitance of the pixel, a dual conversion gain transistor DCX and a dual conversion gain capacitor DGC can be further included. The dual conversion gain transistor DCX can be turned on in response to a control signal DGS and can be used as the dual conversion gain capacitor DGC configured to store the charge of the first floating diffusion region FD1.

[0037] The circuitry within each pixel PX can be distributed across two physically isolated pixel regions. Therefore, it can be understood that circuitry within two pixel regions can be shared. Figure 2 In the example embodiment shown, multiple first photodiodes PD1 and second photodiodes PD2 can share the column line COL. Therefore, while a first pixel voltage corresponding to the charge of the multiple first photodiodes PD1 is output to the column line COL, the second photodiode PD2 can be isolated from the column line COL. For example, while the first pixel voltage is output to the column line COL, the first switching element SW1 can be turned off, thereby isolating the second photodiode PD2 from the column line COL.

[0038] In order to use the charge of the first photodiode PD1 to generate the first pixel voltage and output the voltage to the column line COL, the first transfer transistor TX1 can be turned on, so that the charge generated by the first photodiode PD1 can accumulate in the first floating diffusion region FD1.

[0039] Similarly, while the second pixel voltage corresponding to the charge of the second photodiode PD2 is output to the column line COL, the plurality of first photodiodes PD1 can be isolated from the column line COL. For example, while the second pixel voltage is output to the column line COL, the first transfer transistor TX1 can be turned off, thereby isolating the plurality of first photodiodes PD1 from the column line COL.

[0040] To generate the second pixel voltage and output it to the column line COL, the first switching element SW1 and the second switching element SW2 can be turned on, and the second floating diffusion region FD2 and the first floating diffusion region FD1 can be connected to each other. The charge generated by the second photodiode PD2 and stored in the storage capacitor SC can accumulate in the first floating diffusion region FD1 and the second floating diffusion region FD2 and can be converted into a voltage by the source follower transistor SF.

[0041] In addition, the first switching element SW1 can be turned on and the second switching element SW2 can be turned off, so that the charge of the second photodiode PD2 can be converted into voltage by the source follower transistor SF.

[0042] Additionally, the first switching element SW1 can be turned off, and the second switching element SW2 can be turned off, so that the charge of the first photodiode PD1 can be converted into a voltage by the source follower transistor SF. The voltages converted in each step can be combined to generate the second pixel voltage of the second photodiode PD2.

[0043] In an example embodiment, the second photodiode PD2 can be used to sense flickering external light sources or to improve the dynamic range of the image sensor 1. To improve the dynamic range of the image sensor 1, while the first pixel voltage generated by the charges of the multiple first photodiodes PD1 is output multiple times, the second pixel voltage generated by the charges of the second photodiode PD2 can be output only once.

[0044] The area of ​​the first photodiode PD1 can be relatively larger than the area of ​​the second photodiode PD2. In an example embodiment, an image accurately representing a flickering external light source is generated using the charge generated by the second photodiode PD2, and the charge generated by the plurality of first photodiodes PD1 can be used to generate a general image. Furthermore, by controlling the exposure time of light received by each of the first photodiodes PD1 and the second photodiode PD2 and transmitting voltage to a column line COL via a shutter method, the dynamic range and image quality of the image sensor can be improved.

[0045] Figure 2 The pixel PX in the image can be implemented to have, for example, Figure 3 The unit pixel area is arranged in the middle.

[0046] refer to Figure 3 In the example embodiment, the pixel array 10 of the image sensor 1 may include a plurality of unit pixels PX, and the pixel region PA assigned to each pixel PX may include a first pixel region PA1 and a second pixel region PA2. For example, the pixel array 10 may include a first pixel region PA1 as a general pixel and a second pixel region PA2 as an autofocus pixel. The position and arrangement of the second pixel region PA2 may vary, but... Figure 2In this configuration, the second pixel region PA2 can extend from one side surface of the first pixel region PA1. Specifically, when the first pixel region PA1 is a polygonal shape (e.g., an octagonal shape) having space therein, the second pixel region PA2 can be implemented as a polygonal shape sharing one side of it. Therefore, a boundary isolation pattern 103a can be disposed between the first pixel region PA1 and the second pixel region PA2, and the boundary isolation pattern 103a can be the same as the first isolation pattern 103 surrounding the first pixel region PA1 and the second pixel region PA2. The area of ​​the first pixel region PA1 can be larger than the area of ​​the second pixel region PA2; therefore, the size of the first photodiode PD1 included therein can also be larger than the size of the second photodiode PD2.

[0047] When the second pixel region PA2 extends onto a surface of the first pixel region PA1, the second pixel region PA2 can have an inclination in the diagonal d1 direction rather than in the X or Y direction. Therefore, the second pixel region PA2 can be positioned within the spacing between two adjacent first pixel regions PA1, but the position of the second pixel region PA2 is not limited to this. Figure 3 The example shown can be varied.

[0048] Figure 4 It is shown Figure 3 A top view of one of the pixel regions shown. Figure 5 It is shown Figure 4 The image sensor shown is a cross-sectional view. Figure 6 It is shown Figure 5 A magnified view of a portion shown to illustrate... Figure 5 Region "B" in the text.

[0049] The image sensor 1 may include a first structure L1 corresponding to the pixel array 10 and a second structure L2 corresponding to the logic circuit 20 coupled to the first structure L1.

[0050] In the first structure L1 of the pixel array 10, a first isolation pattern 103 may be disposed between pixel regions PA that define a unit pixel PX, and each pixel region PA may include a first pixel region PA1 with a polygonal shape (e.g., a first pixel region PA1 with an octagonal shape) and a second pixel region PA2 with a quadrilateral shape, the second pixel region PA2 sharing one side implemented as the boundary isolation pattern 103a.

[0051] The first pixel region PA1 may occupy a larger area than the second pixel region PA2, and may include a first floating diffusion region FD1, a first transfer gate TG1 of a first transfer transistor TX1, and gate structures 125 and 126 of multiple transistors. The second pixel region PA2 may include a second floating diffusion region FD2 and a second transfer gate TG2 of a second transfer transistor TX2. A ground region GND may be provided in the first pixel region PA1 and the second pixel region PA2.

[0052] The first floating diffusion region FD1 located in the first pixel region PA1 and the second floating diffusion region FD2 located in the second pixel region PA2 may be doped with impurities of a first conductivity type, and the charge generated by the first photodiode PD1 and the second photodiode PD2 may accumulate therein. For example, the first conductivity type impurity may be an N-type impurity.

[0053] The first floating diffusion region FD1 and the second floating diffusion region FD2 can be connected to at least one contact plug 150, and the first floating diffusion region FD1 and the second floating diffusion region FD2 can be adjacent to transfer gates TG1 and TG2. The first transfer gate TG1 and the second transfer gate TG2 can be adjacent to the first photodiode PD1 and the second photodiode PD2 respectively formed inside the first isolation pattern 103 in the first direction (Z direction).

[0054] When a first bias voltage is applied to the first transfer gate TG1 and the second transfer gate TG2, the charge generated by the first photodiode PD1 and the second photodiode PD2 may not move to the floating diffusion regions FD1 and FD2. When the voltage of the first transfer gate TG1 and the voltage of the second transfer gate TG2 increases to a second bias voltage higher than the first bias voltage, the charge generated by the first photodiode PD1 and the second photodiode PD2 may move to the floating diffusion regions FD1 and FD2. For example, the first bias voltage may be negative, and the second bias voltage may be positive. The absolute value of the first bias voltage may be less than the absolute value of the second bias voltage.

[0055] exist Figure 4In the illustrated example embodiment, the first floating diffusion region FD1 and the second floating diffusion region FD2 can extend in a second direction (X direction) and / or a third direction (Y-axis direction). The first floating diffusion region FD1 can extend to have a quadrilateral shape, but the illustrated embodiment is not limited to this, and the first floating diffusion region FD1 can be configured to ensure maximum area in the first pixel region PA1. The second floating diffusion region FD2 can be configured to ensure maximum area in the second pixel region PA2, and can have a shape similar to that of the second pixel region PA2. Therefore, the first floating diffusion region FD1 and the second floating diffusion region FD2 can have different shapes and different areas. However, the shapes of the first floating diffusion region FD1 and the second floating diffusion region FD2 are not limited to this, and can vary in the illustrated embodiment.

[0056] A first transfer gate TG1 connected to a first photodiode PD1 can be disposed in a first pixel region PA1, and a second transfer gate TG2 connected to a second photodiode PD2 can be disposed in a second pixel region PA2.

[0057] In the transistor, the second switching element SW2, the reset transistor RX, the source follower transistor SF, the select transistor SEL, and the dual-conversion gain transistor DCX can be disposed in the first pixel region PA1, and the circuit elements may not be disposed in the second pixel region PA2, or fewer circuit elements may be disposed in the second pixel region PA2 than in the first pixel region PA1. The transistor, excluding the first transfer gate TG1 and the second transfer gate TG2, may include gate structures 125, 126, and 128 and active regions 123 disposed on both sides of the gate structures 125, 126, and 128. The area of ​​each active region 123 may be smaller than the area of ​​the first floating diffusion region FD1 and the area of ​​the second floating diffusion region FD2. This may be because the areas of the first floating diffusion region FD1 and the second floating diffusion region FD2, in which the charge generated by each photodiode PD1 and PD2 accumulates, may need to be relatively large. Pixel regions PA1 and PA2 may each also include a second isolation pattern (STI: shallow trench isolation) 105 to isolate the active region 123.

[0058] The active region 123 for the ground region GND may be further included in each of the pixel regions PA1 and PA2. The ground region GND may be isolated from the first floating diffusion region FD1 and the second floating diffusion region FD2 and the transistor, and may not be in contact with the first transfer gate TG1 and the second transfer gate TG2. In addition, the ground region GND may be doped with a second conductivity type impurity that is different from the conductivity type impurities of the first floating diffusion region FD1, the second floating diffusion region FD2, and the active region 123.

[0059] Contact plugs 150 and 151 may be disposed in the first transfer gate TG1 and the second transfer gate TG2, the first floating diffusion region FD1 and the second floating diffusion region FD2, the gate structures 125, 126 and 128, the active region 123 and the ground region GND.

[0060] The substrate 101 can be configured as a semiconductor substrate. For example, the substrate 101 can be formed of a semiconductor material (e.g., a single-crystal silicon substrate).

[0061] The substrate 101 may include a surface S1 and another surface S2 opposite to the surface S1, and the first photodiode PD1 and the second photodiode PD2 may be formed in the substrate 101 in two first pixel regions PA1 and PA2 located between the surface S1 and the other surface S2. The first photodiode PD1 and the second photodiode PD2 may be adjacent to the first transfer gate TG1 and the second transfer gate TG2 respectively in the Z direction perpendicular to the surface S1 of the substrate 101.

[0062] Optical unit 180 can be disposed on another surface S2 of substrate 101 adjacent to the first photodiode PD1 and the second photodiode PD2 in the Z direction (vertical direction). Optical unit 180 may include a color filter 181, a mesh structure 183, a planarization layer 185, and a microlens 187. Color filter 181 can be isolated from the color filters of other adjacent pixels by mesh structure 183 and can transmit light of a predetermined wavelength band. Microlens 187 can refract light incident on pixel PX and can focus the light onto photodiodes PD1 and PD2. First photodiode PD1 and second photodiode PD2 can generate charge in response to light passing through optical unit 180.

[0063] The circuit elements can be disposed on a surface S1 of the substrate 101, which is one side of the first photodiode PD1 and the second photodiode PD2 in the Z direction (vertical direction). Therefore, the optical unit 180 and the circuit elements can be disposed on opposite sides of the first photodiode PD1 and the second photodiode PD2 in the first direction (Z direction), respectively.

[0064] The first photodiode PD1 and the second photodiode PD2 located in the substrate 101 can be isolated from each other, and a first isolation pattern 103 can be formed on the surface of the substrate 101, including octagonal prisms and quadrilateral prisms. The first isolation pattern 103 may include a boundary isolation pattern 103a that isolates the first pixel region PA1 and the second pixel region PA2 that form a pixel region PA from each other. The boundary isolation pattern 103a may be formed on one side, but its exemplary embodiments are not limited thereto, and the boundary isolation pattern 103a can be understood as a first isolation pattern 103 shared between the first pixel region PA1 and the second pixel region PA2 in the pixel region PA.

[0065] The first isolation pattern 103 may include a conductive material (e.g., a semiconductor material) in the central region, and may also include a semiconductor material containing impurities having a second conductivity type different from the first conductivity type.

[0066] A pad can be formed around a conductive material, and a trench insulating layer 104 can be formed between the pad and the substrate 101. Therefore, the conductive material in the first isolation pattern 103 can be electrically insulated from the substrate 101. When a conductive material is included in the first isolation pattern 103, the ability to collect charge from photodiodes PD1 and PD2 can be improved during dark current flow. A substrate insulating region can be further included between the first photodiode PD1 and the second photodiode PD2 and the trench insulating layer 104, but exemplary embodiments are not limited thereto.

[0067] The active region 123 of the circuit element and the second isolation pattern 105 (STI) of the first floating diffusion region FD1 and the second floating diffusion region FD2 can be formed in the substrate 101 from a surface S1 of the substrate 101.

[0068] The second isolation pattern 105 can be formed by removing the entire surface S1 of the substrate 101 to a predetermined depth, except for the region where the active region 123 of the circuit elements is disposed and the region where the first floating diffusion region FD1 and the second floating diffusion region FD2 are disposed, and stacking insulating material.

[0069] The second isolation pattern 105 can also be set on the first isolation pattern 103. For example Figure 5As shown, the second isolation pattern 105 can be aligned in the Z direction on the first isolation pattern 103 and can form a PD isolation pattern IS that separates each pixel region PA. The PD isolation pattern IS can also separate the first pixel region PA1 and the second pixel region PA2. The second isolation pattern 105 located on the first isolation pattern 103 can be set to have a width larger than the first width W1 of the upper part of the first isolation pattern 103, and a lower width larger than the first width W1 of the upper part of the first isolation pattern 103.

[0070] The upper surface of the second isolation pattern 105 may be substantially coplanar with one surface S1 of the substrate 101, but its exemplary embodiments are not limited thereto, and the upper surface may be coplanar with the upper surface of the gate insulating layer 128.

[0071] The second isolation pattern 105 may have a width that decreases from the upper surface to the lower surface; therefore, the second isolation pattern 105 may have sloping side surfaces. The second isolation pattern 105 may include a pad 106 surrounding the side and lower surfaces, which may conceal grooves located on the pad 106, and may be provided with an insulating material. The insulating material may be a material such as a silicon oxide film, a silicon oxynitride film, or a silicon carbide film. In this case, in the PD isolation pattern IS extending in the Z direction between the second isolation pattern 105 and the first isolation pattern 103, the pad 106 may not be provided on the bottom surface of the second isolation pattern 105 that contacts the upper part of the first isolation pattern 103, but exemplary embodiments are not limited thereto.

[0072] As described above, the first pixel region PA1 and the second pixel region PA2 may include a first photodiode PD1 and a second photodiode PD2, a first floating diffusion region FD1 and a second floating diffusion region FD2 as a surface S1 of the substrate 101, and a first transfer gate TG1 and a second transfer gate TG2 respectively adjacent to the first floating diffusion region FD1 and the second floating diffusion region FD2.

[0073] In the first pixel region PA1, transistors as circuit elements can be disposed, and the gate electrode 125 of each transistor can include a semiconductor material, such as silicon, germanium, or a combination thereof. The gate electrode 125 can include a layer of conductive material doped with N-type or P-type, or it can include an undoped layer.

[0074] The first floating diffusion region FD1 and the second floating diffusion region FD2 may include multiple regions doped with impurities at different concentrations, but exemplary embodiments thereof are not limited thereto. When multiple regions are included, the regions may be doped at higher concentrations in a direction away from the first transfer gate TG1 and the second transfer gate TG2.

[0075] The first transfer gate TG1 and the second transfer gate TG2 may include a transfer gate electrode, a gate insulating layer 128, and a transfer gate spacer (not shown). The transfer gate electrode may be formed of a conductive material such as polysilicon, metal, or metal silicide, and the first bias voltage and the second bias voltage described above may be applied to the transfer gate electrode. The gate insulating layer 128 may be disposed between the transfer gate electrode and the substrate 101. The transfer gate electrode may include a multilayer structure, and the multiple layers may have different shapes. For example, the lower electrode layer may be disposed in a first direction between the upper electrode layer and the first photodiode PD1 and the second photodiode PD2, and may have a width that decreases toward the first photodiode PD1 and the second photodiode PD2. The lower electrode layer may be disposed below one surface S1 of the substrate 101 and may be buried in the substrate 101, and the upper electrode layer may have a region disposed above one surface S1 of the substrate 101. The gate insulating layer 128 may be formed along the interface surface between the transfer gate electrode and the substrate 101. The transfer gate spacer may be disposed between the first floating diffusion region FD1 and the second floating diffusion region FD2 and the upper electrode layer.

[0076] The gate structures 125, 126, and 128 of the transistor, other than the first transfer gate TG1 and the second transfer gate TG2, may have shapes different from those of the transfer gates TG1 and TG2. The gate structures 125, 126, and 128 of the transistor may be formed on the substrate 101 and may include a gate electrode 125, a gate insulating layer 128, and a gate spacer 126.

[0077] The active region 123 can be disposed on both sides of the gate structures 125, 126, and 128 of the transistor, excluding the transfer gates TG1 and TG2, and can form each of the source and drain regions S / D. The active region 123 can be formed by implanting a first conductivity type impurity to a predetermined depth on a surface S1 of the substrate 101.

[0078] As an example of transistors other than the first transfer gate TG1 and the second transfer gate TG2, in the reset transistor RX, source follower transistor SF, select transistor SEL, dual conversion gain transistor DCX and / or second switching element SW2 disposed in the first pixel region PA1, the active region 123 of a surface S1 of substrate 101 may be included in the source / drain regions S / D located on both sides of the gate structures 125, 126 and 128.

[0079] The areas of the transistors other than the first transfer gate TG1 and the second transfer gate TG2 can be different, but the heights of the gate structures 125, 126 and 128 can be substantially the same and can include the same material.

[0080] A substrate insulating layer 165 and an upper insulating layer 164 may be provided to cover the transfer gates TG1 and TG2 and the gate structures 125, 126 and 128, and a first interlayer insulating layer 160 may be provided thereon.

[0081] The substrate insulating layer 165 may be conformally formed on one surface S1 of the substrate 101. The substrate insulating layer 165 may conformally cover the transfer gates TG1 and TG2, the gate structures 125, 126 and 128, and the substrate 101 on the transfer gates TG1 and TG2 and the gate structures 125, 126 and 128. The substrate insulating layer 165 may include silicon oxide or a low-knO material.

[0082] The substrate insulating layer 165 may conformally cover the transfer gates TG1 and TG2, the gate structures 125, 126 and 128 of each circuit element (e.g., gate electrode 125, gate spacer 126 and gate insulating layer 128) and the exposed substrate 101.

[0083] An upper insulating layer 164 may be disposed on a substrate insulating layer 165. The upper insulating layer 164 may comprise a material different from that of the substrate insulating layer 165 and may conformally cover the circuit elements and the exposed substrate 101 to have a thickness greater than that of the substrate insulating layer 165. The upper insulating layer 164 may comprise silicon nitride, silicon oxynitride, or a low-k material. The upper insulating layer 164 may be formed of a material different from that of the substrate insulating layer 165, thereby allowing the upper insulating layer 164 to be used as an etch stop layer during the process.

[0084] The substrate insulating layer 165 and the upper insulating layer 164 can have different functions, and by including different materials, the substrate insulating layer 165 and the upper insulating layer 164 can protect the underlying circuit elements and the semiconductor substrate 101. The total thickness of the substrate insulating layer 165 and the upper insulating layer 164 can be between 30 nm and 50 nm, and preferably between 30 nm and 40 nm. In addition, the upper insulating layer 164 can have the maximum thickness within the above range.

[0085] A first interlayer insulating layer 160 may be provided on substrate 101. The first interlayer insulating layer 160 may cover the gate electrodes 125 of transfer gates TG1 and TG2, source follower transistor SF, reset transistor RG, dual conversion gain transistor DCX, and select transistor SEL, and the substrate 101 therebetween, on upper insulating layer 164. The first interlayer insulating layer 160 may comprise at least one single film or a multi-film structure selected from silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and porous low-k films.

[0086] The first interlayer insulating layer 160 can be formed to have a predetermined thickness, can have a flat upper surface, and through the thickness of the first interlayer insulating layer 160, from a surface S1 of the substrate 101 to the upper surface of the first interlayer insulating layer 160, can have a second height h2.

[0087] In order to be electrically connected to the first floating diffusion region FD1 and the second floating diffusion region FD2, the active region 123 and the gate electrode 125, the contact plugs 150 and 151 can penetrate the substrate insulating layer 165, the upper insulating layer 164 and the first interlayer insulating layer 160, and can be connected to the upper surface of the first floating diffusion region FD1, the second floating diffusion region FD2, the active region 123 and the gate electrode 125.

[0088] Contact plugs 150 and 151 can be disposed on the side and bottom surfaces of diffusion barriers 150a and 151a, and metallic material can be embedded in diffusion barriers 150a and 151a.

[0089] The diffusion barriers 150a and 151a can be TiN, TaN, etc., and the contact plugs 150 and 151 can include conductive materials such as W, Al and Cu.

[0090] The first switching element SW1 can be spaced apart from a surface S1 of the substrate 101 on the first interlayer insulating layer 160.

[0091] The first switching element SW1 may have the shape of a thin-film transistor (TFT) and may include a conductive material layer 170 comprising a material different from that of the substrate 101.

[0092] The first switching element SW1 can be disposed on the upper surface of the first interlayer insulating layer 160, can be spaced apart from the substrate 101 in the Z direction, and can be physically spaced apart from the first photodiode PD1 and the second photodiode PD2 located in the substrate 101.

[0093] From a circuit perspective, the first switching element SW1 can be configured as a switching element connecting the first floating diffusion region FD1 to the second floating diffusion region FD2. Specifically, the first switching element SW1 can be configured as a transistor, and the source portion 170S can be connected to the second floating diffusion region FD2 of the second pixel region PA2, while the drain portion 170D can be connected to the first floating diffusion region FD1 of the first pixel region PA1.

[0094] In the first switching element SW1, the source portion 170S and the drain portion 170D can be connected to the first pixel region PA1 and the second pixel region PA2 respectively, and the two pixel regions PA1 and PA2 can be electrically connected to each other.

[0095] By forming the first switching element SW1 spaced apart from the substrate 101, the halos effect can be prevented not only when the gate voltage is turned on, but also when the state is turned off, from the excessive photoelectric charge generated by the first photodiode PD1 located in the substrate 101 passing through the substrate 101 and being directly injected into the source portion 170S.

[0096] By setting the first switching element SW1, which connects the two pixel regions PA1 and PA2, to be separated from the substrate 101, reliability degradation due to charge in the substrate 101 can be prevented.

[0097] Therefore, the conductive material layer 170 can be disposed on the first interlayer insulating layer 160.

[0098] The conductive material layer 170 can be configured to have a second length W2, while as Figure 4 As shown, the PD isolation pattern IS spans between the first pixel region PA1 and the second pixel region PA2. One end of the conductive material layer 170 can be disposed on the first pixel region PA1, and the other end of the conductive material layer 170 can be disposed on the second pixel region PA2.

[0099] When the conductive material layer 170 has a quadrilateral shape (e.g., a rectangular shape) spanning the PD isolation pattern IS, the conductive material layer 170 can span the PD isolation pattern IS such that one end and the other end of the conductive material layer 170 can be disposed on different pixel regions PA1 and PA2. Specifically, the conductive material layer 170 can cover the first width W1 of the boundary isolation pattern 103a in the first isolation pattern 103 included in the PD isolation pattern IS. In this case, the configuration covering the first width W1 indicates that the center l of the first width W1 and the center of the second length W2 of the conductive material layer 170 can be coaxial, and also indicates that the second length W2 can cover the first width W1.

[0100] The conductive material layer 170 may have a first thickness t1 and may have a flat upper surface and a flat lower surface. The first thickness t1 may be equal to or less than the thickness of the active region 123 of the substrate 101, but exemplary embodiments thereof are not limited thereto.

[0101] The conductive material layer 170 may include a material different from that of the substrate 101, and for example, the conductive material layer 170 may include at least one of IGZO, ZnO, In2O3, TiO2, etc. as an oxide semiconductor, or may include polycrystalline silicon or graphene. When the conductive material layer 170 includes graphene, the conductive material layer 170 may be implemented with a thickness less than when the conductive material layer 170 includes a different material.

[0102] The conductive material layer 170 may include a channel portion 170C and a source portion 170S and a drain portion 170D disposed on both sides of the channel portion 170C. The channel portion 170C is the portion of the conductive material layer 170 that overlaps perpendicularly with the gate electrode 175 above it.

[0103] Here, the source portion 170S and the drain portion 170D can be highly doped with impurities, and can be doped with, for example, N-type or P-type impurities. In this doping process, the gate electrode 175 can be used as a doping mask. Doping can be performed from the upper surface to the lower surface of the source portion 170S and the drain portion 170D.

[0104] The upper gate insulating layer 173, which serves as an insulating film, can be formed on the conductive material layer 170 and can be formed substantially along the upper surface of the first interlayer insulating layer 160. The upper gate insulating layer 173 can be formed of an inorganic insulating material (e.g., silicon oxide or silicon nitride).

[0105] A gate electrode 175 corresponding to the channel portion 170C can be formed on the upper gate insulating layer 173. The gate electrode 175 can serve as a top gate electrode 175. The gate electrode 175 can have a third width W3 smaller than the second length W2, and can be as follows: Figure 4 The example shown extends in a direction perpendicular to the conductive material layer 170, but its exemplary embodiments are not limited thereto.

[0106] The second interlayer insulating layer 161 can be disposed on the gate electrode 175.

[0107] The second interlayer insulating layer 161 may comprise a material substantially the same as that of the first interlayer insulating layer 160, and the upper interconnect 158 ​​and contact passages may be disposed therein. The contact passages may comprise a metal such as tungsten (W), aluminum (Al), or copper (Cu), and tungsten may preferably be used.

[0108] The contact path can have a columnar shape and can have a sloping side surface with a width decreasing toward the substrate 101.

[0109] Contact plugs 150 and 151 can respectively contact the lower surface of the conductive material layer 170 (i.e., one end and the other end of the lower surface of the source portion 170S and the drain portion 170D).

[0110] like Figure 5As shown, contact plugs 150 and 151 can be implemented in multiple layers, and a second contact plug 151, respectively connected to the source portion 170S and the drain portion 170D, can be disposed on the first contact plug 150. The first contact plug 150 can have a first length h1, and the first length h1 can be less than the second height h2 of the upper surface of the first interlayer insulating layer 160. Contact plugs 150 and 151 connected to the source portion 170S or the drain portion 170D can be in direct contact with each other through the upper surface of the first contact plug 150 and the lower surface of the second contact plug 151, such that the sum of the lengths of the first contact plug 150 and the second contact plug 151 can be substantially equal to the second height h2. In a portion of the contact plugs 150 and 151 connected to the source portion 170S or the drain portion 170D, the first contact plug 150 and the second contact plug 151 can be connected to each other through an upper interconnect 158. In this case, the length of the second contact plug 151 can be less than the length of the second contact plug 151 directly connected to it.

[0111] The upper surface of the first contact plug 150 and the lower surface of the second contact plug 151 can be in direct contact with each other, and the upper surface of the second contact plug 151 can be in direct contact with the lower surface of the source portion 170S and the lower surface of the drain portion 170D.

[0112] Each of the source portion 170S and the drain portion 170D may also include an ohmic contact layer 172 on at least a portion of the lower surface that contacts the upper surface of the second contact plug 151, but exemplary embodiments thereof are not limited thereto.

[0113] Because the first switching element SW1, which electrically connects the first pixel region PA1 to the second pixel region PA2, can be physically spaced from the substrate 101, leakage due to halo effects can be prevented. Therefore, since the first switching element SW1 is turned on and off only by the voltage of the gate electrode 175, the reliability of the element can be ensured.

[0114] Alternatively, the upper interconnect 158 ​​located between the first switching element SW1 and the substrate 101 may not be provided. That is, since the upper interconnect 158, except for the first contact plug 150 and the second contact plug 151 which are in direct contact with the first switching element SW1, is not provided below the first switching element SW1 (especially the channel portion 170C), leakage due to unnecessary parasitic capacitance can be reduced.

[0115] The first structure L1 may include first joining structures 166 and 169.

[0116] The first bonding structures 166, 169 may include a first bonding insulating layer 166 and a first bonding pad 169, and may perform hybrid bonding with the second bonding structure of the second structure L2.

[0117] The second structure L2 may include a logic substrate 401, a second interconnect structure 430 connected to the second circuit element 420, second bonding structures 466 and 469 located on the second interconnect structure 430, and a logic insulating layer 440 covering the second circuit element 420 and the second interconnect structure 430 on the logic substrate 401. The second bonding structures 466 and 469 may be connected to the second interconnect structure 430. The second bonding structures 466 and 469 may include a metallic material, such as copper (Cu). The second bonding structures 466 and 469 may include bonding pads 469, and bonding pads 469 may be physically bonded to first bonding pads 169 and may provide an electrical connection path. The second bonding insulating layer 466 may be bonded to the first bonding insulating layer 166 and may provide a hybrid bonding. The logic insulating layer 440 may cover the second circuit element 420 and the second interconnect structure 430.

[0118] In the following text, reference will be made to Figure 7 , Figure 8 and Figure 9 Describe an example implementation. Figure 7 and Figure 8 Is with Figure 6 The region "B" in the image sensor corresponds to a magnified view of the pixel region according to the example embodiment. Figure 9 Is with Figure 5 Corresponding cross-sectional view.

[0119] refer to Figure 7 In addition to the first switching element SW1, the image sensor 1a in the example embodiment can be connected to... Figure 6 The image sensor 1 in it is the same.

[0120] The arrangement of the first switching element SW1 can be consistent with... Figure 4 The arrangement is the same. By setting the first switching element SW1, which connects the two pixel regions PA1 and PA2 to each other, to be spaced apart from the substrate 101, reliability degradation due to charge in the substrate 101 can be prevented.

[0121] Figure 7 The first switching element SW1 may have a gate electrode 175 disposed in the first interlayer insulating layer 160.

[0122] Because the gate electrode 175 is arranged to overlap horizontally with the second contact plug 151, the first switching element SW1 can be formed as a bottom-gate transistor. Therefore, the upper surface of the gate electrode 175 and the upper surface of the first interlayer insulating layer 160 can be coplanar with each other.

[0123] The upper gate insulating layer 173 can be disposed on the upper surface of the gate electrode 175, the upper surface of the second contact plug 151, and the upper surface of the first interlayer insulating layer 160. Therefore, the upper gate insulating layer 173 can be configured to be flat and not curved.

[0124] A conductive material layer 170 extending perpendicularly to the gate electrode 175 can be disposed on the upper gate insulating layer 173. For example... Figure 4 As shown, the conductive material layer 170 can be configured to span the PD isolation pattern IS located between the first pixel region PA1 and the second pixel region PA2. One end of the conductive material layer 170 can be disposed on the first pixel region PA1, and the other end of the conductive material layer 170 can be disposed on the second pixel region PA2.

[0125] The conductive material layer 170 may include a channel portion 170C and a source portion 170S and a drain portion 170D disposed on both sides of the channel portion 170C. The channel portion 170C is the portion of the conductive material layer 170 that overlaps perpendicularly with the gate electrode 175 below.

[0126] Here, the source portion 170S and the drain portion 170D can be doped with impurities at a high concentration. For example, the source portion 170S can be doped with N-type or P-type impurities. The source portion 170S and the drain portion 170D can be doped from the top surface to the bottom surface.

[0127] Contact pads 159 may be disposed between the source portion 170S and the drain portion 170D of the conductive material layer 170 and the second contact plug 151. Contact pads 159 may be made of a conductive material, such as a metallic material like tungsten. A second interlayer insulating layer 161 may be disposed on the conductive material layer 170.

[0128] The material description of each component of the first switching element SW1 can be compared with... Figure 3 , Figure 4 , Figure 5 and Figure 6 The same as in.

[0129] refer to Figure 8 In addition to the first switching element SW1, the image sensor 1b in the example embodiment can be connected to... Figure 6 The image sensor 1 in it is the same.

[0130] The arrangement of the first switching element SW1 can be consistent with... Figure 4The arrangement is the same. By setting the first switching element SW1, which connects the two pixel regions PA1 and PA2 to each other, to be spaced apart from the substrate 101, reliability degradation due to charge in the substrate 101 can be prevented.

[0131] Figure 8 The first switching element SW1 may also include a bottom gate electrode 176 disposed in the first interlayer insulating layer 160.

[0132] The bottom gate electrode 176 can be configured to overlap horizontally with the second contact plug 151, and the top gate electrode 175 can be configured to overlap with the bottom gate electrode 176 in the Z direction, so that the first switching element SW1 can be formed as a dual-gate transistor.

[0133] The upper surface of the bottom gate electrode 176 and the upper surface of the first interlayer insulating layer 160 can be coplanar.

[0134] The bottom gate insulating layer 174 can be disposed on the upper surface of the bottom gate electrode 176, the upper surface of the second contact plug 151, and the upper surface of the first interlayer insulating layer 160. Therefore, the bottom gate insulating layer 174 can be configured to be flat and not curved.

[0135] A conductive material layer 170 extending perpendicularly to the bottom gate electrode 176 can be disposed on the bottom gate insulating layer 174. For example... Figure 4 As shown, the conductive material layer 170 can be configured to span the PD isolation pattern IS located between the first pixel region PA1 and the second pixel region PA2. One end of the conductive material layer 170 can be disposed on the first pixel region PA1, and the other end of the conductive material layer 170 can be disposed on the second pixel region PA2.

[0136] The conductive material layer 170 may include a channel portion 170C and a source portion 170S and a drain portion 170D disposed on both sides of the channel portion 170C. The channel portion 170C is the portion of the conductive material layer 170 that overlaps vertically with the bottom gate electrode 176 below and the top gate electrode 175 above.

[0137] Here, the source portion 170S and the drain portion 170D can be highly doped with impurities, and can be doped with, for example, N-type or P-type impurities. The source portion 170S and the drain portion 170D can be doped from the top surface to the bottom surface.

[0138] Contact pads 179 may be disposed between the source portion 170S and the drain portion 170D of the conductive material layer 170 and the second contact plug 151. Contact pads 179 may be made of a conductive material, such as a metallic material like tungsten. A second interlayer insulating layer 161 may be disposed on the conductive material layer 170.

[0139] The upper gate insulating layer 173 can be configured to cover the conductive material layer 170, and the top gate electrode 175, overlapping the channel portion 170C, can be disposed on the upper gate insulating layer 173. The configuration of the upper gate insulating layer 173 and the top gate electrode 175 can be configured in accordance with... Figure 6 The same as in.

[0140] The material of each component of the first switching element SW1 can be the same as that of... Figure 3 , Figure 4 , Figure 5 and Figure 6 The same as in.

[0141] refer to Figure 9 In addition to the first switching element SW1, the image sensor 1c in the example embodiment can be connected to... Figure 5 The image sensor 1 in it is the same.

[0142] The stacking configuration of the first switching element SW1 can be with Figure 6 The same applies to the substrate 101. By setting the first switching element SW1, which connects the two pixel regions to each other, to be spaced apart from the substrate 101, reliability degradation due to charge in the substrate 101 can be prevented.

[0143] Figure 9 The first switching element SW1 can be configured not to overlap with the PD isolation pattern IS, particularly the boundary isolation pattern 103a, in the Z direction. For this purpose, the upper interconnect 158 ​​can be further disposed between the first contact plug 150 and the second contact plug 151.

[0144] The upper interconnect 158 ​​can be connected between the upper surface of the first contact plug 150 and the lower surface of the second contact plug 151, and the first contact plug 150 and the second contact plug 151 can be configured to be offset in the Z direction without overlapping and electrically connected to each other.

[0145] Therefore, the first switching element SW1 can be configured not to overlap with the PD isolation pattern IS and the boundary isolation pattern 103a located between the first pixel region PA1 and the second pixel region PA2 in the Z direction, and can be shifted to the first pixel region PA1 with a larger area. Thus, the degree of freedom in the position of the first switching element SW1 can be increased, and the component can be arranged in various shapes.

[0146] In the above description, the first switching element SW1 can be implemented as a stacked transistor, so that the source portion 170S and the drain portion 170D can be connected across the first pixel region PA1 and the second pixel region PA2, respectively. However, the example embodiment is not limited to this, and all circuit elements shared in the pixel region can be implemented as stacked transistors.

[0147] Figure 10 This is a circuit diagram illustrating a pixel circuit according to an example embodiment. Figure 11 This is a top view showing a pixel circuit according to an example embodiment. Figure 12 It shows along Figure 11 A cross-sectional view of the image sensor cut by line II-II'.

[0148] refer to Figure 10 Each pixel PX may include four photodiodes PD1 to PD4, four transfer transistors TX1 to TX4, four floating diffusion regions FD1 to FD4, a reset transistor RX, a select transistor SEL, a dual conversion gain transistor DCX, and source follower transistors SF1 and SF2.

[0149] The first photodiode PD1 to the fourth photodiode PD4 can be connected to the first transfer transistor TX1 to the fourth transfer transistor TX4 respectively, and can be driven by the first source follower transistor SF1 and the second source follower transistor SF2.

[0150] Each pixel PX can be constructed as a pixel region PA, and a pixel region PA can include, for example: Figure 11 The four sub-pixel regions PA1 to PA4 are shown. These four sub-pixel regions PA1 to PA4 can be arranged in a 2×2 configuration. The first sub-pixel region PA1 may include a first transfer transistor TX1, a first photodiode PD1, and a first floating diffusion region FD1. In the first pixel region PA1, the first photodiode PD1 can be connected to the first floating diffusion region FD1 via the first transfer transistor TG1. Similarly, the second photodiodes PD2 to the fourth photodiodes PD4 in the second to fourth sub-pixel regions PA2 to PA4 can be connected to the second to fourth floating diffusion regions FD2 to FD4 via the second to fourth transfer transistors TX2 and TX4, respectively.

[0151] In the four adjacent sub-pixel regions PA1 to PA4, the first floating diffusion region FD1 to the fourth floating diffusion region FD4 can be configured to be physically isolated from each other by the second isolation pattern 105 and electrically connected to each other by the dual conversion gain transistor DCX.

[0152] When charge is stored in the floating diffusion region by the conducting transfer transistors TX1 to TX4, the dual-conversion gain transistor DCX can store the charge in the floating diffusion region FD1 to FD4 within itself by turning the dual-conversion gain transistor DCX on and off, thus acting as a capacitor. Therefore, the charge accumulation capability of the floating diffusion region FD1 to FD4 can be improved.

[0153] Therefore, the dual-conversion-gain transistor DCX can be configured to extend from the center n1 of the four sub-pixel regions PA1 to PA4 to the four sub-pixel regions PA1 to PA4 respectively. For example, as Figure 11 As shown, the dual conversion gain transistor DCX can be configured to pass through the center n1 region of the four sub-pixel regions PA1 to PA4 and overlap with each of the four sub-pixel regions PA1 to PA4 by a predetermined area.

[0154] The four adjacent sub-pixel regions PA1 to PA4 can share pixel circuitry, and the shared pixel circuitry can include a dual conversion gain transistor DCX, a reset transistor RX, a first source follower transistor SF1, a second source follower transistor SF2, and a selection transistor SEL.

[0155] For example, in addition to transfer transistors TX1 and TX2, each of the four sub-pixel regions PA1 to PA4 may also include a transistor. Two of the four transistors included in the four sub-pixel regions PA1 to PA4 may be configured to be connected in parallel with each other, thereby providing a first source follower transistor SF1 and a second source follower transistor SF2. One of the other two transistors may be configured to be provided as a select transistor SEL, and the other transistor may be configured to be provided as a reset transistor RX. The dual conversion gain transistor DCX may be spaced apart from the substrate 101, may be disposed on the upper part of the substrate 101, and may be shared.

[0156] refer to Figure 12 The image sensor 1d may include a first structure L1 corresponding to the pixel array 10 and a second structure L2 associated with it and corresponding to the logic circuit 20. Most components of the first structure L1 and the second structure L2 may be connected to... Figures 1 to 6 The components of image sensor 1 are the same.

[0157] Figure 12 The image sensor 1d may include contact plugs 150 connected to the first floating diffusion regions FD1 to the fourth floating diffusion regions FD4 in the first sub-pixel regions PA1 to the fourth sub-pixel regions PA4.

[0158] The contact plug 150 can be formed to penetrate the first interlayer insulating layer 160, and the dual conversion gain transistor DCX can be disposed on the first interlayer insulating layer 160.

[0159] The dual-conversion gain transistor DCX can be configured to overlap with the center n1 of the pixel region PA (i.e., the PD isolation pattern IS), and can have a quadrilateral or circular shape that overlaps with at least a portion of each pixel region PA.

[0160] The dual-conversion-gain transistor DCX may include a conductive material layer 171, an upper gate insulating layer 173, and a gate electrode 175.

[0161] The conductive material layer 171 can represent the shape of the dual-conversion gain transistor DCX, can overlap with the gate electrode 175 in the Z direction, and can have an area larger than that of the gate electrode 175. Therefore, the conductive material layer 171 can be represented by a similar shape that is concentric with the gate electrode 175 in a plane.

[0162] Unlike Figure 6 The conductive material layer 170 and conductive material layer 171 may not include source and drain portions and may be doped with impurities at a low concentration. Therefore, when a large gate voltage is applied to the gate electrode 175, the dual-conversion gain transistor DCX can be used as a capacitor to draw and store the charge of the connected first floating diffusion regions FD1 to the fourth floating diffusion regions FD4.

[0163] Therefore, the contact plugs 150 connected to the first floating diffusion region FD1 to the fourth floating diffusion region FD4 respectively can be simultaneously connected to the conductive material layer 171.

[0164] In this case, the contact plug 150 can be connected to the portion of the conductive material layer 171 that does not overlap with the gate electrode 175.

[0165] The materials of the upper gate insulating layer 173 and the gate electrode 175 can be the same as those of the upper gate insulating layer 173 and the gate electrode 175. Figure 6 The materials are the same, and the second interlayer insulating layer 161 can be configured to cover the dual-conversion gain transistor DCX.

[0166] As described above, the dual conversion gain transistor DCX shared by the four sub-pixel regions PA1 to PA4 can also be spaced apart from the substrate 101 and can be formed to include a semiconductor different from the substrate 101 on the first interlayer insulating layer 160.

[0167] exist Figure 10 , Figure 11 and Figure 12 In this configuration, the dual-conversion-gain transistor DCX can be arranged as a stacked transistor, but it is possible to implement a configuration including stacked transistors (which are...). Figures 2 to 9 The image sensor includes a dual-conversion gain transistor (DCX) and a switching element (SW1, which is a stacked transistor). Additionally, other transistors in the circuitry, besides the transfer transistor (TX), can also be implemented as stacked transistors according to the pixel circuit design.

[0168] Figure 13 This is a cross-sectional view showing an image sensor according to an example embodiment.

[0169] refer to Figure 13 The image sensor 10e may include: a second structure L2, including logic circuitry 20; a third structure L3, disposed below the second structure L2 and including a pixel array 10; and a first structure L1, located below the third structure L3.

[0170] Image sensor 10e may include a first structure L1 having a first substrate 101, a third structure L3 having a third substrate 301, and a second structure L2 having a logic substrate 401. The second structure L2 may be configured as a logic chip including logic circuitry 20, and the first structure L1 and the third structure L3 may be configured as an image sensor structure including a plurality of pixels PX. The first structure L1 may include a first switching element SW1 and a transfer gate TG, and the third structure L3 may include transistors other than the first switching element SW1 and the transfer gate TG.

[0171] The first structure L1 may include Figures 1 to 6 The first substrate 101 described herein includes a first switching element SW1, transfer transistors TG1 and TG2, floating diffusion regions FD1 and FD2, and photodiodes PD1 and PD2, and may include the first switching element SW1 located between the first interlayer insulating layer 160 and the second interlayer insulating layer 161. First bonding structures 166 and 169 may be included on the upper part of the second interlayer insulating layer 161. The drain portion 170D and the source portion 170S of the first switching element SW1 may be connected to the first floating diffusion region FD1 and the second floating diffusion region FD2, respectively. The first structure L1 may include all optical units 180 located on another surface of the first substrate 101, and its description may be consistent with... Figure 5 The same as in.

[0172] The third structure L3 may include a third substrate 301 having a lower surface facing the first structure L1 and an upper surface opposite to the lower surface, an element isolation film 305 defining an active region 310 in the third substrate 301, a circuit element 320 located on the upper surface of the third substrate 301, an interconnection region 375 connected to the circuit element 320, third lower bonding structures 391 and 393 located on the lower surface of the third substrate 301, third upper bonding structures 385 and 369 located on the upper surface of the third substrate 301, a third lower insulating layer 380 located on the lower surface of the third substrate 301, and a third upper insulating layer 370 located on the upper surface of the third substrate 301.

[0173] The third circuit element 320 may include transistors disposed therein, excluding transfer gates TG1 and TG2 and the first switching element SW1. An interconnect region 375 may be disposed between the third substrate 301 and the second structure L2. The interconnect region 375 may apply electrical signals to the third circuit element 320. Third upper bonding structures 385 and 369 may be structures for bonding with the second structure L2. The third upper bonding structures 385 and 369 may include a metallic material such as copper (Cu), or may be implemented as a bonding insulating layer.

[0174] The third lower insulating layer 380 may include a bonding insulating layer 393 having a predetermined thickness from its lower surface. The bonding insulating layer 393 may be used for dielectric-dielectric bonding with the first bonding insulating layer 166 of the first structure L1.

[0175] The third lower bonding structure 390 may be a structure for bonding with the first structure L1. The third lower bonding structure 390 may include a third bonding pad 391 located on the lower surface of the third substrate 301, a landing structure 397 disposed on the upper surface of the third substrate 301, a third bonding passage 395 disposed between the third bonding pad 391 and the landing structure 397, and a side surface insulating layer 396 disposed between the third substrate 301 and the third bonding passage 395. The third bonding pad 391 may include a metal material such as copper (Cu), and the third bonding passage 395 may include a metal material such as copper (Cu), tungsten (W), etc. The third bonding pad 391 may include the same metal material as the third bonding passage 395, but exemplary embodiments are not limited thereto.

[0176] The second structure L2 may include a logic substrate 401, a second interconnect structure 430 connected to the second circuit element 420, a second circuit element isolation pattern 405, a second active region 410, second bonding structures 469 and 466 located on the second interconnect structure 430, and a logic insulating layer 440 covering the second circuit element 420 and the second interconnect structure 430 on the logic substrate 401. The second bonding structures 469 and 466 may be connected to the second interconnect structure 430. The second bonding structures 469 and 466 may include a metallic material, such as copper (Cu). The second bonding structures 469 and 466 may include bonding pads 469, thereby providing an electrical connection path. The logic insulating layer 440 may cover the second circuit element 420 and the second interconnect structure 430, and may cover a portion of the second bonding structures 469 and 466.

[0177] As described above, by dividing the image sensor chip, which includes a pixel array, into two structures L1 and L3, and by performing hybrid bonding between the first structure L1 and the third structure L3 via a third lower bonding structure 390, an image sensor 1e can be realized that hybrid bonding is performed through the three structures L1, L2 and L3.

[0178] In the following text, reference will be made to Figure 14A , Figure 14B , Figure 14C and Figure 14D A method for manufacturing an image sensor according to an example embodiment is described. Figure 14A , Figure 14B , Figure 14C and Figure 14D It shows the manufacturing process. Figure 5 A cross-sectional view of the method for using the pixel array of image sensor 1.

[0179] refer to Figure 14A A substrate 101 can be prepared, and a second isolation pattern 105 and a first isolation pattern 103 can be formed from one surface S1 of the substrate 101. Circuit elements can also be formed on one surface S1 of the substrate 101.

[0180] Specifically, photodiodes PD1 to PD2 can be formed in substrate 101, and a second isolation pattern 105 defining the active region 123 can be formed by forming a trench on one surface S1 of substrate 101 and burying the trench. In this case, an oxide film can be formed on the inner wall of the trench, and a nitride film can be formed as a pad 106.

[0181] A portion of the second isolation pattern 105 can be opened, and a deep trench for forming the first isolation pattern 103 can be formed. The deep trench can be formed in an octagonal columnar shape or a quadrilateral columnar shape to separate sub-pixel regions PA1 and PA2.

[0182] That is, a deep trench can be formed from the bottom surface of the second isolation pattern 105, a trench insulating layer 104 can be formed, and a first isolation pattern 103 as a conductive material can be formed at the center. Polysilicon can be stacked as the conductive material. Subsequently, the trench can be buried in the second isolation pattern 105, and a device isolation insulating film can be formed.

[0183] In this case, an insulating material can be deposited and planarized until one surface of the substrate 101 is exposed, thereby forming a second isolation pattern 105.

[0184] Transfer gates TG1 and TG2, as well as gate structures 125, 126, and 128 of transistors, can be formed. First, openings can be formed to open regions corresponding to transfer gates TG1 and TG2, and the depth of the openings can extend vertically into the substrate 101 to approach photodiodes PD1 and PD2.

[0185] A gate insulating layer 128 can be formed on the inner surface of the opening and on one surface S1 of the substrate 101. Forming the gate insulating layer 128 may include removing the surface oxide film by performing a cleaning process as a pretreatment and depositing a silicon oxide film as the gate insulating layer 128. In this case, the gate insulating layer 128 can be formed entirely on another region of one surface S1 of the substrate 101 in which the transistor is formed, specifically, not on the second isolation pattern 105. The opening can be buried and a conductive layer can be formed. In this case, the conductive layer can be formed by stacking polysilicon, and a conductive layer with conductivity can be formed by depositing polysilicon and ion implanting the polysilicon. In this case, a conductive layer can be over-deposited on the entire one surface S1 of the substrate 101, thereby also allowing the conductive layers of other transistors to be formed simultaneously.

[0186] By patterning the conductive layer, the transfer gates TG1 and TG2, as well as the gate electrodes 125 of other transistors, can be formed simultaneously. In this case, the gate insulating layer 128 can be retained under each gate electrode 125, and the gate spacer 126 can be formed on the side surface of the gate electrode 125.

[0187] Impurities of the first conductivity type can be ion implanted onto the gate electrode 125 and the gate spacer 126.

[0188] For example, impurities such as P and As can be implanted as the first conductivity type impurity. In this case, the first conductivity type impurity can also be implanted into the floating diffusion regions FD1 and FD2, and the implantation concentrations can be different from each other, but the example embodiment is not limited to this. Alternatively, a grounding region can be formed by implanting impurities of different conductivity types.

[0189] A substrate insulating layer 165 can be formed, and activation, i.e., diffusion of implanted impurity ions, can be performed by annealing.

[0190] Additionally, after annealing, a nitride film can be formed as the upper insulating layer 164 to protect the element. In this case, the substrate insulating layer 165 and the upper insulating layer 164 can be formed conformally according to the shape of each element.

[0191] A first interlayer insulation layer 160 can be formed, and contact plugs 150 and 151 that penetrate the first interlayer insulation layer 160 and contact each element can be formed.

[0192] Contact plugs 150 and 151 can be formed by forming via holes, forming diffusion barriers 150a and 151a, depositing the metal material to be buried, and planarizing the material. Diffusion barriers 150a and 151a can be TiN, TaN, etc., and the metal material can include conductive materials such as W, Al, Cu, etc.

[0193] refer to Figure 14B A preliminary conductive material layer 170P with a predetermined area can be formed on the upper surface of the first interlayer insulating layer 160.

[0194] The initial conductive material layer 170P may include a material different from the substrate 101, and as an example, the initial conductive material layer 170P may include at least one of IGZO, ZnO, In2O3, TiO2, etc. as an oxide semiconductor, or may include polycrystalline silicon or graphene. When the conductive material layer 170 may include graphene, the conductive material layer 170 may be implemented to have a thickness smaller than when using another material.

[0195] An undoped preliminary conductive material layer 170P can be formed by deposition to have a first thickness t1. When the preliminary conductive material layer 170P comprises an oxide semiconductor (e.g., IGZO), low-temperature deposition can be performed to protect the underlying circuit elements and substrate 101.

[0196] An upper gate insulating layer 173 covering a preliminary conductive material layer 170P can be deposited on the first interlayer insulating layer 160. The upper gate insulating layer 173 may include silicon oxide or silicon oxynitride.

[0197] A gate electrode 175 may be deposited on the upper gate insulating layer 173. The gate electrode 175 may include the same material as the gate electrode 125 on the substrate 101, may include doped polysilicon, and may include other metals.

[0198] refer to Figure 14C The source portion 170S and the drain portion 170D can be formed by ion implantation of conductive impurities using the gate electrode 175 as a mask pattern.

[0199] The source portion 170S and the drain portion 170D can be doped from the upper surface to the lower surface of the conductive material layer 170 by overdoping conductive impurities, and an undoped channel portion 170C can be formed in the region overlapping with the gate electrode 125.

[0200] refer to Figure 14D It can form an upper interconnect 158, and can form joining structures 166 and 169, and as... Figure 5In this process, a second structure L2 can be formed on the upper surface, and an optical unit 180 can be formed on the other surface S2 of the substrate 101, thereby forming Figure 5 Image sensor 1 in the image sensor.

[0201] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. An image sensor, the image sensor comprising: A substrate, the substrate including pixel regions, each pixel region including a photodiode; A floating diffusion region is disposed on one surface of the substrate in each pixel region and configured to store charge transferred from the photodiode; A circuit element configured to transmit an optoelectronic signal based on the charge in the floating diffusion region; as well as A first interlayer insulating layer covers the floating diffusion region on one surface of the substrate. Wherein, at least one of the circuit elements includes: A conductive material layer, wherein the conductive material layer is disposed on the first interlayer insulating layer and includes a source region and a drain region; and A gate electrode is disposed on the conductive material layer between the source region and the drain region. The source region is connected to one of the pixel regions, and the drain region is connected to another pixel region within the pixel region.

2. The image sensor according to claim 1, wherein, The source and drain regions of the conductive material layer include semiconductors containing impurities of a first conductivity type.

3. The image sensor according to claim 1, further comprising: A first isolation pattern is configured in the substrate to isolate the photodiode. The conductive material layer overlaps perpendicularly with at least a portion of the first isolation pattern.

4. The image sensor according to claim 1, wherein, The lower surface of the conductive material layer is spaced apart from one of the surfaces of the substrate by a predetermined distance.

5. The image sensor according to claim 1, wherein, The conductive material layer comprises a material different from that of the substrate.

6. The image sensor according to claim 1, wherein, The conductive material layer comprises an oxide semiconductor or polycrystalline silicon, and the substrate comprises monocrystalline silicon.

7. The image sensor according to claim 1, wherein, At least one of the circuit elements connects to or blocks the floating diffusion area of ​​an adjacent pixel area.

8. The image sensor according to claim 7, wherein, The adjacent pixel regions have different areas.

9. The image sensor according to claim 7, in, The adjacent pixel region includes: A first pixel region, the first pixel region including a first photodiode; and The second pixel region includes a second photodiode and has an area smaller than that of the first pixel region. Wherein, the drain region of the conductive material layer is connected to the first floating diffusion region of the first pixel region, and the source region of the conductive material layer is connected to the second floating diffusion region of the second pixel region.

10. The image sensor of claim 1, further comprising a contact plug electrically connected to the circuit element, and in, The contact plug is in contact with the lower surface of the conductive material layer.

11. The image sensor of claim 1, further comprising an upper insulating layer located between the conductive material layer and the substrate, and in, No interconnection structure is provided in the upper insulating layer.

12. The image sensor according to claim 1, wherein, The gate electrode is located at a horizontal height higher than the upper surface of the conductive material layer.

13. The image sensor of claim 1, further comprising a first isolation pattern in the substrate configured to isolate the photodiode, and in, The conductive material layer is offset from the first isolation pattern between the one pixel region and the other pixel region, which are respectively electrically connected to the source region and the drain region.

14. The image sensor according to claim 1, wherein, Another circuit element is configured as a dual-conversion gain transistor comprising the gate electrode and the conductive material layer, wherein the conductive material layer is commonly connected to a floating diffusion region of an adjacent pixel region.

15. An image sensor, the image sensor comprising: A substrate, the substrate including a first pixel region and a second pixel region, the first pixel region including a first photodiode, and the second pixel region including a second photodiode; A first isolation pattern defines a first pixel region and a second pixel region in the substrate; A first floating diffusion region is located on a surface of the substrate and is configured to store charge transferred from the first photodiode in the first pixel region; A second floating diffusion region is located on one surface of the substrate and is configured to store charge transferred from the second photodiode in the second pixel region; A source follower transistor, the source follower transistor being located on one surface of the substrate and configured to amplify the charge of the first floating diffusion region and the charge of the second floating diffusion region and to transmit a signal; A first interlayer insulating layer covers the source follower transistor, the first floating diffusion region, and the second floating diffusion region on the one surface of the substrate. as well as A switching element is disposed on the first interlayer insulating layer and overlaps perpendicularly with the first isolation pattern located between the first pixel region and the second pixel region. The switching element includes a gate electrode and a conductive material layer, wherein the conductive material layer includes a source region and a drain region located on both sides of the gate electrode. The drain region and the source region are electrically connected to the first floating diffusion region and the second floating diffusion region, respectively.

16. The image sensor according to claim 15, wherein, The area of ​​the first pixel region is larger than the area of ​​the second pixel region.

17. The image sensor according to claim 15, wherein, The conductive material layer spans the first isolation pattern located between the first pixel region and the second pixel region, the drain region on one side is disposed on the first pixel region, and the source region on the other side is disposed on the second pixel region.

18. The image sensor according to claim 15, wherein, The lower surface of the conductive material layer is physically separated from one surface of the substrate.

19. The image sensor according to claim 15, wherein, The source and drain regions of the conductive material layer are doped with conductive impurities from the top to the bottom surface.

20. An image sensor, the image sensor comprising: A pixel array comprising a plurality of pixel regions arranged in a direction parallel to a surface of a substrate, each of the plurality of pixel regions comprising at least one photodiode located in the substrate, a color filter disposed on another surface of the substrate opposite to the one surface, and at least one element disposed on the one surface. as well as A logic circuit configured to acquire pixel signals from the plurality of pixel regions. The pixel array includes: A floating diffusion region is disposed in each of the plurality of pixel regions on the one surface of the substrate and configured to store charge transferred from the photodiode; The at least one element is configured to transmit photoelectric signals based on the charge of the floating diffusion region; and A first interlayer insulating layer covers the floating diffusion region on one surface of the substrate. Wherein, the at least one element includes: A conductive material layer, wherein the conductive material layer is disposed on the first interlayer insulating layer and includes a source region and a drain region; and A gate electrode is disposed on the conductive material layer between the source region and the drain region. The source region is connected to one of the plurality of pixel regions, and the drain region is connected to another of the plurality of pixel regions.

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