Cmos image sensor and method of manufacturing the same

Abstract

The application discloses a CMOS image sensor, comprising: a substrate having opposite front and back surfaces; a photodiode extending from the back surface of the substrate into the substrate; a deep trench capacitor arranged in a trench of the substrate, the trench extending from the front surface of the substrate into the substrate; a transfer gate arranged on the front surface of the substrate; and an interconnection structure arranged on the front surface of the substrate, the deep trench capacitor and the transfer gate being electrically connected through the interconnection structure when the CMOS image sensor is in operation. The deep trench capacitor structure is constructed on the front surface of the substrate, which greatly improves the full-well capacity of the pixel, and the shallow photodiode and the deep photodiode work cooperatively, which effectively alleviates the tailing effect during signal reading and effectively suppresses the charge overflow phenomenon.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a CMOS image sensor and its manufacturing method. Background Technology

[0002] With the continuous advancement of integrated circuit manufacturing processes and the development of fields such as artificial intelligence, the application of Complementary Metal-Oxide-Semiconductor (CMOS) image sensors is becoming increasingly widespread. As the pixel size of image sensors continues to shrink, higher demands are placed on the photoelectric conversion and charge storage capabilities within the pixels to achieve higher resolution and imaging quality. Currently, the 4T (Four-Transistor, 4T) active pixel structure has become the mainstream solution due to its excellent reset efficiency and low noise characteristics. (Reference) Figure 1 The 4T active pixel structure is mainly composed of a reset transistor (RST), a transfer gate (TG), a source follower (SF), and a row select transistor (RS), and works in conjunction with a photodiode (PD) and a floating diffusion (FD) region.

[0003] Although the aforementioned 4T architecture is mature and widely used, its single-transfer tube design still faces physical bottlenecks. Specifically, during the charge transfer stage, due to the potential barrier formed when the TG is off, it is often difficult to completely deplete the photogenerated charge within the PD, resulting in some electrons remaining within the PD. These residual charges are slowly released after exposure, easily causing a trailing effect, leading to image retention and hysteresis distortion. Furthermore, since the charge-voltage conversion in the traditional 4T structure relies on a shallow floating diffusion region, its inherent capacitance, i.e., full-well capacity, is limited. When the light is strong or the exposure time is too long, the converted electrons are very likely to exceed the upper limit of the FD's well capacity and overflow to surrounding pixels, causing blooming in the readout image and resulting in severe distortion of bright details. Summary of the Invention

[0004] This application provides a CMOS image sensor and its manufacturing method, which can solve the problems of trailing effect and highlight overflow in the traditional 4T pixel structure as the pixel size of image sensors continues to shrink in related technologies.

[0005] On one hand, embodiments of this application provide a CMOS image sensor, including: A substrate having opposing front and back sides; A photodiode, the photodiode extending from the back side of the substrate into the substrate; A deep trench capacitor is disposed in a trench in the substrate, the trench extending from the front side of the substrate into the substrate; A transfer gate is disposed on the front side of the substrate; An interconnect structure is disposed on the front side of the substrate, and when the CMOS image sensor is in operation, the deep trench capacitor and the transfer gate are electrically connected through the interconnect structure.

[0006] In some embodiments, the photodiode includes a deep photodiode and a shallow photodiode, wherein the shallow photodiode is located on the side closer to the front side of the substrate, and the deep photodiode is located below the shallow photodiode and closer to the back side of the substrate.

[0007] In some embodiments, the deep trench capacitor includes a dielectric layer and a conductive layer sequentially from the inner wall of the trench inwards. In some embodiments, the image sensor further includes a color filter layer and a microlens, the color filter layer and the microlens being located on the back side of the substrate, wherein the color filter layer is located between the microlens and the photodiode.

[0008] In some embodiments, the filter layer and the microlens overlap the photodiode in a direction perpendicular to the back surface of the substrate.

[0009] On the other hand, embodiments of this application provide a method for manufacturing a CMOS image sensor, comprising at least the following steps: A substrate is provided, the substrate having opposing front and back sides, and a groove is formed on the front side of the substrate; A dielectric layer is formed, which covers the front side of the substrate and the surface exposed by the trench; A conductive layer is formed on the dielectric layer; A planarization process is performed to remove the dielectric and conductive layers outside the trenches, and the dielectric and conductive layers inside the trenches constitute a deep trench capacitor. A photodiode is formed in the substrate on the back side; A transfer gate is formed on the front side of the substrate; An interconnect structure is formed on the front side of the substrate so that the deep trench capacitor is electrically connected to the transfer gate when the CMOS image sensor is in operation.

[0010] In some embodiments, the photodiode includes a deep photodiode and a shallow photodiode, wherein the shallow photodiode is located on the side closer to the front side of the substrate, and the deep photodiode is located below the shallow photodiode and closer to the back side of the substrate; Forming a photodiode in the substrate on the back side includes: Ion implantation is performed to form a deep photodiode extending inward from the back side of the substrate; Ion implantation is performed to form a shallow photodiode extending inward from the back side of the substrate.

[0011] In some embodiments, the dielectric layer is made of silicon dioxide.

[0012] In some embodiments, the material of the conductive layer includes polycrystalline silicon.

[0013] In some embodiments, the manufacturing method further includes: A color filter layer and a microlens are formed on the back side of the substrate. The color filter layer is located between the microlens and the photodiode. The color filter layer and the microlens overlap with the photodiode in a direction perpendicular to the back side.

[0014] The technical solution of this application has at least the following advantages: By constructing a deep trench capacitor structure on the front side of the substrate, the full-well capacity of the pixels is significantly improved. Furthermore, through the synergistic operation of shallow and deep photodiodes, the trailing effect during signal readout is effectively mitigated, and charge overflow is effectively suppressed, ensuring complete preservation of image details in the highlight areas.

[0015] Furthermore, by integrating the manufacturing of deep trench capacitors into the front-end process stage, the compatibility with existing isolation trench processes is fully utilized, significantly reducing the overall process implementation threshold and manufacturing cost, and improving the mass production feasibility of the technical solution.

[0016] Furthermore, by adopting a back-illuminated architecture, the interconnect structure on the front of the substrate is completely avoided from the photosensitive area, creating an optical path between the microlens and the photodiode without physical obstruction. This significantly reduces the reflection and absorption losses of photons during transmission, achieving high optical coupling efficiency. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a circuit diagram of a 4T pixel structure in the prior art.

[0019] Figure 2 This is a flowchart illustrating a method for manufacturing a CMOS image sensor according to an exemplary embodiment of this application.

[0020] Figures 3 to 7 This is a cross-sectional schematic diagram of a method for manufacturing a CMOS image sensor provided in an exemplary embodiment of this application. Detailed Implementation

[0021] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0024] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0025] refer to Figure 7 This illustrates a cross-sectional schematic diagram of a CMOS image sensor provided in an exemplary embodiment of this application. Figure 7 As shown, the device includes: The substrate 100 has a front side 100a and a back side 100b. For example, the present invention is a backside-illuminated (BSI) CMOS image sensor, wherein the front side 100a is the side on which the semiconductor elements and interconnects of the CMOS image sensor are pre-formed, and the back side 100b is the side on which light is received.

[0026] Photodiode 110 extends into substrate 100 from the back side 100b of the substrate; optionally, photodiode 110 includes a deep photodiode 111 and a shallow photodiode 112, wherein the shallow photodiode 112 is located on the side near the front side 100a of the substrate, and the deep photodiode 111 is located below the shallow photodiode 112 and near the back side 100b of the substrate.

[0027] A deep trench capacitor 130 is disposed in a trench of a substrate, the trench extending from the front side 100a of the substrate into the substrate 100; optionally, the deep trench capacitor 130 includes a dielectric layer 131 and a conductive layer 132, the deep trench capacitor 130 including the dielectric layer 131 and the conductive layer 132 sequentially from the inner wall of the trench inward.

[0028] The transfer gate 120 is disposed on the front side 100a of the substrate. Optionally, the transfer gate 120 is designed to span over the photodiode 110 and the deep trench capacitor 130.

[0029] An interconnect structure 140 is disposed on the front side of the substrate 100. When the CMOS image sensor is working, the deep trench capacitor 130 and the transfer gate 120 are electrically connected through the interconnect structure 140. Optionally, a heavily doped region (not shown in the figure) is disposed in the front side 100a of the substrate next to the transfer gate 120, and the deep trench capacitor 130 and the transfer gate 120 are electrically connected through the heavily doped region.

[0030] Optionally, the CMOS image sensor further includes a color filter layer 150 and a microlens 160, which are located on the back side 100b of the substrate. The color filter layer 150 is located between the photodiode 110 and the microlens 160, and the color filter layer 150 and the microlens 160 overlap with the photodiode 110 in a direction perpendicular to the back side 100b of the substrate.

[0031] When the CMOS image sensor of the present invention is working, it specifically performs the following process: First, in the integration stage, light is incident from the back side of the substrate 100b, passes through the microlens 160 and the color filter layer 150 in sequence, and enters the photodiode 110 region; at this time, the shallow photodiode 112 and the deep photodiode 111 work together to convert incident light of different wavelengths into photogenerated electrons using PN junctions of different depths; then, in the charge transfer stage, a high-level voltage is applied to the transfer gate 120, so that an inversion channel is formed on the semiconductor surface below the transfer gate 120. Under the action of the lateral electric field, the photogenerated charge stored in the photodiode 110 is transferred to the deep trench capacitor 130; subsequently, in the charge storage and conversion stage, the deep trench capacitor 130 stores the transferred photogenerated charge and converts the charge into a corresponding voltage signal; finally, in the signal readout stage, the source follower (not shown in the figure) located on the front side of the substrate 100a senses the voltage change on the deep trench capacitor 130 through the interconnect structure 140, and after amplification, it is output to the external readout circuit by the row selector (not shown in the figure). After the current frame signal is read, the reset transistor (not shown in the figure) is turned on again to reset the deep trench capacitor 130. This process is repeated to complete the acquisition of continuous images.

[0032] This invention utilizes the large surface area of ​​the trench structure to form a deep trench capacitor with a large aspect ratio and side area between the dielectric layer and the conductive layer. By replacing the traditional shallow floating diffusion region capacitor with a deep trench capacitor, the full-well capacity is significantly improved. At the same time, the large capacitance characteristic reduces the voltage fluctuation amplitude caused by unit charge, effectively mitigates the tailing effect during signal readout, and effectively suppresses charge overflow under high light conditions.

[0033] In one exemplary embodiment, this application also provides a method for manufacturing a CMOS image sensor, referring to... Figure 2 It illustrates a flowchart of a manufacturing method for a CMOS image sensor provided in an exemplary embodiment of this application, the manufacturing method comprising: Step S1: Provide a substrate having a front and a back side, and form a groove on the front side of the substrate; refer to Figure 3 The diagram shows a cross-sectional view of a substrate provided in an exemplary embodiment of this application after step S1. The substrate 100 has a front side 100a and a back side 100b, and a groove 200 is formed on the front side of the substrate.

[0034] Optionally, the material of the substrate 100 may include silicon, germanium, indium antimonide, indium arsenide, indium phosphide, gallium nitride, gallium arsenide, gallium antimonide, lead telluride, or combinations thereof. Trenchings can be used to separate and define pixel units. The type of trench can be designed as a predetermined structure as needed, such as shallow trench isolation (STI), deep trench isolation (DTI), or local oxide of silicon (LOCOS). The shape of the trench can be designed as a predetermined geometry as needed, such as a rectangular, inverted trapezoidal, or other polygonal shape in vertical cross-section.

[0035] Step S2: Form a dielectric layer that covers the front side of the substrate and the exposed surface of the trench; Step S3: Form a conductive layer on the dielectric layer; refer to Figure 4 The diagram shows a cross-sectional view after steps S2 and S3 in an exemplary embodiment of this application. A dielectric layer 131 is formed, covering the front side 100a of the substrate and the exposed surface of the trench 200; then a conductive layer 132 is formed on the dielectric layer 131.

[0036] Optionally, the dielectric layer 131 may be made of oxides, nitrides, or high dielectric constant materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), or tantalum oxide (Ta2O5). In this embodiment, the dielectric layer 131 is made of silicon dioxide (SiO2). The conductive layer 132 may be made of titanium nitride (TiN) or polycrystalline silicon. In this embodiment, the conductive layer 133 is made of polycrystalline silicon.

[0037] Step S4: Perform planarization to remove the dielectric and conductive layers outside the trench. The dielectric and conductive layers inside the trench form a deep trench capacitor. refer to Figure 5 The diagram shows a cross-sectional view after step S4 in an exemplary embodiment of this application. Exemplarily, a chemical mechanical polishing (CMP) process can be used for planarization to remove the dielectric layer 131 and conductive layer 132 outside the trench, where the dielectric layer 131 and conductive layer 132 within the trench constitute a deep trench capacitor 130.

[0038] Through steps S1 to S4, a deep trench capacitor, which can replace the floating diffusion region capacitor, is formed on the front side of the substrate. This deep trench capacitor offers flexible structural design; the trench geometry can be adjusted to a predetermined structure according to the pixel layout requirements. Furthermore, since the trench depth and sidewall profile are controllable, it achieves excellent electrical isolation between pixels while effectively reducing lateral crosstalk. In addition, this embodiment integrates the fabrication of the deep trench capacitor into the front-end of line (FEOL) stage, ensuring full compatibility with existing trench isolation processes. This avoids the high difficulty associated with performing corresponding steps in the back-end of line (BEOL) stage, significantly reducing the overall process implementation difficulty and manufacturing cost.

[0039] Step S5: Form a photodiode in the substrate on the back side; Optionally, the photodiode includes a deep photodiode and a shallow photodiode, with the shallow photodiode located on the side closer to the front of the substrate and the deep photodiode located below the shallow photodiode and closer to the back of the substrate.

[0040] The method of forming a photodiode in the substrate 100 on the back side includes: Step S51: Ion implantation is performed to form a deep photodiode extending inward from the back side of the substrate; Step S52: Ion implantation is performed to form a shallow photodiode extending inward from the back side of the substrate.

[0041] refer to Figure 6 The diagram illustrates a cross-sectional view after step S5 in an exemplary embodiment of this application. The photodiode 110 includes a deep photodiode 111 and a shallow photodiode 112. The shallow photodiode 112 is located on the side near the front side 100a of the substrate, and the deep photodiode 111 is located below the shallow photodiode 112 and near the back side 100b of the substrate. Heavy doping and light doping ion implantation processes are performed, using different implantation energies to form photodiodes with different junction depths: first, heavy doping ion implantation is performed to form the deep photodiode 111 extending inward from the back side of the substrate, followed by light doping ion implantation to form the shallow photodiode 112 extending inward from the back side of the substrate.

[0042] Specifically, in the process implementation of this embodiment, the difference between deep photodiode 111 and shallow photodiode 112 lies in the energy and dosage of ion implantation: high implantation energy is used to form deep photodiode 111, allowing impurity ions to penetrate deep into the substrate; low implantation energy is used to form shallow photodiode 112, causing impurity ions to be distributed on the side closer to the front of the substrate. Furthermore, the lateral boundaries and contours of the doped regions are defined by patterned photoresist; after ion implantation, lattice damage is repaired through thermal annealing (tempering) and the incorporated impurity ions are activated, thereby giving them photoconductive properties.

[0043] Step S6: Form a transfer gate on the front side of the substrate; Step S7: An interconnect structure is formed on the front side of the substrate so that the deep trench capacitor is electrically connected to the transfer gate when the CMOS image sensor is working.

[0044] refer to Figure 7 The diagram shows a cross-sectional view after steps S6 and S7 in an exemplary embodiment of this application. A transfer gate 120 is formed on the front side of the substrate, and then an interconnect structure 140 is formed on the front side of the substrate so that a deep trench capacitor 130 is electrically connected to the transfer gate 120 when the CMOS image sensor is in operation.

[0045] Optionally, the manufacturing method of a CMOS image sensor also includes: In step S8, a color filter layer and a microlens are formed on the back side of the substrate. The color filter layer is located between the microlens and the photodiode. The color filter layer and the microlens overlap with the photodiode in the direction perpendicular to the back side.

[0046] Continue to refer to Figure 7 A color filter layer 150 and a microlens 160 are formed on the back side of the substrate. The color filter layer is located above the photodiode, and the microlens is located above the color filter layer. The color filter layer and the microlens overlap with the photodiode in the direction perpendicular to the back side.

[0047] Through steps S5 to S8, a photoelectric conversion structure consisting of a stack of shallow and deep photodiodes is formed on the back side of the substrate. The shallow photodiodes are mainly used to absorb short-wavelength incident light, while the deep photodiodes are mainly used to absorb long-wavelength incident light. The increased depletion region volume significantly improves the full-well capacity of the pixel. The design of the deep and shallow junctions working together effectively suppresses charge overflow in high-light environments. In addition, the interconnect structure on the front side of the substrate completely avoids the photosensitive area, so that only the necessary color filter layer exists between the microlens and the photodiode. There are no opaque metal wirings or thick dielectric layers that block light, thus creating an optical path without physical obstruction, reducing the reflection and absorption loss of photons during transmission, and achieving high optical coupling efficiency.

[0048] In summary, this invention significantly improves the full-well capacity of pixels by constructing a deep trench capacitor structure on the front side of the substrate. Furthermore, through the synergistic operation of shallow and deep photodiodes, it effectively alleviates the trailing effect during signal readout, effectively suppresses charge overflow, and ensures complete preservation of image details in highlight areas.

[0049] Furthermore, by integrating the manufacturing of deep trench capacitors into the front-end process stage, this invention fully utilizes the compatibility with existing isolation trench processes, significantly reducing the overall process implementation threshold and manufacturing cost, and improving the mass production feasibility of the technical solution.

[0050] Furthermore, by employing a back-illuminated architecture, the interconnect structure on the front side of the substrate is completely avoided from the photosensitive area, thus constructing an optical path between the microlens and the photodiode without physical obstruction. This significantly reduces the reflection and absorption losses of photons during transmission, achieving high optical coupling efficiency.

[0051] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A CMOS image sensor, characterized in that, include: A substrate having opposing front and back sides; A photodiode, the photodiode extending from the back side of the substrate into the substrate; A deep trench capacitor is disposed in a trench in the substrate, the trench extending from the front side of the substrate into the substrate; A transfer gate is disposed on the front side of the substrate; An interconnect structure is disposed on the front side of the substrate, and when the CMOS image sensor is in operation, the deep trench capacitor and the transfer gate are electrically connected through the interconnect structure.

2. The image sensor according to claim 1, characterized in that, The photodiode includes a deep photodiode and a shallow photodiode, wherein the shallow photodiode is located on the side closer to the front side of the substrate, and the deep photodiode is located below the shallow photodiode and closer to the back side of the substrate.

3. The image sensor according to claim 1, characterized in that, The deep trench capacitor comprises a dielectric layer and a conductive layer sequentially from the inner wall of the trench inward.

4. The image sensor according to claim 1, characterized in that, The image sensor further includes a color filter layer and a microlens, the color filter layer and the microlens being located on the back side of the substrate, wherein the color filter layer is located between the microlens and the photodiode.

5. The image sensor according to claim 4, characterized in that, The filter layer and the microlens overlap with the photodiode in a direction perpendicular to the back surface of the substrate.

6. A method for manufacturing a CMOS image sensor, characterized in that, At least the following steps are included: A substrate is provided, the substrate having opposing front and back sides, and a groove is formed on the front side of the substrate; A dielectric layer is formed, which covers the front side of the substrate and the surface exposed by the trench; A conductive layer is formed on the dielectric layer; A planarization process is performed to remove the dielectric and conductive layers outside the trenches, and the dielectric and conductive layers inside the trenches constitute a deep trench capacitor. A photodiode is formed in the substrate on the back side; A transfer gate is formed on the front side of the substrate; An interconnect structure is formed on the front side of the substrate so that the deep trench capacitor is electrically connected to the transfer gate when the CMOS image sensor is in operation.

7. The manufacturing method according to claim 6, characterized in that, The photodiode includes a deep photodiode and a shallow photodiode, wherein the shallow photodiode is located on the side closer to the front side of the substrate, and the deep photodiode is located below the shallow photodiode and closer to the back side of the substrate; Forming a photodiode in the substrate on the back side includes: Ion implantation is performed to form a deep photodiode extending inward from the back side of the substrate; Ion implantation is performed to form a shallow photodiode extending inward from the back side of the substrate.

8. The manufacturing method according to claim 6, characterized in that, The dielectric layer is made of silicon dioxide.

9. The manufacturing method according to claim 6, characterized in that, The conductive layer is made of polycrystalline silicon.

10. The manufacturing method according to claim 6, characterized in that, The manufacturing method further includes: A color filter layer and a microlens are formed on the back side of the substrate. The color filter layer is located between the microlens and the photodiode. The color filter layer and the microlens overlap with the photodiode in a direction perpendicular to the back side.

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