Integrated slit probe and method of making same

Abstract

The application relates to the technical field of integrated optoelectronic devices, in particular to an integrated-slit detector and a preparation method thereof, wherein the integrated-slit detector comprises a detection chip with a top surface and a bottom surface arranged oppositely; and a slit is arranged through the detection chip, and the slit penetrates through the top surface and the bottom surface of the detection chip along the thickness direction of the detection chip. The integrated-slit detector disclosed in the application is characterized in that the slit is arranged through the detection chip of the detector, so that the slit is fixedly arranged in the detector, the probability of accidental displacement of the slit is reduced, and the real-time monitoring of the position matching degree of the slit and a primary image plane of spectral imaging is realized through the imaging capability of the detector itself and the mechanical characteristics of the fixed arrangement of the slit and the detector, so that the problem of defocus caused by the change of the relative position of the slit and the primary image plane of spectral imaging is effectively inhibited, the risk of spectral aliasing and the reduction of the signal-to-noise ratio of the spectral imaging system is reduced, and the spectral imaging precision of the detector is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a detector with an integrated slit and its fabrication method. Background Technology

[0002] Hyperspectral imaging technology is widely used in remote sensing, industrial inspection, agricultural monitoring, and medical imaging. Traditional hyperspectral imaging systems employ a push-broom architecture, primarily composed of the following components: a primary imaging lens: imaging the target using traditional optical imaging methods; considering the spectrometer interface, a telecentric image-side lens is generally used; a slit: located at the focal plane of the primary imaging lens, used to select a linear region of light to enter the spectrometer; a spectrometer: using dispersive elements (gratings, prisms, etc.) to disperse the light passing through the slit according to wavelength and refocus it for imaging; and an area array detector: receiving the image carrying spectral information after re-imaging. The signal of each row of pixels is a single-band image corresponding to the slit image. Finally, through platform movement, a two-dimensional image is completed in space, and combined with continuous spectral information, a hyperspectral image "cube" is formed. In existing technologies, the slit, as an independent optical element, is spatially separated from the detector and fixed and aligned using precision mechanical structures. Existing technologies have the following drawbacks: First, the slit is fixed and assembled using a mechanical structure, making it impossible to monitor the matching or alignment status of the slit and the focal plane of the spectral imaging system in real time and continuously. Factors such as temperature changes, long-term stress release, and transportation vibrations can cause changes in the relative position of the slit and the focal plane of the spectral imaging system, leading to inaccurate alignment or defocus. This allows stray light that should be filtered out to pass through the slit, severely affecting filtering capabilities, causing spectral aliasing, and reducing spectral imaging accuracy. Furthermore, defocus causes the slit image on the detector to form a blurred and broadened spot, reducing the system's spectral resolution. The blurred and broadened slit image also causes energy dispersion in the optical signal, weakening the effective signal strength received by the detector and consequently reducing the signal-to-noise ratio.

[0003] Second, it cannot achieve automatic focusing of the focal plane of the slit and spectral imaging system. After defocusing occurs, it cannot achieve real-time adjustment and continuous monitoring of the relative position of the focal plane of the slit and spectral imaging system.

[0004] Third, in existing technologies, the slit is treated as an independent optical element and is spatially separated from the detector, which easily increases the system volume and reduces the system's space utilization. Summary of the Invention

[0005] The purpose of this invention is to provide an integrated slit detector and its fabrication method, so as to solve the problem that the spectral accuracy of detectors in the prior art still needs to be improved.

[0006] The technical solution of the present invention is: a detector with an integrated slit, comprising: a detector chip having a top surface and a bottom surface disposed opposite to each other; and a slit disposed through the detector chip, the slit penetrating the top surface and the bottom surface of the detector chip along the thickness direction of the detector chip.

[0007] Preferably, the slit has a light inlet located on the top surface of the detector chip; the slit also has a light outlet located on the bottom surface of the detector chip; and along a direction parallel to the surface of the detector chip, the lateral dimension of the light outlet is greater than or equal to the lateral dimension of the light inlet.

[0008] Preferably, along a direction perpendicular to the surface of the detector chip, the detector chip includes a photosensitive layer wafer, an interconnect layer, and a circuit layer wafer stacked sequentially. The photosensitive layer wafer is used to convert optical signals into electrical signals, and the circuit layer wafer is used to convert electrical signals into digital signals. The interconnect layer has a first surface and a second surface disposed opposite to each other. The first surface is in direct contact with the photosensitive layer wafer, and the second surface is in direct contact with the circuit layer wafer. The interconnect layer is used to electrically connect the photosensitive layer wafer and the circuit layer wafer. The detector chip also includes a redistribution layer, which is disposed on the side of the photosensitive layer wafer that is in direct contact with the first surface and the side of the circuit layer wafer that is in direct contact with the second surface. The redistribution layer includes metal wiring, one end of which is connected to the edge of the slit, and the other end extends in a direction away from the slit.

[0009] Preferably, the detector further includes a substrate, the detection chip is disposed on the substrate, and the substrate is electrically connected to the detection chip, the substrate being used to support the detection chip; the slit extends along the thickness direction of the detection chip and is disposed through the substrate.

[0010] This application also discloses a method for fabricating a detector with an integrated slit, comprising: providing a photosensitive layer wafer; forming a first slit segment in the photosensitive layer wafer, the first slit segment penetrating the photosensitive layer wafer; providing a circuit layer wafer; forming a second slit segment in the circuit layer wafer, the second slit segment penetrating the circuit layer wafer; forming an interconnect layer on the circuit layer wafer, the interconnect layer having a third slit segment, the third slit segment and the second slit segment being coaxially connected; bonding the photosensitive layer wafer and the circuit layer wafer to form a detector chip, wherein the first slit segment, the second slit segment and the third slit segment are connected, and the first slit segment, the second slit segment and the third slit segment constitute a slit.

[0011] Preferably, the processes for forming the first slit segment in the photosensitive layer wafer and the second slit segment in the circuit layer wafer both include: deep reactive ion etching or laser etching.

[0012] Preferably, after forming the first slit segment in the photosensitive layer wafer and before bonding the photosensitive layer wafer and the circuit layer wafer, the fabrication method further includes: the photosensitive layer wafer having a first top surface and a first bottom surface disposed opposite to each other; forming a first redistribution layer on the first bottom surface of the photosensitive layer wafer; the first redistribution layer includes metal wiring; one end of the metal wiring is connected to the edge of the first slit segment, and the other end extends in a direction away from the first slit segment; after forming the second slit segment in the circuit layer wafer and before bonding the photosensitive layer wafer and the circuit layer wafer, the fabrication method further includes: the circuit layer wafer having a second top surface and a second bottom surface disposed opposite to each other; forming a second redistribution layer on the second top surface of the circuit layer wafer; the second redistribution layer includes metal wiring; one end of the metal wiring is connected to the edge of the second slit segment, and the other end extends in a direction away from the second slit segment.

[0013] Preferably, after bonding the photosensitive layer wafer and the circuit layer wafer to form a detector chip, the fabrication method further includes: providing a substrate, wherein the detector chip is disposed on the substrate and the substrate is electrically connected to the detector chip, and the substrate is used to support the detector chip; forming a fourth slit segment in the substrate, the fourth slit segment being disposed through the substrate, and the fourth slit segment communicating with the second slit segment.

[0014] Preferably, in the steps of forming a first redistribution layer on the first bottom surface of the photosensitive layer wafer and forming a second redistribution layer on the second top surface of the circuit layer wafer, stress-compensating vias and redundant metal bridging structures are provided in the first redistribution layer and the second redistribution layer.

[0015] Compared with the prior art, the advantages of the present invention are: (1) The detector with integrated slit disclosed in this application, wherein the slit is disposed through the detector chip, so that the slit is fixedly disposed inside the detector, which helps to reduce the probability of the slit being accidentally displaced, thereby effectively suppressing the problem of defocusing caused by the change in the relative position of the slit and the spectral imaging primary image plane spectral imaging system, reducing the risk of spectral aliasing and signal-to-noise ratio reduction in the spectral imaging system, and thus helping to improve the spectral imaging accuracy of the detector.

[0016] (2) The detector with integrated slit disclosed in this application, wherein the slit is disposed inside the detector, which is beneficial to reduce the volume of the detection system and improve the space utilization and integration of the detection system including the detector.

[0017] (3) The detector with integrated slit disclosed in this application, wherein the slit is fixedly disposed in the detector chip, and through the detector’s own imaging capability and the mechanical characteristics of the slit and the detector being fixedly disposed, real-time monitoring of the position matching degree between the slit and the primary image plane of the spectral imaging system is realized. Since the slit is fixedly disposed inside the detector, when the position of the slit needs to be adjusted, the position of the slit can be adjusted accordingly by adjusting the position of the detector, which helps to reduce the difficulty of adjusting the slit position, thereby realizing real-time dynamic adjustment of the relative position of the slit and the focal plane of the spectral imaging system. Attached Figure Description

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments: Figure 1 This is a schematic cross-sectional view of a detector with an integrated slit as described in this invention. Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure along the A1-A2 direction; Figure 3 for Figure 1 A schematic diagram of the cross-sectional structure along the B1-B2 direction; Figure 4 This is a flowchart illustrating the fabrication method of an integrated slit detector according to the present invention.

[0019] Among them: 10. Detection chip; 11. Top surface; 12. Bottom surface; 13. Photosensitive layer wafer; 14. Interconnect layer; 15. Circuit layer wafer; 131. First bottom surface; 141. First surface; 142. Second surface; 151. First top surface; 20. Slit; 21. First slit segment; 22. Second slit segment; 23. Third slit segment; 24. Fourth slit segment; 211. Light inlet, 212. Light outlet; 41. Rerouting layer; 401. First rerouting layer; 402. Second rerouting layer; 411. Metal wiring; 412. Stress-compensated vias; 413. Redundant bridging structure. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to specific embodiments: To facilitate understanding, the application scenario of this application is first explained. In detection scenarios with high requirements for spectral imaging, traditional detectors and slits are placed separately. Due to the combined effects of temperature changes, long-term stress release, and transportation vibrations, the relative position of the slit and the primary focal plane of the spectral imaging system, i.e., the focal plane of the imaging lens, changes. This leads to inaccurate alignment or defocusing between the slit and the focal plane, and it is difficult to effectively monitor the relative position of the slit and the primary focal plane of the spectral imaging system. As a result, light that should pass through the slit is partially blocked, reducing the system's signal-to-noise ratio. Near-field light that should be filtered out also passes through the slit, causing spatial interference. At the same time, in the traditional method that only ensures the spatial imaging clarity of the end detector, if the slit plane does not coincide with the primary image plane, its conjugate relationship with the end detector will also cause defocusing, leading to spectral aliasing and ultimately reducing the accuracy of spectral imaging. Therefore, this application provides a detector with an integrated slit and its fabrication method.

[0021] like Figure 1 As shown, an integrated slit detector includes: a detector chip 10 having a top surface 11 and a bottom surface 12 disposed opposite to each other; and a slit 20 disposed through the detector chip 10, the slit 20 penetrating through the top surface 11 and the bottom surface 12 of the detector chip 10 along the thickness direction of the detector chip 10.

[0022] The detector chip 10 is used to convert the received optical signal into an electrical signal.

[0023] The detector chip 10 efficiently converts the light signal incident on its surface into an electrical signal that can be analyzed and imaged. Specifically, the detector chip 10 completes the photoelectric signal conversion based on the internal photoelectric effect of its semiconductor material.

[0024] As an example, the detector chip 10 is a complementary metal-oxide-semiconductor (CMOS) chip. The stacked CMOS chip adopts a parallel processing architecture, which is conducive to realizing the parallel processing of optical signals by the detector chip 10, thereby improving the processing efficiency of the detector chip 10 in photoelectric signal conversion. In addition, the stacked CMOS chip has a complementary transistor structure, which is conducive to reducing the static power consumption and dynamic power consumption of the detector chip 10, and is conducive to improving the service life and reliability of the detector chip 10.

[0025] Specifically, the detector chip 10 employs a stacked complementary metal-oxide-semiconductor (CMOS) chip. The stacked CMOS chip has a larger photosensitive area, which is beneficial for increasing the amount of light signal received by the detector chip 10, thereby improving its sensitivity and resolution. Furthermore, the stacked CMOS chip combines different functional layers, which helps to significantly reduce the physical size of the detector chip 10, further reducing the overall size of the detection system. In other embodiments, the detector chip may also employ a front-illuminated or back-illuminated CMOS chip.

[0026] The top surface 11 is used as the incident surface for incident rays.

[0027] The incident light enters the detector chip 10 from the top surface 11, which limits the orientation of the top surface 11 of the detector chip 10 toward the spectral imaging system. This reduces the possibility of the detector chip 10 being inverted or having installation position deviations during the detector fabrication process, and helps to improve the reliability of the detector.

[0028] The bottom surface 12 is used as the exit surface for incident light.

[0029] The bottom surface 12 and the top surface 11 are arranged opposite to each other, that is, the top surface 11 and the bottom surface 12 are arranged opposite each other in space along the thickness direction of the detector chip 10, forming a "top-in, bottom-out" vertical transmission structure. This allows the incident light to travel in a straight line along the thickness direction of the detector chip 10, avoiding the need to set the incident light path and the outgoing light path on the same side of the detector chip 10. This helps to simplify the spectral imaging system and the detector, and improve the structural integration of the detector.

[0030] The slit 20 is used to limit the cross-sectional shape and width of the incident light rays, forming a linear aperture.

[0031] The slit 20 limits the width of the beam, causing irregular incident light rays to form a linear aperture, precisely filtering and outputting monochromatic light of the desired specific wavelength.

[0032] The slit 20 is disposed through the detector chip 10 of the detector, so that the slit 20 is fixed inside the detector. This helps to reduce the probability of the slit 20 being accidentally displaced, thereby effectively suppressing the problem of defocusing caused by changes in the relative position of the slit 20 and the primary image plane of the spectral imaging, reducing the risk of spectral aliasing and reduced signal-to-noise ratio in the spectral imaging system, and thus helping to improve the spectral imaging accuracy of the detector.

[0033] The slit 20 is located inside the detector, which helps to reduce the size of the detection system and improve the space utilization and integration of the detection system including the detector.

[0034] It should be noted that the slit 20 is fixedly disposed in the detector chip 10, that is, the slit 20 has the mechanical property of being coplanar with the surface of the photosensitive layer wafer 13 of the detector chip 10.

[0035] It should also be noted that the position of the primary image plane and the focal plane in a spectral imaging system are... The detector achieves real-time monitoring of the positional matching degree between the slit and the primary image plane of the spectral imaging system by utilizing its own imaging capabilities and the mechanical characteristics of the fixed setting of the slit and the detector. Since the slit 20 is fixedly set inside the detector, when the position of the slit 20 needs to be adjusted, the position of the slit 20 can be adjusted accordingly by adjusting the position of the detector, which helps to reduce the difficulty of adjusting the position of the slit 20, thereby realizing real-time dynamic adjustment of the relative position of the slit 20 and the primary image plane of the spectral imaging system.

[0036] In some embodiments, the slit 20 has a light inlet 211, which is located on the top surface 11 of the detector chip 10; the slit 20 also has a light outlet 212, which is located on the bottom surface 12 of the detector chip 10.

[0037] The light inlet 211 is used as the inlet for incident light to enter the slit 20.

[0038] The light inlet 211 is located on the top surface 11 of the detector chip 10. The top surface 11 serves as the incident surface of the incident light, so that the light inlet 211 and the incident surface of the incident light are on the same side, reducing the difficulty of incident light.

[0039] like Figure 1 As shown, the light inlet 211 is located at the central axis of the top surface 11. The spectral imaging system that emits incident light adopts a coaxial system, which helps to reduce the difficulty of aligning the light inlet 211 with the optical axis of the spectral imaging system. This facilitates the perpendicular incidence of incident light into the light inlet 211, effectively suppressing off-axis aberrations caused by misalignment between the optical axis of the spectral imaging system and the light inlet 211. This also helps to improve the uniformity of the spectral resolution of the image formed by the slit 20. Furthermore, since the light inlet 211 is located at the central axis of the top surface 11, and the slit 20 is correspondingly positioned on the central axis of the detector chip 10 along the thickness direction, the photosensitive areas of the detector chip 10 on both sides of the slit 20 are symmetrically arranged along the thickness direction. This improves the uniformity of the light signal received by the detector chip 10 and avoids the problems of spectral distortion and decreased imaging spatial resolution caused by the asymmetry of the electrical signals converted and output by the detector chips 10 on both sides of the slit 20.

[0040] The light outlet 212 is used as the outlet for emitting incident light rays from the slit 20.

[0041] The light outlet 212 is located on the bottom surface 12 of the detector chip 10. The bottom surface 12 serves as the exit surface for the incident light, so that the light outlet 212 and the exit surface for the incident light are on the same side, reducing the difficulty of the incident light exiting.

[0042] It should be noted that the light inlet 211 is located at the central axis of the top surface 11, and the corresponding light outlet 212 is located at the central axis of the bottom surface 12.

[0043] In some embodiments, along a direction parallel to the surface of the detector chip 10, the lateral dimension of the light outlet 212 is greater than or equal to the lateral dimension of the light inlet 211.

[0044] like Figure 1 As shown, the inner diameter of the slit 20 gradually increases from the light inlet 211 to the light outlet 212. The incident light has a divergence angle, and the optical path of the incident light after entering the slit 20 diverges at a certain angle. The gradually increasing inner diameter of the slit 20 helps improve the matching degree between the incident light with its divergence angle and the sidewall of the slit 20. This effectively reduces the cutting effect of the vertical sidewall on the incident light with its divergence angle when the slit 20 uses a vertical sidewall, avoiding excessive loss of the incident light and allowing more incident light to pass through the slit 20, which is beneficial for improving the output signal strength of the detector. Simultaneously, it helps reduce the reflection and scattering of the incident light on the sidewall of the slit 20, effectively suppressing stray light and further improving the spectral resolution of the spectrometer imaging. In other embodiments, the inner diameter of the slit gradually increases from the light inlet to the light outlet, and the sidewall of the slit has a corresponding tilt angle.

[0045] In some embodiments, along a direction perpendicular to the surface of the detector chip 10, the detector chip 10 includes a photosensitive layer wafer 13, an interconnect layer 14, and a circuit layer wafer 15 stacked sequentially. The photosensitive layer wafer 13 is used to convert optical signals into electrical signals, and the circuit layer wafer 15 is used to convert electrical signals into digital signals. The interconnect layer 14 has a first surface 141 and a second surface 142 disposed opposite to each other. The first surface 141 is in direct contact with the photosensitive layer wafer 13, and the second surface 142 is in direct contact with the circuit layer wafer 15. The interconnect layer 14 is used to electrically connect the photosensitive layer wafer 13 and the circuit layer wafer 15.

[0046] The photosensitive layer wafer 13 is used to convert the optical signal received by the detector chip 10 into an electrical signal.

[0047] The photosensitive wafer 13 includes a photosensitive layer (not shown in the figure). This photosensitive layer uses a photosensitive material to absorb incident light and convert the optical signal into an electrical signal that the detector chip 10 can recognize and process. For example... Figure 2As shown, the slit 20 is positioned at the central axis of the surface of the photosensitive layer wafer 13, so that the photosensitive layer wafers 13 on both sides of the slit 20 have symmetrical and identical surface areas. This is beneficial to improving the uniformity of the light signal received by the photosensitive layer wafer 13, thereby improving the efficiency and consistency of the photoelectric signal conversion of the detector chips 10 on both sides of the slit 20. It also avoids the problems of spectral distortion and decreased imaging spatial resolution caused by the asymmetry of the electrical signals converted and output by the detector chips 10 on both sides of the slit 20.

[0048] In some embodiments, the photosensitive layer is made of silicon, gallium nitride, mercury cadmium telluride, telluride, or perovskite. As an example, the photosensitive layer of the detector chip 10 is made of silicon, which has the advantages of mature fabrication process and low cost. Furthermore, the silicon-based photosensitive layer wafer 13 meets the detection requirements in the visible to near-infrared light bands, which is beneficial for expanding the application scenarios of the detector chip 10.

[0049] The circuit layer wafer 15 is used to convert the electrical signals output from the photosensitive layer wafer 13 into digital signals.

[0050] The circuit layer wafer 15 integrates an analog-to-digital converter (ADC) (not shown) and signal processing circuitry (not shown), which amplifies and converts the relatively weak analog electrical signals, such as charge, converted by the photosensitive layer wafer 13 into digital signals. As an example, the circuit layer wafer 15 also integrates dynamic random access memory (DRAM). DRAM enables rapid temporary storage of high-speed image data converted to digital signals by the ADC, avoiding data congestion when the circuit layer wafer 15 outputs digital signals, and improving the efficiency of signal processing and transmission of the detector chip 10.

[0051] As an example, the detector chip 10 uses a stacked complementary metal-oxide-semiconductor chip. During the formation process, the circuit layer wafer 15 and the photosensitive layer wafer 13 are fabricated independently, avoiding the fact that the photosensitive element and the circuit are set on the same wafer in traditional chips. This allows the circuit layer wafer 15 to have a larger design area and space, which is beneficial to improving the design complexity and accuracy of the circuit layer wafer 15, thereby improving the working performance of the detector chip 10.

[0052] like Figure 1As shown, the slit 20 is positioned at the central axis of the surface of the circuit layer wafer 15, so that the circuit layer wafers 15 on both sides of the slit 20 have symmetrical and identical surface areas. This is beneficial to improving the uniformity of the electrical signals received by the circuit layer wafer 15 after conversion by the photosensitive layer wafer 13, thereby improving the efficiency and consistency of the electrical signal processing by the detector chips 10 on both sides of the slit 20, and avoiding the problems of spectral distortion and decreased imaging spatial resolution caused by the asymmetry of the digital signals converted and output by the detector chips 10 on both sides of the slit 20.

[0053] Interconnect layer 14 is used to electrically connect photosensitive layer wafer 13 and circuit layer wafer 15.

[0054] As an example, the detector chip 10 uses a stacked complementary metal-oxide-semiconductor chip, and the interconnect layer 14 realizes the electrical connection between the photosensitive layer wafer 13 and the circuit layer wafer 15 in the vertical direction, which helps to shorten the signal transmission path between the photosensitive layer wafer 13 and the circuit layer wafer 15, while reducing signal loss during transmission.

[0055] It should be noted that the interconnect layer 14 is composed of metal wires (not shown in the figure) and vertical connection components (not shown in the figure). The interconnect layer 14 also includes: contact holes (not shown in the figure), which are located in direct contact between the interconnect layer 14 and the photosensitive layer wafer 13 and the circuit layer wafer 15. The interconnect layer 14 achieves electrical connection with the photosensitive element of the photosensitive layer wafer 13 and the circuit structure of the circuit layer wafer 15 through the contact holes; and through-holes (not shown in the figure), which are used to connect multiple metal wires of different levels. The through-holes include through-silicon vias (TSVs). The inner sidewalls of the through-silicon vias are filled with metal material to form an electrical path through the interconnect layer 14.

[0056] The interconnect layer 14 has a first surface 141 and a second surface 142 arranged opposite to each other. That is, the first surface 141 and the second surface 142 are arranged opposite to each other in space along the thickness direction of the interconnect layer 14, which is beneficial to realize the vertical transmission of signals along the thickness direction of the interconnect layer 14.

[0057] The first surface 141 is in direct contact with the photosensitive layer wafer 13 to achieve electrical connection between the interconnect layer 14 and the photosensitive layer wafer 13; the second surface 142 is in direct contact with the circuit layer wafer 15 to achieve electrical connection between the interconnect layer 14 and the circuit layer wafer 15.

[0058] In some embodiments, the detector chip 10 further includes a redistribution layer 41, which is disposed on the side of the photosensitive layer wafer 13 that is in direct contact with the first surface 141, and on the side of the circuit layer wafer 15 that is in direct contact with the second surface 142.

[0059] The redistribution layer 41 is used to reconstruct the electrical connection structure between the photosensitive layer wafer 13 and the interconnect layer 14, and between the circuit layer wafer 15 and the interconnect layer 14.

[0060] The redistribution layer (RDL) 41 redistributes the ports used for electrical connections on the photosensitive layer wafer 13 and the circuit layer wafer 15, extending them to preset positions on the surfaces of the photosensitive layer wafer 13 and the circuit layer wafer 15. The preset positions are located on the surfaces of the photosensitive layer wafer 13 and the circuit layer wafer 15 away from the slit 20. By fanning out the ports used for electrical connections, a larger-spacing and more flexible array of electrical connection surfaces is formed. This avoids the problems of high interconnection difficulty and low flexibility caused by excessively small spacing and dense layout between ports. It improves the structural layout flexibility of electrical connections between the photosensitive layer wafer 13 and the interconnect layer 14, and between the circuit layer wafer 15 and the interconnect layer 14, and reduces interconnection difficulty. In addition, the redistribution layer 41 achieves a more compact and efficient vertical interconnection between the photosensitive layer wafer 13 and the circuit layer wafer 15 through shorter interconnection paths. This helps to reduce parasitic effects and impedance mismatch during signal transmission and improves the integrity of signal transmission of the detector chip 10.

[0061] In some embodiments, the redistribution layer 41 includes a metal wire 411, one end of which is connected to the edge of the slit 20 and the other end extends in a direction away from the slit 20.

[0062] like Figures 2 to 3 As shown, the metal wiring 411 extends along the slit 20 on the surface of the photosensitive layer wafer 13 and the circuit layer wafer 15, and is connected to the port (not shown) located at the edge of the sidewall of the slit 20. The other end of the metal wiring 411 extends away from the slit 20 in a fan-shaped arrangement, and the distance between the other ends of adjacent metal wiring 411 is greater than the distance between adjacent ports. The end of the metal wiring 411 that is not connected to the port serves as the connection point for electrical connection, thereby realizing the transmission of optical signals of incident light in the slit 20. Compared with the direct interconnection through the port at the edge of the sidewall of the slit 20, the metal wiring 411 increases the spacing between connection points, reduces the difficulty of realizing interlayer interconnection, and improves the structural layout flexibility of interlayer interconnection. In addition, the larger distance between the ends of adjacent metal wiring 411 that are not connected to the port means that more metal wiring 411 can be accommodated for interlayer interconnection, thereby further improving the structural density and structural complexity of the redistribution layer 41, and thus realizing the electrical connection between the photosensitive layer wafer 13 and the circuit layer wafer 15 more efficiently.

[0063] Continue to refer to Figures 2 to 3 In some embodiments, the redistribution layer 41 further includes stress-compensating vias 412 and redundant bridging structures 413.

[0064] The stress-compensating via 412 is used to release and alleviate the mechanical stress of the redistribution layer 41.

[0065] The different layers of the redistribution layer 41, as well as the redistribution layer 41 and the photosensitive layer wafer 13, and the redistribution layer 41 and the circuit layer wafer 15, have different coefficients of thermal expansion due to the different materials. When the detector chip 10 undergoes a process environment with a high degree of temperature change in a short period of time, the different degrees of expansion and contraction of the different structures cause a large mechanical stress concentration problem between the layers. By setting multiple stress compensation vias 412 on the redistribution layer 41, the redistribution layer 41 has additional space for micro-deformation during the thermal expansion and contraction process. This effectively disperses and absorbs the mechanical stress between the different layers of the redistribution layer 41 and the layers of the detector chip 10, reducing the risk of interlayer tearing of the detector chip 10 or cracking of the redistribution layer 41 due to excessive stress concentration or excessive stress. This is beneficial to improving the structural stability and reliability of the detector.

[0066] The redundant bridging structure 413 is used to connect and secure the metal wiring 411.

[0067] like Figures 2 to 3 As shown, the redundant bridging structure 413 is disposed between adjacent metal wirings 411 and is fixedly connected to the metal wirings 411, providing additional support for the metal wirings 411. This makes the metal wirings 411 more structurally stable under the condition of mechanical stress concentration, reducing the risk of accidental breakage or deformation of the metal wirings 411. In addition, as an example, the redundant bridging structure 413 is a metal structure with good conductivity. As a backup conductive path for the metal wirings 411, it effectively suppresses the circuit open circuit problem caused by accidental breakage of the metal wirings 411, which is beneficial to improving the reliability of the detection chip 10.

[0068] In some embodiments, the detector further includes a substrate 111, a detection chip 10 is disposed on the substrate 111, and the substrate 111 is electrically connected to the detection chip 10. The substrate 111 is used to support the detection chip 10. The slit 20 extends coaxially and is disposed through the substrate 111.

[0069] The substrate 111 provides a solid mechanical support and physical protection for the probe chip 10, preventing damage to the probe chip 10 during external assembly and other processes. In addition, the substrate 111 has a multi-layer wiring structure (not shown in the figure), which enables electrical connection with the surface port of the probe chip 10, thereby enabling the probe chip 10 to transmit signals to the external circuit system with low loss and high efficiency.

[0070] like Figure 1As shown, the slit 20 extends coaxially and is disposed through the substrate 111, so that the slit 20 is completely disposed through the detector chip 10 and the substrate 111, ensuring that the incident light is unobstructed during the transmission of the slit 20, forming a light path through the detector chip 10 and the substrate 111, increasing the light flux of the incident light in the slit 20, and reducing the accidental loss of the incident light.

[0071] This application also discloses a method for fabricating a detector with an integrated slit, referring to... Figure 4 , Figure 4 This is a flowchart illustrating a method for fabricating an integrated slit detector according to the present invention.

[0072] S1, Provide photosensitive layer wafer 13.

[0073] The photosensitive layer wafer 13 is used to convert the optical signal received by the detector chip into an electrical signal.

[0074] refer to Figure 1 The photosensitive layer wafer 13 includes a photosensitive layer, which uses photosensitive material to absorb incident light and convert the light signal into an electrical signal that the detection chip can recognize and process.

[0075] In some embodiments, the photosensitive layer is made of silicon, gallium nitride, mercury cadmium telluride, telluride, or perovskite. As an example, silicon is used as the material for the photosensitive layer, which has the advantages of mature fabrication process and low cost. Furthermore, the silicon-based photosensitive layer wafer 13 meets the detection requirements in the visible to near-infrared light bands, which is beneficial for expanding the application scenarios of the detection chip.

[0076] S2. A first slit segment 21 is formed in the photosensitive layer wafer 13, and the first slit segment 21 extends through the photosensitive layer wafer 13.

[0077] refer to Figure 1 The first slit segment 21 penetrates the photosensitive layer wafer 13, which helps reduce the difficulty of setting up the subsequent slit through the detector chip. In addition, the first slit segment 21 is located at the central axis along the thickness direction of the photosensitive layer wafer 13, so that the photosensitive layer wafers 13 on both sides of the first slit segment 21 have symmetrical and identical surface areas. This helps to improve the uniformity of the light signal received by the photosensitive layer wafer 13, thereby improving the efficiency consistency of photoelectric signal conversion of the detector chips on both sides of the first slit segment 21. This avoids the problems of spectral distortion and decreased imaging spatial resolution caused by the asymmetry of the electrical signals converted and output by the detector chips on both sides of the first slit segment 21.

[0078] In some embodiments, the process of forming the first slit segment 21 in the photosensitive layer wafer 13 includes a deep reactive ion etching (DRIE) process or a laser etching process. As an example, the process of forming the first slit segment 21 in the photosensitive layer wafer 13 employs a deep reactive ion etching (DRIE) process. The DRIE process, through vertical ion bombardment and slit sidewall passivation protection, enables the formed first slit segment 21 to have high anisotropy, i.e., good verticality. Furthermore, the DRIE process can achieve a first slit segment 21 with a high aspect ratio, meeting the requirements for forming the first slit segment 21 in photosensitive layer wafers 13 with different thicknesses under different process requirements.

[0079] In some embodiments, after forming the first slit segment 21 in the photosensitive layer wafer 13 and before bonding the photosensitive layer wafer and the circuit layer wafer, the fabrication method further includes: the photosensitive layer wafer 13 having a first top surface (not shown) and a first bottom surface 131 disposed opposite to each other, and forming a first redistribution layer 401 on the first bottom surface 131 of the photosensitive layer wafer 13. The first redistribution layer 401 includes metal wiring 411, one end of which is connected to the edge of the first slit segment 21, and the other end extends in a direction away from the first slit segment 21.

[0080] The first redistribution layer 401 is used to reconstruct the electrical connection structure between the photosensitive layer wafer 13 and the subsequently formed interconnect layers.

[0081] The first redistribution layer (RDL) 401 rewires the ports used for electrical connections on the photosensitive wafer 13 and extends them to a preset position on the first bottom surface 131. The preset position is the location on the first bottom surface 131 of the photosensitive wafer 13 away from the first slit segment 21. By fanning out the ports used for electrical connections, a larger spacing and more flexible layout of the electrical connection surface array is formed. This avoids the problems of high interconnection difficulty and low flexibility caused by excessively small spacing and dense layout between ports. It improves the structural layout flexibility of realizing electrical connections between the photosensitive wafer 13 and the interconnect layer and reduces interconnection difficulty. In addition, the first redistribution layer 401 achieves a more compact and efficient vertical interconnection between the photosensitive wafer 13 and the subsequently formed circuit layer wafer through a shorter interconnection path. This helps to reduce parasitic effects and impedance mismatch during signal transmission and improves the integrity of signal transmission of the detector chip.

[0082] In some embodiments, the redistribution layer 401 includes a metal wiring 411, one end of which is connected to the edge of the first slit segment 21, and the other end extends in a direction away from the first slit segment 21.

[0083] like Figure 3As shown, the metal wiring 411 extends along the first slit segment 21 on the first bottom surface 131 of the photosensitive layer wafer 13 and connects to the port (not shown) located at the edge of the sidewall of the first slit segment 21. The other end of the metal wiring 411 extends away from the first slit segment 21 in a fan-shaped arrangement, and the distance between the other ends of adjacent metal wiring 411 is greater than the spacing between adjacent ports. The end of the metal wiring 411 that is not connected to the port serves as the connection point for electrical connection, thereby realizing the transmission of optical signals of incident light in the first slit segment 21. Compared to interconnecting directly through the ports on the sidewall edge of the first slit segment 21, the metal wiring 411 increases the spacing between connection points, reduces the difficulty of achieving interlayer interconnection, and improves the structural layout flexibility of interlayer interconnection. In addition, the distance between the ends of adjacent metal wiring 411 that are not connected to the ports is larger, which means that more metal wiring 411 can be accommodated for interlayer interconnection, thereby further improving the structural density and structural complexity of the first rewiring layer 401, and thus more efficiently realizing the electrical connection between the photosensitive layer wafer 13 and the circuit layer wafer.

[0084] In some embodiments, in the step of forming a first redistribution layer 401 on the first bottom surface 131 of the photosensitive layer wafer 13, stress compensation vias 412 and redundant metal bridging structures 413 are provided in the first redistribution layer 401.

[0085] The stress-compensating via 412 is used to release and alleviate the mechanical stress of the first redistribution layer 401.

[0086] The different layers of the first wiring layer 401, as well as the layer between the first wiring layer 401 and the photosensitive wafer 13, have different coefficients of thermal expansion due to the different materials. When the subsequently formed detector chip undergoes a process environment with a high degree of temperature change in a short period of time, the different degrees of expansion and contraction of the different structures will cause a large mechanical stress concentration between the layers. By setting multiple stress compensation vias 412 on the first wiring layer 401, the first wiring layer 401 has additional space for micro-deformation during the thermal expansion and contraction process. This effectively disperses and absorbs the mechanical stress between the different layers of the first wiring layer 401 and between the layers of the detector chip, reducing the risk of interlayer tearing of the detector chip or cracking of the first wiring layer 401 due to excessive stress concentration or excessive stress. This is beneficial to improving the structural stability and reliability of the detector.

[0087] The redundant bridging structure 413 is used to connect and secure the metal wiring 411.

[0088] refer to Figure 2The redundant bridging structure 413 is disposed between adjacent metal wirings 411 and is fixedly connected to the metal wirings 411, providing additional support for the metal wirings 411. This makes the metal wirings 411 more structurally stable under the condition of mechanical stress concentration, reducing the risk of accidental breakage or deformation of the metal wirings 411. In addition, as an example, the redundant bridging structure 413 is a metal structure with good conductivity. As a backup conductive path for the metal wirings 411, it effectively suppresses the circuit open circuit problem caused by accidental breakage of the metal wirings 411, which is beneficial to improving the reliability of the detection chip.

[0089] S3, provides circuit layer wafer 15.

[0090] The circuit layer wafer 15 is used to convert the electrical signals output from the photosensitive layer wafer 13 into digital signals.

[0091] The circuit layer wafer 15 integrates an analog-to-digital converter (ADC) (not shown) and signal processing circuitry (not shown), which amplifies and converts the relatively weak analog electrical signals, such as charge, converted by the photosensitive layer wafer 13 into digital signals. As an example, the circuit layer wafer 15 also integrates dynamic random access memory (DRAM). DRAM enables rapid temporary storage of high-speed image data converted to digital signals by the ADC, avoiding data congestion when the circuit layer wafer 15 outputs digital signals, thus improving the efficiency of signal processing and transmission of the detection chip.

[0092] S4. A second slit segment 22 is formed in the circuit layer wafer 15, and the second slit segment 22 is disposed through the circuit layer wafer 15.

[0093] refer to Figure 1 The second slit segment 22 penetrates the circuit layer wafer 15, which helps to reduce the difficulty of setting up the subsequent slit through the detector chip. The second slit segment 22 is located at the central axis of the circuit layer wafer 15 along the thickness direction, so that the circuit layer wafers 15 on both sides of the second slit segment 22 have symmetrical and identical surface areas. This helps to improve the uniformity of the electrical signals received by the circuit layer wafer 15 after conversion by the photosensitive layer wafer 13, thereby improving the efficiency and consistency of the electrical signal processing of the detector chips on both sides of the second slit segment 22, and avoiding the problems of spectral distortion and decreased imaging spatial resolution caused by the asymmetry of the digital signals converted and output by the detector chips on both sides of the second slit segment 22.

[0094] In some embodiments, the process of forming the second slit segment 22 in the circuit layer wafer 15 includes a deep reactive ion etching (DRIE) process or a laser etching process. As an example, the process of forming the second slit segment 22 in the circuit layer wafer 15 employs a deep reactive ion etching (DRIE) process. The DRIE process, through vertical ion bombardment and slit sidewall passivation protection, enables the formed second slit segment 22 to have high anisotropy, i.e., good verticality. Furthermore, the DRIE process can achieve a high aspect ratio second slit segment 22, meeting the requirements for forming the second slit segment 22 in circuit layer wafers 15 with different thicknesses under different process requirements.

[0095] In some embodiments, after forming the second slit segment 22 in the circuit layer wafer 15 and before bonding the photosensitive layer wafer 13 and the circuit layer wafer 15, the fabrication method further includes: the circuit layer wafer 15 having a second top surface 151 and a second bottom surface (not shown) disposed opposite to each other; forming a second redistribution layer 402 on the second top surface 151 of the circuit layer wafer 15; the second redistribution layer 402 including metal wiring 411; one end of the metal wiring 411 being connected to the edge of the second slit segment 22; and the other end extending in a direction away from the second slit segment 22.

[0096] The description of the second routing layer 402 is similar to that of the first routing layer 401 mentioned above, and will not be repeated here.

[0097] In some embodiments, in the step of forming a second redistribution layer 402 on the second top surface 151 of the circuit layer wafer 15, stress compensation vias 412 and redundant metal bridging structures 413 are provided in the second redistribution layer 402.

[0098] For details regarding the specific structure and implementation of the stress-compensating via 412 and the redundant metal bridging structure 413 in the second wiring layer 402, please refer to the relevant descriptions in the foregoing embodiments, which will not be repeated here.

[0099] S5. An interconnect layer 14 is formed on the circuit layer wafer 15. The interconnect layer 14 has a third slit segment 23, which is connected to the second slit segment 22.

[0100] Interconnect layer 14 is used to electrically connect photosensitive layer wafer 13 and circuit layer wafer 15.

[0101] It should be noted that the interconnect layer 14 is composed of metal wires (not shown in the figure) and vertical connection components (not shown in the figure). The interconnect layer 14 also includes: contact holes (not shown in the figure), which are located in direct contact between the interconnect layer 14 and the photosensitive layer wafer 13 and the circuit layer wafer 15. The interconnect layer 14 achieves electrical connection with the photosensitive element of the photosensitive layer wafer 13 and the circuit structure of the circuit layer wafer 15 through the contact holes; and through-holes (not shown in the figure), which are used to connect multiple metal wires of different levels. The through-holes include silicon vias, and the inner sidewalls of the silicon vias are filled with metal material to form an electrical path through the interconnect layer 14.

[0102] In this embodiment, the interconnect layer 14 realizes the electrical connection between the photosensitive layer wafer 13 and the circuit layer wafer 15 in the vertical direction, which helps to shorten the signal transmission path between the photosensitive layer wafer 13 and the circuit layer wafer 15, while reducing signal loss during transmission.

[0103] The interconnect layer 14 has a third slit segment 23, which helps to reduce the difficulty of the subsequent process of realizing the interconnection between the first slit segment 21 and the second slit segment 23. In addition, the third slit segment 23 and the second slit segment 22 are coaxially connected, which helps to reduce the difficulty of realizing the interconnection between the first slit segment 21, the second slit segment 22 and the third slit segment 23 when bonding the circuit layer wafer 15 and the photosensitive layer wafer 13.

[0104] S6. Bond the photosensitive layer wafer 13 and the circuit layer wafer 15 to form a detector chip 10. The first slit segment 21, the second slit segment 22 and the third slit segment 23 are connected, and the first slit segment 21, the second slit segment 22 and the third slit segment 23 form a slit 20.

[0105] The detector chip 10 is used to convert the received optical signal into an electrical signal.

[0106] The detector chip 10 efficiently converts the optical signal incident on the photosensitive wafer 13 into an electrical signal that can be analyzed and imaged. Specifically, the detector chip 10 completes the photoelectric signal conversion based on the internal photoelectric effect of the semiconductor material of the detector chip 10.

[0107] As an example, the detector chip 10 is a complementary metal-oxide-semiconductor chip. The stacked CMOS chip adopts a parallel processing architecture, which is conducive to realizing the parallel processing of optical signals by the detector chip 10, thereby improving the processing efficiency of the detector chip 10 in photoelectric signal conversion. In addition, the stacked CMOS chip has a complementary transistor structure, which is conducive to reducing the static power consumption and dynamic power consumption of the detector chip 10, and is conducive to improving the service life and reliability of the detector chip 10.

[0108] Specifically, the detector chip 10 employs a stacked complementary metal-oxide-semiconductor (CMOS) chip. The stacked CMOS chip has a larger photosensitive area, which is beneficial for increasing the amount of light signal received by the detector chip 10, thereby improving its sensitivity and resolution. Furthermore, the stacked CMOS chip combines different functional layers, which helps to significantly reduce the physical size of the detector chip 10, further reducing the overall size of the detection system. In other embodiments, the detector chip may also employ a front-illuminated or back-illuminated CMOS chip.

[0109] In some embodiments, the bonding process for the photosensitive layer wafer 13 and the circuit layer wafer 15 includes copper-copper direct bonding or dielectric bonding. As an example, the bonding process for the photosensitive layer wafer 13 and the circuit layer wafer 15 is copper-copper direct bonding. Copper-copper direct bonding can shorten the spacing between adjacent connection points; that is, on a chip of the same area, copper-copper direct bonding can effectively increase the number of connection points, increase the number of signal transmission channels between the photosensitive layer wafer 13 and the circuit layer wafer 15, and improve the signal transmission bandwidth of the detector. Furthermore, copper has higher conductivity than traditional solder materials, which helps to reduce the resistance of the interconnect structure, thereby reducing signal loss and delay during signal transmission and improving the efficiency and quality of detector signal transmission.

[0110] The slit 20 is used to limit the cross-sectional shape and width of the incident light rays, forming a linear aperture.

[0111] The slit 20 limits the width of the beam, causing irregular incident light rays to form a linear aperture, precisely filtering and outputting monochromatic light of the desired specific wavelength.

[0112] In this embodiment, the slit 20 is disposed through the detector chip 10 of the detector, so that the slit 20 is fixedly disposed inside the detector. This helps to reduce the probability of the slit 20 being accidentally displaced, thereby effectively suppressing the problem of defocusing caused by changes in the relative position of the slit 20 and the primary image plane of the spectral imaging, reducing the risk of spectral aliasing and reduced signal-to-noise ratio in the spectral imaging system, and thus helping to improve the spectral imaging accuracy of the detector.

[0113] The slit 20 is located inside the detector, which helps to reduce the size of the detection system and improve the space utilization and integration of the detection system including the detector.

[0114] The detector, through its own imaging capabilities and the mechanical characteristics of the fixed installation of the slit 20 and the detector, achieves real-time monitoring of the positional matching degree between the slit 20 and the primary image plane of the spectral imaging system. Since the slit 20 is fixedly installed inside the detector, when the position of the slit 20 needs to be adjusted, the position of the slit 20 can be adjusted accordingly by adjusting the position of the detector, which helps to reduce the difficulty of adjusting the position of the slit 20, thereby achieving real-time dynamic adjustment of the relative position of the slit 20 and the focal plane of the spectral imaging system.

[0115] In some embodiments, after bonding the photosensitive layer wafer 13 and the circuit layer wafer 15 to form the detector chip 10, the fabrication method further includes: providing a substrate 111, wherein the detector chip 10 is disposed on the substrate 111 and the substrate 1111 is electrically connected to the detector chip 10, and the substrate 111 is used to support the detector chip 10; forming a fourth slit segment 24 in the substrate 111, wherein the fourth slit segment 24 is disposed through the substrate 111 and the fourth slit segment 24 is connected to the second slit segment 22.

[0116] The substrate 111 provides a solid mechanical support and physical protection for the probe chip 10, preventing damage to the probe chip 10 during external assembly and other processes. In addition, the substrate 111 has a multi-layer wiring structure (not shown in the figure), which enables electrical connection with the surface port of the probe chip 10, thereby enabling the probe chip 10 to transmit signals to the external circuit system with low loss and high efficiency.

[0117] refer to Figure 2 The fourth slit segment 24 is connected to the second slit segment 22. The fourth slit segment 24, the first slit segment 21, the second slit segment 22 and the third slit segment 23 together form the slit 20, so that the slit 20 is completely disposed in the detector chip 10 and the substrate 111, ensuring that the incident light is unobstructed during the transmission of the slit 20, forming a light path that passes through the detector chip 10 and the substrate 111, increasing the light flux of the incident light in the slit 20 and reducing the accidental loss of the incident light.

[0118] The above embodiments are merely illustrative of the technical concept and features of the present invention, intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and should not be construed as limiting the scope of protection of the present invention. It will be apparent to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects. The scope of the present invention is defined by the appended claims rather than the foregoing description, and thus all changes falling within the meaning and scope of the equivalents of the claims are intended to be included within the present invention.

Claims

1. A detector integrating a slit, characterized in that, include: The detector chip has a top surface and a bottom surface that are set opposite to each other; A slit is disposed throughout the detector chip, and the slit extends through the top and bottom surfaces of the detector chip along the thickness direction of the detector chip.

2. The detector with integrated slits according to claim 1, characterized in that: The slit has a light inlet located on the top surface of the detector chip; the slit also has a light outlet located on the bottom surface of the detector chip. Along a direction parallel to the surface of the detector chip, the lateral dimension of the light outlet is greater than or equal to the lateral dimension of the light inlet.

3. The detector with integrated slits according to claim 1, characterized in that: Along a direction perpendicular to the surface of the detector chip, the detector chip includes a photosensitive layer wafer, an interconnect layer wafer, and a circuit layer wafer stacked sequentially. The photosensitive layer wafer is used to convert optical signals into electrical signals, and the circuit layer wafer is used to convert electrical signals into digital signals. The interconnect layer has a first surface and a second surface disposed opposite to each other. The first surface is in direct contact with the photosensitive layer wafer, and the second surface is in direct contact with the circuit layer wafer. The interconnect layer is used to electrically connect the photosensitive layer wafer and the circuit layer wafer. The detection chip also includes a redistribution layer, which is disposed on the side of the photosensitive layer wafer that is in direct contact with the first surface, and on the side of the circuit layer wafer that is in direct contact with the second surface. The redistribution layer includes metal wiring, one end of which is connected to the edge of the slit, and the other end extends away from the slit.

4. The detector with integrated slits according to claim 1, characterized in that: The detector also includes a substrate, the detection chip is disposed on the substrate, and the substrate is electrically connected to the detection chip. The substrate is used to support the detection chip. The slit extends along the thickness direction of the detection chip and penetrates the substrate.

5. A method for fabricating a detector with an integrated slit, characterized in that, include: Provide photosensitive layer wafers; A first slit segment is formed in the photosensitive layer wafer, and the first slit segment is disposed through the photosensitive layer wafer; Provide circuit layer wafers; A second slit segment is formed in the circuit layer wafer, and the second slit segment is disposed through the circuit layer wafer; An interconnect layer is formed on the circuit layer wafer, the interconnect layer having a third slit segment, the third slit segment being connected to the second slit segment; The photosensitive layer wafer and the circuit layer wafer are bonded to form a detector chip. The first slit segment, the second slit segment, and the third slit segment are connected and form a slit.

6. The method for fabricating an integrated slit detector according to claim 5, characterized in that: The processes for forming the first slit segment in the photosensitive layer wafer and the second slit segment in the circuit layer wafer both include: deep reactive ion etching or laser etching.

7. The method for fabricating an integrated slit detector according to claim 5, characterized in that: After forming the first slit segment in the photosensitive layer wafer and before bonding the photosensitive layer wafer and the circuit layer wafer, the fabrication method further includes: the photosensitive layer wafer having a first top surface and a first bottom surface disposed opposite to each other; forming a first redistribution layer on the first bottom surface of the photosensitive layer wafer; the first redistribution layer includes metal wiring; one end of the metal wiring is connected to the edge of the first slit segment, and the other end extends in a direction away from the first slit segment. After forming the second slit segment in the circuit layer wafer and before bonding the photosensitive layer wafer and the circuit layer wafer, the fabrication method further includes: the circuit layer wafer having a second top surface and a second bottom surface disposed opposite to each other; forming a second redistribution layer on the second top surface of the circuit layer wafer; the second redistribution layer including metal wiring; one end of the metal wiring being connected to the edge of the second slit segment; and the other end extending in a direction away from the second slit segment.

8. The method for fabricating an integrated slit detector according to claim 5, characterized in that: After bonding the photosensitive layer wafer and the circuit layer wafer to form a detector chip, the fabrication method further includes: providing a substrate, wherein the detector chip is disposed on the substrate and the substrate is electrically connected to the detector chip, and the substrate is used to support the detector chip; forming a fourth slit segment in the substrate, the fourth slit segment being disposed through the substrate, and the fourth slit segment communicating with the second slit segment.

9. The method for fabricating an integrated slit detector according to claim 5, characterized in that: In the steps of forming a first redistribution layer on the first bottom surface of the photosensitive layer wafer and forming a second redistribution layer on the second top surface of the circuit layer wafer, stress-compensating vias and redundant metal bridging structures are provided in the first redistribution layer and the second redistribution layer.

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