Detection substrate, method of manufacturing the same, and flat panel detector

Abstract

A detection substrate is provided, comprising: a substrate and a thin-film transistor, a third conductive layer, and a photodetector sequentially disposed away from the substrate. The third conductive layer includes a first conductive portion, and the thin-film transistor is electrically connected to the photodetector through the first conductive portion. The third conductive layer includes a first sub-layer and a second sub-layer. In a third direction, the first sub-layer has a first thickness, and the second sub-layer has a second thickness, wherein the first thickness is less than the second thickness. The first conductive portion includes a first main portion and a first edge portion. The orthographic projection of the photodetector on the substrate falls within the orthographic projection of the first main portion on the substrate. The first edge portion at least partially surrounds the first main portion. The first main portion includes a first surface, which is the surface of the first main portion disposed away from the substrate. The first edge portion includes a second surface, which is the surface of the first edge portion disposed away from the substrate. The second surface is closer to the substrate than the first surface.

Description

Technical Field

[0001] This disclosure relates to the field of detection technology, and in particular to a detection substrate, a method for preparing the substrate, and a flat panel detector. Background Technology

[0002] A photoelectric converter can be mounted on the detector substrate as a light sensor to detect brightness. This type of detector substrate can be used in medical devices such as flat panel detectors for X-ray detection. The detector substrate typically includes thin-film transistors. The fabrication process of the photoelectric converter and the high-dose X-ray irradiation environment may cause the performance of the thin-film transistors on the detector substrate to degrade, affecting the overall performance of the detector substrate.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] In one aspect, a detection substrate is provided, comprising: a substrate; at least one thin-film transistor located on one side of the substrate; a third conductive layer located on the side of the thin-film transistor away from the substrate; and at least one photoelectric converter located on the side of the third conductive layer away from the substrate, wherein the detection substrate includes a first conductive portion located in the third conductive layer, and the at least one thin-film transistor is electrically connected to the at least one photoelectric converter through the first conductive portion; the third conductive layer includes a first sublayer and a second sublayer, the first sublayer being located on the side of the second sublayer away from the substrate, the first sublayer having a first thickness in a third direction, and the second sublayer having a second thickness in a third direction, the first thickness being... The thickness is less than the second thickness, and the third direction is parallel to the direction of the substrate toward the thin film transistor; the first conductive portion includes a first body portion and a first edge portion, at least one of the photoelectric converters' orthogonal projections on the substrate falls within the orthogonal projection of the first body portion on the substrate, and the first edge portion at least partially surrounds the first body portion; the first body portion includes a first surface located in the first sublayer, the first surface being the surface of the first body portion away from the substrate, and the first edge portion includes a second surface located in the first sublayer, the second surface being the surface of the first edge portion away from the substrate, and in the third direction, the second surface is closer to the substrate relative to the first surface.

[0005] According to some exemplary embodiments, the first surface and the second surface have a first height difference in a third direction, and the ratio of the first height difference to the first thickness is less than 0.7.

[0006] According to some exemplary embodiments, the probe substrate further includes a first passivation layer located between the thin-film transistor and the third conductive layer, the first passivation layer including a first via, the first conductive portion being electrically connected to the thin-film transistor through the first via; the first conductive portion further includes a second edge portion located on the side of the first body portion near the thin-film transistor, at least a portion of the second edge portion being located in the first via; and the second edge portion including a filling portion located in the first via, the surface of the filling portion away from the substrate and the first surface having a second height difference in a third direction, the second height difference being greater than the first height difference.

[0007] According to some exemplary embodiments, at least one of the photoelectric converters is projected onto the substrate and falls within the projection of the first passivation layer onto the substrate; and the first passivation layer has a third thickness in a third direction, the ratio of the third thickness to the first height difference being greater than or equal to 4.

[0008] According to some exemplary embodiments, the probe substrate includes a second body portion and a third edge portion located in the first passivation layer, wherein at least one orthogonal projection of the photoelectric converter on the substrate falls within the orthogonal projection of the second body portion on the substrate, and the third edge portion is located on the side of the second body portion away from the thin-film transistor; the surface of the third edge portion away from the substrate and the surface of the second body portion away from the substrate have a third height difference in a third direction, and the ratio of the third height difference to the first height difference is greater than or equal to 3; and the probe substrate further includes a protective layer located on the side of the photoelectric converter away from the substrate, and the surface of the third edge portion away from the substrate is covered by the protective layer.

[0009] According to some exemplary embodiments, the probe substrate further includes a fourth edge portion located in the first passivation layer, the fourth edge portion being located on the side of the second body portion near the thin film transistor, the fourth edge portion including a first side surface, the first side surface including a first sub-side surface and a second sub-side surface, the first sub-side surface being located on the side of the second sub-side surface away from the substrate, the first sub-side surface having a first slope angle, the second sub-side surface having a second slope angle, the first slope angle being greater than the second slope angle, and the first slope angle being greater than 75°.

[0010] According to some exemplary embodiments, the probe substrate further includes a sacrificial layer located between the first passivation layer and the third conductive layer, wherein the orthographic projection of the photoelectric converter on the substrate falls within the orthographic projection of the sacrificial layer on the substrate; and the material of the sacrificial layer includes oxide.

[0011] According to some exemplary embodiments, the probe substrate includes a sacrificial portion located in the sacrificial layer, wherein the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the sacrificial portion on the substrate at least partially overlap; and the edges of the orthographic projections of the first conductive portion on the substrate and the edges of the orthographic projections of the sacrificial portion on the substrate have a first spacing distance in a second direction, the first spacing distance being in the range of 0.5 micrometers to 2 micrometers, the second direction being perpendicular to the third direction.

[0012] According to some exemplary embodiments, the detection substrate includes a plurality of detection units arranged in an array in a first direction and a second direction, the first direction and the second direction intersecting; the detection substrate includes a plurality of sacrificial portions located in the sacrificial layer, at least one of the detection units includes a thin film transistor, a photoelectric converter and a sacrificial portion; and two adjacent sacrificial portions are spaced apart by a second spacing distance in the first direction, the ratio of the second spacing distance to the first spacing distance being greater than or equal to 6.

[0013] According to some exemplary embodiments, the orthographic projection of the sacrificial portion on the substrate and the orthographic projection of the thin-film transistor on the substrate are spaced apart.

[0014] According to some exemplary embodiments, the probe substrate includes: a first conductive layer, a first semiconductor layer, and a first insulating layer, wherein the first insulating layer is located between the first conductive layer and the first semiconductor layer; the thin-film transistor includes a control electrode and an active portion, wherein the control electrode of the thin-film transistor is located in the first conductive layer, and the active portion of the thin-film transistor is located in the first semiconductor layer; the material of the first insulating layer includes silicon nitride, and the ratio of the number of silicon atoms to the number of nitrogen atoms in the first insulating layer is in the range of 1.2 to 2.

[0015] According to some exemplary embodiments, the crystal structure of the first insulating layer includes a plurality of silicon-hydrogen bonds and a plurality of silicon-nitrogen bonds, wherein the ratio of the number of silicon-hydrogen bonds to the number of silicon-nitrogen bonds in the crystal structure of the first insulating layer is in the range of 0.03 to 0.22.

[0016] According to some exemplary embodiments, the first insulating layer is located on the side of the first conductive layer away from the substrate, and the first semiconductor layer is located on the side of the first insulating layer away from the substrate; the probe substrate includes a second conductive portion located in the first conductive layer, the control electrode is located in the second conductive portion, the second conductive portion includes a second side surface, the second side surface has a third slope angle, the third slope angle being in the range of 20° to 30°.

[0017] According to some exemplary embodiments, the detection substrate further includes a second conductive layer located between the first semiconductor layer and the third conductive layer, the second conductive layer including a third conductive portion and a fourth conductive portion, the thin film transistor further including a first electrode and a second electrode, the first electrode of the thin film transistor being located in the third conductive portion, and the second electrode of the thin film transistor being located in the fourth conductive portion; the third conductive portion is electrically connected to the first conductive portion through the first via; the second conductive portion includes a third main body portion and a first branch portion, the third main body portion extending along a first direction, the first branch portion being located on the side of the third main body portion facing the photoelectric converter, the orthographic projection of the first branch portion on the substrate and the orthographic projection of the active portion on the substrate at least partially overlap; and the orthographic projection of the first branch portion on the substrate and the orthographic projection of the third conductive portion on the substrate at least partially overlap, the overlapping portion of the projections of the first branch portion and the third conductive portion having a first width in a first direction, the ratio of the first width to the first spacing distance being less than or equal to 3.6.

[0018] According to some exemplary embodiments, the orthographic projection of the active portion on the substrate falls within the orthographic projection of the third conductive layer on the substrate; and / or, the detection substrate further includes a light-shielding layer located on the side of the photoelectric converter away from the substrate, the light-shielding layer including a light-shielding portion, the orthographic projection of the active portion on the substrate falling within the orthographic projection of the light-shielding portion on the substrate.

[0019] According to some exemplary embodiments, the probe substrate further includes a planarization layer located on the side of the photoelectric converter away from the substrate, wherein the orthographic projection of the thin-film transistor on the substrate falls within the orthographic projection of the planarization layer on the substrate; and the material of the planarization layer includes a silicon-containing organic material.

[0020] According to some exemplary embodiments, the second conductive layer is located on the side of the first semiconductor layer away from the substrate, the active portion includes a first electrode region, a second electrode region, and a channel region, the channel region being located between the first electrode region and the second electrode region; and the first electrode region is electrically connected to the first electrode of the thin-film transistor, and the second electrode region is electrically connected to the second electrode of the thin-film transistor.

[0021] According to some exemplary embodiments, the first insulating layer is located on the side of the first semiconductor layer away from the substrate, the first conductive layer is located on the side of the first insulating layer away from the substrate, and the probe substrate further includes a second conductive layer located on the side of the first semiconductor layer close to the substrate; the active portion includes a first electrode region, a second electrode region, and a channel region, the channel region being located between the first electrode region and the second electrode region; and the first conductive portion and the first electrode region are electrically connected, the second conductive layer includes a third conductive portion, the third conductive portion and the second electrode region being electrically connected.

[0022] According to some exemplary embodiments, the first insulating layer is located on the side of the first semiconductor layer away from the substrate, and the first conductive layer is located on the side of the first insulating layer away from the substrate; the probe substrate further includes: a second insulating layer located on the side of the first conductive layer away from the substrate; and a second conductive layer located on the side of the second insulating layer away from the substrate, the second conductive layer including a third conductive portion and a fourth conductive portion, and the second insulating layer including a second via and a third via; the active portion includes a first electrode region, a second electrode region, and a channel region, the channel region being located between the first electrode region and the second electrode region, the third conductive portion being electrically connected to the first electrode region through the second via, and the fourth conductive portion being electrically connected to the second electrode region through the third via.

[0023] According to some exemplary embodiments, the first insulating layer comprises a single layer of silicon nitride film; or, the first insulating layer comprises at least one of a silicon nitride / hydrogenated silicon nitride stack, a silicon nitride / hydrogenated silicon nitride / silicon nitride stack, a hydrogenated silicon nitride / silicon nitride stack, a silicon nitride / silicon oxide stack, and a hydrogenated silicon nitride / silicon oxide stack.

[0024] According to some exemplary embodiments, the first passivation layer includes: a third sublayer; a fourth sublayer located on the side of the third sublayer away from the substrate; and a fifth sublayer located on the side of the fourth sublayer away from the substrate, the fifth sublayer comprising silicon oxide, the fourth sublayer comprising silicon nitride, the third sublayer comprising silicon nitride; and the ratio of the thickness of the fourth sublayer in the third direction to the thickness of the third sublayer in the third direction is in the range of 0.2 to 1.

[0025] In another aspect, a flat panel detector is provided, comprising a detection substrate as described in any of the preceding claims.

[0026] In another aspect, a method for fabricating a detector substrate is provided, comprising: providing a substrate; forming at least one thin-film transistor on one side of the substrate; sequentially forming a second sublayer and a first sublayer on the side of the thin-film transistor away from the substrate, and performing a patterning process on the first sublayer and the second sublayer to form a third conductive layer; and forming at least one photoelectric converter on the side of the third conductive layer away from the substrate, wherein the first sublayer has a first thickness in a third direction, the second sublayer has a second thickness in a third direction, the first thickness is less than the second thickness, and the third direction is perpendicular to the substrate; the third conductive layer includes a first conductive portion, and at least one of the thin-film transistors... The tube is electrically connected to at least one of the photoelectric converters via the first conductive portion; the first conductive portion includes a first body portion and a first edge portion, the orthographic projection of at least one of the photoelectric converters on the substrate falls within the orthographic projection of the first body portion on the substrate, and the first edge portion at least partially surrounds the first body portion; the first body portion includes a first surface located in the first sublayer, the first surface being the surface of the first body portion away from the substrate, and the first edge portion includes a second surface located in the first sublayer, the second surface being the surface of the first edge portion away from the substrate, and in a third direction, the second surface is closer to the substrate relative to the first surface. Attached Figure Description

[0027] Other objects and advantages of this disclosure will become apparent from the following description of the disclosure with reference to the accompanying drawings, and will help to provide a comprehensive understanding of the disclosure.

[0028] Figure 1 This is a schematic diagram of the structure of a flat panel detector according to an exemplary embodiment of the present disclosure.

[0029] Figure 2 This is a schematic diagram of the structure of a probe substrate according to an exemplary embodiment of the present disclosure.

[0030] Figure 3 This is a partial planar schematic diagram of a probe substrate according to an exemplary embodiment of the present disclosure.

[0031] Figure 4 It is along Figure 3 A schematic diagram of the cross-section taken by the midline AA'.

[0032] Figure 5 This is a partial planar schematic diagram of a third conductive layer and a photoelectric converter in a probe substrate according to an exemplary embodiment of the present disclosure.

[0033] Figure 6 It is based on Figure 5 SEM image of a local membrane layer in the P1 region.

[0034] Figure 7 It is based on Figure 5 SEM image of a local membrane layer in the P2 region.

[0035] Figure 8 This is a partial planar schematic diagram of a portion of a film layer in a probe substrate according to an exemplary embodiment of the present disclosure.

[0036] Figure 9 It is based on Figure 8 SEM image of a local membrane layer in the P3 region.

[0037] Figure 10 It is based on Figure 8 SEM image of a local membrane layer in the P4 region.

[0038] Figure 11 This is a schematic diagram of the structure of the first passivation layer in a probe substrate according to an exemplary embodiment of the present disclosure.

[0039] Figure 12 It is based on Figure 3 SEM image of a local membrane layer in the P5 region.

[0040] Figure 13 This is a SEM test image of a local film layer of a thin-film transistor in a probe substrate according to an exemplary embodiment of the present disclosure.

[0041] Figure 14 This is a schematic plan view of a portion of a film layer in a probe substrate according to an exemplary embodiment of the present disclosure.

[0042] Figure 15 This is a schematic plan view of a portion of a film layer in a probe substrate according to an exemplary embodiment of the present disclosure.

[0043] Figure 16 This is a schematic diagram of the structure of a probe substrate according to an exemplary embodiment of the present disclosure.

[0044] Figure 17 This is a schematic diagram of the structure of a probe substrate according to an exemplary embodiment of the present disclosure.

[0045] Figure 18 This is a schematic diagram of the structure of a probe substrate according to an exemplary embodiment of the present disclosure.

[0046] Figure 19 This is a flowchart of a method for preparing a probe substrate according to an exemplary embodiment of the present disclosure.

[0047] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of this disclosure may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0049] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0050] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0051] In this document, unless otherwise specified, directional terms such as "up," "down," "left," "right," "inner," and "outer" are used to indicate orientation or positional relationships based on the accompanying drawings, and are used only for the convenience of describing this disclosure, and are not intended to indicate or imply that the device, element, or component referred to must have a specific orientation, or be constructed or operated in a specific orientation. It should be understood that when the absolute position of the described object changes, the relative positional relationships they represent may also change accordingly. Therefore, these directional terms should not be construed as limitations on this disclosure.

[0052] In this document, the directional terms "first direction" and / or "second direction" are used to describe different orientations of the probe substrate or flat panel detector, such as the row orientation and column orientation of the probe substrate. It should be understood that such representations are merely exemplary descriptions and not limitations of this disclosure.

[0053] In this article, "parallel" or "nearly parallel" refers to a state in which two straight lines, two planes, or a straight line and a plane form an angle greater than -10° and less than 10°, and therefore also includes states in which the angle is greater than -5° and less than 5°. Similarly, "perpendicular" refers to a state in which two straight lines, two planes, or a straight line and a plane form an angle greater than 80° and less than 100°, and therefore also includes states in which the angle is greater than 85° and less than 95°.

[0054] With the development of technology, flat X-ray panel detectors (FPXD) are emerging as new medical and industrial-grade products with increasingly diverse applications.

[0055] Figure 1 This is a schematic diagram of the structure of a flat panel detector according to an exemplary embodiment of the present disclosure. Figure 2 This is a schematic diagram of the structure of a probe substrate according to an exemplary embodiment of the present disclosure.

[0056] By way of example, embodiments of this disclosure provide a flat panel detector 200. (Referring to...) Figure 1 and Figure 2 The flat panel detector 200 may include a detector substrate 100 and a non-visible light (e.g., X-ray) conversion layer 18 covering the detector substrate 100. The detector substrate 100 is provided with an array of thin-film transistors (20) and a photoelectric converter 8. The conversion layer 18 can convert non-visible light into visible light, and then the photoelectric converter 8 converts the visible light into an electrical signal, which is then stored. When the thin-film transistors 20 connected to the photoelectric converter 8 are turned on, the electrical signal is output to a processor, where it is processed to obtain image information.

[0057] For example, the detector substrate 100 may include a substrate 1, a plurality of thin film transistors 20 arranged in an array on the substrate 1, and a photoelectric converter 8 connected to the first electrode of the thin film transistors 20.

[0058] For example, refer to Figure 2 The detection substrate 100 may also include multiple intersecting gate lines and read signal lines RL. For example, the gate lines may extend along a first direction X, and the read signal lines RL may extend along a second direction Y, with the first direction X and the second direction Y intersecting.

[0059] For example, multiple gate lines and multiple read signal lines RL can intersect to define multiple arrayed detection units 50. Each detection unit 50 is provided with at least one thin-film transistor 20 and a photoelectric converter 8 connected to the thin-film transistor 20.

[0060] For example, the gate of the thin film transistor 20 can be connected to at least one gate line, the first electrode of the thin film transistor 20 can be electrically connected to a photoelectric converter 8, and the second electrode of the thin film transistor 20 can be connected to a read signal line RL.

[0061] For example, the first electrode of the thin-film transistor 20 can be the source electrode, and the second electrode of the thin-film transistor 20 can be the drain electrode; or, the first electrode of the thin-film transistor 20 can be the drain electrode, and the second electrode of the thin-film transistor 20 can be the source electrode.

[0062] For example, the thin-film transistor 20 may include an N-type thin-film transistor or a P-type thin-film transistor.

[0063] For example, the photoelectric converter 8 may include a photoresistor, a phototransistor, a photodiode, or an optocoupler.

[0064] In some flat panel detectors, thin-film transistors may include oxide thin-film transistors. The low leakage current of oxide thin-film transistors can improve the detection accuracy of flat panel detectors.

[0065] The inventors discovered that in some flat panel detectors, the thin-film transistors (TFTs) on the detection substrate can only meet the requirements for applications with X-ray doses below 2000 Gy, and cannot meet the requirements for higher dose X-ray irradiation. This is because in the fabrication process of some detection substrates, the photoelectric converter is processed after the TFT processing. The etching process of the photoelectric converter may damage the already fabricated TFTs, thus affecting their X-ray resistance. Furthermore, under high-dose X-ray irradiation, some TFTs exhibit negative bias (e.g., a negative shift in the threshold voltage), causing them to fail to switch normally, thereby affecting the X-ray resistance of the detection substrate.

[0066] In some embodiments of this disclosure, by optimizing the design of multiple film layers in the detector substrate, the damage to the thin-film transistor caused by the fabrication process of the photoelectric converter can be reduced and / or the X-ray resistance of the thin-film transistor itself can be improved, thereby enabling the detector substrate to meet the application scenarios with high X-ray doses.

[0067] Figure 3 This is a partial planar schematic diagram of a probe substrate according to an exemplary embodiment of the present disclosure. Figure 4 It is along Figure 3 A schematic diagram of the cross-section taken by the midline AA'. Figure 5 This is a partial planar schematic diagram of the third conductive layer and the photoelectric converter in the detector substrate according to an exemplary embodiment of the present disclosure. Figure 6 It is based on Figure 5 SEM images of a localized membrane layer in the P1 region. Figure 7 It is based on Figure 5 SEM image of a local membrane layer in the P2 region.

[0068] Exemplary embodiments of this disclosure provide a probe substrate 100, in conjunction with reference to... Figures 3-4 The detector substrate 100 may include: a substrate 1; at least one thin film transistor 20 located on one side of the substrate 1; a third conductive layer 7 located on the side of the thin film transistor 20 away from the substrate 1; and at least one photoelectric converter 8 located on the side of the third conductive layer 7 away from the substrate 1.

[0069] For example, thin-film transistor 20 may include an oxide thin-film transistor.

[0070] For example, the photoelectric converter 8 may include a photoresistor, a phototransistor, a photodiode, or an optocoupler.

[0071] For example, the photoelectric converter 8 may include a PIN photodiode. Alternatively, the photoelectric converter 8 may include a stacked P-type semiconductor layer, an intrinsic semiconductor layer, and an N-type semiconductor layer.

[0072] For example, the detector substrate 100 may include a first conductive portion 71 located in the third conductive layer 7, and at least one thin film transistor 20 may be electrically connected to at least one photoelectric converter 8 through the first conductive portion 71.

[0073] For example, the first conductive portion 71 can be used as the lower lead-out electrode of the photoelectric converter 8. For instance, the N-type semiconductor layer or the P-type semiconductor layer in the photoelectric converter 8 can be electrically connected to the first conductive portion 71.

[0074] For example, the area of ​​the photoelectric converter 8 projected onto the substrate can be larger than the area of ​​the thin-film transistor 20 electrically connected to the photoelectric converter 8 projected onto the substrate.

[0075] In some embodiments, to increase the area ratio of the photoelectric converter 8, the spacing between the thin-film transistor 20 and the photoelectric converter 8 can be designed to be smaller. During the etching process of the photoelectric converter 8, the etching process may damage nearby thin-film transistors, leading to a decrease in the performance of the thin-film transistors.

[0076] In some embodiments of this disclosure, the damage to thin-film transistors caused by the photoelectric converter etching process can be reduced by optimizing the structure and location of the third conductive layer.

[0077] For example, in conjunction with reference Figures 4-6 The first conductive portion 71 may include a first main body portion 711 and a first edge portion 712.

[0078] For example, the orthographic projection of at least one photoelectric converter 8 on the substrate can fall within the orthographic projection of the first main body portion 711 on the substrate.

[0079] It should be noted that, in the embodiments disclosed herein, the first main body portion 711 refers to the portion of the third conductive layer 7 located directly below the photoelectric converter 8. For example, the orthographic projection of at least one photoelectric converter 8 on the substrate and the orthographic projection of the first main body portion 711 on the substrate can completely overlap.

[0080] For example, the first edge portion 712 may at least partially surround the first body portion 711. At least a portion of the first edge portion 712 may be located on the side of the first body portion 711 away from the thin-film transistor 20. For example, refer to Figure 5 The first edge portion 712 may include: a first sub-edge portion 7121 of an elongated rectangular shape extending along the second direction Y on the right side of the first main body portion 711, a second sub-edge portion 7122 of an elongated rectangular shape extending along the first direction X on the lower side of the first main body portion 711, and a third sub-edge portion 7123 of an elongated rectangular shape extending along the second direction Y on the lower left side of the first main body portion 711.

[0081] With this design, the orthographic projection of the etching boundary of the photoelectric converter onto the substrate falls within the orthographic projection of the third conductive layer onto the substrate. Thus, the third conductive layer can be used as an etching barrier layer for the photoelectric converter, which helps to reduce the damage to other underlying film layers (such as the film layer where the thin-film transistor is located) caused by the etching process of the photoelectric converter.

[0082] In some embodiments, the third conductive layer 7 may be designed with multiple film layers stacked together.

[0083] For example, refer to Figure 6 The third conductive layer 7 may include a first sublayer 701 and a second sublayer 702, wherein the first sublayer 701 is located on the side of the second sublayer 702 away from the substrate.

[0084] For example, the first sublayer 701 may have a first thickness H1 in the third direction Z, and the second sublayer 702 may have a second thickness H2 in the third direction Z, which is parallel to the direction of the substrate toward the thin film transistor.

[0085] For example, the third direction Z can be perpendicular to the surface 101 of the substrate 1 facing the thin film transistor 20. It should be noted that, in the embodiments of this disclosure, the first thickness H1 refers to the average thickness of the first sublayer 701 in the third direction Z, and the second thickness H2 refers to the average thickness of the second sublayer 702 in the third direction Z.

[0086] For example, the first thickness H1 can be smaller than the second thickness H2.

[0087] For example, the first thickness H1 can be greater than or equal to 80 nanometers. For instance, the first thickness H1 can be equal to 80 nanometers, 85 nanometers, 90 nanometers, 100 nanometers, or 120 nanometers.

[0088] For example, the second thickness H2 can be greater than or equal to 100 nanometers. For instance, the second thickness H2 can be equal to 100 nanometers, 150 nanometers, 200 nanometers, 300 nanometers, 500 nanometers, or 800 nanometers.

[0089] For example, the material of the first sublayer 701 may include at least one of metals, metal compounds or metal alloys such as molybdenum, titanium, titanium nitride, molybdenum titanide, molybdenum niobide and molybdenum-titanium alloys.

[0090] For example, the material of the second sublayer 702 may include a conductive metal such as copper or aluminum.

[0091] For example, the first main body portion 711 may include a first surface S711 located in the first sublayer 701, the first surface S711 being the surface of the first main body portion 711 away from the substrate. The first edge portion 712 may include a second surface S712 located in the first sublayer 701, the second surface S712 being the surface of the first edge portion 712 away from the substrate.

[0092] For example, on the third direction Z, the second surface S712 may be closer to the substrate relative to the first surface S711.

[0093] This design allows for the use of a highly conductive second sublayer to improve the overall conductivity of the third conductive layer. Simultaneously, the use of an etch-resistant first sublayer as the top metal of the third conductive layer enhances its etch resistance. Consequently, the third conductive layer exhibits a superior etch barrier effect during the etching process of the photoelectric converter, preventing damage to the underlying thin-film transistors.

[0094] For example, the first surface S711 and the second surface S712 may have a first height difference M1 in the third direction Z. Here, the first height difference M1 refers to the average height difference between the first surface S711 and the second surface S712 in the third direction Z.

[0095] For example, the ratio of the first height difference M1 to the first thickness H1 can be less than 0.7. For instance, the ratio of the first height difference M1 to the first thickness H1 can be equal to 0.65, 0.625, 0.6, 0.5, or 0.4.

[0096] For example, the first height difference M1 can be greater than or equal to 50 nanometers. For instance, the first height difference M1 can be equal to 50 nanometers, 55 nanometers, 60 nanometers, 65 nanometers, or 70 nanometers.

[0097] By optimizing the film structure and thickness of the third conductive layer, the first edge of the first conductive part can form a wrapping effect on the photoelectric converter. At the same time, the first sub-layer in the first edge will not be completely etched away in the etching process of the photoelectric converter. This is beneficial to improving the conductivity of the first conductive part and the protection performance of the first conductive part for the underlying film layer. This is beneficial to improving the X-ray tolerance of the thin film transistor.

[0098] In some embodiments, refer to Figure 6 The third conductive layer 7 may also include a sixth sublayer 703, which may be located on the side of the second sublayer 702 close to the substrate.

[0099] For example, the material type of the sixth sublayer 703 and the material type of the first sublayer 701 may be the same or different.

[0100] For example, the third conductive layer 7 may include at least one of the following stacked structures: a molybdenum / aluminum / molybdenum stack, a titanium / aluminum / titanium stack, a titanium nitride / aluminum / titanium stack, a molybdenum titanide / copper / molybdenum titanium alloy stack, a molybdenum niobide / copper / molybdenum titanium alloy stack, and a molybdenum titanium alloy / copper / molybdenum titanium alloy stack.

[0101] The third conductive layer adopts a stacked design, which can ensure good conductivity of the third conductive layer while further improving the protection effect of the underlying film layer in the etching process of the photoelectric converter.

[0102] For example, in conjunction with reference Figures 3-5 and Figure 7 The probe substrate 100 may also include a first passivation layer 5 located between the thin-film transistor 20 and the third conductive layer 7.

[0103] For example, the first passivation layer 5 may include an inorganic film layer. For instance, the first passivation layer 5 may include at least one or a combination of multiple films such as silicon oxide, silicon nitride, and hydrogenated silicon nitride.

[0104] For example, the first passivation layer 5 may include a first via VO1, and the first conductive portion 71 may be electrically connected to the thin film transistor 20 through the first via VO1.

[0105] For example, the first conductive portion 71 may further include a second edge portion 713, which may be located on the side of the first body portion 711 near the thin-film transistor 20. For example, refer to Figure 5The second edge portion 713 may include this rectangular portion located at the upper left corner of the first body portion 711.

[0106] For example, at least a portion of the second edge portion 713 may be located in the first via VO1. The orthographic projection of the first via VO1 on the substrate may fall within the orthographic projection of the second edge portion 713 on the substrate.

[0107] For example, in conjunction with reference Figures 4-7 The second edge portion 713 may include a filling portion 7130 located in the first via VO1. The surface S713 of the filling portion 713 away from the substrate and the first surface S711 may have a second height difference M2 in the third direction Z. The second height difference M2 refers to the average height difference between the surface S713 of the filling portion 713 away from the substrate and the first surface S711 in the third direction Z.

[0108] For example, the second height difference M2 can be greater than the first height difference M1. For instance, the second height difference M2 can be equal to 90 nanometers, 95 nanometers, 100 nanometers, 105 nanometers, or 110 nanometers. The first height difference M1 can be equal to 50 nanometers, 55 nanometers, 60 nanometers, 65 nanometers, or 70 nanometers.

[0109] With this design, on the one hand, the first via in the first passivation layer can be used to realize the electrical connection between the first conductive part and the thin-film transistor, ensuring a good electrical connection effect between the photoelectric converter and the thin-film transistor; on the other hand, the combination of the first passivation layer and the third conductive layer can be used to protect the thin-film transistor below during the etching step of the photoelectric converter, which is beneficial to further reduce the impact of the photoelectric converter etching process on the thin-film transistor, improve the reliability of the thin-film transistor, and enhance the X-ray tolerance of the detection substrate.

[0110] For example, the first passivation layer 5 may include a silicon nitride film layer.

[0111] In some embodiments, during the etching process of the photoelectric converter, the etching process may cause an etching loss of about 200 nanometers in the silicon nitride film layer in the first passivation layer.

[0112] In some embodiments of this disclosure, in order to improve the protection effect of the first passivation layer on the thin-film transistor during the photoelectric converter etching process, the thickness of the first passivation layer can be increased.

[0113] For example, refer to Figure 5 The orthographic projection of the first via VO1 on the substrate and the orthographic projection of the photoelectric converter 8 on the substrate can be set at intervals.

[0114] For example, refer to Figure 8At least one photoelectric converter 8 can have its orthographic projection on the substrate fall within the orthographic projection of the first passivation layer 5 on the substrate. For example, the area of ​​the first passivation layer 5 excluding the first via VO1 can be a single film covering the entire surface.

[0115] For example, the orthogonal projection of the thin-film transistor 20 on the substrate can be substantially covered by the orthogonal projection of the first passivation layer 5 on the substrate.

[0116] For example, in conjunction with reference Figure 4 and Figure 6 The first passivation layer 5 may have a third thickness H3 in the third direction Z. Here, the third thickness H3 refers to the average thickness of the first passivation layer 5 in the third direction Z.

[0117] For example, the ratio of the third thickness H3 to the first height difference M1 can be greater than or equal to 4. For instance, the ratio of the third thickness H3 to the first height difference M1 can be equal to 4, 5, 6, 7 or 8.

[0118] For example, the third thickness H3 can be greater than or equal to 250 nanometers. For instance, the third thickness H3 can be equal to 250 nanometers, 300 nanometers, 400 nanometers, 600 nanometers, or 800 nanometers.

[0119] By designing the first passivation layer to be thicker, it is possible to avoid etching through the first passivation layer during the etching process of the photoelectric converter, thereby preventing damage to the underlying thin-film transistor. This helps to improve the protective effect of the first passivation layer on the thin-film transistor.

[0120] Exemplary, in some embodiments of this disclosure, reference is made to Figure 3 and Figure 4 The probe substrate 100 may also include a sacrificial layer 6 located between the first passivation layer 5 and the third conductive layer 7.

[0121] For example, the orthogonal projection of the photoelectric converter 8 on the substrate can fall within the orthogonal projection of the sacrificial layer 6 on the substrate.

[0122] For example, the material of the sacrificial layer 6 may include an oxide. For instance, the material of the sacrificial layer 6 may include at least one of oxide materials such as indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), or praseodymium-doped indium gallium zinc oxide (Pr-IGZO).

[0123] This design allows the sacrificial layer to further block damage to the underlying thin-film transistors caused by the photoelectric converter etching process. At the same time, during the fabrication of the sacrificial layer, it can replenish oxygen in the channel region of the underlying thin-film transistor, which helps improve the X-ray resistance of the thin-film transistor.

[0124] For example, in conjunction with reference Figure 3 and Figure 4 The sacrificial layer 6 may include a sacrificial portion 61, and the orthographic projection of the first conductive portion 71 on the substrate and the orthographic projection of the sacrificial portion 61 on the substrate may at least partially overlap.

[0125] For example, the orthographic projection of the photoelectric converter 8 onto the substrate can fall into the overlapping area of ​​the orthographic projections of the sacrificial portion 61 and the first conductive portion 71 onto the substrate.

[0126] For example, the edge 710 of the orthogonal projection of the first conductive portion 71 on the substrate and the edge 610 of the orthogonal projection of the sacrificial portion 61 on the substrate may have a first spacing distance Z1 in the second direction Y, the second direction Y being perpendicular to the third direction Z.

[0127] For example, the first spacing distance Z1 can be in the range of 0.5 micrometers to 2 micrometers. For instance, the first spacing distance Z1 can be equal to 0.5 micrometers, 0.8 micrometers, 1.2 micrometers, 1.6 micrometers or 2 micrometers.

[0128] This design allows for a larger perimeter between the sacrificial portion and the first conductive portion, which improves the blocking effect of the combination of the sacrificial layer and the third conductive layer on the etching process of the photoelectric converter. This further reduces the damage to the underlying thin-film transistor caused by the etching process of the photoelectric converter.

[0129] In some embodiments, a portion of the film layer (e.g., the first passivation layer 5) in the detection substrate may release free hydrogen under X-ray irradiation. The free hydrogen may include one or more combinations of atomic hydrogen, hydrogen ions, or negative hydrogen ions.

[0130] In some embodiments, the sacrificial portion 61 may be disposed directly below the photoelectric converter 8, and at least a portion of the sacrificial layer material in the surrounding area of ​​the photoelectric converter 8 may be etched away to form an etched groove. For example, the sacrificial layer material above the area where the thin-film transistor 20 is located may be etched away.

[0131] For example, the orthographic projection of the sacrificial portion 61 on the substrate and the orthographic projection of the thin-film transistor 20 on the substrate can be arranged at intervals.

[0132] This design allows for two main benefits: firstly, it increases the ventilation channels above the thin-film transistor, enabling the release of water and oxygen generated by multiple film layers in the region where the thin-film transistor is located; secondly, it allows hydrogen (H) generated during the photoelectric converter fabrication process to be released in subsequent high-temperature processes, which is beneficial for improving the stability and reliability of the thin-film transistor's characteristics.

[0133] In some embodiments of this disclosure, on the side of the photoelectric converter 8 away from the thin-film transistor 20, since there is no sacrificial layer 6 to block it, the etching process of the photoelectric converter 8 may cause over-etching in a local area of ​​the first passivation layer 5, forming a step.

[0134] In an exemplary embodiment of this disclosure, a protective layer may be formed on the side of the photoelectric converter away from the substrate to cover and protect the over-etching step of the first passivation layer.

[0135] Figure 8 This is a partial planar schematic diagram of a portion of a film layer in a probe substrate according to an exemplary embodiment of the present disclosure. Figure 9 It is based on Figure 8 SEM image of a local membrane layer in the P3 region.

[0136] Exemplary, in some embodiments of this disclosure, reference is made to Figures 3-4 and Figures 8-9 The first passivation layer 5 may include a second main body portion 511 and a third edge portion 512.

[0137] For example, the orthographic projection of at least one photoelectric converter 8 on the substrate can fall within the orthographic projection of the second main body portion 511 on the substrate.

[0138] It should be noted that, in the embodiments of this disclosure, the second main body portion 511 refers to the portion of the first passivation layer 5 located directly below the photoelectric converter 8. For example, the orthographic projection of at least one photoelectric converter 8 on the substrate and the orthographic projection of the second main body portion 511 on the substrate can completely overlap.

[0139] With this design, the orthographic projection of the etching boundary of the photoelectric converter onto the substrate can fall within the orthographic projection of the first passivation layer onto the substrate. Thus, the first passivation layer can be used as an etching barrier layer for the photoelectric converter, which helps to reduce the damage to other underlying film layers (such as the film layer where the thin-film transistor is located) caused by the etching process of the photoelectric converter.

[0140] For example, refer to Figure 8 The third edge portion 512 may be located on the side of the second body portion 511 away from the thin-film transistor 20. For example, the third edge portion 512 may include this rectangular portion located on the right side of the second body portion 511.

[0141] For example, refer to Figure 9 The surface S512 of the third edge portion 512 that is away from the substrate and the surface S511 of the second main body portion 511 that is away from the substrate may have a third height difference M3 in the third direction Z.

[0142] It should be noted that, in the embodiments of this disclosure, the third height difference M3 refers to the average height difference in the third direction Z between the surface S512 of the third edge portion 512 away from the substrate and the surface S511 of the second main body portion 511 away from the substrate.

[0143] For example, in conjunction with reference Figure 4 , Figure 6 and Figure 9 The ratio of the third height difference M3 to the first height difference M1 can be greater than or equal to 3. For example, the ratio of the third height difference M3 to the first height difference M1 can be equal to 3, 4, 5, 6 or 7.

[0144] For example, the third height difference M3 can be less than the third thickness H3.

[0145] For example, the third height difference M3 can be approximately 200 nanometers.

[0146] For example, the detector substrate 100 may also include a protective layer 17 located on the side of the photoelectric converter 8 away from the substrate 1, and the surface S512 of the third edge portion 512 away from the substrate may be covered by the protective layer 17.

[0147] For example, the material of the protective layer 17 may include silicon oxide or silicon nitride.

[0148] This design prevents the first passivation layer, located in the area surrounding the photoelectric converter, from being over-etched through, thus improving its protective effect on the underlying film. Simultaneously, a protective layer can be used to encapsulate and protect the over-etched areas of the first passivation layer, reducing the likelihood of defects such as film cracking in these areas.

[0149] In some embodiments of this disclosure, the first conductive portion in the third conductive layer can be electrically connected to the underlying thin-film transistor via a first via. Since the boundary of the first conductive portion is close to the first via, during the etching process of the third conductive layer, over-etching may occur in a portion of the first passivation layer near the first via region.

[0150] In some embodiments of this disclosure, the film structure and thickness of the first passivation layer can be optimized to reduce the impact of the third conductive layer etching process on the portion of the first passivation layer near the first via region.

[0151] Figure 10 It is based on Figure 8 SEM image of a local membrane layer in the P4 region.

[0152] Exemplary, in some embodiments of this disclosure, reference is made to Figure 4 , Figure 8 and Figure 10 The first passivation layer 5 can be designed as a stack. By adjusting the material type and thickness of multiple sub-layers in the first passivation layer, a portion of the film layer near the first via region can form a side surface with a vertical and sloping morphology during the etching process of the third conductive layer.

[0153] For example, the first passivation layer 5 may include a stack of silicon oxide / silicon nitride; or, the first passivation layer 5 may include a stack of silicon oxide / silicon nitride / silicon oxide.

[0154] For example, the first passivation layer 5 may further include a fourth edge portion 513 located on the side of the second body portion 511 near the thin-film transistor 20. For instance, the fourth edge portion 513 may include the portion located to the left of the first via VO1 and adjacent to the boundary 7131 of the second edge portion 713.

[0155] For example, refer to Figure 10 The fourth edge portion 513 may include a first side surface L1, which may include a first sub-side surface L11 and a second sub-side surface L12. The first sub-side surface L11 is located on the side of the second sub-side surface L12 away from the substrate.

[0156] For example, the first sub-side L11 may have a first slope angle θ1, and the second sub-side L12 may have a second slope angle θ2.

[0157] It should be noted that the first slope angle θ1 refers to the angle between the first sub-side L11 and the first plane direction, and the second slope angle θ2 refers to the angle between the second sub-side L12 and the first plane direction. The first plane direction is perpendicular to the third direction Z.

[0158] For example, the first slope angle θ1 can be greater than the second slope angle θ2.

[0159] For example, the first slope angle θ1 can be greater than 75°. For instance, the first slope angle θ1 can be equal to 78°, 80°, 83°, 85°, or 90°.

[0160] For example, the second slope angle θ2 can be less than 60°. For instance, the second slope angle θ2 can be equal to 58°, 50°, 42°, 35°, or 30°.

[0161] For example, the height H11 of the first sub-side L11 in the third direction Z can be approximately 130 nanometers.

[0162] For example, the height H12 of the second sub-side L12 in the third direction Z can be approximately 130 nanometers.

[0163] By optimizing the structure and thickness of the first passivation layer, the first side of the first passivation layer near the first opening can form a vertical and sloping surface morphology. This allows the first passivation layer to provide better support for the third conductive layer above, while also improving the climbing continuity of the subsequently prepared protective layer. This results in better protection of the edges of the first passivation layer and the third conductive layer by the protective layer, which is beneficial to improving the reliability of the probe substrate.

[0164] For example, the material of the first sublayer 701 in the third conductive layer 7 may include molybdenum, and the material of the second sublayer 702 may include aluminum.

[0165] In some embodiments, since the etching rate of the first sublayer 701 is slower than that of the second sublayer 702, the first sublayer 701 can protrude from the surface of the second sublayer 702 away from the substrate toward the side closer to the thin-film transistor 20, thereby forming a protrusion T701 (e.g. Figure 10 The area indicated by the middle arrow P6).

[0166] Figure 11 This is a schematic diagram of the structure of the first passivation layer in a probe substrate according to an exemplary embodiment of the present disclosure.

[0167] Exemplary, in some embodiments of this disclosure, reference is made to Figure 11 The first passivation layer 5 may include: a third sublayer 501; a fourth sublayer 502 located on the side of the third sublayer 501 away from the substrate; and a fifth sublayer 503 located on the side of the fourth sublayer 502 away from the substrate.

[0168] For example, the fifth sublayer 503 may include silicon oxide, the fourth sublayer 502 may include hydrogenated silicon nitride, and the third sublayer 501 may include silicon nitride.

[0169] For example, the total thickness of the third sublayer 501, the fourth sublayer 502, and the fifth sublayer 503 in the third direction Z can be in the range of 100 nm to 800 nm, i.e., 100 nm ≤ H51 + H52 + H53 ≤ 800 nm. Here, H51 is the thickness of the third sublayer 501 in the third direction Z, H52 is the thickness of the fourth sublayer 502 in the third direction Z, and H53 is the thickness of the fifth sublayer 503 in the third direction Z.

[0170] For example, the ratio of the thickness H52 of the fourth sublayer 502 in the third direction Z to the thickness H51 of the third sublayer 501 in the third direction Z can be in the range of 0.2 to 1. For instance, the ratio of the thickness H52 of the fourth sublayer 502 in the third direction Z to the thickness H51 of the third sublayer 501 in the third direction Z can be equal to 1:1, 1:2, 1:3, 1:4, 2:3, 2:5, 3:4 or 3:5.

[0171] This design reduces the number of silicon-hydrogen bonds in the first passivation layer, which helps to reduce hydrogen diffusion to the active part. It can improve the etching resistance of the first passivation layer during the fabrication of the photoelectric converter, while reducing the impact of the first passivation layer on the active part of the thin-film transistor under X-ray irradiation.

[0172] In some embodiments of this disclosure, the detection substrate may include multiple detection units, and the boundary between adjacent detection units may be reduced as the resolution increases.

[0173] Figure 12 It is based on Figure 3 SEM image of a local membrane layer in the P5 region.

[0174] Exemplary, in some embodiments of this disclosure, reference is made to Figure 2 , Figure 3 and Figure 12 The detection substrate 100 may include multiple detection units 50, which may be arranged in an array along a first direction X and a second direction Y, wherein the first direction X and the second direction Y intersect. For example, Figure 3 A detection unit 50 and a portion of a sacrificial layer 6 in another detection unit located to the left of the detection unit 50 are shown.

[0175] For example, the sacrificial layer 6 may include a plurality of sacrificial portions 61, and at least one detection unit 50 may include a thin film transistor 20, a photoelectric converter 8, and a sacrificial portion 61.

[0176] For example, in at least one detection unit 50, the orthogonal projection of the photoelectric converter 8 on the substrate can fall within the orthogonal projection of the sacrificial portion 61 on the substrate.

[0177] For example, two adjacent sacrificial portions 61 may be spaced apart by a second spacing distance Z2 in the first direction X. For example, refer to Figure 3 The two sacrificial parts 61 may each include a boundary 611 extending along the second direction Y, and the spacing between adjacent boundaries 611 in the two adjacent sacrificial parts in the first direction X may be equal to the second spacing distance Z2.

[0178] For example, the ratio of the second interval distance Z2 to the first interval distance Z1 can be greater than or equal to 6. For instance, the ratio of the second interval distance Z2 to the first interval distance Z1 can be equal to 6, 8, 10, 15, 20, or 24.

[0179] For example, the second spacing distance Z2 can be approximately 12 micrometers.

[0180] This design ensures that the sacrificial layer effectively blocks the etching process of the photoelectric converter while increasing the fill rate of the photoelectric converter. This improves the signal amplitude in the detection substrate, thereby enhancing the detection sensitivity of the flat panel detector.

[0181] In some embodiments of this disclosure, at least a portion of the multiple film layers in which the thin-film transistor is located can be optimized to improve the stability of the thin-film transistor and its resistance to X-rays.

[0182] Figure 13 This is a SEM test image of a local film layer of a thin-film transistor in a probe substrate according to an exemplary embodiment of the present disclosure.

[0183] Exemplary, in some embodiments of this disclosure, reference is made to Figure 4 and Figure 13 The probe substrate 100 may include: a first conductive layer 2, a first semiconductor layer 3 and a first insulating layer GI, wherein the first insulating layer GI may be located between the first conductive layer 2 and the first semiconductor layer 3.

[0184] For example, the thin film transistor 20 may include a control electrode G and an active part ACT. The control electrode G of the thin film transistor 20 may be located in the first conductive layer 2, and the active part ACT of the thin film transistor 20 may be located in the first semiconductor layer 3.

[0185] For example, the material of the first insulating layer GI may include silicon nitride.

[0186] In some embodiments, the first insulating layer GI may include a single layer of silicon nitride film.

[0187] In other embodiments, the first insulating layer GI may include at least one of a silicon nitride / hydrogenated silicon nitride stack, a silicon nitride / hydrogenated silicon nitride / silicon nitride stack, a hydrogenated silicon nitride / silicon nitride stack, a silicon nitride / silicon oxide stack, and a hydrogenated silicon nitride / silicon oxide stack.

[0188] By optimizing the film structure and material type of the first insulating layer, the hole-trapping ability of the first insulating layer can be improved and the amount of hydrogen released from the first insulating layer can be reduced. This can improve the phenomenon of hydrogen-induced degradation of thin-film transistors induced by X-ray irradiation. Furthermore, the first insulating layer can be used to trap ionized holes, which helps to reduce the impact of X-ray irradiation on the performance of thin-film transistors, thereby improving the X-ray resistance of the detection substrate.

[0189] For example, the ratio of the number of silicon atoms to the number of nitrogen atoms in the first insulating layer GI can be in the range of 1.2 to 2. For instance, the ratio of the number of silicon atoms to the number of nitrogen atoms in the first insulating layer GI can be equal to 1.2, 1.4, 1.6, 1.8 or 2.

[0190] By increasing the number of silicon atoms in the first insulating layer, the internal stress of the first insulating layer can be reduced, which can improve the problem of cracking of the first insulating layer. At the same time, a large number of Si-Si bonds and silicon dangling bonds can be formed in the first insulating layer, generating a large number of deep energy level traps. When electron-hole pairs are generated by X-ray irradiation, most of the holes can be captured by the deep traps formed by Si-Si bonds, and the charge is confined inside the first insulating layer, which is beneficial to improving the threshold negative drift phenomenon of thin film transistors.

[0191] For example, the crystal structure of the first insulating layer GI may include a plurality of silicon-hydrogen bonds and a plurality of silicon-nitrogen bonds, and the ratio of the number of silicon-hydrogen bonds to the number of silicon-nitrogen bonds in the crystal structure of the first insulating layer GI may be in the range of 0.03 to 0.22. For example, the ratio of the number of silicon-hydrogen bonds to the number of silicon-nitrogen bonds in the crystal structure of the first insulating layer GI may be equal to 0.03, 0.06, 0.09, 0.15, 0.18 or 0.22.

[0192] For example, the silicon-hydrogen bond content in the crystal structure of the first insulating layer GI can range from 3% to 18%, and the silicon-nitrogen bond content can range from 82% to 97%. For instance, the silicon-hydrogen bond content in the crystal structure of the first insulating layer GI can be approximately 4.18%, and the silicon-nitrogen bond content can be approximately 95.82%. As another example, the silicon-hydrogen bond content in the crystal structure of the first insulating layer GI can be approximately 12.38%, and the silicon-nitrogen bond content can be approximately 87.62%.

[0193] By reducing the number of silicon-hydrogen bonds in the first insulating layer, the amount of free hydrogen generated by the decomposition of the first insulating layer under X-ray irradiation can be significantly reduced, which helps to reduce hydrogen diffusion to the active part. At the same time, it can also reduce the number of interface defects in the first insulating layer, avoid the generation of X-ray induced interface traps at the interface, and further improve the X-ray resistance of thin film transistors.

[0194] In some embodiments, the thin-film transistor 20 may employ a bottom gate design.

[0195] For example, in conjunction with reference Figure 4 and Figure 13 The first insulating layer GI can be located on the side of the first conductive layer 2 away from the substrate 1, and the first semiconductor layer 3 can be located on the side of the first insulating layer GI away from the substrate.

[0196] For example, the probe substrate 100 may include a second conductive portion 22 located in the first conductive layer 2, and the control electrode G may be located in the second conductive portion 22. For instance, the portion of the second conductive portion 22 that overlaps with the projection of the active portion ACT may be the control electrode G of a thin-film transistor.

[0197] For example, the probe substrate 100 may also include a second conductive layer 4 located between the first semiconductor layer 3 and the third conductive layer 7, and the second conductive layer 4 may include a third conductive portion 43 and a fourth conductive portion 44.

[0198] The thin-film transistor 20 may also include a first electrode S and a second electrode D. The first electrode S of the thin-film transistor 20 may be located in the third conductive part 43, and the second electrode D of the thin-film transistor 20 may be located in the fourth conductive part 44.

[0199] For example, the second conductive portion 22 may include a second side surface L22, which may be the side of the second conductive portion 22 near the first electrode S or the second electrode D of the thin film transistor.

[0200] For example, the second side L22 may have a third slope angle θ3. The third slope angle θ3 may be in the range of 20° to 30°. For example, the third slope angle θ3 may be equal to 20°, 22°, 24°, 27° or 30°.

[0201] This design allows for a smaller slope angle on the second side of the second conductive part, which improves the continuity of the slope between the first insulating layer and the second conductive layer above the second conductive part. This helps reduce the probability of wire breaks in the conductive part of the second conductive layer and cracks in the first insulating layer, thereby improving the stability of the thin-film transistor and reducing the probability of leakage and short circuits.

[0202] Figure 14 This is a schematic plan view of a portion of a film layer in a probe substrate according to an exemplary embodiment of the present disclosure.

[0203] For example, in conjunction with reference Figure 3 , Figure 4 and Figure 14 The third conductive part 43 can be electrically connected to the first conductive part 71 through the first through hole VO1.

[0204] The second conductive part 22 may include a third main body part 221 and a first branch part 222. The third main body part 221 may extend along the first direction X, and the first branch part 222 may be located on the side of the third main body part 221 facing the photoelectric converter 8.

[0205] For example, the orthographic projection of the first branch 222 onto the substrate and the orthographic projection of the active portion ACT onto the substrate can at least partially overlap. The portion of the first branch 222 that overlaps with the projection of the active portion ACT can be the control electrode G of a thin-film transistor.

[0206] For example, the orthographic projection of the first branch 222 on the substrate and the orthographic projection of the third conductive portion 43 on the substrate may at least partially overlap. The overlapping portion of the projections of the first branch 222 and the third conductive portion 43 may have a first width d1 in the first direction X.

[0207] For example, the ratio of the first width d1 to the first spacing distance Z1 can be less than or equal to 3.6. For instance, the ratio of the first width d1 to the first spacing distance Z1 can be equal to 0.5, 0.9, 1.6, 2.4, 3, or 3.6.

[0208] For example, the first width d1 can be less than or equal to 1.8 micrometers. For instance, the first width d1 can be equal to 0.4 micrometers, 0.8 micrometers, 1.2 micrometers, 1.5 micrometers, or 1.8 micrometers.

[0209] This design reduces the overlap area between the first branch and the third conductive part, which helps to reduce the probability of short circuits in the second and third conductive parts. This, in turn, reduces the probability of short circuits between the control electrode and the source / drain electrode in the thin-film transistor.

[0210] In some embodiments, refer to Figure 14 The orthographic projection of the sacrificial layer 6 onto the substrate and the orthographic projection of the thin-film transistor 20 onto the substrate can at least partially overlap. For example, the orthographic projection of the active portion ACT in the thin-film transistor onto the substrate can fall within the orthographic projection of the sacrificial layer 6 onto the substrate.

[0211] This design allows the active part of the thin-film transistor to be separated from the photoelectric converter using a sacrificial layer. This further reduces the damage to the thin-film transistor caused by the etching process of the photodiode, and helps to improve the reliability and X-ray resistance of the thin-film transistor.

[0212] In some embodiments of this disclosure, one or more conductive layers above the thin-film transistor can also be used as a light-shielding film to block the thin-film transistor, thereby reducing the impact of external light (such as X-rays) on the performance of the thin-film transistor.

[0213] Figure 15 This is a schematic plan view of a portion of a film layer in a probe substrate according to an exemplary embodiment of the present disclosure.

[0214] Exemplary, in some embodiments of this disclosure, reference is made to Figure 4 and Figure 15The orthographic projection of the active part ACT on the substrate can fall within the orthographic projection of the third conductive layer 7 on the substrate, thus the third conductive layer can be used to block the light directed towards the thin film transistor.

[0215] Exemplary, in some embodiments of this disclosure, reference is made to Figure 3 and Figure 4 The detector substrate 100 may also include a light-shielding layer 11, which may be located on the side of the photoelectric converter 8 away from the substrate 1.

[0216] For example, the light-shielding layer 11 may include a light-shielding part 111, and the orthographic projection of the active part ACT on the substrate may fall within the orthographic projection of the light-shielding part 111 on the substrate, so that the light-shielding layer can be used to block the light incident on the thin film transistor.

[0217] For example, the detector substrate 100 may also include a fourth conductive layer 16, which may be located on the side of the photoelectric converter 8 away from the substrate 1.

[0218] For example, the fourth conductive layer 16 may include indium tin oxide.

[0219] By way of example, the probe substrate may further include a fifth conductive portion 165 located in the fourth conductive layer 16. The fifth conductive portion 165 may be used as the upper lead-out electrode of the photoelectric converter 8.

[0220] In some embodiments, the orthographic projection of the active part ACT onto the substrate may fall into the overlapping area of ​​the projections of the third conductive layer 7 and the light-shielding layer 11.

[0221] With this design, at least one of the third conductive part and the light-shielding layer can be used to block external light, which can reduce the impact of external light on the thin-film transistor and improve the stability and X-ray resistance of the thin-film transistor.

[0222] For example, return to reference Figure 4 The detector substrate 100 may also include a planarization layer 9 located on the side of the photoelectric converter 8 away from the substrate 1.

[0223] For example, the orthographic projection of the thin-film transistor 20 on the substrate can fall within the orthographic projection of the planarization layer 9 on the substrate.

[0224] For example, the material of the planarization layer 9 may include a silicon-containing organic material.

[0225] This design allows the incident X-rays to be attenuated to a certain extent, while also capturing electrons or holes generated by X-ray excitation in some of the film layers in the detection substrate. In addition, the planarization layer can block external moisture and suppress the diffusion of free hydrogen to the side closer to the thin-film transistor, which is beneficial to improving the X-ray resistance of the thin-film transistor.

[0226] For example, the probe substrate 100 may also include a third insulating layer 10 located between the planarization layer 9 and the light-shielding layer 11.

[0227] For example, the third insulating layer 10 may include silicon nitride, which can improve the bonding strength between the planarization layer and the fourth conductive layer.

[0228] For example, in conjunction with reference Figure 3 and Figure 4 The probe substrate 100 may include: a fourth via VO4 penetrating the third insulating layer 10, a fifth via VO5 penetrating the planarization layer 9, and a sixth via VO6 penetrating the protective layer 17.

[0229] For example, the light-shielding part 111 can be electrically connected to the fifth conductive part 165 through the fourth through hole VO4, the fifth through hole VO5 and the sixth through hole VO6.

[0230] This design makes it easy to bring out the electrodes of the photoelectric converter.

[0231] For example, continue to refer to Figure 4 The detector substrate 100 may further include: a fourth insulating layer 12 located on the side of the light-shielding layer 11 away from the substrate; and a fifth conductive layer 13 located on the side of the fourth insulating layer 12 away from the substrate.

[0232] For example, refer to Figure 3 The orthographic projection of the photoelectric converter 8 on the substrate can fall within the orthographic projection of the fifth conductive layer 13 on the substrate.

[0233] In some embodiments of this disclosure, the thin-film transistor may employ a bottom-gate design.

[0234] For example, refer to Figure 4 The second conductive layer 4 can be located on the side of the first semiconductor layer 3 away from the substrate.

[0235] For example, the active part ACT may include a first pole region A1, a second pole region A3 and a channel region A2, wherein the channel region A2 may be located between the first pole region A1 and the second pole region A3.

[0236] For example, the first electrode region A1 can be electrically connected to the first electrode S of the thin-film transistor 20, and the second electrode region A3 can be electrically connected to the second electrode D of the thin-film transistor 20. For instance, the first electrode S of the thin-film transistor 20 can be directly connected to the first electrode region A1, and the second electrode D of the thin-film transistor 20 can be directly connected to the second electrode region A3.

[0237] This design facilitates the connection between the source / drain and active parts of the thin-film transistor, eliminating the need for an insulating layer between the second conductive layer and the first semiconductor layer. This reduces the number of film layers and lowers processing costs.

[0238] Figure 16 This is a schematic diagram of the structure of a probe substrate according to an exemplary embodiment of the present disclosure.

[0239] Figure 16 Other structures of the probe substrate shown in the embodiment and Figure 4 The other structures of the detector substrate in the illustrated embodiment are basically the same and will not be described in detail here. The following will focus on... Figure 16 The probe substrate and shown in the embodiment Figure 4 The differences in the probe substrate of the illustrated embodiment will be described in detail.

[0240] For example, refer to Figure 16 The first insulating layer GI may include a single layer of silicon nitride.

[0241] For example, the third conductive layer 7 can be directly disposed on the side of the first passivation layer 5 away from the substrate. That is, a sacrificial layer may not be disposed between the third conductive layer 7 and the first passivation layer 5.

[0242] This design allows for several advantages. First, the combination of the first passivation layer and the third conductive layer can reduce the damage to the underlying thin-film transistors caused by the photoelectric converter etching process. Second, it reduces the need for sacrificial layers, which helps lower the production cost of the detection substrate. Third, the first insulating layer can be a single-layer silicon nitride design, which can reduce the thin-film transistors' tolerance to X-ray irradiation.

[0243] In some embodiments of this disclosure, the thin-film transistor may employ a top-gate design.

[0244] Figure 17 This is a schematic diagram of the structure of a probe substrate according to an exemplary embodiment of the present disclosure.

[0245] Exemplary, in some embodiments of this disclosure, reference is made to Figure 17 The first insulating layer GI can be located on the side of the first semiconductor layer 3 away from the substrate 1, and the first conductive layer 2 can be located on the side of the first insulating layer GI away from the substrate 1.

[0246] For example, the thin-film transistor 20 may include a control electrode G and an active part ACT. The control electrode G of the thin-film transistor 20 may be located in the first conductive layer 2, and the active part ACT may be located in the first semiconductor layer 3, so that the control electrode G can serve as the top gate of the thin-film transistor 20.

[0247] For example, the active part ACT may include a first pole region A1, a second pole region A3 and a channel region A2, with the channel region A2 located between the first pole region A1 and the second pole region A3.

[0248] For example, the first electrode region A1 and the second electrode region A3 can be made conductive through a doping process.

[0249] For example, the probe substrate 100 may also include a second conductive layer 4 located on the side of the first semiconductor layer 3 near the substrate 1.

[0250] The second conductive layer 4 may include a third conductive portion 43, which may be electrically connected to the second electrode region A3. The second electrode D of the thin-film transistor may be located in the third conductive portion 43.

[0251] For example, the detection substrate may include a third conductive layer 7 located between the thin-film transistor 20 and the photoelectric converter 8. The third conductive layer 7 may include a first conductive portion 71, which may be electrically connected to a first electrode region A1. The first electrode S of the thin-film transistor may be located in the first conductive portion 71.

[0252] This design allows for the formation of a top-gate thin-film transistor (TFT). The second conductive layer is located on the side of the first conductive layer closest to the substrate, thus its morphology is unaffected by the first conductive layer, reducing the requirement for the side slope angle of the first conductive layer. Simultaneously, the active portion can be electrically connected to the first / third conductive portion through localized conductor formation, which helps reduce the impact of hydrogen on the TFT during photoelectric converter fabrication. Furthermore, the first conductive portion can be reused as the first electrode of the TFT, reducing its area and increasing the area ratio (fill rate) of the photodiode in the detection unit. This, in turn, improves the signal amplitude in the detection substrate and enhances the detection sensitivity of the flat panel detector.

[0253] For example, Figure 17 In the embodiment shown, multiple film layers located above the first passivation layer 5 and Figure 4 In the illustrated embodiment, the multiple film layers located above the first passivation layer 5 can employ the same design. For example, refer to... Figure 17The detection substrate 100 may further include: a first passivation layer 5 located on the side of the first conductive layer 2 away from the substrate 1; a third conductive layer 7 located on the side of the first passivation layer 5 away from the substrate 1; a photoelectric converter 8 located on the side of the third conductive layer 7 away from the substrate 1; a fourth conductive layer 16 located on the side of the photoelectric converter 8 away from the substrate 1; a planarization layer 9 located on the side of the fourth conductive layer 16 away from the substrate 1; a third insulating layer 10 located on the side of the planarization layer 9 away from the substrate 1; and a light-shielding layer 11 located on the side of the third insulating layer 10 away from the substrate 1.

[0254] Figure 18 This is a schematic diagram of the structure of a probe substrate according to an exemplary embodiment of the present disclosure.

[0255] Exemplary, in some embodiments of this disclosure, reference is made to Figure 18 The first insulating layer GI can be located on the side of the first semiconductor layer 3 away from the substrate 1, and the first conductive layer 2 can be located on the side of the first insulating layer GI away from the substrate 1.

[0256] For example, the thin-film transistor 20 may include a control electrode G and an active part ACT. The control electrode G of the thin-film transistor 20 may be located in the first conductive layer 2, and the active part ACT may be located in the first semiconductor layer 3, so that the control electrode G can serve as the top gate of the thin-film transistor 20.

[0257] For example, the active part ACT may include a first pole region A1, a second pole region A3 and a channel region A2, with the channel region A2 located between the first pole region A1 and the second pole region A3.

[0258] For example, the first pole region A1 and the second pole region A3 can be made conductive through doping.

[0259] For example, the probe substrate 100 may further include: a second insulating layer 19 located on the side of the first conductive layer 2 away from the substrate 1; and a second conductive layer 4 located on the side of the second insulating layer 19 away from the substrate 1.

[0260] For example, the second conductive layer 4 may include a third conductive portion 43 and a fourth conductive portion 44, and the second insulating layer 19 may include a second via VO2 and a third via VO3.

[0261] For example, the third conductive part 43 can be electrically connected to the first electrode region A1 through the second via VO2.

[0262] For example, the fourth conductive part 44 can be electrically connected through the third via VO3 and the second electrode region A3.

[0263] This design allows for the protection of the active component by utilizing a second insulating layer, which helps reduce parasitic capacitance in the thin-film transistor, improves the switching speed of the thin-film transistor, and reduces power consumption.

[0264] For example, the detection substrate 100 may further include: a photoconverter 8 located on the side of the third conductive layer 7 away from the substrate 1; a fourth conductive layer 16 located on the side of the photoconverter 8 away from the substrate 1; a third insulating layer 10 located on the side of the fourth conductive layer 16 away from the substrate 1; a planarization layer 9 located on the side of the third insulating layer 10 away from the substrate 1; and a light-shielding layer 11 located on the side of the third insulating layer 10 away from the substrate 1.

[0265] For example, the probe substrate 100 may also include a buffer layer buf located between the first semiconductor layer 3 and the substrate 1.

[0266] For example, the light-shielding layer 11 may include a light-shielding portion 111, and the orthographic projection of the thin-film transistor on the substrate may at least partially overlap with the orthographic projection of the light-shielding portion 111 on the substrate.

[0267] For example, the third conductive layer 7 may further include a seventh conductive portion 72. The light-shielding portion 111 may be electrically connected to the seventh conductive portion 72. The seventh conductive portion 72 may be used as a signal trace in the probe substrate.

[0268] For example, the light-shielding part 111 can be electrically connected to the photoelectric converter 8 through the fourth conductive layer 16.

[0269] This design allows for both the shielding of the thin-film transistor and the electrical connection between the photoelectric converter and the external circuitry.

[0270] For example, return to reference Figure 1 Embodiments of this disclosure also provide a flat panel detector 200, which may include the detection substrate 100 as described in any of the preceding embodiments. It should be understood that the flat panel detectors of the embodiments of this disclosure have the same beneficial effects as the detection substrates provided in the foregoing embodiments.

[0271] Figure 19 This is a flowchart of a method for preparing a probe substrate according to an exemplary embodiment of the present disclosure.

[0272] Exemplary embodiments of this disclosure also provide a method for fabricating a probe substrate. (See reference...) Figure 3 , Figure 4 and Figure 19 The method for preparing the probe substrate may include the following steps S01-S04.

[0273] In step S01, a substrate 1 is provided. For example, substrate 1 may include a glass substrate.

[0274] In step S02, at least one thin-film transistor 20 is formed on one side of the substrate 1.

[0275] For example, the thin-film transistor 20 may include a top-gate thin-film transistor or a bottom-gate thin-film transistor.

[0276] For example, a first conductive layer 2, a first insulating layer GI, a first semiconductor layer 3, and a second conductive layer 4 can be sequentially formed on one side of a substrate to form a thin film transistor 20.

[0277] For example, the first conductive layer 2 may include a single layer of metal such as molybdenum or copper; or the first conductive layer 2 may include a stack of two layers of metal such as molybdenum niobate / copper, molybdenum-titanium alloy / copper, or titanium / copper; or the first conductive layer 2 may include a stack of three layers of metal such as molybdenum niobate / copper / molybdenum-titanium alloy, molybdenum-titanium alloy / copper / molybdenum-titanium alloy, or molybdenum titanate / copper / molybdenum-titanium alloy.

[0278] For example, the thickness of the first conductive layer 2 can be in the range of 100 nanometers to 1000 nanometers.

[0279] For example, the material of the first insulating layer GI may include silicon nitride.

[0280] In some embodiments, the first insulating layer GI may comprise a single layer of silicon nitride film. The thickness of the first insulating layer GI may be in the range of 200 nanometers to 500 nanometers.

[0281] In some embodiments, the first insulating layer GI may include at least one of a silicon nitride / hydrogenated silicon nitride stack, a silicon nitride / hydrogenated silicon nitride / silicon nitride stack, a hydrogenated silicon nitride / silicon nitride stack, a silicon nitride / silicon oxide stack, and a hydrogenated silicon nitride / silicon oxide stack.

[0282] When the first insulating layer GI adopts a stacked structure design including a silicon nitride film layer, the thickness of the silicon nitride film layer can be in the range of 50 nanometers to 200 nanometers.

[0283] For example, the thickness of the first semiconductor layer 3 can be in the range of 30 nanometers to 150 nanometers.

[0284] For example, the first semiconductor layer 3 may comprise a single layer of metal oxide. For instance, the first semiconductor layer 3 may comprise an oxide film formed of a material doped with a high-mobility oxide in indium tin oxide (ITO). Alternatively, the first semiconductor layer 3 may comprise indium gallium zinc oxide (IGZO), aluminum indium gallium zinc oxide (Al-ITZO), or praseodymium-doped oxide.

[0285] Exemplarily, the first semiconductor layer 3 may also include a stacked structure. For example, the first semiconductor layer 3 may include a stack of high mobility material / ordinary indium gallium zinc oxide (IGZO), wherein the stacking order of the high mobility material / ordinary indium gallium zinc oxide (IGZO) can be interchanged.

[0286] For example, the second conductive layer 4 may include at least one of the following stacked structures: molybdenum niobate / copper stack, molybdenum titanium alloy / copper stack, molybdenum / aluminum / molybdenum stack, titanium / aluminum / titanium stack, titanium nitride / aluminum / titanium stack, molybdenum titanate / copper / molybdenum titanium alloy stack, molybdenum niobate / copper / molybdenum titanium alloy stack, and molybdenum titanium alloy / copper / molybdenum titanium alloy stack.

[0287] For example, the thickness of the second conductive layer 4 can be in the range of 100 nanometers to 1000 nanometers.

[0288] In step S03, refer to... Figure 4 and Figure 6 A second sublayer 702 and a first sublayer 701 are sequentially formed on the side of the thin-film transistor 20 away from the substrate 1, and a patterning process is performed on the first sublayer 701 and the second sublayer 702 to form a third conductive layer 7.

[0289] For example, the first sublayer 701 may have a first thickness H1 in the third direction Z, and the second sublayer 702 may have a second thickness H2 in the third direction Z, where the first thickness H1 is smaller than the second thickness H2, and the third direction Z is perpendicular to the substrate. For example, the third direction Z is parallel to the direction of the substrate 1 toward the thin-film transistor 20.

[0290] For example, a sixth sublayer 703 may be prepared before the second sublayer 702 is prepared, and then the sixth sublayer 703, the second sublayer 702 and the first sublayer 701 are patterned to form a third conductive layer 7.

[0291] For example, the third conductive layer 7 may include a molybdenum / aluminum / molybdenum stack, or the third conductive layer 7 may include a titanium / aluminum / titanium stack.

[0292] In some embodiments, a first passivation layer 5 may be formed on the side of the second conductive layer 4 away from the substrate before the third conductive layer 7 is formed.

[0293] For example, refer to Figure 11 The first passivation layer 5 may include: a third sublayer 501; a fourth sublayer 502 located on the side of the third sublayer 501 away from the substrate; and a fifth sublayer 503 located on the side of the fourth sublayer 502 away from the substrate.

[0294] For example, the fifth sublayer 503 may include silicon oxide, the fourth sublayer 502 may include hydrogenated silicon nitride, and the third sublayer 501 may include silicon nitride.

[0295] For example, the total thickness of the third sublayer 501, the fourth sublayer 502 and the fifth sublayer 503 in the third direction Z can be in the range of 100 nanometers to 800 nanometers, that is, 100nm≤H51+H52+H53≤800nm.

[0296] For example, the ratio of the thickness H52 of the fourth sublayer 502 in the third direction Z to the thickness H51 of the third sublayer 501 in the third direction Z can be in the range of 0.2 to 1. For instance, the ratio of the thickness H52 of the fourth sublayer 502 in the third direction Z to the thickness H51 of the third sublayer 501 in the third direction Z can be equal to 1:1, 1:2, 1:3, 1:4, 2:3, 2:5, 3:4 or 3:5.

[0297] In some embodiments, after the first passivation layer 5 is prepared and before the third conductive layer 7 is prepared, a sacrificial layer 6 may also be formed on the side of the first passivation layer 5 away from the substrate.

[0298] For example, the material of the sacrificial layer 6 may include an oxide. For instance, the material of the sacrificial layer 6 may include at least one of oxide materials such as indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), or praseodymium-doped indium gallium zinc oxide (Pr-IGZO).

[0299] In step S04, at least one photoelectric converter 8 is formed on the side of the third conductive layer 7 away from the substrate 1.

[0300] For example, the third conductive layer 7 may include a first conductive portion 71, and at least one thin film transistor 20 may be electrically connected to at least one photoelectric converter 8 through the first conductive portion 71.

[0301] For example, in conjunction with reference Figures 4-6 The first conductive portion 71 may include a first main body portion 711 and a first edge portion 712.

[0302] For example, the orthographic projection of at least one photoelectric converter 8 on the substrate can fall within the orthographic projection of the first main body portion 711 on the substrate.

[0303] For example, the first edge portion 712 may at least partially surround the first body portion 711. For instance, at least a portion of the first edge portion 712 may be located on the side of the first body portion 711 away from the thin-film transistor 20.

[0304] The first main body portion 711 may include a first surface S711 located in the first sublayer 701, the first surface S711 being the surface of the first main body portion 711 away from the substrate. The first edge portion 712 may include a second surface S712 located in the first sublayer 701, the second surface S712 being the surface of the first edge portion 712 away from the substrate.

[0305] For example, on the third direction Z, the second surface S712 may be closer to the substrate relative to the first surface S711.

[0306] This method allows the orthogonal projection of the etching boundary of the photoelectric converter on the substrate during the fabrication process to fall within the orthogonal projection of the third conductive layer on the substrate. Thus, the third conductive layer can be used as an etching barrier layer for the photoelectric converter, which helps to reduce the damage to other underlying film layers (such as the film layer where the thin-film transistor is located) caused by the etching process of the photoelectric converter.

[0307] For example, the first surface S711 and the second surface S712 may have a first height difference M1 in the third direction Z.

[0308] For example, the ratio of the first height difference M1 to the first thickness H1 can be less than 0.7. For instance, the ratio of the first height difference M1 to the first thickness H1 can be equal to 0.65, 0.625, 0.6, 0.5, or 0.4.

[0309] For example, the first height difference M1 can be greater than or equal to 50 nanometers. For instance, the first height difference M1 can be equal to 50 nanometers, 55 nanometers, 60 nanometers, 65 nanometers, or 70 nanometers.

[0310] This method allows the first edge of the first conductive portion to form a wrapping effect on the photoelectric converter, while the first sub-layer in the first edge portion will not be completely etched away during the etching process of the photoelectric converter. This is beneficial to improving the conductivity of the first conductive portion and the protective performance of the first conductive portion on the underlying film layer, thereby further improving the X-ray tolerance of the thin film transistor.

[0311] For example, the method for fabricating the detector substrate may further include: sequentially forming one or more of the following film layers on the side of the photoelectric converter 8 away from the substrate 1: a fourth conductive layer 16, a planarization layer 9, a third insulating layer 10, a light-shielding layer 11, a fourth insulating layer 12, and a fifth conductive layer 13.

[0312] While some embodiments of the general concept of this disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general concept of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A detection substrate, characterized in that, include: Substrate; At least one thin-film transistor is located on one side of the substrate. The third conductive layer is located on the side of the thin-film transistor away from the substrate. and At least one photoelectric converter is located on the side of the third conductive layer away from the substrate. The detection substrate includes a first conductive portion located in the third conductive layer, and at least one thin-film transistor is electrically connected to at least one photoelectric converter through the first conductive portion; The third conductive layer includes a first sub-layer and a second sub-layer. The first sub-layer is located on the side of the second sub-layer away from the substrate. The first sub-layer has a first thickness in a third direction, and the second sub-layer has a second thickness in a third direction. The first thickness is less than the second thickness. The third direction is parallel to the direction of the substrate toward the thin film transistor. The first conductive portion includes a first main body portion and a first edge portion, wherein at least one of the photoelectric converters is projected onto the substrate and falls within the projection of the first main body portion onto the substrate, and the first edge portion at least partially surrounds the first main body portion; The first body portion includes a first surface located in the first sublayer, the first surface being the surface of the first body portion away from the substrate, and the first edge portion includes a second surface located in the first sublayer, the second surface being the surface of the first edge portion away from the substrate, and in a third direction, the second surface being closer to the substrate relative to the first surface.

2. The detection substrate according to claim 1, wherein, The first surface and the second surface have a first height difference in a third direction, and the ratio of the first height difference to the first thickness is less than 0.

7.

3. The detection substrate according to claim 2, wherein, The probe substrate further includes a first passivation layer located between the thin-film transistor and the third conductive layer. The first passivation layer includes a first via, and the first conductive portion is electrically connected to the thin-film transistor through the first via. The first conductive portion further includes a second edge portion located on the side of the first body portion near the thin-film transistor, and at least a portion of the second edge portion is located in the first via; and The second edge portion includes a filling portion located in the first via, wherein the surface of the filling portion away from the substrate and the first surface have a second height difference in a third direction, and the second height difference is greater than the first height difference.

4. The detection substrate according to claim 3, wherein, At least one of the photoelectric converters has its orthogonal projection onto the substrate falling within the orthogonal projection of the first passivation layer onto the substrate. as well as The first passivation layer has a third thickness in the third direction, and the ratio of the third thickness to the first height difference is greater than or equal to 4.

5. The detection substrate according to claim 3 or 4, wherein, The detection substrate includes a second main body portion and a third edge portion located in the first passivation layer, wherein at least one of the photoelectric converters is projected onto the substrate and falls within the projection of the second main body portion onto the substrate, and the third edge portion is located on the side of the second main body portion away from the thin film transistor. The surface of the third edge portion away from the substrate and the surface of the second main body portion away from the substrate have a third height difference in a third direction, and the ratio of the third height difference to the first height difference is greater than or equal to 3; and The detection substrate also includes a protective layer located on the side of the photoelectric converter away from the substrate, and the surface of the third edge away from the substrate is covered by the protective layer.

6. The detection substrate according to claim 5, wherein, The probe substrate further includes a fourth edge portion located in the first passivation layer. The fourth edge portion is located on the side of the second body portion near the thin film transistor. The fourth edge portion includes a first side surface. The first side surface includes a first sub-side surface and a second sub-side surface. The first sub-side surface is located on the side of the second sub-side surface away from the substrate. The first sub-side surface has a first slope angle, and the second sub-side surface has a second slope angle. The first slope angle is greater than the second slope angle, and the first slope angle is greater than 75°.

7. The detector substrate according to any one of claims 3-6, wherein, The detection substrate further includes a sacrificial layer located between the first passivation layer and the third conductive layer, wherein the orthographic projection of the photoelectric converter on the substrate falls within the orthographic projection of the sacrificial layer on the substrate; and The material of the sacrificial layer includes oxides.

8. The detection substrate according to claim 7, wherein, The probe substrate includes a sacrificial portion located in the sacrificial layer, and the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the sacrificial portion on the substrate at least partially overlap; as well as The edge of the orthographic projection of the first conductive portion on the substrate and the edge of the orthographic projection of the sacrificial portion on the substrate have a first interval distance in a second direction, the first interval distance being in the range of 0.5 micrometers to 2 micrometers, and the second direction being perpendicular to the third direction.

9. The detection substrate according to claim 8, wherein, The detection substrate includes multiple detection units, which are arranged in an array in a first direction and a second direction, and the first direction and the second direction intersect. The detection substrate includes a plurality of sacrificial portions located in the sacrificial layer, and at least one detection unit includes a thin-film transistor, a photoelectric converter, and a sacrificial portion; as well as Two adjacent sacrificial portions are spaced apart by a second interval distance in a first direction, and the ratio of the second interval distance to the first interval distance is greater than or equal to 6.

10. The detection substrate according to claim 8 or 9, wherein, The orthographic projection of the sacrificial portion on the substrate and the orthographic projection of the thin-film transistor on the substrate are spaced apart.

11. The detector substrate according to any one of claims 8-10, wherein, The detection substrate includes: a first conductive layer, a first semiconductor layer and a first insulating layer, wherein the first insulating layer is located between the first conductive layer and the first semiconductor layer; The thin-film transistor includes a control electrode and an active part, wherein the control electrode of the thin-film transistor is located in the first conductive layer, and the active part of the thin-film transistor is located in the first semiconductor layer. The material of the first insulating layer includes silicon nitride, and the ratio of the number of silicon atoms to the number of nitrogen atoms in the first insulating layer is in the range of 1.2 to 2.

12. The detection substrate according to claim 11, wherein, The crystal structure of the first insulating layer includes multiple silicon-hydrogen bonds and multiple silicon-nitrogen bonds, and the ratio of the number of silicon-hydrogen bonds to the number of silicon-nitrogen bonds in the crystal structure of the first insulating layer is in the range of 0.03 to 0.

22.

13. The detection substrate according to claim 11 or 12, wherein, The first insulating layer is located on the side of the first conductive layer away from the substrate, and the first semiconductor layer is located on the side of the first insulating layer away from the substrate. The detection substrate includes a second conductive portion located in the first conductive layer, and the control electrode is located in the second conductive portion. The second conductive portion includes a second side surface, and the second side surface has a third slope angle, which is in the range of 20° to 30°.

14. The detection substrate according to claim 12, wherein, The detection substrate further includes a second conductive layer located between the first semiconductor layer and the third conductive layer. The second conductive layer includes a third conductive portion and a fourth conductive portion. The thin film transistor further includes a first electrode and a second electrode. The first electrode of the thin film transistor is located in the third conductive portion, and the second electrode of the thin film transistor is located in the fourth conductive portion. The third conductive part is electrically connected to the first conductive part through the first via; The second conductive portion includes a third main body and a first branch. The third main body extends along a first direction, and the first branch is located on the side of the third main body facing the photoelectric converter. The orthographic projection of the first branch on the substrate and the orthographic projection of the active portion on the substrate at least partially overlap. as well as The orthographic projection of the first branch on the substrate and the orthographic projection of the third conductive part on the substrate at least partially overlap, the overlapping portion of the projections of the first branch and the third conductive part having a first width in a first direction, and the ratio of the first width to the first interval distance being less than or equal to 3.

6.

15. The detector substrate according to claim 11, wherein, The orthogonal projection of the active part on the substrate falls within the orthogonal projection of the third conductive layer on the substrate. And / or, The detection substrate further includes a light-shielding layer located on the side of the photoelectric converter away from the substrate. The light-shielding layer includes a light-shielding portion, and the orthographic projection of the active portion on the substrate falls within the orthographic projection of the light-shielding portion on the substrate.

16. The detector substrate according to any one of claims 1-15, wherein, The detection substrate further includes a planarization layer located on the side of the photoelectric converter away from the substrate, wherein the orthographic projection of the thin-film transistor on the substrate falls within the orthographic projection of the planarization layer on the substrate; and The planarization layer is made of silicon-containing organic materials.

17. The detector substrate according to claim 14, wherein, The second conductive layer is located on the side of the first semiconductor layer away from the substrate. The active portion includes a first electrode region, a second electrode region, and a channel region, the channel region being located between the first electrode region and the second electrode region. The first electrode region is electrically connected to the first electrode of the thin-film transistor, and the second electrode region is electrically connected to the second electrode of the thin-film transistor.

18. The detection substrate according to claim 11, wherein, The first insulating layer is located on the side of the first semiconductor layer away from the substrate, the first conductive layer is located on the side of the first insulating layer away from the substrate, and the probe substrate further includes a second conductive layer located on the side of the first semiconductor layer close to the substrate. The active portion includes a first electrode region, a second electrode region, and a channel region, wherein the channel region is located between the first electrode region and the second electrode region; and The first conductive portion is electrically connected to the first electrode region, and the second conductive layer includes a third conductive portion, which is electrically connected to the second electrode region.

19. The detection substrate according to claim 11, wherein, The first insulating layer is located on the side of the first semiconductor layer away from the substrate, and the first conductive layer is located on the side of the first insulating layer away from the substrate. The detection substrate further includes: a second insulating layer located on the side of the first conductive layer away from the substrate; The second conductive layer is located on the side of the second insulating layer away from the substrate. The second conductive layer includes a third conductive portion and a fourth conductive portion. The second insulating layer includes a second via and a third via. The active portion includes a first electrode region, a second electrode region, and a channel region. The channel region is located between the first electrode region and the second electrode region. The third conductive portion is electrically connected to the first electrode region through the second via. The fourth conductive portion is electrically connected to the second electrode region through the third via.

20. The detection substrate according to claim 11, wherein, The first insulating layer comprises a single layer of silicon nitride film; or, The first insulating layer includes at least one of the following: a silicon nitride / hydrogenated silicon nitride stack, a silicon nitride / hydrogenated silicon nitride / silicon nitride stack, a hydrogenated silicon nitride / silicon nitride stack, a silicon nitride / silicon oxide stack, and a hydrogenated silicon nitride / silicon oxide stack.

21. The detection substrate according to claim 3, wherein, The first passivation layer includes: a third sublayer; a fourth sublayer located on the side of the third sublayer away from the substrate; and a fifth sublayer located on the side of the fourth sublayer away from the substrate, the fifth sublayer comprising silicon oxide, the fourth sublayer comprising silicon nitride, and the third sublayer comprising silicon nitride; and The ratio of the thickness of the fourth sublayer in the third direction to the thickness of the third sublayer in the third direction is in the range of 0.2 to 1.

22. A flat panel detector, characterized in that, Includes the probe substrate as described in any one of claims 1-21.

23. A method for preparing a detector substrate, characterized in that, include: Provide substrates; At least one thin-film transistor is formed on one side of the substrate. A second sublayer and a first sublayer are sequentially formed on the side of the thin-film transistor away from the substrate, and a patterning process is performed on the first sublayer and the second sublayer to form a third conductive layer. The first sublayer has a first thickness in a third direction, the second sublayer has a second thickness in a third direction, the first thickness is less than the second thickness, and the third direction is perpendicular to the substrate. At least one photoelectric converter is formed on the side of the third conductive layer away from the substrate. The third conductive layer includes a first conductive portion, and at least one of the thin-film transistors is electrically connected to at least one of the photoelectric converters through the first conductive portion; The first conductive portion includes a first main body portion and a first edge portion, wherein at least one of the photoelectric converters is projected onto the substrate and falls within the projection of the first main body portion onto the substrate, and the first edge portion at least partially surrounds the first main body portion; The first body portion includes a first surface located in the first sublayer, the first surface being the surface of the first body portion away from the substrate, and the first edge portion includes a second surface located in the first sublayer, the second surface being the surface of the first edge portion away from the substrate, and in a third direction, the second surface being closer to the substrate relative to the first surface.

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